Electronic optical system structure of multi-electron-beam photoetching equipment and manufacturing method of electronic optical system structure

Abstract

The invention discloses an MEMS (Micro Electro Mechanical System)-based electron optical system structure in multi-electron beam photoetching equipment and a manufacturing method, the electron optical system structure in an MEMS device is a core component, and the electron optical system structure can be used for splitting, collecting and focusing an electron beam incident in a hole and realizing the functions of adjusting centering and astigmatism. Through a control chip, transmission lines are utilized, the transmission lines are connected with the salient points corresponding to the different metal lines, and voltage is applied to the metal film layer beside the MEMS micropore array. The electric field intensity is controlled by adjusting the voltage in the metal film, the functions of collecting and focusing the incident electron beam are achieved, finally beam spots can be projected to any position in a writing field, and miniaturization of an electron optical system is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-nano manufacturing, and particularly relates to a structure of an electron optical system of a multi-electron beam lithography equipment and a manufacturing method thereof. Background Art

[0002] Due to advantages such as high resolution, high throughput, and low manufacturing cost, multi-electron beam parallel lithography is the only solution for the mass production of chip mask manufacturing in the process nodes of 3nm and below, and has an irreplaceable position.

[0003] In traditional Gaussian beam, or even deformed beam (combining different-shaped diaphragms to form a surface beam spot with a specific pattern) equipment, the electron optical system is mainly assembled by discrete modules such as electron guns, beam shutters, diaphragms, electron lenses, and deflectors; these discrete and bulky components make it difficult to expand the number of electron beam light columns. Therefore, it is difficult to meet the efficiency requirements when manufacturing complex mask patterns in the 3nm and below nodes. On the contrary, in the electron optical system of multi-electron beam lithography equipment, MEMS manufacturing technology is used to integrate beam splitting, focusing, deflection and other modules on-chip. By using the dedicated MEMS micro-hole array therein, the number of electron light columns can be expanded to hundreds, thousands, or even hundreds of thousands of fields, thereby realizing multi-electron beam parallel lithography and greatly improving the mask manufacturing efficiency. As one of the core components of multi-electron beam lithography equipment, the electron optical system undertakes important functions such as beam splitting, focusing, blocking, and deflection of electron beam current, and is the key to realizing large-scale parallel electron beam lithography and ensuring that the beam spot ≤ 12nm. It is urgent to develop new low-cost, miniaturized and high-performance device architectures and manufacturing solutions. Summary of the Invention

[0004] The purpose of the present invention is to propose a structure of an electron optical system of a multi-electron beam lithography equipment and a manufacturing method thereof. The electron optical system includes metal bumps connected to the chip, MEMS wiring metal connecting different metal layers, a micro-hole metal layer for changing the electric field in the holes, an insulating micro-hole dielectric layer, a structural substrate, micro-holes, a low-k dielectric layer, a metal deflector, a packaging dielectric layer, etc.

[0005] The technical solution adopted by the present invention is a structure of an electron optical system of a multi-electron beam lithography equipment and a manufacturing method thereof. The structure of the electron optical system includes four parts: a multi-layer metal / dielectric film layer, a substrate, a metal deflector, and a packaging layer. Among them, the multi-layer metal / dielectric film layer, as the core component, can converge and focus the electron beam incident on the surface. The preparation steps include depositing a multi-layer metal / dielectric stack film, patterning, filling, etching, planarization, and sidewall passivation layer deposition on the front side of the wafer. The control chip uses a transmission line to input signals into a distributor. After the distributor processes the signals, different voltages are applied to the through holes in the MEMS microhole array. By adjusting the voltage difference between different metal / insulating layers, functions such as focusing, converging, deflecting, and projecting the incident electron beam can be realized. Finally, the spot size can be scaled down to a sub-10-nanometer scale, and the focal depth can be flexibly adjusted by controlling the number of film layers, which is beneficial to the miniaturization of the electron optical system.

[0006] The preparation method of the MEMS microhole array in the electron optical system proposed by the present invention is specifically as follows:

[0007] S1, Prepare a silicon substrate (crystal orientation 110), highly doped (>1e19), and spin-coat SU-8 photoresist on the front side of the substrate with a thickness of 50 μm, expose and develop it. Subsequently, use the photoresist as a mask to etch the substrate until 50 - 10 μm remains.

[0008] S2, Spin-coat a filler (SOC) on the front side of the substrate and planarize it until the silicon layer is exposed.

[0009] S3, Grow a 200-nm SiNx dielectric thin film on the front side of the substrate, and then magnetron sputter-grow a 200-nm tungsten (W) metal thin film.

[0010] S4, Spin-coat AZ5214 photoresist, expose and develop it. Subsequently, use the photoresist as a mask to pattern the metal, and then remove the photoresist.

[0011] S5, Deposit a 400-nm SiNx dielectric thin film, and then use CMP to planarize the surface.

[0012] S6, Repeat steps S3, S4, and S5 until the target layered structure is reached.

[0013] S7, Spin-coat AZ5214 on the film layer structure multiple times, expose and develop it, and use dry plasma etching to etch the dielectric SiNx to form deep holes connected to the metal holes corresponding to different metal layers at the bottom.

[0014] S8, Deposit an adhesion layer TiW and a seed layer Ru by ALD, and then use electroplating to fill copper (Cu) in the obtained deep holes above. After filling, CMP is used to planarize its surface.

[0015] S9. Grow a dielectric thin film SiNx on the flattened surface obtained above, spin coat photoresist on it, expose, develop, and etch to expose the top of the metal wire;

[0016] S10. Repeat step S8;

[0017] S11. Spin coat AZ5214 on the surface of the above wiring layer, expose, develop, and etch using the photoresist as a mask to form a multi-layer metal / dielectric micro-hole array coaxial with the bottom silicon through-hole;

[0018] S12. Flip the wafer, deposit a low-k dielectric layer (silicon fluoride) on the back, spin coat AZ5214 on it, expose, develop, and etch to pattern it;

[0019] S13. Repeat step S8;

[0020] S14. Deposit SiO2 by ICPCVD, then spin coat AZ5214 on it, expose, develop, and etch to pattern a hole coaxial with the through-hole on the front side;

[0021] S15. Using the dielectric layer deposited in the previous step as a mask, self-align and etch the bottom silicon to etch through the through-hole;

[0022] S16. After removing the native oxide layer on the surface of the obtained structure by DHF, immerse it in a combined solution of TMAH and IPA for treatment to reduce the sidewall roughness;

[0023] S17. Spin coat and fill photoresist in the obtained micro-holes, expose and develop, deposit tin metal bumps on the top of the corresponding metal wires, and then remove the photoresist;

[0024] S18. Deposit a via passivation layer (ALD - alumina) to complete the dedicated MEMS micro-hole array structure.

[0025] In the electro-optical system structure of the present invention, it is characterized in that: the micro-hole array unit can be highly densely integrated to realize functions such as the convergence, scaling, and focusing of multiple electron beams.

[0026] In the electro-optical system structure of the present invention, it is characterized in that: the dedicated MEMS micro-hole array unit can be synergistically optimized through the multi-layer metal / dielectric micro-hole array distributed on the front side to realize the convergence, scaling, and focusing of electron beams;

[0027] In the electro-optical system structure of the present invention, it is characterized in that: the purpose of etching the dielectric through-holes in the dedicated MEMS micro-hole array unit is to expose the metal connected to each metal hole in each layer, and reserve transmission lines for the ASIC control chip and the distributor. By independently controlling the electric field of each layer of metal in each micro-hole array, the morphology of each independent electron beam current can be flexibly adjusted.

[0028] As described above, as the core array device structure and manufacturing method of an electron optical system structure and its manufacturing method for a multi-electron beam lithography equipment of the present invention, it has the following beneficial effects:

[0029] 1. The MEMS micro-hole array can be highly integrated densely, achieving multi-electron beam exposure while improving efficiency and reducing costs;

[0030] 2. Through the collaborative optimization of multi-layer metal / dielectric micro-hole arrays distributed on the front / back sides of the silicon wafer, higher-efficiency beam convergence, scaling, and focusing of the electron beam can be achieved; the beam convergence structures on the front and back sides can greatly ensure the achievement of a sub-10nm beam spot;

[0031] 3. The preparation process of the dedicated MEMS micro-hole array is completely compatible with the CMOS process, with low costs and easy integration;

[0032] 4. This electron optical system has advantages such as simple processes, high reliability, miniaturization, and easy integration, and can be applied to multi-electron beam lithography manufacturing equipment for chips at the 3nm and below nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure of the electron optical system of the present invention applied to a multi-electron beam lithography equipment;

[0034] Figures 2 - 15 It is a flowchart for the preparation of a dedicated MEMS micro-hole array unit in the structure of the electron optical system of the present invention:

[0035] Figures 2 - 4 It is a preparation method for a dedicated MEMS micro-hole array unit, and it is a schematic diagram of the structure after etching, filling, and planarization of the silicon wafer substrate in specific steps S1 and S2;

[0036] Figure 5 It is a preparation method for a dedicated MEMS micro-hole array unit, and it is a schematic diagram of the structure after depositing a dielectric film and then depositing a metal film on the silicon wafer in specific step S3;

[0037] Figure 6 It is a preparation method for a dedicated MEMS micro-hole array unit, and it is a schematic diagram of the structure obtained after depositing a dielectric film on the patterned metal and planarizing in specific steps S4 and S5;

[0038] Figure 7 It is a preparation method for a dedicated MEMS micro-hole array unit, and it is a schematic diagram of the structure after depositing metal multiple times and patterning, depositing a dielectric film and planarizing on the front side of the silicon wafer in specific step S6;

[0039] Figure 8 It is a preparation method for a dedicated MEMS micro-hole array unit, and it is a schematic diagram of the through-hole structure formed after multiple exposures and etching to connect to different metal holes in specific step S7;

[0040] Figure 9 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram after metal filling of the metal via holes and wiring layers in specific steps S8, S9, and S10;

[0041] Figure 10 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram after forming through holes by etching multi-layer metal / dielectric in specific step S11;

[0042] Figure 11 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram after depositing low-k material on the back side of the wafer and patterning it in specific step S12.

[0043] Figure 12 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram after depositing an adhesion layer, a seed layer, electroplating copper and polishing on the obtained structure in specific step S13;

[0044] Figure 13 It is a preparation method of a dedicated MEMS microhole array unit. After encapsulating the dielectric layer on the top of the structure and patterning it in specific step S14.

[0045] Figure 14 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram of the formed through vias after etching the low-k dielectric layer and the silicon layer using the encapsulation dielectric layer as a mask in specific steps S15 and S16.

[0046] Figure 15 It is a preparation method of a dedicated MEMS microhole array unit. It is a schematic structural diagram of the final dedicated MEMS microhole array after depositing metal bumps connected to metal wires on the top of the structure and depositing a passivation layer on the sidewalls in specific steps S17 and S18.

[0047] The following description is made in conjunction with the accompanying drawings:

[0048] 1 - Tin metal bump; 2 - Metal through hole; 3 - Metal layer in the hole; 4 - Insulating dielectric layer in the hole; 5 - Silicon wafer substrate; 6 - Electron beam optical through hole; 7 - Low dielectric constant material; 8 - Deflector; 9 - Encapsulation dielectric material. Specific embodiments

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please refer to Figures 1 to 15 , it should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the relevant part of the process flow in the present invention is shown in the diagrams, rather than all the detailed process steps when implemented according to the actual process flow. The actual process flow and related experimental parameters during its actual implementation can be changed according to actual needs.

[0051] This embodiment provides a structure of an electron optical system of a multi-electron beam lithography equipment and a manufacturing method thereof, which is formed by encapsulating after connecting a control chip unit and a dedicated MEMS microhole array through a transmission line. Among them, the MEMS microhole array unit is the core component, including a silicon substrate, a front multi-layer metal / dielectric microhole array, metal wires connecting different metal layers on the front, through-silicon vias, metal deflectors, a packaging dielectric layer, and a passivation layer on the sidewall of the silicon via, etc.

[0052] A preparation method for the above-mentioned dedicated MEMS microhole array unit is as follows:

[0053] S1. Prepare a 4-inch silicon substrate (crystal orientation 110), highly doped (>1e19), and spin-coat SU-8 photoresist on the front of the substrate with a thickness of 50 um, expose and develop it. Subsequently, using the photoresist as a mask, etch the substrate using the BOSCH process (SF6:C4F8 gas flow ratio 9:7) until it is etched to a remaining thickness of 50 - 10 um;

[0054] S2. Spin-coat a filler (SOC) on the front of the substrate, and then perform CMP planarization until the silicon layer is exposed;

[0055] S3. Use ICPCVD to grow a 200-nm SiNx dielectric thin film on the front of the substrate at 260 °C, and then magnetron sputter to grow a 200-nm tungsten (W) metal thin film;

[0056] S4. Spin-coat AZ5214 photoresist, expose and develop it. Subsequently, using the photoresist as a mask, etch the exposed metal W using SF6 + Ar gas until etching stops at the dielectric layer, and then remove the photoresist;

[0057] S5. Deposit a 400-nm SiNx dielectric thin film under the same parameters of ICPCVD, and then use CMP to planarize the surface;

[0058] S6. Repeat steps S3, S4, and S5 until the target layered structure is achieved (repeat 5 times to reach a 10-layer film structure).

[0059] S7. Spin-coat AZ5214 on the film structure multiple times, expose it, develop it, and etch SiNx using ICP dry plasma (with CF4 as the main etching gas) to form deep holes connected to the corresponding metal holes of the different metal layers at the bottom.

[0060] S8. Deposit an adhesion layer TiW and a seed layer Ru by ALD, and then fill copper (Cu) into the obtained deep holes by electroplating. The electroplating copper voltage is 0.55 - 0.7V, and the solution is CuSO4 / H2SO4 / NaCl / polymer with concentrations of 1mol / L, 0.5mol / L, 0.001mol / L respectively. After filling, planarize its surface by CMP.

[0061] S9. Grow a 200nm dielectric thin film SiNx on the surface after the above-mentioned planarization by ICPCVD, spin-coat photoresist on it, expose it, develop it, and etch to expose the top of the metal line.

[0062] S10. Repeat step S8.

[0063] S11. Spin-coat AZ5214 on the surface of the above-mentioned wiring layer, expose it, develop it, and etch to form a multi-layer metal / dielectric micro-hole array coaxial with the through-silicon via at the bottom (using SF6 as the main etching gas) with the photoresist as the mask.

[0064] S12. Flip the wafer, deposit a 10um low-k dielectric layer (organic silicon) on the back, spin-coat AZ5214 on it, expose it, develop it, and etch to pattern it.

[0065] S13. Repeat step S8.

[0066] S14. Deposit SiO2 by ICPCVD, then spin-coat AZ5214 on it, expose it, develop it, and etch to pattern coaxial holes with the through-holes on the front side.

[0067] S15. Using the dielectric layer deposited in the previous step as the mask, self-align etch the bottom silicon to etch through the through-hole.

[0068] S16. After briefly etching the surface natural oxide layer of the obtained structure by DHF, immerse it in a combined solution of TMAH and IPA for treatment to reduce the sidewall roughness.

[0069] S17. Spin-coat and fill photoresist in the obtained micro-holes, expose and develop it, deposit tin metal bumps on the top of the corresponding metal lines, and then remove the photoresist.

[0070] S18, Through-hole passivation layer deposition (ALD - alumina), completing the dedicated MEMS micro-hole array structure.

[0071] The specific examples, working principles, and preparation methods described above further elaborate on the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electron optical system structure of a multi-electron beam lithography equipment, characterized in that: The structure consists of a bump (1), a MEMS wiring metal (2), a microporous metal layer (3), a microporous dielectric layer (4), a structural substrate (5), a micropore (6), a low-k dielectric layer (7), a deflector (8), and a packaging dielectric layer (9); the packaging dielectric layer (9), the low-k dielectric layer (7), the structural substrate (5), and the microporous dielectric layer (4) are arranged in sequence from bottom to top, each microporous metal layer (3) is arranged in parallel in the microporous dielectric layer (4), each microporous metal layer (3) is connected to the bump (1) through the MEMS wiring metal (2), and the bump (1) is used to be electrically connected to a control chip; the micropore (6) runs through the middle of the packaging dielectric layer (9), the low-k dielectric layer (7), the structural substrate (5), and the microporous dielectric layer (4); the deflector (8) is arranged in the low-k dielectric layer (7) on the wall of the micropore (6); During operation, a voltage is transmitted to a bump (1) on the MEMS through a transmission line connected to a control chip, and the bump (1) then transmits the voltage to a microporous metal layer (3) of a different film layer through a wiring layer (2) filled with metal in the structure; the voltage on the microporous metal layer (3) is changed by a signal from the control chip to achieve the purpose of adjusting the electric field intensity in the hole; and a microporous dielectric layer (4) is used between the microporous metal layers (3) to isolate the current.

2. The electron optical system structure of a multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The control chip controls the voltage transmitted to the microporous metal layer (3) through an electrical signal, so as to change the electric field between the microporous metal layers (3), transmit voltage and control signals to the microporous units, and perform the functions of converging and focusing the electron beam. In addition, when the electron beam passes through the through hole (6), it will be affected by the voltage applied to the through hole side wall deflector (8), thereby changing the trajectory of the electron beam, thereby achieving the purpose of exposure at different positions.

3. The electron optical system structure of a multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The transmission line is a wire bonding or optical fiber transmission method; the electronic optical structure is manufactured in batches on a structural substrate (5) to achieve multi-hole integration and is applied to multi-electron beam lithography equipment.

4. The electron optical system structure of a multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The structural substrate (5) is a highly doped silicon substrate with a doping concentration of >1e19 / cm 3 , resistivity less than 10 -2 Ω·cm.

5. The electron optical system structure of multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: Each metal circular hole in each layer of the microholes (6) is connected to a corresponding metal wire, so that its voltage can be individually controlled by a control chip, and cooperates with other metal holes to achieve the effects of electron beam splitting, focusing and zooming.

6. The electron optical system structure of a multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The array of micropores (6) is connected to the connection wires and the distributor via the PCB board and the bumps (1); the distributor can process the signal sent by the control chip to distribute the voltage to the target metal pores, so as to realize the control of an electron beam flow individually; the number of layers of the microporous metal layer (3) / microporous dielectric layer (4) coating is ≧2.

7. The electron optical system structure of multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The diameter of the micropores (6) is 1-5 μm, the pore diameter deviation of each membrane layer does not exceed 2%, the thickness of each membrane layer is 50-500 nm, and the thickness deviation of each layer does not exceed 5%.

8. The electron optical system structure of multi-electron beam lithography equipment and the manufacturing method thereof according to claim 1, characterized in that: The microporous metal layer (3) / microporous dielectric layer (4) is coated with molybdenum, tungsten, aluminum, ruthenium, nickel metal, and silicon oxide, silicon nitride, hafnium oxide, aluminum oxide dielectric insulating layer; The deflector (8) is made of copper; the passivation layer on the sidewall of the through hole in the dedicated MEMS micro-hole array is made of molybdenum, tungsten, aluminum, ruthenium, or nickel, and has a thickness of ≧1 nm.

9. A method for manufacturing an electron optical system structure of a multi-electron beam lithography equipment according to any one of claims 1 to 11, characterized in that: The following steps are involved: S1, preparing a double-sided polished structural substrate (5), and performing photoresist coating, exposure, and development on the front side of the structural substrate (5), and then etching the structural substrate (5) to leave 10 to 50 um, with a depth-to-width ratio greater than 100:1; a sidewall roughness less than 10 nm, and a sidewall angle greater than 87°; S2, spin coating a filler on the front side of the structural substrate (5) and flattening until the silicon layer is exposed, and the roughness after flattening is less than 1 nm; S3, growing a microporous dielectric layer (4) and then growing a microporous metal layer (3) on the front side of the structural substrate (5); S4, depositing a dielectric film after patterning the metal film, and planarizing the surface thereof; S5, repeating steps S3 and S4 until the target layered structure is reached; S6, multiple times of coating, exposure, and etching to form deep holes connected to corresponding metal holes of different metal layers at the bottom; S7, filling the deep hole obtained above with metal using a Damascus process, and planarizing the surface thereof; S8, growing a dielectric film on the planarized surface obtained above, and performing photoresist coating thereon, exposing, developing and etching to expose the top of the metal wire; S9, fill metal, complete the wiring layer and flatten its surface; S10, coating, aligning, exposing and etching on the surface of the wiring layer to form a multi-layer metal / dielectric micro-hole array coaxial with the bottom silicon through-hole, S11, flipping the wafer, depositing a low-k dielectric layer on the back side, and patterning it; S12, after depositing the adhesion layer / seed layer, metal is subsequently deposited and planarized until the surface metal is completely removed, thereby completing the preparation of the deflector (8) body; S13, depositing a packaging dielectric layer; S14, etching the dielectric layer using the photoresist as a mask until the dielectric layer deposited on the back side of the wafer is completely etched and then the photoresist is removed; S15, using the dielectric layer deposited in the previous step as a mask, self-aligningly etching the bottom silicon to etch through the through hole; S16, filling the micro-holes obtained above with photoresist, then exposing and developing, depositing metal bumps (5) on the tops of the corresponding metal lines, and then removing the fillers; S17, through-hole passivation layer deposition, completing the dedicated MEMS micro-hole array structure.

10. The method for manufacturing the electron optical system structure of multi-electron beam lithography equipment according to claim 9, characterized in that: In S1, the substrate etching is wet etching: TMAH wet etching, concentration 20% to 30%, temperature 50°C to 90°C, or dry etching: BOSCH process, SF6:C4F8 gas flow ratio 10:7 to 8:7; In S2, the filling method includes spin coating; the filling includes photoresist, or spin-on carbon SOC, spin-on glass SOG; In S4, the surface planarization methods include chemical mechanical polishing (CMP), ion beam etching (IBE), and dry etching; In S5, the multilayer metal / dielectric structure does not emphasize the number of film layers, as long as it can meet the purpose of converging and focusing the electron beam; In S6, the etched structure does not necessarily have to be etched into a hole-shaped structure, as long as the voltage can be transmitted to the metal holes in the hole array; In S6-7, the metal wire etching and filling process does not emphasize patterning the dielectric layer and depositing the metal wires to connect with the metal hole structure in the microhole array after the film layer structure is prepared, or after each metal / dielectric layer is formed; In S6, S8, and S10, the metal / dielectric etching is performed by plasma dry etching; In S11, the low-k dielectric layer is organic silicon, silicon fluoride or polyimide; In S12, the metal deposition method is physical vapor deposition (PVD) or electroplating deposition (ED); In S13, the dielectric layer is silicon oxide; In S15, a wet solution is used to post-treat the silicon sidewall after etching to reduce the roughness of the sidewall; In S17, the passivation layer on the sidewall of the through silicon via is deposited by CVD, PVD or ALD, and the deposited material is Mo or Ru.

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