Voltage regulator and semiconductor device

Abstract

The invention provides a voltage regulator and a semiconductor device, and the voltage regulator can restrain excessive voltage from being generated at an output terminal under the condition that a bonding wire of a voltage adjusting terminal is broken. Comprises: an output transistor having a source connected to an input terminal and a drain connected to an output terminal; a divider resistor, which is connected between the voltage adjustment terminal and a ground terminal, divides the adjustment voltage input to the voltage adjustment terminal, and outputs a feedback voltage; a reference voltage circuit outputting a reference voltage; an error amplifier circuit that controls a gate voltage of the output transistor on the basis of a reference voltage and a feedback voltage; and a disconnection protection circuit including a first MOS transistor having a source connected to the output terminal and a gate connected to the voltage adjustment terminal, the disconnection protection circuit detecting disconnection of the bonding wire of the voltage adjustment terminal.

Description

Technical Field

[0001] The present invention relates to a voltage regulator and a semiconductor device. Background Art

[0002] Generally, a voltage regulator generates a certain voltage from the power supply voltage input to the input terminal and outputs a certain voltage to the output terminal. Moreover, even if the power supply voltage or the load current varies, the output voltage is maintained at a constant value. In order to ensure the accuracy of the output voltage in the case of a large output current, a voltage regulator having a feedback voltage terminal separately provided from the output terminal is known.

[0003] Figure 5 There are an existing voltage regulator and a semiconductor device provided with a feedback voltage terminal.

[0004] The existing voltage regulator 51 includes: an operational amplifier OP1, an output transistor M1, voltage dividing resistors R1 and R2, a protection resistor Rp1, an input terminal Pi1, an output terminal Po1, and a feedback voltage terminal Pf1.

[0005] The semiconductor device 52 includes an input terminal Pi2 and an output terminal Po2. The output terminal Po2 is connected to the output terminal Po1 and the feedback voltage terminal Pf1 of the voltage regulator to supply voltage to the load LD.

[0006] Since the feedback voltage terminal Pf1 is connected to the output terminal Po2, it is not affected by the voltage drop caused by the output current and the bonding wire like the output terminal Po1, and the voltage of the output terminal Po2 is input.

[0007] The protection resistor Rp1 is connected between the output terminal Po1 and the feedback voltage terminal Pf1, and operates to limit the output voltage to a specified voltage in the case where the bonding wire of the feedback voltage terminal Pf1 is broken (for example, refer to Patent Document 1).

[0008] [Prior Art Documents]

[0009] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-128329 Summary of the Invention

[0011] [Problems to be Solved by the Invention]

[0012] However, in the existing voltage regulator, in the case where the bonding wire of the feedback voltage terminal Rf1 is broken, since the protection resistor Rp1 is connected in series with the voltage dividing resistor, there is a problem that the output voltage is higher than the desired voltage value.

[0013] In view of the above situation, the object of the present invention is to provide a voltage regulator that can suppress the generation of an excessive voltage at the output terminal in the case where the bonding wire of the feedback voltage terminal is broken.

[0014] [Technical means for solving the problem]

[0015] The voltage regulator according to an embodiment of the present invention inputs an input voltage from an input terminal and outputs an output voltage to an output terminal. The voltage regulator is characterized by including: an output transistor having a source connected to the input terminal and a drain connected to the output terminal; a voltage dividing resistor connected between a voltage adjustment terminal and a ground terminal, dividing the adjustment voltage input to the voltage adjustment terminal, and outputting a feedback voltage; a reference voltage circuit for outputting a reference voltage; an error amplification circuit for controlling the gate voltage of the output transistor based on the reference voltage and the feedback voltage; and a disconnection protection circuit including a first Metal Oxide Semiconductor (MOS) transistor having a source connected to the output terminal and a gate connected to the voltage adjustment terminal, detecting a break in the bonding wire of the voltage adjustment terminal.

[0016] [Effects of the invention]

[0017] According to the present invention, a voltage regulator can be provided. Since it includes a disconnection protection circuit, that is, a disconnection protection circuit having a first MOS transistor with a source connected to the output terminal and a gate connected to the voltage adjustment terminal and detecting a break in the bonding wire of the voltage adjustment terminal, an excessive voltage can be suppressed from being generated at the output terminal in the case where the voltage adjustment terminal is disconnected. Description of the drawings

[0018] Figure 1 It is a circuit diagram showing an example of the voltage regulator and the semiconductor device according to the embodiment of the present invention.

[0019] Figure 2 It is a circuit diagram showing another example of the voltage regulator according to the present embodiment.

[0020] Figure 3 It is a circuit diagram showing still another example of the voltage regulator according to the present embodiment.

[0021] Figure 4 It is a circuit diagram showing still another example of the voltage regulator according to the present embodiment.

[0022] Figure 5 It is a circuit diagram showing a conventional voltage regulator and semiconductor device.

[0023] [Explanation of symbols]

[0024] 1: Voltage regulator

[0025] 10: Error amplification circuit

[0026] 20: Reference voltage circuit

[0027] R1, R2: Resistors (voltage dividing resistors)

[0028] M1: Output transistor

[0029] M2: MOS transistor (first MOS transistor)

[0030] M3: MOS transistor

[0031] M4, M5, M6, M7, M8: MOS transistors

[0032] VI: Input terminal

[0033] VIp: Input terminal

[0034] VO: Output terminal

[0035] VOp: Output terminal

[0036] VA: Voltage adjustment terminal

[0037] W1, W2, W3: Bonding wires

[0038] 100: Semiconductor device Detailed implementation mode

[0039] Hereinafter, the voltage regulator 1 and the semiconductor device 100 according to the embodiments of the present invention will be described based on the drawings.

[0040] Figure 1 It is a circuit diagram of the voltage regulator 1 and the semiconductor device 100 of the present embodiment.

[0041] The voltage regulator 1 includes: an input terminal VI, an output terminal VO, a voltage adjustment terminal VA, an error amplification circuit 10, a reference voltage circuit 20, resistors R1 and R2 as voltage dividing resistors, an output transistor M1, and a MOS transistor M2 as a disconnection protection circuit.

[0042] The source of the output transistor M1 is connected to the input terminal VI, the drain is connected to the output terminal VO, and the gate is connected to the output terminal of the error amplification circuit 10. The inverting input terminal - of the error amplification circuit 10 is connected to the output terminal of the reference voltage circuit 20, and the non-inverting input terminal + is connected to the connection point of the resistors R1 and R2 (the output terminal of the voltage dividing resistors). The resistors R1 and R2 are connected in series between the voltage adjustment terminal VA and the ground terminal. The source of the MOS transistor M2 is connected to the output terminal VO, the drain is connected to the output terminal of the voltage dividing resistors, and the gate is connected to the voltage adjustment terminal VA.

[0043] The semiconductor device 100 includes an input terminal VIp and an output terminal VOp. The input terminal VIp is connected to the input terminal VI of the voltage regulator 1 through a bonding wire W1. The output terminal VOp is connected to the output terminal VO of the voltage regulator 1 through a bonding wire W2, and further connected to the voltage adjustment terminal VA through a bonding wire W3 to supply the output voltage VOUT to the load LD.

[0044] Since the voltage adjustment terminal VA is connected to the output terminal VOp, it is not affected by the voltage drop caused by the output current and the wiring resistance of the bonding wire W2 like the output terminal VO, and the voltage of the output terminal VOp is input.

[0045] The operation of the voltage regulator 1 will be described.

[0046] The voltage regulator 1 generates a constant voltage based on the input voltage VIN input to the input terminal VI and outputs it as the output voltage VOUT from the output terminal VO. The resistors R1 and R2 generate a feedback voltage Vfb based on the adjustment voltage VADJ input from the voltage adjustment terminal VA. The error amplifier circuit 10 controls the gate voltage of the output transistor M1 based on the reference voltage Vref output from the reference voltage circuit 20 and the feedback voltage Vfb. That is, the output voltage VOUT of the voltage regulator 1 is controlled to a voltage equal to the feedback voltage Vfb and the reference voltage Vref.

[0047] Next, the operation when the bonding wire W3 connected to the voltage adjustment terminal VA is broken will be described.

[0048] When the bonding wire W3 connected to the voltage adjustment terminal VA is broken, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal. The error amplifier circuit 10 controls to lower the gate voltage of the output transistor M1 and increase the output voltage VOUT.

[0049] At this time, the MOS transistor M2 conducts when the gate-source voltage becomes above the threshold voltage due to the rise of the output voltage VOUT as the source voltage and the decrease of the adjustment voltage VADJ as the gate voltage. When the MOS transistor M2 conducts, the feedback voltage Vfb rises to the output voltage VOUT.

[0050] The error amplifier circuit 10 controls the gate voltage of the output transistor M1 so that the feedback voltage Vfb input to the non-inverting input terminal + is equal to the reference voltage Vref of the reference voltage circuit 20 input to the inverting input terminal -. Therefore, the output voltage VOUT is equal to the reference voltage Vref and is stable.

[0051] Therefore, when the bonding wire W3 connected to the voltage adjustment terminal VA of the voltage regulator 1 of the present embodiment is broken, it is possible to suppress an excessive voltage from being generated at the output terminal VOUT.

[0052] In addition, the open-circuit protection circuit does not interfere with the operation of the voltage regulator 1 during normal operation.

[0053] First, before the voltage regulator 1 starts up, since both the output voltage VOUT and the adjustment voltage VADJ are low voltages, the MOS transistor M2 is not turned on.

[0054] Next, when the voltage regulator 1 starts up, as the output voltage VOUT rises, the adjustment voltage VADJ also rises. Therefore, the MOS transistor M2 is not turned on. At this time, the threshold voltage of the MOS transistor M2 only needs to be set to be less than or equal to the voltage drop of the output voltage VOUT at the time of startup.

[0055] Figure 2 FIG. is a circuit diagram showing another example of the open-circuit protection circuit of the voltage regulator 1 of the present embodiment.

[0056] Figure 2 The open-circuit protection circuit includes MOS transistors M2, M3, M4, M5, and M6. The depletion-type MOS transistor M3 serving as a current source is provided between the drain of the MOS transistor 2 and the ground terminal and functions as a pull-down element. The source of the MOS transistor M4 is connected to the ground terminal, and the gate is connected to the drain of the MOS transistor 2. The MOS transistors M5 and M6 form a current mirror circuit, and control the voltage of the gate of the output transistor M1 connected to the output terminal according to the current flowing through the MOS transistor M4 connected to the input terminal.

[0057] The operation when the bonding wire W3 connected to the voltage adjustment terminal VA is broken will be described.

[0058] When the bonding wire W3 connected to the voltage adjustment terminal VA is broken, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal. The error amplifier circuit 10 controls to lower the gate voltage of the output transistor M1 and increase the output voltage VOUT.

[0059] At this time, the MOS transistor M2 conducts when the voltage between the gate and the source becomes equal to or higher than the threshold voltage due to the rise of the output voltage VOUT as the source voltage and the fall of the adjustment voltage VADJ as the gate voltage. When the MOS transistor M2 conducts, the MOS transistor M4, which is pulled down by the current of the MOS transistor M3, conducts due to the rise of the gate voltage. Therefore, the MOS transistor M4 controls the gate voltage of the output transistor M1 to rise via the current mirror circuit of the MOS transistors M5 and M6 and reduces the output voltage VOUT.

[0060] Since the gate voltage is the ground voltage, the MOS transistor M2 turns off when the output voltage VOUT as the source voltage is higher than the threshold voltage. Therefore, the output voltage VOUT stabilizes at a voltage that is higher than the ground voltage by an amount equal to the threshold voltage of the MOS transistor M2.

[0061] Therefore, the voltage regulator 1 of the present embodiment can suppress the generation of an excessive voltage at the output terminal VO when the bonding wire W3 connected to the voltage adjustment terminal VA is broken.

[0062] In addition, the open-circuit protection circuit does not interfere with the operation of the voltage regulator 1 during normal operation.

[0063] First, before the voltage regulator 1 starts up, since both the output voltage VOUT and the adjustment voltage VADJ are low voltages, the MOS transistor M2 is off, and the MOS transistor M4 does not conduct due to the current of the MOS transistor M3.

[0064] Next, when the voltage regulator 1 starts up, as the output voltage VOUT rises, the adjustment voltage VADJ also rises, so the MOS transistor M2 does not conduct. At this time, the threshold voltage of the MOS transistor M2 only needs to be set to be less than or equal to the voltage drop of the output voltage VOUT at startup.

[0065] Figure 3 FIG. [ID] is a circuit diagram showing another example of the open-circuit protection circuit of the voltage regulator 1 of the present embodiment.

[0066] Figure 3 The voltage regulator 1 is configured by connecting the resistor R1 in series with the resistors R1a and R1b in the voltage regulator 1 of [[ID]]. Moreover, the gate of the MOS transistor M2 is connected to the connection point of the resistors R1a and R1b. If the open-circuit protection circuit is configured in this way, the MOS transistor M2 conducts quickly when the bonding wire W3 is broken, so the overshoot of the output voltage VOUT can be suppressed. Figure 2

[0067] Figure 4 FIG. [ID] is a circuit diagram showing another example of the open-circuit protection circuit of the voltage regulator 1 of the present embodiment.​

[0068] Figure 4 The disconnection protection circuit is configured such that in Figure 2 and Figure 3 in the disconnection protection circuit, the MOS transistors M5 and M6 that constitute the current mirror circuit share the active load of the error amplifier circuit 10. If configured in this way, the number of components can be reduced, and thus the voltage regulator 1 can reduce its area.

[0069] As described above, in the voltage regulator 1 according to the present embodiment, since the disconnection protection circuit is included in the voltage adjustment terminal VA, even if the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected, an excessive voltage generated at the output terminal VO of the voltage regulator 1 can be suppressed.

[0070] In addition, the present invention is not directly limited to the above-described embodiment and can be implemented in various ways. Moreover, various omissions, additions, substitutions, or changes can be made without departing from the gist of the invention. These embodiments or their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

[0071] For example, it may be that Figure 3 a plurality of resistors R1 are connected in series, and the gate of the first MOS transistor is connected to an arbitrary connection point of the resistor R1.

Claims

1. A voltage regulator, which receives an input voltage from an input terminal and outputs an output voltage to an output terminal, wherein the voltage regulator comprises: an output transistor, a source connected to the input terminal and a drain connected to the output terminal; A voltage dividing resistor is connected between the voltage adjustment terminal and the ground terminal, divides the adjustment voltage input to the voltage adjustment terminal, and outputs a feedback voltage; A reference voltage circuit outputs a reference voltage; an error amplifier circuit, which controls the gate voltage of the output transistor based on the reference voltage and the feedback voltage; as well as The disconnection protection circuit includes a first metal oxide semiconductor transistor having a source connected to the output terminal and a gate connected to the voltage adjustment terminal, and detects disconnection of a bonding wire of the voltage adjustment terminal.

2. The voltage regulator according to claim 1, characterized in that In the line break protection circuit, The drain of the first metal oxide semiconductor transistor is connected to the output terminal of the voltage dividing resistor. When disconnection of the bonding wire is detected, the output voltage is dropped to the reference voltage.

3. The voltage regulator according to claim 1, characterized in that The line break protection circuit comprises: a current source connected between the drain of the first metal oxide semiconductor transistor and the ground terminal; a second metal oxide semiconductor transistor, a gate of which is connected to the drain of the first metal oxide semiconductor transistor, and a source of which is connected to the ground terminal; and a current mirror circuit, wherein the input terminal is connected to the drain of the second metal oxide semiconductor transistor, and the output terminal is connected to the gate of the output transistor, When disconnection of the bonding wire is detected, the output voltage is dropped to a voltage higher than a ground voltage by an amount corresponding to a threshold voltage of the first metal oxide semiconductor transistor.

4. The voltage regulator according to claim 3, characterized in that: The voltage dividing resistor is formed by connecting a plurality of first resistors in series between the voltage adjustment terminal and an output terminal of the voltage dividing resistor, and the gate of the first metal oxide semiconductor transistor is connected to any connection point of the first resistors.

5. The voltage regulator according to claim 3, characterized in that: The current mirror circuit is configured to be shared with an active load of the error amplifier circuit.

6. A semiconductor device, characterized in that: The input terminal of the voltage regulator according to any one of claims 1 to 5 is connected to an input pin, and the output terminal and the voltage adjustment terminal are connected to an output pin.

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