Low dropout regulator

Abstract

The invention relates to a low dropout regulator. The low-dropout linear voltage regulator comprises a low-dropout linear voltage stabilizing circuit, a variable current source, a first clamping unit and a second clamping unit, and the variable current source is connected with an adjusting tube of the low-dropout linear voltage stabilizing circuit and provides a current signal corresponding to the output current of the adjusting tube; the first clamping unit is connected with the variable current source and used for generating a first internal voltage according to the current signal; the second clamping unit is connected with the first clamping unit and an error amplifying circuit of the low-dropout linear voltage stabilizing circuit, and is used for generating a second internal voltage according to the first internal voltage and providing the second internal voltage to the error amplifying circuit. The power supply rejection ratio and the load regulation rate of the low dropout linear regulator are improved, and the use stability is higher.

Description

Technical Field

[0001] This application relates to the technical field of low-voltage regulation, and particularly to a low-dropout linear regulator. Background Art

[0002] As a commonly used power management chip, a low-dropout linear regulator (LDO) has the advantages of simple structure, low cost, low noise, and simple peripheral circuits, and is widely used in many fields such as medical, computer, industrial infrastructure equipment, and portable products.

[0003] A low-dropout linear regulator generally includes an adjustment transistor, a sampling feedback circuit, and an error amplification circuit. The adjustment transistor is connected between the input terminal and the output terminal. The sampling feedback circuit samples the output voltage and outputs a corresponding feedback voltage to the error amplification circuit. The error amplifier adjusts the conduction degree of the adjustment transistor according to the feedback voltage and the reference voltage, so as to control the current from the input to the output to maintain the stability of the output voltage.

[0004] However, during use, the performance of the low-dropout linear regulator is not ideal, especially the power supply rejection ratio and load regulation rate performance, resulting in low use stability of the low-dropout linear regulator. Summary of the Invention

[0005] Based on this, it is necessary to provide a low-dropout linear regulator that can improve the use stability.

[0006] A low-dropout linear regulator includes:

[0007] A low-dropout linear voltage regulation circuit;

[0008] A variable current source, connected to the adjustment transistor of the low-dropout linear voltage regulation circuit, and providing a current signal;

[0009] A first clamping unit, connected to the variable current source; the first clamping unit is used to generate a first internal voltage according to the current signal;

[0010] A second clamping unit, respectively connected to the first clamping unit and the error amplification circuit of the low-dropout linear voltage regulation circuit; the second clamping unit is used to generate a second internal voltage according to the first internal voltage and provide the second internal voltage to the error amplification circuit.

[0011] In one embodiment, the variable current source includes a sampling transistor; a first pole of the sampling transistor is used to connect to the power input terminal, a control pole of the sampling transistor is connected to the gate of the adjustment transistor, and a second pole of the sampling transistor is connected to the first clamping unit.

[0012] In one embodiment, the sampling transistor has the same type as the regulating transistor.

[0013] In one embodiment, the first clamping unit includes n clamping transistors; the first pole and the control pole of the same clamping transistor are connected, the first pole of the first clamping transistor is connected to the second pole of the sampling transistor, the second pole of the (n - 1)-th clamping transistor is connected to the first pole of the n-th clamping transistor, and the second pole of the n-th clamping transistor is grounded.

[0014] In one embodiment, the clamping transistors are all NMOS transistors.

[0015] In one embodiment, the second clamping unit includes a first transistor; the first pole of the first transistor is used to connect to the power input terminal, the control pole of the first transistor is connected to the first clamping unit, and the second pole of the first transistor is used to connect to the error amplification circuit.

[0016] In one embodiment, the first transistor is an NMOS transistor.

[0017] In one embodiment, the low dropout linear voltage regulator circuit further includes a sampling feedback circuit; wherein,

[0018] the first pole of the regulating transistor is used to connect to the power input terminal, and the second pole of the regulating transistor is used to connect to the power output terminal;

[0019] the sampling feedback circuit is connected to the power output terminal, and the sampling feedback circuit is used to sample the output voltage of the power output terminal and output a feedback voltage;

[0020] the error amplification circuit is connected to the sampling feedback circuit and the control pole of the regulating transistor; the error amplification circuit is used to adjust the voltage of the control pole of the regulating transistor according to the feedback voltage output by the sampling feedback circuit so as to adjust the output voltage of the power output terminal.

[0021] In one embodiment, the error amplification circuit includes:

[0022] an error comparison unit, the error comparison unit is used to connect to the second clamping unit, and the error comparison unit is also connected to the sampling feedback circuit; the error comparison unit is used to generate a reference current according to the second internal voltage provided by the second clamping unit, and is also used to obtain a feedback current according to the feedback voltage, and output an error adjustment voltage according to the reference current and the feedback current;

[0023] a driving unit, connected to the error comparison unit and the control pole of the regulating transistor; the driving unit is used to adjust the voltage of the control pole of the regulating transistor according to the error adjustment voltage.

[0024] In one embodiment, the error comparison unit includes a second transistor and a third transistor; a first pole of the second transistor is used to connect to the second clamping unit, a control pole and a second pole of the second transistor are connected to a first pole of the third transistor; a second pole of the third transistor is grounded, and a control pole of the third transistor is connected to the sampling feedback circuit; the first pole of the third transistor is further connected to the driving unit.

[0025] In one embodiment, the driving unit includes a fourth transistor and a fifth transistor; a first pole of the fourth transistor is used to connect to a power input terminal, a control pole and a second pole of the fourth transistor are connected to a control pole of the regulating transistor, and the second pole of the fourth transistor is further connected to a first pole of the fifth transistor; a second pole of the fifth transistor is grounded, and a control pole of the fifth transistor is connected to the first pole of the third transistor.

[0026] In one embodiment, the sampling feedback circuit includes a first sampling resistor and a second sampling resistor; a first end of the first sampling resistor is connected to the power output terminal, and a second end of the first sampling resistor is grounded through the second sampling resistor; wherein, a common terminal where the first sampling resistor and the second sampling resistor are connected is connected to the error amplification circuit.

[0027] For the above low dropout linear regulator, the variable current source outputs a current signal corresponding to the current of the regulating transistor, so that the first clamping unit generates a first internal voltage corresponding to the current signal, and then the second clamping unit outputs a second internal voltage according to the first internal voltage. Since the first internal voltage corresponds to the current of the regulating transistor, the power supply voltage provided to the error amplification circuit corresponds to the current of the regulating transistor and does not change with the change of the input power supply. Thus, the ability of the low dropout linear voltage regulation circuit to suppress the fluctuation of the input power supply can be enhanced, and the power supply rejection ratio performance of the low dropout linear regulator can be improved. In addition, since the output current of the regulating transistor is the load current, the power supply voltage provided to the error amplification circuit corresponds to the load current, so that the load current can be offset during the cooperation process of the error amplification circuit and the regulating transistor, thereby reducing the influence of the load current on the output voltage and improving the load regulation rate performance of the low dropout linear regulator. Therefore, the low dropout linear regulator with improved power supply rejection ratio and load regulation rate performance has higher use stability. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 Schematic diagram of a module of a low dropout linear regulator for an embodiment;

[0030] Figure 2 Circuit schematic diagram of a low dropout linear regulator for an embodiment;

[0031] Figure 3 Schematic diagram of the circuit structure of a low dropout linear regulator for another embodiment. Detailed implementation manners

[0032] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It can be understood that the terms "first", "second", etc. used in this application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0035] It can be understood that in the following embodiments, "connection", if there is an electrical signal or data transfer between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0036] It can be understood that "at least one" means one or more, and "a plurality" means two or more. "At least part of an element" means part or all of the element.

[0037] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0038] In one embodiment, a low dropout linear regulator is provided. As Figure 1 shown, the low dropout linear regulator includes a low dropout linear voltage regulation circuit 100. The low dropout linear voltage regulation circuit 100 is used to convert the input power supply VDD connected to the power input terminal into a stable output voltage Vout, while maintaining a small input-output voltage difference (i.e., low dropout).

[0039] Among them, the low dropout linear voltage regulation circuit 100 includes an adjustment transistor P1. The first pole of the adjustment transistor P1 is used to connect to the power input terminal, and the second pole of the adjustment transistor P1 is used to connect to the power output terminal. When the voltage of the control pole of the adjustment transistor P1 changes, its conduction degree changes, thereby adjusting the output voltage Vout.

[0040] The type of the adjustment transistor P1 can be selected according to specific circumstances. In some embodiments, the adjustment transistor P1 is a PMOS (P-channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor field effect transistor). Further, the adjustment transistor P1 is an enhancement-mode PMOS transistor. Among them, the gate of the PMOS transistor serves as the control pole, the source serves as the first pole, and the drain serves as the second pole.

[0041] The low dropout linear voltage regulation circuit 100 further includes a sampling feedback circuit 110. The sampling feedback circuit 110 is connected to the power output terminal and is used to sample the output voltage Vout of the power output terminal and output a feedback voltage VFB.

[0042] Since fluctuations in the input power supply VDD or changes in the load may affect the output voltage Vout, sampling the output voltage Vout to obtain a feedback voltage VFB corresponding to the output voltage Vout and adjusting the subsequent output voltage Vout according to the feedback voltage VFB can keep the output voltage Vout stable.

[0043] The low dropout linear voltage regulator circuit 100 further includes an error amplifier circuit 120. The error amplifier circuit 120 is connected to the sampling feedback circuit 110 to receive the feedback voltage VFB output by the sampling feedback circuit 110. The error amplifier circuit 120 is also connected to the gate of the adjustment transistor P1. The error amplifier circuit 120 is configured to adjust the voltage of the control electrode of the adjustment transistor P1 according to the feedback voltage VFB, so as to adjust the output voltage Vout of the power supply output terminal, thereby keeping the output voltage Vout stable.

[0044] In the low dropout linear voltage regulator circuit 100, the error amplifier circuit 120 is combined with the sampling feedback circuit 110 to achieve the purpose of feedback adjusting the adjustment transistor P1 according to the output voltage Vout, thereby keeping the output voltage Vout stable. A separate reference source does not need to be set in this circuit, and the circuit structure is simple, which is beneficial to reducing the circuit area cost and power consumption.

[0045] In some embodiments, such as Figure 2 shown, the sampling feedback circuit 110 includes a first sampling resistor RFB1 and a second sampling resistor RFB2. The first end of the first sampling resistor RFB1 is connected to the power supply output terminal, and the second end of the first sampling resistor RFB1 is grounded through the second sampling resistor RFB2. Wherein, the common end where the first sampling resistor RFB1 and the second sampling resistor RFB2 are connected is connected to the error amplifier circuit 120.

[0046] The resistance values of the first sampling resistor RFB1 and the second sampling resistor RFB2 can be set according to specific situations. The first sampling resistor RFB1 and the second sampling resistor RFB2 are connected in series between the power supply output terminal and the ground terminal, and the feedback voltage VFB is output after voltage division. The sampling feedback circuit 110 adopts a voltage division structure, and the circuit structure is simple and easy to implement.

[0047] In some embodiments, the error amplifier circuit 120 includes an error comparison unit 121. The error comparison unit 121 is configured to be connected to the second clamping unit 400, and the error comparison unit 121 is also connected to the sampling feedback circuit 110. The error comparison unit 121 is configured to generate a reference current according to the second internal voltage VDD2 provided by the second clamping unit 400, and is also configured to obtain a feedback current according to the feedback voltage VFB, and output an error adjustment voltage VEAOUT according to the reference current and the feedback current.

[0048] It should be noted that in the related art, a low dropout linear voltage regulator needs to separately set a reference source for providing a reference voltage, so that the error amplifier circuit generates an error adjustment voltage according to the reference voltage and the feedback voltage.

[0049] In this embodiment, the error comparison unit 121 can generate a reference current corresponding to a reference voltage, obtain a feedback current based on the feedback voltage VFB, and generate an error adjustment voltage VEAOUT. Thus, it is no longer necessary to separately set a reference source, significantly saving the circuit cost of the low-dropout linear regulator and reducing power consumption.

[0050] The error amplification circuit 120 further includes a driving unit 122, and the driving unit 122 is connected to the control electrode of the error comparison unit 121 and the adjustment transistor P1. The driving unit 122 is configured to adjust the voltage of the gate of the adjustment transistor P1 according to the error adjustment voltage VEAOUT output by the error comparison unit 121.

[0051] The driving unit 122 controls the conduction state of the adjustment transistor P1 connected between the power input terminal and the power output terminal according to the change of the error adjustment voltage VEAOUT, and then adjusts the output voltage Vout, thereby realizing circuit voltage regulation.

[0052] In some embodiments, the error comparison unit 121 includes a second transistor DN1 and a third transistor N1. The first pole of the second transistor DN1 is used to connect to the second clamping unit 400, the control electrode and the second pole of the second transistor DN1 are connected to the first pole of the third transistor N1; the second pole of the third transistor N1 is grounded, and the control electrode of the third transistor N1 is connected to the sampling feedback circuit 110; the first pole of the third transistor N1 is also connected to the driving unit 122.

[0053] Among them, the types of the second transistor DN1 and the third transistor N1 can be selected according to specific circumstances. Exemplarily, both the second transistor DN1 and the third transistor N1 are NMOS (N-channel Metal Oxide Semiconductor, N-channel metal oxide semiconductor field effect transistor). Further, the second transistor DN1 is a depletion-type NMOS transistor, and the third transistor N1 is an enhancement-type NMOS transistor. Among them, the gate of the NMOS transistor is used as the control electrode, the drain is used as the first pole, and the source is used as the second pole.

[0054] In this embodiment, for the depletion-type second transistor DN1, the gate and the source are short-circuited to form a current source, and the current generated by this current source is the reference current.

[0055] The drain of the third transistor N1 is connected to the source of the second transistor DN1, and the source of the third transistor N1 is grounded. When the current flowing through the third transistor N1 is the reference current, the voltage Vgs between the gate and the source of the third transistor N1 is the reference voltage.

[0056] It can be understood that in practical applications, the voltage of the gate of the third transistor N1 is the feedback voltage VFB. Since the output voltage , where RFB1 represents the resistance value of the first sampling resistor RFB1, RFB2 represents the resistance value of the second sampling resistor RFB2, and VFB represents the feedback voltage. Therefore, the reference current and reference voltage of the error comparison unit 121 branch can be determined according to the second transistor DN1. Furthermore, by reasonably setting the resistance values of the first sampling resistor RFB1 and the second sampling resistor RFB2, the required output voltage VOUT can be determined.

[0057] After the low-dropout linear voltage regulator circuit 100 starts to operate, when the output voltage VOUT fluctuates, the feedback voltage VFB fed back by the sampling feedback circuit 110 changes accordingly, so that the corresponding error adjustment voltage VEAOUT can be obtained. Specifically, when the output voltage VOUT decreases, the feedback voltage VFB decreases accordingly, and the current of the third transistor N1 (i.e., the feedback current) decreases and is less than the reference current of the second transistor DN1. At this time, the error adjustment voltage VEAOUT increases. When the output voltage VOUT increases, the feedback voltage VFB increases accordingly, and the current of the third transistor N1 increases and is greater than the reference current of the second transistor DN1. At this time, the error adjustment voltage VEAOUT decreases.

[0058] In this embodiment, the second transistor DN1 generates a fixed reference current. At the same time, the third transistor N1 generates a corresponding changing feedback current according to the received feedback voltage VFB, so that the error adjustment voltage VEAOUT is obtained according to the feedback current and the reference current, enabling the driving unit 122 to dynamically regulate the regulating transistor P1 according to the error adjustment voltage VEAOUT to achieve stable output of the circuit. The second transistor DN1 and the third transistor N1 in the error comparison unit 121 achieve the dual functions of determining the reference voltage and error comparison. The circuit structure is simple, the cost is low, and the cost of the low-dropout linear voltage regulator can be effectively reduced.

[0059] In some embodiments, the driving unit 122 includes a fourth transistor P2 and a fifth transistor N2. The first pole of the fourth transistor P2 is used to connect to the power input terminal. The control pole and the second pole of the fourth transistor P2 are connected to the gate of the regulating transistor P1, and the second pole of the fourth transistor P2 is also connected to the first pole of the fifth transistor N2. The second pole of the fifth transistor N2 is grounded, and the control pole of the fifth transistor N2 is connected to the first pole of the third transistor N1.

[0060] The types of the fourth transistor P2 and the fifth transistor N2 can be selected according to specific situations. Exemplarily, the fourth transistor P2 is a PMOS transistor of the same type as the regulating transistor P1, and the fifth transistor N2 is an NMOS transistor. Further, both the fourth transistor P2 and the fifth transistor N2 are enhancement-type MOS transistors.

[0061] In this embodiment, the fourth transistor P2 is of the same type as the regulating transistor P1 and is dimensionally matched, so as to form a current mirror with the regulating transistor P1 to copy the output current of the regulating transistor P1.

[0062] The gate of the fifth transistor N2 is connected to the drain of the third transistor N1. When the output voltage VOUT decreases, the error adjustment voltage VEAOUT increases, that is, the gate voltage of the fifth transistor N2 increases, and the conduction degree of the fifth transistor N2 increases, so that the gate voltage VGATE of the regulating transistor P1 decreases, and further the output voltage VOUT increases. Conversely, if the sampling voltage VFB is higher than the reference voltage, the gate voltage of the fifth transistor N2 decreases, that is, the error adjustment voltage VEAOUT decreases, the gate voltage VGATE of the regulating transistor P1 increases, and further the output voltage VOUT decreases. Thus, the purpose of stabilizing the output voltage VOUT is achieved, and the circuit structure is simple and the circuit cost is low.

[0063] In actual implementation, the structure of the driving unit 122 can also be adjusted according to actual needs. For example, the fourth transistor P2 in the driving unit 122 can also be replaced by a current source, and the current source is used as the load of the fifth transistor N2. In some embodiments, devices such as a buffer can also be added to the driving unit 122.

[0064] It should be noted that in the low dropout linear regulator of the related art, the error amplifier circuit is directly connected to the power input terminal. Since the input power supply VDD provided by the power input terminal directly supplies power to the error amplifier circuit, the fluctuation of the input power supply VDD will affect the low dropout linear voltage regulation loop, resulting in poor PSRR (Power Supply Rejection Ratio) performance.

[0065] In addition, the power output terminal is used to connect a load, and the load current is equal to the current flowing through the regulating transistor (the current of the sampling circuit is usually in the microampere level, which is very small compared with the load current and can be ignored). As the load current changes, the current flowing through the regulating transistor P1 also changes by the same amplitude, resulting in a change in the output voltage VOUT, and the load regulation (LOADREG) performance of the low dropout linear regulator is low.

[0066] Based on this, in the technical solution of this application, the low dropout linear regulator further includes a variable current source 200. The variable current source 200 is used to connect to the regulating transistor P1 of the low dropout linear voltage regulation circuit 100 and provide a current signal.

[0067] Among them, the current signal provided by the variable current source 200 corresponds to the output current of the regulating transistor P1. The variable current source 200 is used to sample the output current of the regulating transistor P1. That the current signal output by the variable current source 200 corresponds to the output current of the regulating transistor P1 can mean that the current signal output by the variable current source 200 is proportional to the output current of the regulating transistor P1. Since the load current is equal to the output current flowing through the regulating transistor P1, therefore, the current signal output by the variable current source 200 corresponds to the load current, and the current signal output by the variable current source 200 is proportional to the load current.

[0068] The low dropout linear regulator further includes a first clamping unit 300. The first clamping unit 300 is connected to the variable current source 200 and is used to generate a first internal voltage VDD1 according to the current signal.

[0069] The magnitude of the first internal voltage VDD1 corresponds to the current signal output by the variable current source 200, that is, corresponds to the load current. However, the first internal voltage VDD1 is not related to the input power supply VDD. Therefore, when the input power supply VDD fluctuates, the first internal voltage VDD1 will not change following the input power supply VDD.

[0070] The low dropout linear regulator further includes a second clamping unit 400. The second clamping unit 400 is respectively connected to the first clamping unit 300 and the error amplification circuit 120. The second clamping unit 400 is used to generate a second internal voltage VDD2 according to the first internal voltage VDD1.

[0071] Since the second internal voltage VDD2 is obtained based on the first internal voltage VDD1, the second internal voltage VDD2 corresponds to the load current. At the same time, the second internal voltage VDD2 is not affected by the input power supply VDD.

[0072] The second clamping unit 400 is further used to provide the second internal voltage VDD2 to the error amplification circuit 120. Specifically, the second clamping unit 400 provides the second internal voltage VDD2 to the second transistor DN1 in the error amplification circuit 120.

[0073] By supplying a second internal voltage VDD2 to the second transistor DN1, the supply voltage of the second transistor DN1 can be made independent of the variation of the input power supply VDD, and the voltage between the drain and source of the second transistor DN1 is not affected by the input power supply VDD. Thereby, the influence of the input power supply VDD on the low dropout linear regulator circuit 100 is reduced, and thus the power supply rejection ratio performance of the low dropout linear regulator is improved. Moreover, the supply voltage of the error comparison unit 121 corresponds to the load current, and the load current can be introduced into the low dropout linear regulator circuit 100. During the cooperation of the devices in the adjustment transistor P1, the error comparison unit 121, and the driving unit 122, the load current is cancelled out. Thereby, the influence of the output voltage VOUT on the variation of the load current is reduced, and the load regulation performance of the low dropout linear regulator is improved.

[0074] For the above-mentioned low dropout linear regulator, the variable current source 200 outputs a current signal corresponding to the current of the adjustment transistor P1, enabling the first clamping unit 300 to generate a first internal voltage VDD1 corresponding to the current signal, and then the second clamping unit 400 outputs a second internal voltage VDD2 according to the first internal voltage VDD1. Since the first internal voltage VDD1 corresponds to the current of the adjustment transistor P1, the supply voltage provided to the error amplification circuit 120 corresponds to the current of the adjustment transistor P1 and does not change with the variation of the input power supply VDD. Thus, the ability of the low dropout linear regulator circuit 100 to suppress the fluctuation of the input power supply can be enhanced, and the power supply rejection ratio performance of the low dropout linear regulator is improved. In addition, since the output current of the adjustment transistor P1 is the load current, the supply voltage provided to the error amplification circuit 120 corresponds to the load current, enabling the load current to be cancelled out during the cooperation of the error amplification circuit 120 and the adjustment transistor P1. Thereby, the influence of the load current on the output voltage is reduced, and the load regulation performance of the low dropout linear regulator is improved. Thus, the low dropout linear regulator with improved power supply rejection ratio and load regulation performance has higher use stability.

[0075] In some embodiments, as Figure 3 shown, the variable current source 200 includes a sampling transistor P3. The first pole of the sampling transistor P3 is used to connect to the power input terminal, the control pole of the sampling transistor P3 is used to connect to the gate of the adjustment transistor P1, and the second pole of the sampling transistor P3 is connected to the first clamping unit 300.

[0076] The sampling transistor P3 is used to sample the current of the adjustment transistor P1 and output a current signal corresponding to the output current of the adjustment transistor P1. This current signal is not related to the magnitude of the input power supply VDD connected to the power input terminal, such that the subsequent first internal voltage VDD1 and second internal voltage VDD2 obtained based on this current signal are not affected by the input power supply VDD.

[0077] In actual implementation, the type of the sampling transistor P3 can be set with reference to the regulating transistor P1. In some embodiments, the sampling transistor P3 and the regulating transistor P1 are MOS transistors of the same type. When the regulating transistor P1 is a PMOS transistor, the sampling transistor P3 is a PMOS transistor with a size matching that of the regulating transistor P1. Thus, the sampling transistor P3 and the regulating transistor P1 form a current mirror structure, and the sampling transistor P3 outputs a current signal proportional to the output current of the regulating transistor P1.

[0078] Specifically, the current signal output by the sampling transistor P3 . Among them, , (W / L) P3 represents the aspect ratio of the sampling transistor P3, (W / L) P1 represents the aspect ratio of the regulating transistor P1, and IOUT represents the output current of the regulating transistor P1.

[0079] Thus, the proportional relationship between the current signal and the load current can be ensured, so that in the process of cooperation among various devices in the subsequent circuit, the load current can be better canceled, and the influence of the load current on the output voltage VOUT can be reduced.

[0080] In some embodiments, the first clamping unit 300 includes n clamping transistors. The first pole and the control pole of the same clamping transistor are connected. The first pole of the first clamping transistor is connected to the second pole of the sampling transistor P3. The second pole of the (n - 1)th clamping transistor is connected to the first pole of the nth clamping transistor. The second pole of the nth clamping transistor is grounded.

[0081] Among them, n is an integer greater than or equal to 2, and the specific value of n and the type of the clamping transistor can be set according to specific circumstances. For example, the clamping transistor can be an enhancement-type NMOS transistor, a PMOS transistor, or other transistors with a clamping function.

[0082] In a specific embodiment, as Figure 3 shown, the first clamping unit 300 includes two NMOS transistors, namely the clamping transistor N3 and the clamping transistor N4. The gate and the drain of the clamping transistor N3 are both connected to the drain of the sampling transistor P3. The gate and the drain of the clamping transistor N4 are both connected to the source of the clamping transistor N3. The source of the clamping transistor N4 is grounded.

[0083] In this embodiment, the clamping transistor N3 and the clamping transistor N4 receive the current signal output by the sampling transistor P3. The first internal voltage VDD1 obtained according to the current signal is equal to the sum of the voltage VGS3 between the gate and the source of the clamping transistor N3 and the voltage VGS4 between the gate and the source of the clamping transistor N4, that is, VDD1 = VGS3 + VGS4. Further derivation can obtain:

[0084] VDD1 = VGS3 + VGS4

[0085]

[0086]

[0087] / L) N4}^0.5。

[0088] Wherein, VTH N3 represents the threshold voltage of the clamping transistor N3, and VTH N4 represents the threshold voltage of the clamping transistor N4; un represents the electron mobility, and cox represents the oxide capacitance; (W / L) N3 represents the width-to-length ratio of the clamping transistor N3, and (W / L) N4 represents the width-to-length ratio of the clamping transistor N4.

[0089] It can be seen from the formula that the first internal voltage VDD1 is not related to the input power supply VDD. Therefore, when the input power supply VDD fluctuates, the first internal voltage VDD1 will not be affected, thereby improving the power supply rejection ratio performance of the low-dropout linear regulator.

[0090] In this embodiment, by setting two NMOS transistors and diode-connecting the clamping transistor N3 and the clamping transistor N4, a first internal voltage VDD1 of about 1.4V can be obtained. In actual implementation, the required number of clamping transistors, such as three or more clamping transistors, can be set according to the specific parameters of the input power supply VDD and the low-dropout linear voltage regulation circuit 100.

[0091] In some embodiments, the first clamping unit 300 may include a zener diode, which is connected between the sampling transistor P3 and the ground and is used to provide the required first internal voltage VDD1 to the second clamping unit 400. The zener diode has a voltage regulation characteristic, which can make the first internal voltage VDD1 stable and reliable, thereby enhancing the reliability of the circuit.

[0092] In some embodiments, the second clamping unit 400 includes a first transistor DN2. The first pole of the first transistor DN2 is used to connect to the power input terminal, the control pole of the first transistor DN2 is connected to the first clamping unit 300, and the second pole of the first transistor DN2 is used to connect to the error amplification circuit 120.

[0093] The first transistor DN2 is used to obtain a second internal voltage VDD2 according to the first internal voltage VDD1 and output the second internal voltage VDD2 to the second transistor DN1, so as to make the power supply voltage of the second transistor DN1 stable and not affected by the input power supply VDD.

[0094] The type and quantity of the first transistor DN2 can be set according to specific circumstances. In some embodiments, the first transistor DN2 is an NMOS transistor. Further, the first transistor DN2 is a depletion-type NMOS transistor.

[0095] It can be understood that the second internal voltage VDD2 is the voltage VGS between the gate and source of the first internal voltage VDD1 and the first transistor DN2, DN2 i.e., VDD2 = VDD1 - VGS DN2 , and further derivation can obtain:

[0096] VDD2 = VDD1 - VGS DN2

[0097] / L) N4}^0.5 - VGS DN2 .

[0098] It can be seen that the second internal voltage VDD2 is not related to the input power supply VDD, so it will not change with the fluctuation of the input power supply VDD. Therefore, the power supply of the low-dropout linear voltage regulator circuit 100 is stable, and the power supply rejection ability is improved.

[0099] Further, the current flowing through the fourth transistor P2 , where K2 = (W / L) P2 / (W / L) P1 , (W / L) P2 represents the aspect ratio of the fourth transistor P2.

[0100] The current I flowing through the fifth transistor N2 N2 is:

[0101] , where (W / L) N2 represents the aspect ratio of the fifth transistor N2, un represents the electron mobility, cox represents the gate oxide capacitance per unit area, VTH N2 represents the threshold voltage of the fifth transistor N2, and VEAOUT represents the error adjustment voltage.

[0102] The error adjustment voltage VEAOUT is:

[0103] .

[0104] The voltage VDS between the drain and source of the second transistor DN1 DN1 is: VDS DN1 = VDD2 - VEAOUT, so it can be obtained:

[0105]

[0106] 。

[0107] Since it can be derived that: , where VTH N1 represents the threshold voltage of the third transistor N1, VDS DN1 represents the voltage between the drain and source of the second transistor DN1, λ represents the channel length modulation coefficient, (W / L) DN1 represents the width-to-length ratio of the second transistor DN1, (W / L) N1 represents the width-to-length ratio of the third transistor N1.

[0108] Therefore, it can be obtained that:

[0109]

[0110] 。

[0111] From the above derivation, it can be seen that by designing appropriate values of K1 and K2, the load current IOUT term in the voltage VDS DN1 between the drain and source of the second transistor DN1 can be canceled, and then the load current IOUT term in the output voltage VOUT disappears, thereby improving the variation of the output voltage VOUT with the load current IOUT and enhancing the load regulation performance of the circuit.

[0112] To better understand the above embodiments, the following will be explained in detail in conjunction with an optional embodiment. Please refer to Figure 3 , in one embodiment, the low dropout linear regulator includes a low dropout linear voltage regulation circuit 100, a variable current source 200, a first clamping unit 300, and a second clamping unit 400. The low dropout linear voltage regulation circuit 100 includes an adjustment transistor P1, a sampling feedback circuit 110, an error comparison unit 121, and a driving unit 122. Among them, the sampling feedback circuit 110 includes a first sampling resistor RFB1 and a second sampling resistor RFB2; the error comparison unit 121 includes a second transistor DN1 and a third transistor N1, the second transistor DN1 is a depletion-type NMOS transistor, and the third transistor N1 is an enhancement-type NMOS transistor; the driving unit 122 includes a fourth transistor P2 and a fifth transistor N2; the fourth transistor P2 is an enhancement-type PMOS transistor, and the fifth transistor N2 is an enhancement-type NMOS transistor.

[0113] The variable current source 200 includes a sampling transistor P3, which is a PMOS transistor of the same type and size-matched with the adjustment transistor P1. The first clamping unit 300 includes a clamping transistor N3 and a clamping transistor N4, both of which are enhancement-mode NMOS transistors. The second clamping unit 400 includes a first transistor DN2, which is a depletion-mode NMOS transistor.

[0114] In the low-dropout linear voltage regulation loop, the common-source amplifier composed of the second transistor DN1 and the third transistor N1 serves as the first stage of the loop, and the common-source amplifier composed of the fifth transistor N2 and the fourth transistor P2 serves as the second stage of the loop to provide drive for the adjustment transistor P1, and the adjustment transistor P1 serves as the third stage of the loop.

[0115] Specifically, the current I DN1 of the second transistor DN1 and the current I N1 of the third transistor N1 can be expressed as the following formulas:

[0116] ; (1)

[0117] ; (2)

[0118] where, (W / L) DN1 represents the width-to-length ratio of the second transistor DN1, (W / L) N1 represents the width-to-length ratio of the third transistor N1, VTH DN1 represents the threshold voltage of the second transistor DN1, VTH N1 represents the threshold voltage of the third transistor N1, un represents the electron mobility, cox represents the gate oxide capacitance per unit area, and VFB represents the feedback voltage.

[0119] When the current I DN1 of the second transistor DN1 and the current I N1 of the third transistor N1 are equal, the formula (3) can be obtained:

[0120] I DN1 = I N1 ; (3)

[0121] From formulas (1), (2), and (3), we can get:

[0122] ; (4)

[0123] Furthermore, the expression of the output voltage VOUT can be obtained:

[0124]

[0125] Therefore, in the low dropout linear regulator circuit 100, the depletion transistor (the second transistor) DN1 can determine the current of the error comparison unit 121 branch, and then determine the gate voltage of the third transistor N1 (i.e., the feedback voltage VFB). Furthermore, by reasonably setting the first sampling resistor RFB1 and the second sampling resistor RFB2, the expected output voltage VOUT can be obtained.

[0126] The sampling transistor P3 samples the current of the adjustment transistor P1, and the current flowing through the sampling transistor P3 , where K1 = (W / L) P3 / (W / L) P1 , and IOUT represents the output current of the adjustment transistor P1, that is, the load current.

[0127] The first internal voltage VDD1 can be expressed by the following formula (5):

[0128] VDD1 = VGS3 + VGS4

[0129]

[0130]

[0131] }^0.5; (6)

[0132] The second internal voltage VDD2 can be expressed by the following formula (7):

[0133] VDD2 = VDD1 - VGS DN2

[0134] / L) N4}^0.5 - VGS DN2 ; (7)

[0135] It can be seen that the first internal voltage VDD1 generates the second internal voltage VDD2 through DN1 acting as a source follower, and VDD2 = VDD1 - VGS DN2 . The second internal voltage VDD2 does not change with the change of the input power supply VDD, so the power supply of the first stage of the loop is stable, and therefore its PSRR performance is improved.

[0136] Considering the channel length modulation effect of the second transistor DN1, the following formula can be obtained:

[0137] ; (8)

[0138] Combining formulas (2)-(3), we can get:

[0139] ; (9)

[0140] The current flowing through the fourth transistor P2 , where K2 = (W / L) P2 / (W / L) P1 , (W / L) P2 represents the aspect ratio of the fourth transistor P2. The current I N2 flowing through the fifth transistor N2 can be expressed by the following formula (10):

[0141] ; (10)

[0142] where, (W / L) N2 represents the aspect ratio of the fifth transistor N2, un represents the electron mobility, cox represents the gate oxide capacitance per unit area, VTH N2 represents the threshold voltage of the fifth transistor N2, and VEAOUT represents the error adjustment voltage.

[0143] The error adjustment voltage VEAOUT can be expressed by the following formula (11):

[0144] ; (11)

[0145] Therefore, the voltage VDS DN1 between the drain and source of the second transistor DN1 can be expressed by the following formula (12)

[0146] VDS DN1 = VDD2 - VEAOUT; (12), from the above formula, it can be obtained that:

[0147]

[0148]

[0149] .

[0150] Combining formula (9), it can be known that:

[0151]

[0152] .

[0153] Thus, it can be seen that by designing appropriate values of K1 and K2, the load current IOUT term in the voltage VDSDN1 between the drain and source of the second transistor DN1 can be cancelled, and then the load current IOUT term in the output voltage VOUT disappears. Therefore, the output voltage VOUT does not change with the change of the load current IOUT, that is, good LOADREG performance is achieved.

[0154] In the description of this specification, the descriptions referring to terms such as "some embodiments" and "other embodiments" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0155] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0156] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: Low voltage drop linear voltage regulator circuit; A variable current source connected to the adjustment tube of the low voltage difference linear voltage regulator circuit and providing a current signal; A first clamping unit, connected to the variable current source; The first clamping unit is used to generate a first internal voltage according to the current signal; A second clamping unit, connected to the first clamping unit and the error amplifier circuit of the low voltage difference linear voltage stabilization circuit respectively; The second clamping unit is used for generating a second internal voltage according to the first internal voltage, and providing the second internal voltage to the error amplifying circuit.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The variable current source comprises a sampling transistor; a first electrode of the sampling transistor is used to connect to a power input terminal, a control electrode of the sampling transistor is connected to a gate of the adjustment tube, and a second electrode of the sampling transistor is connected to the first clamping unit.

3. The low voltage dropout linear regulator according to claim 2, characterized in that: The sampling transistor and the adjustment transistor are of the same type.

4. The low voltage dropout linear regulator according to claim 2, characterized in that: The first clamping unit includes n clamping transistors; the first electrode of the same clamping transistor is connected to the control electrode, the first electrode of the first clamping transistor is connected to the second electrode of the sampling transistor, the second electrode of the n-1th clamping transistor is connected to the first electrode of the nth clamping transistor, and the second electrode of the nth clamping transistor is grounded.

5. The low voltage dropout linear regulator according to claim 4, characterized in that: The clamping transistors are all NMOS transistors.

6. The low voltage dropout linear regulator according to claim 2, characterized in that: The second clamping unit includes a first transistor; a first electrode of the first transistor is used to connect to a power input terminal, a control electrode of the first transistor is connected to the first clamping unit, and a second electrode of the first transistor is used to connect to the error amplifier circuit.

7. The low voltage dropout linear regulator according to claim 6, characterized in that: The first transistor is an NMOS transistor.

8. The low voltage dropout linear regulator according to any one of claims 1 to 7, characterized in that: The low voltage difference linear voltage regulator circuit also includes a sampling feedback circuit; wherein, The first electrode of the adjustment tube is used to connect to the power input terminal, and the second electrode of the adjustment tube is used to connect to the power output terminal; The sampling feedback circuit is connected to the power supply output end, and the sampling feedback circuit is used to sample the output voltage of the power supply output end and output a feedback voltage; The error amplifier circuit is connected to the sampling feedback circuit and the control electrode of the adjustment tube; the error amplifier circuit is used to adjust the voltage of the control electrode of the adjustment tube according to the feedback voltage output by the sampling feedback circuit to adjust the output voltage of the power supply output end.

9. The low voltage dropout linear regulator according to claim 8, characterized in that: The error amplification circuit comprises: an error comparison unit, the error comparison unit being connected to the second clamping unit and further connected to the sampling feedback circuit; the error comparison unit being used to generate a reference current according to a second internal voltage provided by the second clamping unit, and being used to obtain a feedback current according to the feedback voltage, and outputting an error adjustment voltage according to the reference current and the feedback current; A driving unit is connected to the error comparison unit and the control electrode of the adjustment tube; the driving unit is used to adjust the voltage of the control electrode of the adjustment tube according to the error adjustment voltage.

10. The low voltage dropout linear regulator according to claim 9, characterized in that: The error comparison unit includes a second transistor and a third transistor; the first electrode of the second transistor is used to connect to the second clamping unit, and the control electrode and the second electrode of the second transistor are connected to the first electrode of the third transistor; the second electrode of the third transistor is grounded, and the control electrode of the third transistor is connected to the sampling feedback circuit; the first electrode of the third transistor is also connected to the driving unit.

11. The low voltage dropout linear regulator according to claim 10, characterized in that: The driving unit includes a fourth transistor and a fifth transistor; the first electrode of the fourth transistor is used to connect to the power input terminal, the control electrode and the second electrode of the fourth transistor are connected to the control electrode of the adjustment tube, and the second electrode of the fourth transistor is also connected to the first electrode of the fifth transistor; the second electrode of the fifth transistor is grounded, and the control electrode of the fifth transistor is connected to the first electrode of the third transistor.

12. The low voltage dropout linear regulator according to claim 8, characterized in that: The sampling feedback circuit includes a first sampling resistor and a second sampling resistor; a first end of the first sampling resistor is connected to the power supply output end, and a second end of the first sampling resistor is grounded through the second sampling resistor; wherein a common end where the first sampling resistor and the second sampling resistor are connected is connected to the error amplifier circuit.

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