Reference voltage generating circuit

Abstract

The invention discloses a reference voltage generation circuit, and a band-gap reference circuit of the reference voltage generation circuit uses the voltage and current characteristics of NPN transistors to add the base-emitter voltage of triodes and the base-emitter voltage difference of a fourth NPN transistor and a ninth NPN transistor in proportion to obtain a reference voltage irrelevant to temperature; a twelfth NPN triode is introduced into the band-gap reference circuit, and a base-emitter voltage difference value of a transistor can be copied to the two ends of a fifth resistor in proportion by adjusting the proportion of a first resistor and a second resistor, so that the circuit can normally work under low voltage; meanwhile, the base-emitter voltage difference value of the two NPN transistors is expressed by the voltage dropped on the first resistor and the second resistor, an operational amplifier does not need to be introduced, and the area and the power consumption of the circuit are saved; in addition, the divider resistor string at the output end of the circuit can generate any voltage lower than the reference voltage, and the requirements of the chip for different reference voltages are met.

Description

Technical Field

[0001] The present invention relates to the design technology of chip analog integrated circuits, and particularly to a reference voltage generation circuit. Background Art

[0002] In analog integrated circuits, many reference voltages of different magnitudes are usually used. A voltage source with a small temperature coefficient can be used as the reference voltage for modules such as ADC (AC-DC conversion), and it is an indispensable part of the circuit. In circuit design, a circuit containing a backup power supply usually requires the reference voltage generation circuit to still work properly to generate a reset signal when the backup power supply drops to a lower voltage, which poses a challenge to circuit design.

[0003] Out of consideration for the chip application scenario, when the main power supply VCC drops below the threshold, it is considered to use the backup power supply VBAT to supply power to the chip, which means that when the main power supply VCC drops below the threshold and the backup power supply VBAT drops below the threshold, two detection signals are required to reset the main power supply VCC domain circuit and the backup power supply VBAT domain circuit respectively. In a typical design, the reset signal voltage VPDR_VBAT of the backup power supply VBAT is lower than the reset signal voltage VPDR_VCC of the main power supply VCC. In a chip system with a minimum operating voltage of 2V, VPDR_VCC is set to 1.75V, and VPDR_VBAT is set to 1.65V. Considering the influence of temperature change and process deviation, the actual reset signal voltage VPDR during use may drop to 1.6V or lower. Since the generation of the reset signal voltage VPDR is to compare the voltage division of the power supply voltage with the output of the reference voltage, it is required that the reference voltage can still work properly when it is below 1.6V.

[0004] Common reference voltage generation circuits are usually based on the characteristics of BJT transistors: ① The base-emitter voltage (VBE) of a triode is negatively correlated with the absolute temperature. ② The difference in base-emitter voltages (ΔVBE) between two transistors is positively correlated with the absolute temperature. Thus, by adding these two voltage quantities in proportion, a voltage quantity independent of temperature can be obtained. As Figure 1 shown, M is a coefficient.

[0005] A commonly used reference voltage generation circuit designed based on the above principle is as Figure 2 shown. The output reference voltage VBG is obtained by adding the base-emitter voltage VBE of the first triode Q1 and the voltage (ΔVBE) across the second resistor R2. The main disadvantage of this circuit structure is that it introduces the offset error of the operational amplifier and reflects it to the output after amplification. At the same time, this circuit structure usually requires a relatively high power supply voltage and large power consumption.

[0006] Another commonly used reference voltage generation circuit is as follows Figure 3 As shown, it utilizes the characteristics of transistors to generate a temperature-independent current, and then generates different voltages through resistors with different resistances. In the figure, the second resistor R2 is used to reduce the voltage across the transistor, enabling the circuit to operate at a lower power supply voltage. The main drawback of this method is that the mismatch between current mirrors will cause a certain error in the finally output reference voltage VBG, and it cannot be corrected. At the same time, this circuit also requires an operational amplifier with high gain and high power supply rejection ratio, imposing additional requirements on power consumption and circuit area. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a reference voltage generation circuit that can operate at a low power supply voltage and has low power consumption.

[0008] To solve the above technical problem, the reference voltage generation circuit provided by the present invention includes a bandgap reference circuit;

[0009] The bandgap reference circuit includes a fourth NPN transistor Q4, a twelfth NPN transistor Q12, a ninth NPN transistor Q9, a first resistor R1, a second resistor R2, and a fifth resistor R5;

[0010] One end of the first resistor R1 is connected to the base of the fourth NPN transistor Q4, and the other end is connected to one end of the second resistor R2 and the collector of the twelfth NPN transistor Q12;

[0011] The other end of the second resistor R2 is connected to the base of the twelfth NPN transistor Q12, the base of the ninth NPN transistor Q9, and one end of the fifth resistor R5;

[0012] The collectors of the fourth NPN transistor Q4 and the ninth NPN transistor Q9 are connected to the operating voltage VP;

[0013] The emitters of the fourth NPN transistor Q4, the twelfth NPN transistor Q12, and the ninth NPN transistor Q9 are all grounded;

[0014] The other end of the fifth resistor R5 serves as the reference voltage VBG output terminal.

[0015] Preferably, the bandgap reference circuit further includes a sixth PMOS transistor M6, a seventh PMOS transistor M7, and an eighth PMOS transistor M8;

[0016] The source terminals of the sixth PMOS transistor M6, the seventh PMOS transistor M7, and the eighth PMOS transistor M8 are connected to the main power supply VCC;

[0017] The gate terminals of the sixth PMOS transistor M6, the seventh PMOS transistor M7, and the drain terminals of the seventh PMOS transistor M7 are all shorted to the node VP1, and the collector of the ninth NPN transistor Q9 is connected to the node VP1;

[0018] The gate terminal and the drain terminal of the sixth PMOS transistor M6 and the gate terminal of the eighth PMOS transistor M8 are all shorted to the node VP2, and the collector of the fourth NPN transistor Q4 is connected to the node VP2;

[0019] The drain terminal of the eighth PMOS transistor M8 is connected to the output terminal of the reference voltage VBG.

[0020] Preferably, the fourth NPN transistor Q4 is a single NPN transistor, and the ninth NPN transistor Q9 is formed by a plurality of NPN transistors connected in parallel.

[0021] Preferably, the resistance value of the first resistor R1 is twice the resistance value of the second resistor R2.

[0022] Preferably, the reference voltage generating circuit further includes a startup circuit;

[0023] The startup circuit includes a fifth NMOS transistor M5, a third resistor R3, a tenth NPN transistor Q10, and an eleventh NPN transistor Q11;

[0024] For the fifth NMOS transistor M5, its drain terminal is connected to the node VP2, its source terminal is connected to the output terminal of the reference voltage VBG, and its gate terminal is connected to one end of the third resistor R3, the collector and the base of the tenth NPN transistor Q10;

[0025] For the eleventh NPN transistor Q11, its base and collector are connected to the emitter of the tenth NPN transistor Q10, and its emitter is grounded;

[0026] The other end of the third resistor R3 is connected to the main power supply VCC.

[0027] Preferably, the reference voltage generating circuit further includes a voltage dividing resistor string;

[0028] The voltage dividing resistor string includes at least two resistors connected in series between the output terminal of the reference voltage VBG and the ground;

[0029] The series connection point of adjacent resistors in the voltage dividing resistor string serves as the output terminal of the reference voltage Vref.

[0030] Preferably, the voltage dividing resistor string is composed of a sixth resistor R6 and a fourth resistor R4 connected in series.

[0031] The reference voltage generation circuit of the present invention uses the voltage-current characteristics of NPN transistors in its bandgap reference circuit. The base-emitter voltage VBE of a triode and the difference in base-emitter voltages ΔVBE of two transistors (the fourth NPN transistor Q4 and the ninth NPN transistor Q9) are added proportionally to obtain a reference voltage VBG independent of temperature. The difference in base-emitter voltages ΔVBE of the two transistors is represented by the voltage dropped across the first resistor R1 and the second resistor R2. In this way, an operational amplifier does not need to be introduced, which can save the circuit area and power consumption (the power consumption of the overall circuit can be within 300 nA). At the same time, since the twelfth NPN transistor Q12 is introduced into the circuit, by adjusting the ratio of the first resistor R1 and the second resistor R2, ΔVBE can be copied proportionally to both ends of the fifth resistor R5, so that the circuit can operate normally at a lower voltage (such as 1.4V). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present invention, the following briefly introduces the drawings required for the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] Figure 1 is a schematic diagram of a common reference voltage generation circuit;

[0034] Figure 2 is a common reference voltage generation circuit;

[0035] Figure 3 is another common reference voltage generation circuit;

[0036] Figure 4 is an embodiment of the reference voltage generation circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0038] The "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0040] Embodiment 1

[0041] A reference voltage generating circuit is as Figure 4 shown, which includes a bandgap reference circuit;

[0042] The bandgap reference circuit includes a fourth NPN transistor Q4, a twelfth NPN transistor Q12, a ninth NPN transistor Q9, a first resistor R1, a second resistor R2 and a fifth resistor R5;

[0043] One end of the first resistor R1 is connected to the base of the fourth NPN transistor Q4, and the other end is connected to one end of the second resistor R2 and the collector of the twelfth NPN transistor Q12;

[0044] The other end of the second resistor R2 is connected to the base of the twelfth NPN transistor Q12, the base of the ninth NPN transistor Q9 and one end of the fifth resistor R5;

[0045] The collectors of the fourth NPN transistor Q4 and the ninth NPN transistor Q9 are connected to the operating voltage VP;

[0046] The emitters of the fourth NPN transistor Q4, the twelfth NPN transistor Q12 and the ninth NPN transistor Q9 are all grounded;

[0047] The other end of the fifth resistor R5 serves as the reference voltage VBG output terminal.

[0048] The derivation process of the reference voltage is as follows:

[0049] According to the circuit, the reference voltage VBG can be expressed as the base-emitter voltage Vbe of the transistor and the voltage across the fifth resistor R5:

[0050] Ic is the collector current of the twelfth NPN transistor Q12, and β is the transistor amplification factor;

[0051] The base-emitter voltage difference (ΔVBE) between the two transistors can be expressed as:

[0052]

[0053] If the ratio of R1 and R2 is properly set, the ΔV in the above formula be can be substituted into the expression of VBG, and the following result can be obtained:

[0054]

[0055] It can be seen from the above formula that VBG is the result of adding VBE and ΔVBE proportionally. By adjusting the ratio of the fifth resistor R5 and the second resistor R2, a voltage output that is basically unchanged with temperature can be obtained, usually around 1.2V.

[0056]

[0057] Preferably, the resistance value of the first resistor R1 is twice that of the second resistor R2.

[0058] For the reference voltage generation circuit of Embodiment 1, its bandgap reference circuit utilizes the voltage-current characteristics of NPN transistors to add the base-emitter voltage VBE of the transistor and the base-emitter voltage difference ΔVBE between two transistors (the fourth NPN transistor Q4 and the ninth NPN transistor Q9) proportionally to obtain a reference voltage VBG independent of temperature; the base-emitter voltage difference ΔVBE between the two transistors is represented by the voltage dropped across the first resistor R1 and the second resistor R2, so that an operational amplifier can be avoided, saving the area and power consumption of the circuit (the power consumption of the overall circuit can be within 300 nA); at the same time, since the twelfth NPN transistor Q12 is introduced into the circuit, by adjusting the ratio of the first resistor R1 and the second resistor R2, ΔVBE can be copied proportionally to both ends of the fifth resistor R5, so that the circuit can work normally at a lower voltage (such as 1.4V). The reference voltage generation circuit of Embodiment 1 can work at a low power supply voltage and has low power consumption. In a chip system including a backup power supply, when the overall circuit drops below 1.65V under the backup power supply, a reset signal voltage VPDR_VBAT can be normally generated to ensure the normal operation and reset of the backup power supply circuit.

[0059] Embodiment 2

[0060] Based on the reference voltage generation circuit of Embodiment 1, the bandgap reference circuit further includes a sixth PMOS transistor M6, a seventh PMOS transistor M7, and an eighth PMOS transistor M8;

[0061] The source terminals of the sixth PMOS transistor M6, the seventh PMOS transistor M7, and the eighth PMOS transistor M8 are connected to the main power supply VCC;

[0062] The gate terminal of the sixth PMOS transistor M6, the gate terminal and the drain terminal of the seventh PMOS transistor M7 are all short - connected to the node VP1, and the collector of the ninth NPN transistor Q9 is connected to the node VP1;

[0063] The gate terminal and the drain terminal of the sixth PMOS transistor M6, and the gate terminal of the eighth PMOS transistor M8 are all short - connected to the node VP2, and the collector of the fourth NPN transistor Q4 is connected to the node VP2;

[0064] The drain terminal of the eighth PMOS transistor M8 is connected to the output terminal of the reference voltage VBG.

[0065] To obtain a suitable ΔVBE, the fourth NPN transistor Q4 is generally a single NPN transistor, while the ninth NPN transistor Q9 is generally composed of multiple NPN transistors connected in parallel, and the number of parallel transistors will also be substituted into the calculation formula to assist in the analysis.

[0066] For the reference voltage generation circuit of Embodiment 2, if the eighth PMOS transistor M8 is to operate in the saturation region, |V Ds，M8 |≥|V GS，M8 -V th，M8 |=V dsat，M8 , so the required main power supply VCC voltage is V BG +|V DS，M8 |≥V BG +V dsat，M8 , where Vdsat is the saturation drain - source voltage. Observing this formula, it can be seen that if the overdrive voltage of the eighth PMOS transistor M8 is properly set, the circuit can operate at a main power supply VCC voltage of 1.4V. At the same time, the eighth PMOS transistor M8 in the circuit can help clamp the voltage of the node VP2. The eighth PMOS transistor M8 can be used to adjust the drain - gate voltage difference of the current mirror, weaken the channel - length modulation effect, and reduce the offset error between them. Usually, the current flowing through the eighth PMOS transistor M8 is adjusted to be close to the current flowing through the sixth PMOS transistor M6 and the seventh PMOS transistor M7 that form the current mirror. Therefore, the gate voltage of the eighth PMOS transistor M8 (the voltage of the node VP2) will be close to the gate voltages of the sixth PMOS transistor M6 and the seventh PMOS transistor M7 (the voltage of the node VP1), and to a certain extent, weaken the influence of the channel - length modulation effect of the PMOS transistors forming the current mirror between the sixth PMOS transistor M6 and the seventh PMOS transistor M7.

[0067] Embodiment 3

[0068] Based on Embodiment 2, the reference voltage generation circuit further includes a startup circuit;

[0069] The startup circuit includes a fifth NMOS transistor M5, a third resistor R3, a tenth NPN transistor Q10, and an eleventh NPN transistor Q11;

[0070] For the fifth NMOS transistor M5, its drain terminal is connected to node VP2, its source terminal is connected to the output terminal of the reference voltage VBG, and its gate terminal is connected to one end of the third resistor R3, the collector and base of the tenth NPN transistor Q10;

[0071] For the eleventh NPN transistor Q11, its base and collector are connected to the emitter of the tenth NPN transistor Q10, and its emitter is grounded;

[0072] The other end of the third resistor R3 is connected to the main power supply VCC.

[0073] In the reference voltage generation circuit of Embodiment 3, its startup circuit is a circuit that enables the auxiliary core circuit to quickly reach the voltage stable point when the power supply is powered on. As a startup transistor, the fifth NMOS transistor M5 helps the voltage of node VP2 to be quickly established when the power supply voltage is powered on, enabling the current mirror formed by the sixth PMOS transistor M6 and the seventh PMOS transistor M7 to be quickly turned on. After the circuit is stable, due to the negative feedback of the reference voltage VBG on the fifth NMOS transistor M5, the fifth NMOS transistor M5 will be completely turned off, without leakage problems.

[0074] Embodiment 4

[0075] Based on Embodiment 2, the reference voltage generation circuit further includes a voltage dividing resistor string;

[0076] The voltage dividing resistor string includes at least two resistors connected in series between the output terminal of the reference voltage VBG and the ground;

[0077] The series connection point of adjacent resistors in the voltage dividing resistor string serves as the output terminal of the reference voltage Vref.

[0078] Preferably, the voltage dividing resistor string is composed of a sixth resistor R6 and a fourth resistor R4 connected in series.

[0079] In the reference voltage generation circuit of Embodiment 4, the voltage dividing resistor string can output an arbitrary value of a temperature-independent reference voltage Vref (less than or equal to the reference voltage VBG generated by the bandgap reference circuit) through voltage division, can generate multiple reference voltage signals with high precision without the need for an operational amplifier, facilitating the use of other modules in the chip, and can also work normally under a lower power supply voltage, meeting the application scenarios of low-power chips.

[0080] In addition, the load capacity of the eighth PMOS transistor M8 is relatively strong. If the size of the eighth PMOS transistor M8 is set to be relatively large, when an additional load within a certain range is added to the voltage-dividing resistor string, the output voltage will not change significantly due to the change in the load.

[0081] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A reference voltage generation circuit, characterized in that, it includes a bandgap reference circuit; The bandgap reference circuit includes a fourth NPN transistor (Q4), a twelfth NPN transistor (Q12), a ninth NPN transistor (Q9), a first resistor (R1), a second resistor (R2), and a fifth resistor (R5); One end of the first resistor (R1) is connected to the base of the fourth NPN transistor (Q4), and the other end is connected to one end of the second resistor (R2) and the collector of the twelfth NPN transistor (Q12); The other end of the second resistor (R2) is connected to the base of the twelfth NPN transistor (Q12), the base of the ninth NPN transistor (Q9), and one end of the fifth resistor (R5); The collectors of the fourth NPN transistor (Q4) and the ninth NPN transistor (Q9) are connected to the working voltage; The emitters of the fourth NPN transistor (Q4), the twelfth NPN transistor (Q12), and the ninth NPN transistor (Q9) are all grounded; The other end of the fifth resistor (R5) is used as the reference voltage (VBG) output terminal.

2. The reference voltage generation circuit according to claim 1, characterized in that, The bandgap reference circuit further includes a sixth PMOS transistor (M6), a seventh PMOS transistor (M7), and an eighth PMOS transistor (M8); The source terminals of the sixth PMOS transistor (M6), the seventh PMOS transistor (M7), and the eighth PMOS transistor (M8) are connected to the main power supply (VCC); The gate terminal of the sixth PMOS transistor (M6), the gate terminal and the drain terminal of the seventh PMOS transistor (M7) are all short-circuited to the node VP1, and the collector of the ninth NPN transistor (Q9) is connected to the node VP1; The gate terminal and the drain terminal of the sixth PMOS transistor (M6), and the gate terminal of the eighth PMOS transistor (M8) are all short-circuited to the node VP2, and the collector of the fourth NPN transistor (Q4) is connected to the node VP2; The drain terminal of the eighth PMOS transistor (M8) is connected to the reference voltage (VBG) output terminal.

3. The reference voltage generation circuit according to claim 1, characterized in that, The fourth NPN transistor (Q4) is a single NPN transistor, and the ninth NPN transistor (Q9) is composed of multiple NPN transistors connected in parallel.

4. The reference voltage generation circuit according to claim 1, characterized in that, The resistance value of the first resistor (R1) is twice the resistance value of the second resistor (R2).

5. The reference voltage generation circuit according to claim 2, characterized in that, The reference voltage generation circuit further includes a startup circuit; The startup circuit includes a fifth NMOS transistor (M5), a third resistor (R3), a tenth NPN transistor (Q10), and an eleventh NPN transistor (Q11); For the fifth NMOS transistor (M5), its drain terminal is connected to the node VP2, its source terminal is connected to the reference voltage (VBG) output terminal, and its gate terminal is connected to one end of the third resistor (R3), the collector and the base of the tenth NPN transistor (Q10); For the eleventh NPN transistor (Q11), its base and collector are connected to the emitter of the tenth NPN transistor (Q10), and its emitter is grounded; The other end of the third resistor (R3) is connected to the main power supply (VCC).

6. The reference voltage generation circuit according to claim 2, wherein, the reference voltage generation circuit further includes a voltage dividing resistor string; the voltage dividing resistor string includes at least two resistors connected in series between the output terminal of the reference voltage (VBG) and the ground; the series connection point of adjacent resistors in the voltage dividing resistor string serves as the output terminal of the reference voltage (Vref).

7. The reference voltage generation circuit according to claim 6, wherein, the voltage dividing resistor string is composed of a sixth resistor (R6) and a fourth resistor (R4) connected in series.

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