Abnormal power failure diagnosis method and device

Abstract

The invention provides an abnormal power failure diagnosis method and device, and relates to the technical field of power failure diagnosis, the device comprises an MCU, the MCU is connected with a selection switch through a line, and one end of the selection switch is provided with a capacitor. Hardware hidden dangers can be eliminated at the beginning of power-on through hardware self-inspection in the system pre-starting stage, and it is guaranteed that operation baselines of the whole delay power supply module and the MCU are correct; according to the following capacitor energy charging function, a super capacitor is connected in parallel to the 12V low-voltage power supply side, and the charging current and voltage slope are monitored in real time, so that even if the capacitor stably and safely stores enough energy, overcharge damage is prevented, and monitoring is interrupted by data heartbeat of an MCU and a BMS master controller and power-down cmd, it is ensured that the system can sense a power-off instruction in time at any time, and the power-off state of the system is ensured to be stable and reliable. And persistent storage of the key operation parameters is completed in an atomicity write-in mode, so that the data loss risk caused by communication timeout or software faults is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power failure diagnosis, and in particular to a method and device for diagnosing abnormal power failure. Background Art

[0002] In key areas such as industrial automation, new energy vehicles, and data centers, abnormal power outages in equipment can lead to loss of operational data, confusion in control parameters, and even hardware damage, potentially causing serious safety incidents and economic losses. Especially in high-reliability scenarios such as battery management systems (BMS) and smart grid equipment, critical data must be quickly and persistently stored after an abnormal power outage, and the cause of the power outage must be accurately diagnosed to guide maintenance decisions. Current industry standards (such as ISO 26262 and IEC 61508) have clear requirements for power outage protection. For example, after a power outage, a power delay of at least 50ms to 2 minutes must be maintained to ensure data integrity, and contextual information such as the power outage type, timestamp, and device status must be recorded.

[0003] Existing abnormal power outage protection solutions often rely on backup batteries or traditional capacitors for short-term power supply. Most systems lack hardware self-test capabilities during the pre-startup phase, making it impossible to eliminate circuit hazards during the initialization phase. The capacitor charging process lacks real-time monitoring of current and voltage slopes, making it easy for overcharging to cause capacitor lifespan degradation or undercharging to prevent sufficient energy storage. Software-triggered storage processes during power outages are susceptible to communication delays or program errors, potentially generating invalid fragmented data. Existing solutions have difficulty distinguishing between planned and abnormal power outages and lack the ability to determine the type of power outage in real time, resulting in a lack of key information such as timestamps and SOC / SOH during fault tracing. Traditional hardware switching circuits have a response time exceeding 10ms, which cannot meet the millisecond-level power loss edge detection requirements. Furthermore, the parallel connection of the backup power supply and the main power supply can easily trigger reverse current surges, causing secondary damage. Therefore, we provide a method and device for diagnosing abnormal power outages. Summary of the Invention

[0004] The purpose of the present invention is to solve the shortcomings existing in the prior art.

[0005] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solution: comprising: an MCU, a selection switch connected to the MCU via a line, a capacitor provided at one end of the selection switch, a resistor provided between the end of the capacitor away from the selection switch and the selection switch, and a 12V low-voltage power supply provided on the side of the selection switch and the capacitor away from the MCU.

[0006] As a preferred embodiment, both ends of the V low-voltage power supply are connected to a circuit installed on the MCU, one end of the selection switch is externally connected to the line, the other end of the selection switch is connected to the capacitor through the line, and both ends of the resistor are respectively connected to one end of the capacitor and the selection switch through the line.

[0007] As a preferred embodiment, the method comprises the following steps:

[0008] S1, system pre-start hardware self-test;

[0009] S2, power supply connected to capacitor charging;

[0010] S3, normal operation monitoring command synchronization;

[0011] S4, capacitor discharge control during normal power-off process;

[0012] S5, abnormal power failure monitoring power supply switching;

[0013] S6, abnormal diagnosis fault mark.

[0014] As a preferred embodiment, in step S1, system pre-startup hardware self-test:

[0015] S1.1. After the MCU is powered on, it first completes clock source selection and clock frequency locking, and configures the startup vector through internal registers to ensure accurate and stable timing of program execution;

[0016] S1.2, outputting a driving test signal through the internal GPIO to detect whether the closing and releasing actions of the relays at both ends of the selector switch (2) a and b are normal, and to determine whether there is a break or short circuit fault in the control circuit;

[0017] S1.3. Use the ADC channel to sample the voltage across the capacitor and compare it with the voltage difference across a resistor of known resistance. Calculate the deviation between the actual resistance and the ideal value to eliminate potential backup power failures caused by rapid capacitor self-discharge or resistor open circuits.

[0018] S1.4. After complete power failure, determine the current residual voltage of the supercapacitor using the short pulse charge and discharge measurement method and compare the result with the preset threshold (3.5V) to ensure that the capacitor has sufficient energy storage space and discharge margin before proceeding to the next step;

[0019] S1.5. Clear the abnormal power-off flag and fault record register stored in NVM to avoid interfering with the judgment of this diagnostic process. At the same time, initialize the state machine and timer in RAM.

[0020] As a preferred embodiment, in step S2, the power supply is connected to the capacitor for charging:

[0021] S2.1. The MCU continuously monitors the arrival of the 12V power supply through an external interrupt or comparison module, and enters the charging preparation state after identifying the power-on edge trigger;

[0022] S2.2. Send a drive command to switch the selector switch to terminal a, close it, connect the supercapacitor in parallel with the 12V power supply and the MCU chip, and start the capacitor charging path;

[0023] S2.3. Use the ADC to sample the capacitor charging current and voltage slope in real time, and calculate the actual capacitance value according to the relationship I = C·dV / dt to ensure that it meets the design (≈1.5F) and the charging curve is smooth without overcurrent or abnormal voltage increase.

[0024] S2.4: When the voltage across the capacitor reaches the preset upper limit (5.5V) and the charging current drops to the microampere level, the MCU confirms the end of charging through a soft timer and stops further driving to prevent overcharging damage.

[0025] S2.5. Mark the "capacitor charged" status in the internal register to provide a conditional judgment basis for the subsequent power-off protection enable logic.

[0026] As a preferred implementation, in step S3, during synchronization of the normal operation detection command:

[0027] S3.1, MCU regularly sends status heartbeat (including key data such as SOC and SOH) to the BMS main control to maintain the active communication link and prevent misjudgment of power due to communication timeout;

[0028] S3.2. Configure interrupts via the CAN bus or UART interface to ensure that once "power-downcmd" arrives, the current task flow is interrupted immediately and the power-down process is prepared.

[0029] S3.3. After receiving the power-off command, the MCU internal state machine switches from the "running state" to the "pre-power-off state", stops non-critical peripherals, and locks RAM data to prevent data inconsistency caused by ongoing write operations;

[0030] S3.4. Merge the latest SOC, SOH, number of charge and discharge cycles, remaining capacity and other information into the NVM write cache area and calculate the CRC checksum to ensure the atomicity and integrity of the write.

[0031] S3.5. Real-time monitoring of NVM write completion interrupts. When all cached data is confirmed to have been written successfully and the CRC check has passed, the power-off process continues; otherwise, a time-limited retry or an error is recorded.

[0032] As a preferred embodiment, in the step S4, the capacitor discharge control in the normal power-off process:

[0033] S4.1, in the pre-power-down state, through SPI / I 2 C bus starts NVM writing to ensure that all critical data is securely stored in the chip ROM;

[0034] S4.2: After the storage completion interrupt arrives, the MCU drives the GPIO to switch the selector switch to terminal b, closing the capacitor to ground or connect the bleeder resistor.

[0035] S4.3. Use the ADC to sample the voltage across the capacitor and monitor its downward discharge slope to verify that the discharge process is stable and free of oscillation. Terminate the discharge after the voltage drops to a safe threshold.

[0036] S4.4. After the discharge action is completed and confirmed, the MCU state machine is switched to the "shutdown state", all peripheral power supplies are disconnected, the clock is turned off, and the MCU enters sleep or power-off mode;

[0037] S4.5. Record a "normal power-off" event in NVM and clear temporary flags such as "capacitor charged" to prepare for the next power-on.

[0038] As a preferred embodiment, in the step S5, abnormal power failure detection power supply switching:

[0039] S5.1, by detecting the hardware interrupt of the 12V input power supply, the pin captures the falling edge and immediately triggers the abnormal power-off process, without relying on the communication command response;

[0040] S5.2: Since the normal power-off command is not executed, the selector switch is still in the closed state at end a, automatically connecting the supercapacitor in parallel to the MCU power supply side without the need for additional drive;

[0041] S5.3, MCU switches to low power mode, adjusts the core frequency to the average operating point (≈

[0042] 4.5V / 0.05A), ensuring sustainable operation for about 60s within the remaining capacitor energy range (E≈13.5J);

[0043] S5.4. During the capacitor power supply period, the NVM data is stored and verified again according to the cache and write mechanism of the normal power-off process to ensure data integrity during abnormal power outage.

[0044] S5.5. The MCU periodically measures the capacitor voltage through a timer and determines the available time based on a preset power model to ensure that all write operations are completed or the device is safely shut down before the power is exhausted.

[0045] As a preferred embodiment, in the step S6, abnormal diagnosis fault marking:

[0046] S6.1. The MCU samples the voltage at the detection point c between the selection switch and the capacitor and compares it with the calibration value of the normal discharge curve to determine whether it is an abnormal discharge state.

[0047] S6.2. Accumulate and record continuous abnormal power-off events in NVM, and write context information such as timestamp, SOC, SOH, etc. to build a fault log;

[0048] S6.3. Place the abnormal power-off flag (bitmask) in a dedicated status register so that the firmware can quickly identify it and prioritize the fault recovery logic when powering on next time.

[0049] S6.4. Synchronously send the diagnostic results to the BMS master control, inform the upper management system of the abnormal power outage through the CAN / UART interface, and recommend countermeasures (check the power line or replace the battery);

[0050] S6.5. During the initialization phase after the next MCU power-on, the previous abnormal power-off log is read and reported, and then the fault flag is cleared to prepare for the system to re-enter the initial self-test.

[0051] Compared with the prior art, the advantages and positive effects of the present invention are:

[0052] 1. In the present invention, the hardware self-check in the system pre-startup phase can eliminate hardware hidden dangers at the beginning of power-on, ensuring that the operating baseline of the entire delayed power supply module and MCU is correct; the subsequent capacitor charging function, by connecting a supercapacitor in parallel on the 12V low-voltage power supply side and monitoring the charging current and voltage slope in real time, can ensure that the capacitor can store sufficient energy steadily and safely while preventing overcharging damage. The data heartbeat and "power-downcmd" interrupt monitoring of the MCU and BMS main control ensure that the system can promptly perceive the power-off instruction at any time and complete the persistent storage of key operating parameters in an atomic write manner, thereby greatly reducing the risk of data loss due to communication timeout or software failure.

[0053] 2. The present invention automatically switches to supercapacitor power supply mode through the mechanism of rapid interruption at the power-off edge and self-maintaining parallel state of the selection switch. Utilizing a 90J-level energy storage and a delay power supply lasting about 60s, the present invention provides sufficient time for the MCU to complete the storage of all data to be written. The voltage sampling function of the series resistor and the detection point c enables the MCU to determine the power-off type in real time and record the abnormal power-off event along with contextual information such as timestamp and SOC / SOH in NVM. This not only ensures data integrity at the moment of power-off, but also provides a detailed basis for fault diagnosis and maintenance decisions during subsequent power-on, thereby significantly improving the reliability, maintainability and operational safety of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 The present invention provides a circuit schematic diagram of a diagnostic device for abnormal power failure;

[0055] Figure 2 A flowchart of a method for diagnosing abnormal power failure proposed by the present invention; Figure 3 The present invention provides a method flow chart of a method for diagnosing abnormal power failure.

[0056] Legend:

[0057] 1. MCU (microcontroller unit); 2. selection switch; 3. capacitor; 4. resistor; 5. 12V low-voltage power supply. DETAILED DESCRIPTION

[0058] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the described embodiments are only part of the embodiments of this application, rather than all the embodiments, and the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0059] It should be further explained that the drawings and implementation methods of the present invention mainly describe the concept of the present invention. On the basis of this concept, the specific forms and settings of some connection relationships, positional relationships, power mechanisms, power supply systems, hydraulic systems and control systems may not be fully described. However, on the premise that those skilled in the art understand the concept of the present invention, those skilled in the art can implement the above-mentioned specific forms and settings in a well-known manner.

[0060] When an element is referred to as being “fixed to” or “disposed on” another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it can be directly connected to the other element or indirectly connected to the other element.

[0061] The directional words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. The terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" indicate the directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0062] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be subsequently positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device may also be positioned in other different ways, and the spatially relative descriptions used herein are interpreted accordingly.

[0063] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, and "several" means one or more, unless otherwise specifically defined.

[0064] A method and device for diagnosing abnormal power failure provided by the present invention will now be described.

[0065] Example 1

[0066] like Figure 1-3 As shown, the present invention provides a technical solution: a diagnostic device for abnormal power failure, comprising: an MCU 1, a selection switch 2 connected to the MCU 1 via a line, a capacitor 3 provided at one end of the selection switch 2, a resistor 4 provided between the end of the capacitor 3 away from the selection switch 2 and the selection switch 2, and a 12V low-voltage power supply 5 provided on the side of the selection switch 2 and the capacitor 3 away from the MCU 1;

[0067] Both ends of the 12V low-voltage power supply 5 are connected to the circuit installed on the MCU1, one end of the selection switch 2 is externally connected to the line, and the other end of the selection switch 2 is connected to the capacitor 3 through the line. Both ends of the resistor 4 are respectively connected to one end of the capacitor 3 and the selection switch 2 through the line.

[0068] In this embodiment, MCU1 connects capacitor 3 in parallel to the 12V low-voltage power supply 5 side through the line drive selection switch 2, so that capacitor 3 is slowly charged and stored energy through resistor 4; once the 12V power supply is interrupted or a power-off command is received, the selection switch 2 remains in the parallel state, and capacitor 3 provides delayed power supply to MCU1 through its own energy storage to ensure the completion of writing of key data. At the same time, by monitoring the voltage at the resistor 4 connected in series between the capacitor 3 and the selection switch 2 and the detection point c, MCU1 can determine the type of power outage (normal shutdown or abnormal power off) and record the abnormal power off event in NVM so that fault diagnosis and processing can be performed after the next power-on.

[0069] Example 2

[0070] like Figure 1-3 As shown, the present invention provides a technical solution: a method for diagnosing abnormal power failure, comprising the following steps:

[0071] S1, system pre-start hardware self-test;

[0072] S2, power supply connected to capacitor charging;

[0073] S3, normal operation monitoring command synchronization;

[0074] S4, capacitor discharge control during normal power-off process;

[0075] S5, abnormal power failure monitoring power supply switching;

[0076] S6, abnormal diagnosis fault mark;

[0077] In the step S1, system pre-startup hardware self-test:

[0078] S1.1. After the MCU is powered on, it first completes clock source selection and clock frequency locking, and configures the startup vector through internal registers to ensure accurate and stable timing of program execution;

[0079] S1.2. Output a drive test signal through the internal GPIO to detect whether the relays at both ends of selector switch 2 (a and b) are closing and releasing normally, and to determine whether there is any open circuit or short circuit fault in the control circuit.

[0080] S1.3. Use the ADC channel to sample the voltage across the capacitor and compare it with the voltage difference across a resistor of known resistance. Calculate the deviation between the actual resistance and the ideal value to eliminate potential backup power failures caused by rapid capacitor self-discharge or resistor open circuits.

[0081] S1.4. After complete power failure, determine the current residual voltage of the supercapacitor using the short pulse charge and discharge measurement method and compare the result with the preset threshold (3.5V) to ensure that the capacitor has sufficient energy storage space and discharge margin before proceeding to the next step;

[0082] S1.5. Clear the abnormal power-off flag and fault record register stored in NVM to avoid interference with the current diagnostic process. Initialize the state machine and timer in RAM.

[0083] In step S2, the power supply is connected to the capacitor for charging:

[0084] S2.1. The MCU continuously monitors the arrival of the 12V power supply through an external interrupt or comparison module, and enters the charging preparation state after identifying the power-on edge trigger;

[0085] S2.2. Send a drive command to switch selector switch 2 to terminal a, closing it. This connects the supercapacitor to the 12V power supply and the MCU chip in parallel, thus starting the capacitor charging path.

[0086] S2.3. Use the ADC to sample the capacitor charging current and voltage slope in real time, and calculate the actual capacitance value according to the relationship I = C·dV / dt to ensure that it meets the design (≈1.5F) and the charging curve is smooth without overcurrent or abnormal voltage increase.

[0087] S2.4: When the voltage across the capacitor reaches the preset upper limit (5.5V) and the charging current drops to the microampere level, the MCU confirms the end of charging through a soft timer and stops further driving to prevent overcharging damage.

[0088] S2.5. Mark the "capacitor charged" status in the internal register to provide a conditional judgment basis for the subsequent power-off protection enable logic;

[0089] In the step S3, during synchronization of the normal operation detection command:

[0090] S3.1, MCU regularly sends status heartbeat (including key data such as SOC and SOH) to the BMS main control to maintain the active communication link and prevent misjudgment of power due to communication timeout;

[0091] S3.2. Configure interrupts via the CAN bus or UART interface to ensure that once "power-downcmd" arrives, the current task flow is interrupted and the power-down process begins.

[0092] S3.3. After receiving the power-off command, the MCU internal state machine switches from the "running state" to the "pre-power-off state", stops non-critical peripherals, and locks RAM data to prevent data inconsistency caused by ongoing write operations;

[0093] S3.4. Merge the latest SOC, SOH, number of charge and discharge cycles, remaining capacity and other information into the NVM write cache area and calculate the CRC checksum to ensure the atomicity and integrity of the write.

[0094] S3.5. Real-time monitoring of NVM write completion interrupts. Once all cached data has been successfully written and the CRC check has passed, the power-off process continues; otherwise, a retry is performed within a limited time or an error is recorded.

[0095] In the step S4, capacitor discharge control of the normal power-off process:

[0096] S4.1, in the pre-power-down state, through SPI / I 2 C bus starts NVM writing to ensure that all critical data is securely stored in the chip ROM;

[0097] S4.2: After the storage completion interrupt arrives, the MCU drives the GPIO to switch selector switch 2 to terminal b, closing the capacitor to ground or connect the capacitor to the bleeder resistor.

[0098] S4.3. Use the ADC to sample the voltage across the capacitor and monitor its downward discharge slope to verify that the discharge process is stable and free of oscillation. Terminate the discharge after the voltage drops to a safe threshold.

[0099] S4.4. After the discharge action is completed and confirmed, the MCU state machine is switched to the "shutdown state", all peripheral power supplies are disconnected, the clock is turned off, and the MCU enters sleep or power-off mode;

[0100] S4.5. Record a "normal power-off" event in the NVM and clear temporary flags such as "capacitor charged" to prepare for the next power-on.

[0101] In the step S5, abnormal power detection power supply switching:

[0102] S5.1, by detecting the hardware interrupt of the 12V input power supply, the pin captures the falling edge and immediately triggers the abnormal power-off process, without relying on the communication command response;

[0103] S5.2: Since the normal power-off command is not executed, the selector switch is still in the closed state at end a, automatically connecting the supercapacitor in parallel to the MCU power supply side without the need for additional drive;

[0104] S5.3: The MCU switches to low-power mode and adjusts the core frequency to the average operating point (≈4.5V / 0.05A), ensuring that it can continue to operate within the remaining capacitor energy range (E≈13.5J) for approximately 60 seconds.

[0105] S5.4. During the capacitor power supply period, the NVM data is stored and verified again according to the cache and write mechanism of the normal power-off process to ensure data integrity during abnormal power outage.

[0106] S5.5, the MCU periodically measures the capacitor voltage through a timer and determines the available time based on a preset power model to ensure that all write operations are completed or the device is safely shut down before the battery is exhausted;

[0107] In the step S6, abnormal diagnosis fault marking:

[0108] S6.1. The MCU samples the voltage at the detection point c between the selection switch and the capacitor and compares it with the calibration value of the normal discharge curve to determine whether it is an abnormal discharge state.

[0109] S6.2. Accumulate and record continuous abnormal power-off events in NVM, and write context information such as timestamp, SOC, SOH, etc. to build a fault log;

[0110] S6.3. Place the abnormal power-off flag (bitmask) in a dedicated status register so that the firmware can quickly identify it and prioritize the fault recovery logic when powering on next time.

[0111] S6.4. Synchronously send the diagnostic results to the BMS master control, inform the upper management system of the abnormal power outage through the CAN / UART interface, and recommend countermeasures (check the power line or replace the battery);

[0112] S6.5. During the initialization phase after the next MCU power-on, the previous abnormal power-off log is read and reported, and then the fault flag is cleared to prepare for the system to re-enter the initial self-test.

[0113] In this embodiment, the system performs hardware self-test through the MCU to ensure that the clock, selection switch, capacitor and other hardware are working properly, and performs voltage calibration on the capacitor. When the 12V power supply is connected, the MCU drives the selection switch to charge the capacitor to provide backup power for subsequent operations. When the system is operating normally, the MCU regularly synchronizes data with the BMS main control and monitors the "power-downcmd" command in real time to prepare for power off. During the power-off process, the MCU first completes data storage and discharges the capacitor through the selection switch to safely shut down the system. In the event of an abnormal power outage, the MCU detects power interruption and switches to capacitor power supply mode to complete data storage and ensure that there is sufficient power to maintain stable operation of the system. The system detects whether it is an abnormal power outage through voltage sampling and records the fault information in NVM so that fault recovery processing can be performed after the next power-on.

[0114] Working principle:

[0115] like Figure 1-3As shown in the figure, after the MCU is powered on, it selects the clock source and locks the clock frequency, ensuring accurate and stable system timing. The MCU then drives a test signal through the GPIO to check whether the relays at both ends of the selector switch are operating normally, ensuring that there are no open or short circuit faults in the control line. The ADC samples the voltage across the capacitor and compares it with the voltage difference of a resistor of known resistance to eliminate the risk of rapid capacitor self-discharge or an open resistor. The system uses short-pulse charge and discharge measurements to confirm the current residual voltage of the capacitor and compares it with a preset threshold to ensure that the capacitor has sufficient energy storage and discharge margin. After the hardware self-test is complete, the MCU clears the abnormal power-off flag stored in the NVM, providing a clean state for the next operation.

[0116] After the system starts, the MCU detects the access of the 12V power supply through an external interrupt or comparison module, and drives the selection switch to charge the capacitor to provide backup power for subsequent system operations. During the charging process, the MCU monitors the charging current and voltage changes of the capacitor through the ADC to ensure that the capacitor is charged smoothly and meets the design requirements. When the capacitor voltage reaches the preset upper limit and the charging current drops to the microampere level, the MCU confirms the charging completion through the soft timer and stops further driving to prevent the capacitor from overcharging. The MCU marks the "capacitor charged" status in the internal register and then enters the normal operation mode. It regularly sends data to the BMS main control to keep the communication link active. During this period, the MCU monitors the power-down command in real time through the CAN bus or UART interface. Once the "power-down cmd" command is received, the MCU switches to the "pre-power-down state", locks important data and completes storage.

[0117] When the system is powered off normally, the MCU completes data storage and controls the capacitor discharge through the selection switch to ensure that the capacitor releases the remaining energy safely. The MCU verifies that the discharge process is stable and without oscillation by monitoring the voltage change of the capacitor discharge until the voltage drops to the safety threshold, terminates the discharge, and enters the shutdown state. During this process, the system will also record the normal power-off event, clear the temporary flag bit to prepare for the next power-on. However, in the case of an abnormal power outage, the MCU automatically switches to the capacitor power supply mode after detecting the power interruption, using the capacitor to provide delayed power supply to complete critical data storage and ensure data integrity. The system determines the type of power outage by comparing the capacitor voltage monitoring with the discharge curve and records the abnormal event in the NVM. The next time it is powered on, the MCU will read and process the fault information and inform the upper management system through the CAN or UART interface to take appropriate fault handling measures, such as checking the power line or replacing the battery, thereby achieving fault diagnosis and recovery.

[0118] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0119] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0120] Unless otherwise specifically stated, the relative arrangement of the parts and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of this application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

Claims

1. A diagnostic device for abnormal power failure, characterized in that: include: An MCU (1) is provided, wherein a selection switch (2) is connected to the MCU (1) via a line, a capacitor (3) is provided at one end of the selection switch (2), a resistor (4) is provided between an end of the capacitor (3) away from the selection switch (2) and the selection switch (2), and a 12V low-voltage power supply (5) is provided on a side of the selection switch (2) and the capacitor (3) away from the MCU (1).

2. The abnormal power failure diagnosis device according to claim 1, characterized in that: Both ends of the 12V low-voltage power supply (5) are connected to a circuit installed on the MCU (1); one end of the selection switch (2) is externally connected to the circuit; the other end of the selection switch (2) is connected to the capacitor (3) through the circuit; and both ends of the resistor (4) are connected to one end of the capacitor (3) and the selection switch (2) through the circuit, respectively.

3. A method for diagnosing abnormal power failure, characterized in that: The following steps are involved: S1, system pre-start hardware self-test; S2, power supply connected to capacitor charging; S3, normal operation detection command synchronization; S4, capacitor discharge control during normal power-off process; S5, abnormal power failure monitoring power supply switching; S6, abnormal diagnosis fault mark.

4. The method for diagnosing abnormal power failure according to claim 3, wherein: In the step S1, system pre-startup hardware self-test: S1.

1. After the MCU is powered on, it first completes clock source selection and clock frequency locking, and configures the startup vector through internal registers to ensure accurate and stable timing of program execution; S1.2, outputting a driving test signal through the internal GPIO to detect whether the closing and releasing actions of the relays at both ends of the selector switch (2) a and b are normal, and to determine whether there is a break or short circuit fault in the control circuit; S1.

3. Use the ADC channel to sample the voltage across the capacitor and compare it with the voltage difference across a resistor of known resistance. Calculate the deviation between the actual resistance and the ideal value to eliminate potential backup power failures caused by rapid capacitor self-discharge or resistor open circuits. S1.

4. After complete power failure, determine the current residual voltage of the supercapacitor using the short pulse charge and discharge measurement method and compare the result with the preset threshold (3.5V) to ensure that the capacitor has sufficient energy storage space and discharge margin before proceeding to the next step; S1.

5. Clear the abnormal power-off flag and fault record register stored in NVM to avoid interfering with the judgment of this diagnostic process. At the same time, initialize the state machine and timer in RAM.

5. The method for diagnosing abnormal power failure according to claim 3, characterized in that: In step S2, the power supply is connected to the capacitor for charging: S2.

1. The MCU continuously monitors the arrival of the 12V power supply through an external interrupt or comparison module, and enters the charging preparation state after identifying the power-on edge trigger; S2.2, sending a drive command to switch the selector switch (2) to terminal a, closing it, connecting the supercapacitor in parallel with the 12V power supply and the MCU chip, and opening the capacitor charging path; S2.

3. Use the ADC to sample the capacitor charging current and voltage slope in real time, and calculate the actual capacitance value according to the relationship I = C·dV / dt to ensure that it meets the design (≈1.5F) and the charging curve is smooth without overcurrent or abnormal voltage increase. S2.4: When the voltage across the capacitor reaches the preset upper limit (5.5V) and the charging current drops to the microampere level, the MCU confirms the end of charging through a soft timer and stops further driving to prevent overcharging damage. S2.

5. Mark the "capacitor charged" status in the internal register to provide a conditional judgment basis for the subsequent power-off protection enable logic.

6. The method for diagnosing abnormal power failure according to claim 3, characterized in that: In the step S3, during synchronization of the normal operation detection command: S3.1, MCU regularly sends status heartbeat (including key data such as SOC and SOH) to the BMS main control to maintain the active communication link and prevent misjudgment of power due to communication timeout; S3.

2. Configure interrupts via the CAN bus or UART interface to ensure that once "power-downcmd" arrives, the current task flow is interrupted and the power-down process begins. S3.

3. After receiving the power-off command, the MCU's internal state machine switches from the "running state" to the "pre-power-off state", stops non-critical peripherals, and locks RAM data to prevent data inconsistency caused by ongoing write operations; S3.

4. Merge the latest SOC, SOH, number of charge and discharge cycles, remaining capacity and other information into the NVM write cache area and calculate the CRC checksum to ensure the atomicity and integrity of the write. S3.

5. Real-time monitoring of NVM write completion interrupts. When all cached data is confirmed to have been written successfully and the CRC check has passed, the power-off process continues; otherwise, a time-limited retry or an error is recorded.

7. The method for diagnosing abnormal power failure according to claim 3, characterized in that: In the step S4, capacitor discharge control of the normal power-off process: S4.1, in the pre-power-down state, through SPI / I 2 C bus starts NVM writing to ensure that all critical data is securely stored in the chip ROM; S4.2, after the storage completion interrupt arrives, the MCU drives the GPIO to switch the selection switch (2) to the b end and close it, connecting the capacitor to the ground or the discharge resistor; S4.

3. Use the ADC to sample the voltage across the capacitor and monitor its downward discharge slope to verify that the discharge process is stable and free of oscillation. Terminate the discharge after the voltage drops to a safe threshold. S4.

4. After the discharge action is completed and confirmed, the MCU state machine is switched to "off state", all peripheral power supplies are disconnected, the clock is turned off, and the MCU enters sleep mode or power-off mode. S4.

5. Record a "normal power-off" event in NVM and clear temporary flags such as "capacitor charged" to prepare for the next power-on.

8. The method for diagnosing abnormal power failure according to claim 3, characterized in that: In the step S5, abnormal power failure detection power supply switching: S5.1, by detecting the hardware interrupt of the 12V input power supply, the pin captures the falling edge and immediately triggers the abnormal power-off process, without relying on the communication command response; S5.2: Since the normal power-off command is not executed, the selector switch is still in the closed state at end a, automatically connecting the supercapacitor in parallel to the MCU power supply side without the need for additional drive; S5.3, MCU switches to low power mode, adjusts the core frequency to the average operating point (≈ 4.5V / 0.05A), ensuring sustainable operation for about 60s within the remaining capacitor energy range (E≈13.5J); S5.

4. During the capacitor power supply period, the NVM data is stored and verified again according to the cache and write mechanism of the normal power-off process to ensure data integrity during abnormal power outage. S5.

5. The MCU periodically measures the capacitor voltage through a timer and determines the available time based on a preset power model to ensure that all write operations are completed or the device is safely shut down before the power is exhausted.

9. The method for diagnosing abnormal power failure according to claim 3, characterized in that: In the step S6, abnormal diagnosis fault marking: S6.

1. The MCU samples the voltage at the detection point c between the selection switch and the capacitor and compares it with the calibration value of the normal discharge curve to determine whether it is an abnormal discharge state. S6.

2. Accumulate and record continuous abnormal power-off events in NVM, and write context information such as timestamp, SOC, SOH, etc. to build a fault log; S6.

3. Place the abnormal power-off flag (bitmask) in a dedicated status register so that the firmware can quickly identify it and prioritize the fault recovery logic when powering on next time. S6.

4. Synchronously send the diagnostic results to the BMS master control, inform the upper management system of the abnormal power outage through the CAN / UART interface, and recommend countermeasures (check the power line or replace the battery); S6.

5. During the initialization phase after the next MCU power-on, the previous abnormal power-off log is read and reported, and then the fault flag is cleared to prepare for the system to re-enter the initial self-test.

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