Bias circuit and low noise amplifier circuit

Abstract

The invention provides a biasing circuit and a low-noise amplification circuit, and the biasing circuit comprises a reference current source, a first current mirror, a second current mirror, a third current mirror, a first transistor and a voltage generation device. The third current mirror comprises a second transistor assembly and a third transistor; and the second transistor component comprises a plurality of transistors which are sequentially connected in series. According to the biasing circuit, the change degree of the working point current of the amplifying circuit along with the power supply voltage can be reduced, and accurate adjustment of the current under different gain gears can be achieved by adjusting the number and the size of the transistors in the second transistor and the transistor structure in the low-noise amplifier.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and particularly to a bias circuit and a low-noise amplifier circuit. Background Art

[0002] As an important component of a wireless communication system, a low-noise amplifier is mainly used in the radio frequency front end of a wireless communication receiver as the first active device in the radio frequency front end of the wireless communication receiver.

[0003] The low-noise amplifier plays a crucial role in the performance of the wireless communication receiver. To ensure the receiving sensitivity of the wireless communication receiver, generally, the low-noise amplifier is required to have a certain gain to amplify the weak signal received by the antenna, and at the same time, it can effectively suppress the noise of the subsequent stage module, and the low-noise amplifier itself also needs to have very low noise.

[0004] When the wireless communication receiver receives a high-power signal transmitted from the antenna, to ensure that the wireless communication receiver does not suffer from distortion and does not damage the subsequent active devices, the low-noise amplifier is required to have a gain adjustable function. To achieve the gain adjustment of the low-noise amplifier, generally, the size of the amplifying transistor of the low-noise amplifier needs to be adjusted according to the level of the gain, and at the same time, a matching bias circuit is required to provide a bias current to achieve as accurate current biasing as possible.

[0005] In the prior art, the bias circuit of the low-noise amplifier usually supplies the bias of two connected transistor structures separately. Although it can meet certain temperature characteristic requirements, since the bias circuit of one of the transistor structures is composed of a diode in series with a resistor, it inevitably causes a large change in its operating point current with the power supply voltage, which limits its application range to a certain extent and cannot achieve precise adjustment of the current according to different gain requirements. Summary of the Invention

[0006] Aiming at the above deficiencies of the prior art, the present invention proposes a bias circuit and a low-noise amplifier circuit to solve the problems that the operating point current of the bias circuit of the low-noise amplifier in the prior art is prone to large changes with the power supply voltage and cannot achieve precise adjustment of the current according to different gain requirements.

[0007] To solve the above technical problems, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a bias circuit, which includes a reference current source, a first current mirror, a second current mirror, a third current mirror, a first transistor, and a voltage generating device; The input end of the reference current source is used to connect an external power supply; The input terminal of the first current mirror is connected to the output terminal of the reference current source; The first input terminal of the second current mirror and the second input terminal of the second current mirror are respectively used to connect to an external power supply, and the third input terminal of the second current mirror is connected to the output terminal of the first current mirror; The third current mirror includes a second transistor assembly and a third transistor; The second transistor assembly includes a plurality of transistors connected in series in sequence. The input terminal of the second transistor assembly is connected to the output terminal of the second current mirror, and the first output terminal of the second transistor assembly is used to output a first bias voltage; The input terminal of the third transistor is connected to the second output terminal of the second transistor assembly. The first output terminal of the third transistor is grounded, and the second output terminal of the third transistor is used to output a second bias voltage; The first input terminal of the first transistor is used to connect to an external power supply, and the second input terminal of the first transistor is connected to the output terminal of the second current mirror; The first end of the voltage generating device is respectively connected to the output terminal of the first transistor and the second output terminal of the third transistor, and the second end of the voltage generating device is grounded; Preferably, the bias circuit further includes a compensation capacitor. The first end of the compensation capacitor is connected to the output terminal of the second current mirror, and the second end of the compensation capacitor is connected to the second output terminal of the third transistor.

[0008] Preferably, the first transistor is a first field effect transistor; the second transistor assembly includes a plurality of second field effect transistors; the third transistor is a third field effect transistor; The drain of the first field effect transistor serves as the first input terminal of the first transistor, the gate of the first field effect transistor serves as the second input terminal of the first transistor, and the source of the first field effect transistor serves as the output terminal of the first transistor; A plurality of the second field effect transistors form a cascode amplifier structure. The drain of the first of the second field effect transistors serves as the input terminal of the second transistor assembly, the source of the last of the second field effect transistors serves as the second output terminal of the second transistor assembly, and the gates of all the second field effect transistors together serve as the first output terminal of the second transistor assembly; The drain of the third field effect transistor serves as the input terminal of the third transistor, the source of the third field effect transistor serves as the first output terminal of the third transistor, and the gate of the third field effect transistor serves as the second output terminal of the third transistor.

[0009] Preferably, the first current mirror includes a fourth field effect transistor and a fifth field effect transistor; The gate of the fourth field-effect transistor is connected to the drain of the fourth field-effect transistor, the source of the fourth field-effect transistor is grounded, and the drain of the fourth field-effect transistor serves as the input terminal of the first current mirror; The gate of the fifth field-effect transistor is connected to the gate of the fourth field-effect transistor, the source of the fifth field-effect transistor is grounded, and the drain of the fifth field-effect transistor serves as the output terminal of the first current mirror.

[0010] Preferably, the second current mirror includes a sixth field-effect transistor and a seventh field-effect transistor; The gate of the sixth field-effect transistor is connected to the drain of the sixth field-effect transistor, the drain of the sixth field-effect transistor serves as the third input terminal of the second current mirror, and the source of the sixth field-effect transistor serves as the first input terminal of the second current mirror; The gate of the seventh field-effect transistor is connected to the gate of the sixth field-effect transistor, the source of the seventh field-effect transistor serves as the second input terminal of the second current mirror, and the drain of the seventh field-effect transistor serves as the output terminal of the second current mirror.

[0011] Preferably, the first transistor is a first triode; the second transistor assembly includes a plurality of second triodes; the third transistor is a third triode; The collector of the first triode serves as the first input terminal of the first transistor, the base of the first triode serves as the second input terminal of the first transistor, and the emitter of the first triode serves as the output terminal of the first transistor; The collector of the first of the plurality of second triodes connected to each other serves as the input terminal of the second transistor assembly, the emitter of the last of the second triodes serves as the second output terminal of the second transistor assembly, and the bases of all the second triodes together serve as the first output terminal of the second transistor assembly; The collector of the third triode serves as the input terminal of the third transistor, the emitter of the third triode serves as the first output terminal of the third transistor, and the base of the third triode serves as the second output terminal of the third transistor.

[0012] Preferably, the first current mirror includes a fourth triode and a fifth triode; The base of the fourth triode is connected to the collector of the fourth triode, the emitter of the fourth triode is grounded, and the collector of the fourth triode serves as the input terminal of the first current mirror; The base of the fifth triode is connected to the base of the fourth triode, the emitter of the fifth triode is grounded, and the collector of the fifth triode serves as the output terminal of the first current mirror.

[0013] Preferably, the second current mirror includes a sixth triode and a seventh triode; The base of the sixth triode is connected to the collector of the sixth triode. The collector of the sixth triode serves as the third input terminal of the second current mirror, and the emitter of the sixth triode serves as the first input terminal of the second current mirror; The base of the seventh triode is connected to the base of the sixth triode. The emitter of the seventh triode serves as the second input terminal of the second current mirror, and the collector of the seventh triode serves as the output terminal of the second current mirror.

[0014] Preferably, the voltage generating device is an eighth field effect transistor; the drain of the eighth field effect transistor serves as the first end of the voltage generating device, the gate of the eighth field effect transistor is connected to the output terminal of the first current mirror, and the source of the eighth field effect transistor serves as the second end of the voltage generating device.

[0015] Preferably, the voltage generating device is a resistor; the first end of the resistor serves as the first end of the voltage generating device, and the second end of the resistor serves as the second end of the voltage generating device.

[0016] In a second aspect, the present invention provides a low-noise amplifier circuit, which includes a cascode amplifier unit, a first inductor, a second inductor, and the bias circuit as described above; The cascode amplifier unit includes a fourth transistor assembly and a fifth transistor; The fourth transistor assembly includes a plurality of transistors connected in series in sequence. The input terminal of the fourth transistor assembly is connected to the second output terminal of the third transistor; The first input terminal of the fifth transistor is connected to the first output terminal of the fourth transistor assembly, and the second input terminal of the fifth transistor is connected to the first output terminal of the second transistor assembly; The first end of the first inductor is connected to the second output terminal of the fourth transistor assembly, and the second end of the first inductor is grounded; The first end of the second inductor is used to connect to an external power supply, and the second end of the second inductor is connected to the output terminal of the fifth transistor.

[0017] Compared with the prior art, in the bias circuit of the present invention, by designing a reference current source, a first current mirror, a second current mirror, a third current mirror, a first transistor, and a voltage generating device, and defining that the third current mirror includes a second transistor assembly and a third transistor, and defining that the second transistor assembly includes a plurality of transistors connected in series in sequence, when it is applied to a low-noise amplifier, the variation degree of the operating point current of the low-noise amplifier with respect to the power supply voltage can be reduced, and precise adjustment of the current at different gain levels can be achieved by adjusting the number and size of the transistors in the second transistor assembly and the transistors in the low-noise amplifier. Description of the Drawings

[0018] The present invention will be described in detail below with reference to the drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings: Figure 1 FIG. is a circuit schematic diagram of a low-noise amplifier provided by the prior art; Figure 2 FIG. is a circuit schematic diagram of a first low-noise amplifier circuit provided by an embodiment of the present invention, which includes a first bias circuit provided by an embodiment of the present invention; Figure 3 FIG. is a circuit schematic diagram of a second low-noise amplifier circuit provided by an embodiment of the present invention, which includes a second bias circuit provided by an embodiment of the present invention. Detailed Embodiments

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above description of the drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of this application or the above drawings are used to distinguish different objects and not to describe a specific order.

[0020] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] Embodiment 1 An embodiment of the present invention provides a bias circuit 100, as shown in combination with Figure 2 and Figure 3 , which includes a reference current source Iref, a first current mirror 1, a second current mirror 2, a third current mirror 3, a first transistor M1, a voltage generating device 4, and a compensation capacitor C0.

[0023] The input end of the reference current source Iref is used to connect to an external power supply VDD; the reference current source Iref is used to provide a reference current.

[0024] The input end of the first current mirror 1 is connected to the output end of the reference current source Iref.

[0025] The first input end of the second current mirror 2 and the second input end of the second current mirror 2 are respectively used to connect to an external power supply VDD, and the third input end of the second current mirror 2 is connected to the output end of the first current mirror 1.

[0026] The third current mirror 3 includes a second transistor assembly T-B and a third transistor T-A.

[0027] The second transistor assembly T-B includes a plurality of transistors connected in series in sequence. The input end of the second transistor assembly T-B is connected to the output end of the second current mirror 2, and the first output end of the second transistor assembly T-B is used to output a first bias voltage.

[0028] The input end of the third transistor T-A is connected to the second output end of the second transistor assembly T-B. The first output end of the third transistor T-A is grounded, and the second output end of the third transistor T-A is used to output a second bias voltage.

[0029] The first input end of the first transistor M1 is used to connect to an external power supply VDD, and the second input end of the first transistor M1 is connected to the output end of the second current mirror 2.

[0030] The first end of the voltage generating device 4 is connected to the output end of the first transistor M1 and the second output end of the third transistor T-A, and the second end of the voltage generating device 4 is grounded.

[0031] The first terminal of the compensation capacitor C0 is connected to the output terminal of the second current mirror 2, and the second terminal of the compensation capacitor is connected to the second output terminal of the third transistor T-A; wherein, the first terminal of the compensation capacitor C0 is the positive electrode, and the second terminal of the compensation capacitor C0 is the negative electrode.

[0032] In this embodiment, the first transistor M1 is a first field-effect transistor; the second transistor assembly T-B includes a plurality of second field-effect transistors; the third transistor T-A is a third field-effect transistor.

[0033] The drain of the first field-effect transistor serves as the first input terminal of the first transistor M1, the gate of the first field-effect transistor serves as the second input terminal of the first transistor M1, and the source of the first field-effect transistor serves as the output terminal of the first transistor M1.

[0034] The drain of the first of the plurality of second field-effect transistors after being connected to each other serves as the input terminal of the second transistor assembly T-B, the source of the last second field-effect transistor serves as the second output terminal of the second transistor assembly T-B, and the gates of all the second field-effect transistors serve as the first output terminal of the second transistor assembly T-B.

[0035] The plurality of second field-effect transistors form a cascode amplification structure, that is, the drain of one of the two adjacent second field-effect transistors is connected to the source of the other field-effect transistor, and the drain of the first second field-effect transistor after being connected to each other serves as the input terminal of the second transistor assembly T-B, and the source of the last second field-effect transistor after being connected to each other serves as the second output terminal of the second transistor assembly T-B.

[0036] The drain of the third field-effect transistor serves as the input terminal of the third transistor T-A, the source of the third field-effect transistor serves as the first output terminal of the third transistor T-A, and the gate of the third field-effect transistor serves as the second output terminal of the third transistor T-A.

[0037] The first current mirror 1 includes a fourth field-effect transistor T-C and a fifth field-effect transistor T-D.

[0038] The gate of the fourth field-effect transistor T-C is connected to the drain of the fourth field-effect transistor T-C, the source of the fourth field-effect transistor T-C is grounded, and the drain of the fourth field-effect transistor T-C serves as the input terminal of the first current mirror 1.

[0039] The gate of the fifth field-effect transistor T-D is connected to the gate of the fourth field-effect transistor T-C, the source of the fifth field-effect transistor T-D is grounded, and the drain of the fifth field-effect transistor T-D serves as the output terminal of the first current mirror 1.

[0040] The second current mirror 2 includes a sixth field-effect transistor T-E and a seventh field-effect transistor T-F.

[0041] The gate of the sixth field-effect transistor T-E is connected to the drain of the sixth field-effect transistor T-E. The drain of the sixth field-effect transistor T-E serves as the third input terminal of the second current mirror 2, and the source of the sixth field-effect transistor T-E serves as the first input terminal of the second current mirror 2.

[0042] The gate of the seventh field-effect transistor T-F is connected to the gate of the sixth field-effect transistor T-E. The source of the seventh field-effect transistor T-F serves as the second input terminal of the second current mirror 2, and the drain of the seventh field-effect transistor T-F serves as the output terminal of the second current mirror 2.

[0043] In this embodiment, as Figure 2 shown, the voltage generating device 4 is the eighth field-effect transistor M0; the drain of the eighth field-effect transistor M0 serves as the first end of the voltage generating device 4, the gate of the eighth field-effect transistor M0 is connected to the output terminal of the first current mirror 1, and the source of the eighth field-effect transistor M0 serves as the second end of the voltage generating device 4.

[0044] As another alternative embodiment of the voltage generating device 4, as Figure 3 shown, the voltage generating device 4 is the resistor R0; the first end of the resistor R0 serves as the first end of the voltage generating device 4, and the second end of the resistor R0 serves as the second end of the voltage generating device 4.

[0045] The bias circuit 100 in this embodiment is applied to the low-noise amplifier circuit 200 to provide a bias current for the low-noise amplifier circuit 200, that is, Figure 2 and Figure 3 the VB connection points in can serve as the output nodes of the bias circuit 100.

[0046] Compared with the prior art, the bias circuit 100 in this embodiment designs the reference current source Iref, the first current mirror 1, the second current mirror 2, the third current mirror 3, the first transistor M1, and the voltage generating device 4, and defines that the third current mirror 3 includes the second transistor assembly T-B and the third transistor T-A, and defines that the second transistor assembly T-B includes a plurality of transistors connected in series in sequence. In this way, when it is applied to the low-noise amplifier circuit 200, the variation degree of the operating point current of the low-noise amplifier circuit 200 with the power supply voltage can be reduced, and the precise adjustment of the current under different gain levels can be achieved by adjusting the number and size of the transistors in the second transistor assembly T-B and the transistors in the low-noise amplifier circuit 200, which is equivalent to adjusting the number and size of the second field-effect transistor and the ninth field-effect transistor to achieve the precise adjustment of the current under different gain levels.

[0047] Embodiment 2 The difference between the embodiment of the present invention and Embodiment 1 is that the first transistor M1 is the first triode; the second transistor assembly T-B includes a plurality of second triodes; the third transistor T-A is the third triode.

[0048] The collector of the first triode serves as the first input terminal of the first transistor M1, the base of the first triode serves as the second input terminal of the first transistor M1, and the emitter of the first triode serves as the output terminal of the first transistor M1.

[0049] The collector of the first of the multiple second triodes after being interconnected serves as the input terminal of the second transistor assembly T-B, the emitter of the last of the second triodes serves as the second output terminal of the second transistor assembly T-B, and the bases of all the second triodes together serve as the second output terminal of the second transistor assembly T-B.

[0050] The emitter of one of two adjacent second triodes is connected to the collector of the other triode, and the collector of the first second triode after being interconnected serves as the input terminal of the second transistor assembly T-B, and the emitter of the last second triode after being interconnected serves as the second output terminal of the second transistor assembly T-B.

[0051] The collector of the third triode serves as the input terminal of the third transistor T-A, the emitter of the third triode serves as the first output terminal of the third transistor T-A, and the base of the third triode serves as the second output terminal of the third transistor T-A.

[0052] The first current mirror 1 includes a fourth triode and a fifth triode.

[0053] The base of the fourth triode is connected to the collector of the fourth triode, the emitter of the fourth triode is grounded, and the collector of the fourth triode serves as the input terminal of the first current mirror 1.

[0054] The base of the fifth triode is connected to the base of the fourth triode, the emitter of the fifth triode is grounded, and the collector of the fifth triode serves as the output terminal of the first current mirror 1.

[0055] The second current mirror 2 includes a sixth triode and a seventh triode.

[0056] The base of the sixth triode is connected to the collector of the sixth triode, the collector of the sixth triode serves as the third input terminal of the second current mirror 2, and the emitter of the sixth triode serves as the first input terminal of the second current mirror 2.

[0057] The base of the seventh triode is connected to the base of the sixth triode, the emitter of the seventh triode serves as the second input terminal of the second current mirror 2, and the collector of the seventh triode serves as the output terminal of the second current mirror 2.

[0058] In addition, the voltage generating device 4 is an eighth triode; the emitter of the eighth triode serves as the input end of the voltage generating device 4, the base of the eighth triode is connected to the output end of the first current mirror 1, and the collector of the eighth triode serves as the output end of the voltage generating device 4.

[0059] Since in this embodiment, all the field effect transistors in Embodiment 1 are replaced with triodes, and the base of the triode corresponds to the gate of the field effect transistor, the emitter of the triode corresponds to the drain of the field effect transistor, and the collector of the triode corresponds to the source of the field effect transistor; therefore, the bias circuit in this embodiment has basically the same working principle and achieved technical effects as the bias circuit 100 in Embodiment 1, and will not be elaborated here.

[0060] Embodiment 3

[0061] An embodiment of the present invention provides a low-noise amplification circuit 200, which includes a cascode amplification unit 5, a first inductor LS, a second inductor LD, and the bias circuit 100 in Embodiment 1.

[0062] The cascode amplification unit 5 includes a fourth transistor assembly T-M and a fifth transistor T-N; The fourth transistor assembly T-M includes a plurality of transistors connected in series in sequence, and the input end of the fourth transistor assembly T-M is connected to the second output end of the third transistor T-A; The first input end of the fifth transistor T-N is connected to the first output end of the fourth transistor assembly T-M, and the second input end of the fifth transistor T-N is connected to the first output end of the second transistor assembly T-B; The first end of the first inductor LS is connected to the second output end of the fourth transistor assembly T-M, and the second end of the first inductor LS is grounded; The first end of the second inductor LD is used to connect to an external power supply, and the second end of the second inductor LD is connected to the output end of the fifth transistor T-N.

[0063] In this embodiment, the fourth transistor assembly T-M includes a plurality of ninth field effect transistors; the fifth transistor T-N is a tenth field effect transistor.

[0064] All the gates of the plurality of ninth field effect transistors together serve as the first input end of the fourth transistor T-M, the drain of one of the ninth field effect transistors after being connected to each other serves as the first output end of the fourth transistor T-M, and the source of another one of the ninth field effect transistors after being connected to each other serves as the second output end of the fourth transistor T-M.

[0065] Multiple ninth field effect transistors form a cascode amplifier structure, that is, the drain of one of the two adjacent ninth field effect transistors is connected to the source of the other field effect transistor, and the drain of the first ninth field effect transistor after being interconnected serves as the first output terminal of the fourth transistor component T-M, and the source of the last ninth field effect transistor after being interconnected serves as the second output terminal of the fourth transistor component T-M.

[0066] The source of the tenth field effect transistor serves as the first input terminal of the fifth transistor T-N, the gate of the tenth field effect transistor serves as the second input terminal of the fifth transistor T-N, and the drain of the tenth field effect transistor serves as the output terminal of the fifth transistor T-N.

[0067] Figure 1 is a low-noise amplifier circuit of the prior art, Figure 1 In (a), the circuit part is a bias circuit. The field effect transistors T2 and T3 form a cascode main amplification branch. The field effect transistor T3 is a common-source transistor, whose source is connected to the first end of the degeneration inductor L1, the second end of the degeneration inductor L1 is grounded, the source of the field effect transistor T3 is connected to the source of the common-gate field effect transistor T2, the drain of the field effect transistor T3 is connected to the first end of the load inductor L2, and the second end of the load inductor L2 is used to connect to an external power supply Vdd. The input end of the reference current source I is used to connect to an external power supply Vdd, and the output end of the reference current source I is connected to the gate of the field effect transistor T2 through voltage division by the field effect transistor T1 and then through the resistor RB2 to form a current mirror. The magnitude of the current in the main amplification branch is adjusted by adjusting the reference current source I or changing the current mirror ratio. The current mirror ratio is the number of field effect transistors T2 / the number of field effect transistors T1. Figure 1 In (b), the circuit part is a low-noise amplification branch, which is used to generate the bias circuit of the common-gate field effect transistor T2. That is, the vb terminal of the (b) circuit part is connected to the vb1 terminal of the (a) circuit part, and it is mainly composed of the field effect transistor T4 and the series resistors R1-R3. The number of field effect transistors, the number and size of the series resistors can be set according to actual requirements; the divided bias voltage is connected to the vb1 terminal of the (a) circuit part through the vb terminal, and is connected to the gate of the field effect transistor T3 through a low-pass filter composed of RB1 and the capacitor C1. Since the bias circuit of the low-noise amplifier in the prior art is relatively simple, its operating point current is greatly affected by the fluctuation of the power supply voltage, and it is not suitable for some scenarios with high application requirements.

[0068] In the bias circuit 100, the current output by the reference current source Iref flows into the second current mirror 2 after passing through the first current mirror 1, and the current is output after passing through the second current mirror 2. A plurality of second field effect transistors and third field effect transistors form a cascode current mirror, which is used to provide a bias current for the low-noise amplifier circuit 200. Moreover, the number and size of the second field effect transistors and the ninth field effect transistors can be flexibly adjusted. It can be understood that after the number of the second field effect transistors and the ninth field effect transistors is adjusted, the corresponding sizes of the second field effect transistors and the ninth field effect transistors will also change accordingly, so as to meet the gain requirements of different gain levels.

[0069] In order to ensure a good current mirroring relationship, it is necessary to ensure that the ratio of the number M of the ninth field effect transistors to the number A of the third field effect transistors is the same as the ratio of the number B of the second field effect transistors to the number N of the tenth field effect transistors, that is, M / A is equal to B / N. Among them, the sixth field effect transistor T-E, the seventh field effect transistor T-F, the first field effect transistor, the voltage generating device 4, and the fifth field effect transistor T-D together form a negative feedback loop, which is used to stabilize the voltages at the connection node X and the connection node Y. The constancy of the voltages at the connection node X and the connection node Y is beneficial to the constancy of the current of the cascode current mirror composed of a plurality of second field effect transistors and third field effect transistors and the constancy of the current mirrored to the low-noise amplifier circuit 200, and reduces the degree of variation of the operating point current of the low-noise amplifier circuit 200 with the power supply voltage and the process, thereby improving the performance consistency of the bias circuit 100 in the RF front-end module or chip.

[0070] In order to ensure the stability of the negative feedback loop in the bias circuit 100, a compensation capacitor C0 is inserted between the connection node X and the connection node Y. By selecting an appropriate capacitance value, that is, the compensation capacitor C0 is a capacitor with an adjustable capacitance value, the negative feedback loop can work in a stable operating state.

[0071] It is equivalent to that the bias circuit 100 can not only stabilize the DC operating point of the circuit, make the current of the low-noise amplifier circuit 200 be accurately mirrored, but also realize the accurate adjustment of the current under different gain levels by adjusting the number and size of the second field effect transistors and the ninth field effect transistors, so as to meet the mirroring requirements of different currents under different gain levels.

[0072] Since the low-noise amplifier circuit 200 in this embodiment includes the bias circuit 100 in the first embodiment, it can also achieve the technical effects achieved by the bias circuit 100 in the first embodiment, which will not be elaborated here.

[0073] Embodiment 4

[0074] The difference between the low-noise amplifier circuit in this embodiment and the low-noise amplifier circuit 200 in Embodiment 3 is that the low-noise amplifier circuit in this embodiment uses the bias circuit in Embodiment 2. In addition, the fourth transistor assembly T-M and the fifth transistor T-N respectively use bipolar transistors instead of field-effect transistors. At this time, the base of the bipolar transistor in this embodiment corresponds to the gate of the field-effect transistor, the collector of the bipolar transistor corresponds to the drain of the field-effect transistor, and the emitter of the bipolar transistor corresponds to the source of the field-effect transistor.

[0075] Since the low-noise amplifier circuit in this embodiment includes the bias circuit in Embodiment 2, it can also achieve the technical effects achieved by the bias circuit in Embodiment 2, which will not be elaborated here.

[0076] It should be noted that each of the embodiments described above with reference to the accompanying drawings is only used to illustrate the present invention and not to limit the scope of the present invention. Those of ordinary skill in the art should understand that any modification or equivalent replacement made to the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the present invention. In addition, unless otherwise specified in the context, words in the singular form include the plural form, and vice versa. In addition, unless otherwise specified, all or part of any embodiment can be used in combination with all or part of any other embodiment.

Claims

1. A bias circuit, characterized in that: The bias circuit includes a reference current source, a first current mirror, a second current mirror, a third current mirror, a first transistor and a voltage generating device; The input end of the reference current source is used to connect to an external power supply; The input terminal of the first current mirror is connected to the output terminal of the reference current source; The first input terminal of the second current mirror and the second input terminal of the second current mirror are respectively used to connect to an external power supply, and the third input terminal of the second current mirror is connected to the output terminal of the first current mirror; The third current mirror comprises a second transistor component and a third transistor; The second transistor component comprises a plurality of transistors connected in series in sequence, an input terminal of the second transistor component is connected to an output terminal of the second current mirror, and a first output terminal of the second transistor component is used to output a first bias voltage; The input terminal of the third transistor is connected to the second output terminal of the second transistor component, the first output terminal of the third transistor is grounded, and the second output terminal of the third transistor is used to output a second bias voltage; The first input terminal of the first transistor is used to connect to an external power supply, and the second input terminal of the first transistor is connected to the output terminal of the second current mirror; A first terminal of the voltage generating device is connected to the output terminal of the first transistor and the second output terminal of the third transistor, respectively, and a second terminal of the voltage generating device is grounded.

2. The bias circuit according to claim 1, wherein: The bias circuit further includes a compensation capacitor; a first end of the compensation capacitor is connected to the output end of the second current mirror, and a second end of the compensation capacitor is connected to the second output end of the third transistor.

3. The bias circuit according to claim 1, wherein: The first transistor is a first field effect transistor; the second transistor assembly includes a plurality of second field effect transistors; the third transistor is a third field effect transistor; The drain of the first field effect transistor serves as the first input terminal of the first transistor, the gate of the first field effect transistor serves as the second input terminal of the first transistor, and the source of the first field effect transistor serves as the output terminal of the first transistor; A plurality of the second field effect transistors form a common source and common gate amplifier structure, wherein the drain of the first second field effect transistor serves as the input end of the second transistor component, wherein the source of the last second field effect transistor serves as the second output end of the second transistor component, and the gates of all the second field effect transistors serve together as the first output end of the second transistor component; The drain of the third field effect tube serves as the input terminal of the third transistor, the source of the third field effect tube serves as the first output terminal of the third transistor, and the gate of the third field effect tube serves as the second output terminal of the third transistor.

4. The bias circuit according to claim 3, wherein: The first current mirror includes a fourth field effect transistor and a fifth field effect transistor; The gate of the fourth field effect transistor is connected to the drain of the fourth field effect transistor, the source of the fourth field effect transistor is grounded, and the drain of the fourth field effect transistor serves as the input end of the first current mirror; The gate of the fifth field effect transistor is connected to the gate of the fourth field effect transistor, the source of the fifth field effect transistor is grounded, and the drain of the fifth field effect transistor serves as the output end of the first current mirror.

5. The bias circuit according to claim 4, wherein: The second current mirror includes a sixth field effect transistor and a seventh field effect transistor; The gate of the sixth field effect transistor is connected to the drain of the sixth field effect transistor, the drain of the sixth field effect transistor serves as the third input terminal of the second current mirror, and the source of the sixth field effect transistor serves as the first input terminal of the second current mirror; The gate of the seventh field effect tube is connected to the gate of the sixth field effect tube, the source of the seventh field effect tube serves as the second input terminal of the second current mirror, and the drain of the seventh field effect tube serves as the output terminal of the second current mirror.

6. The bias circuit according to claim 1, wherein: The first transistor is a first triode; the second transistor assembly includes a plurality of second triodes; the third transistor is a third triode; The collector of the first triode serves as the first input terminal of the first transistor, the base of the first triode serves as the second input terminal of the first transistor, and the emitter of the first triode serves as the output terminal of the first transistor; The collector of the first of the plurality of second triodes connected to each other serves as the input end of the second transistor assembly, the emitter of the last of the second triodes serves as the second output end of the second transistor assembly, and the bases of all the second triodes serve together as the first output end of the second transistor assembly; The collector of the third triode serves as the input end of the third transistor, the emitter of the third triode serves as the first output end of the third transistor, and the base of the third triode serves as the second output end of the third transistor.

7. The bias circuit according to claim 6, wherein: The first current mirror includes a fourth transistor and a fifth transistor; The base of the fourth triode is connected to the collector of the fourth triode, the emitter of the fourth triode is grounded, and the collector of the fourth triode serves as the input end of the first current mirror; The base of the fifth transistor is connected to the base of the fourth transistor, the emitter of the fifth transistor is grounded, and the collector of the fifth transistor serves as the output end of the first current mirror.

8. The bias circuit according to claim 7, wherein: The second current mirror includes a sixth transistor and a seventh transistor; The base of the sixth transistor is connected to the collector of the sixth transistor, the collector of the sixth transistor serves as the third input terminal of the second current mirror, and the emitter of the sixth transistor serves as the first input terminal of the second current mirror; The base of the seventh transistor is connected to the base of the sixth transistor, the emitter of the seventh transistor serves as the second input terminal of the second current mirror, and the collector of the seventh transistor serves as the output terminal of the second current mirror.

9. The bias circuit according to claim 1, wherein: The voltage generating device is an eighth field effect transistor; the drain of the eighth field effect transistor serves as the first end of the voltage generating device, the gate of the eighth field effect transistor is connected to the output end of the first current mirror, and the source of the eighth field effect transistor serves as the second end of the voltage generating device.

10. The bias circuit according to claim 1, wherein: The voltage generating device is a resistor; the first end of the resistor serves as the first end of the voltage generating device, and the second end of the resistor serves as the second end of the voltage generating device.

11. A low noise amplifier circuit, characterized in that: The low-noise amplifier circuit comprises a common-source and common-gate amplifier unit, a first inductor, a second inductor, and a bias circuit as claimed in any one of claims 1 to 10; The cascode amplification unit comprises a fourth transistor component and a fifth transistor; The fourth transistor component includes a plurality of transistors connected in series in sequence, and the input end of the fourth transistor component is connected to the second output end of the third transistor; The first input terminal of the fifth transistor is connected to the first output terminal of the fourth transistor component, and the second input terminal of the fifth transistor is connected to the first output terminal of the second transistor component; A first end of the first inductor is connected to a second output end of the fourth transistor component, and a second end of the first inductor is grounded; A first end of the second inductor is used to be connected to an external power source, and a second end of the second inductor is connected to an output end of the fifth transistor.

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