Resource mapping method, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a resource mapping method, electronic equipment and a computer readable storage medium. The method comprises the steps of performing topological sorting on to-be-mapped actions according to a dependency relationship between the to-be-mapped actions and a meta-heuristic algorithm; according to a topological sorting result, determining the assembly line total stage number occupied by the to-be-mapped action; wherein the assembly line corresponds to a logic state in a reconfigurable matching table (RMT) architecture, and the RMT architecture comprises a plurality of cascaded logic states.

Description

Technical Field

[0001] This application relates to the technical field of programmable networks, and particularly to a resource mapping method, an electronic device, and a computer-readable storage medium. Background Art

[0002] To solve the problem that traditional forwarding plane chips have fixed functions and cannot expand new protocols, Nick McKeown et al. proposed the Reconfigurable Match Action (RMT) architecture and the programmable protocol-independent packet processing language P4, which have performance comparable to that of fixed forwarding chips. Since its birth, P4 has received extensive attention and research in the academic and industrial fields and has been used in areas such as load balancing, network measurement, network supervision and diagnosis, and in-network computing. The P4 language has three major characteristics: reconfigurability, protocol independence, and target independence.

[0003] The P4 compiler is the core tool in the P4 development process and is the bridge connecting the P4 program and the underlying forwarding chip. The forwarding plane application programs developed in the P4 language have the characteristic of being hardware-independent and can only be adapted to different hardware forwarding platforms through translation by the target-related P4 compiler. The P4 development process is as Figure 1 shown, including three stages: P4 program development, static compilation, and runtime table entry management.

[0004] P4 Program Development: P4 programmers develop P4 programs and define the parsing method and processing flow of packets.

[0005] Static Compilation: The P4 compiler compiles the P4 program to generate a parser and match table configuration, as well as a control plane application program interface (API). The parser and match table configuration are the basic configurations for programmable forwarding chips, and the control plane API is used for interaction between the control plane and the forwarding plane.

[0006] Runtime Table Entry Management: After loading the parser and match table configurations generated by static compilation into the forwarding plane. In the running stage, the control plane can drive the issuance, deletion, and modification of table entries through the control plane API, and can also query the content of table entries.

[0007] Among them, the P4 language is designed to support target switches with different architectures, and the RMT switching architecture is one of the most representative ones. The RMT architecture has forwarding capabilities comparable to those of fixed forwarding chips, relatively flexible programmable capabilities, and low power consumption, and is one of the mainstream architectures for programmable forwarding chips. As Figure 2As shown in the figure, the hardware of the RMT architecture consists of three modules: a parser, a multi-stage pipeline, and a deparser. The parser module is used to parse packets. The multi-stage pipeline part corresponds to a cascade of multiple logical stages for modifying packets and making forwarding decisions. The deparser is used to reassemble packets. When the P4 compiler converts a P4 program into the underlying configuration of the RMT architecture hardware, a core function is to map the table entries, actions, etc. in the P4 program to each stage of the RMT pipeline under the conditions of satisfying the dependency relationship and hardware constraints. Since the RMT architecture hardware often has various complex resource constraints, this resource mapping process is a major challenge for the P4 compiler.

[0008] In related technologies, although resource mapping algorithms such as those based on integer linear programming and those based on greedy strategies are provided, they all have certain limitations. For example, although the resource mapping algorithm based on integer linear programming has high resource utilization, its algorithm time complexity is high and it cannot be applied to large-scale problems. While the resource mapping algorithm based on the strategy has high execution efficiency, its resource utilization is low. Summary of the Invention

[0009] The purpose of the embodiments of the present application is to provide a resource mapping method, an electronic device, and a computer-readable storage medium, which can improve the resource utilization while reducing the time complexity of resource mapping.

[0010] To solve the above technical problems, the embodiments of the present application are implemented through the following aspects.

[0011] In a first aspect, the embodiments of the present application provide a resource mapping method, including: performing topological sorting on each of the actions to be mapped according to the dependency relationship between the actions to be mapped and a meta-heuristic algorithm; determining the total number of pipeline stages occupied by the actions to be mapped according to the topological sorting result; where the pipeline corresponds to the logical states in the reconfigurable match table (RMT) architecture, and the RMT architecture includes a cascade of multiple logical states.

[0012] In a second aspect, the embodiments of the present application provide a resource mapping device, including: a sorting module, configured to perform topological sorting on each of the actions to be mapped according to the dependency relationship between the actions to be mapped and a meta-heuristic algorithm; a determining module, configured to determine the total number of pipeline stages occupied by the actions to be mapped according to the topological sorting result; where the pipeline corresponds to the logical states in the reconfigurable match table (RMT) architecture, and the RMT architecture includes a cascade of multiple logical states.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor, and computer-executable instructions stored on the memory and executable on the processor. When the computer-executable instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0014] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer-executable instructions. When the computer-executable instructions are executed by a processor, the steps of the method described in the first aspect are implemented.

[0015] In the embodiment of the present application, by applying a metaheuristic algorithm for P4 compiler resource mapping, multiple topological sorting results of the dependency relationships of the actions to be mapped can be searched. Thus, not only can the time complexity in the resource mapping process be effectively reduced to be applicable to large-scale problems, but also the resource utilization efficiency in the resource mapping process can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Shows a schematic diagram of a P4 development process.

[0018] Figure 2 Shows a schematic diagram of an RMT architecture.

[0019] Figure 3 Shows one of the schematic flowcharts of the resource mapping method provided by the embodiment of the present application.

[0020] Figure 4a Shows another schematic flowchart of the resource mapping method provided by the embodiment of the present application.

[0021] Figure 4b Shows yet another schematic flowchart of the resource mapping method provided by the embodiment of the present application.

[0022] Figure 5 Shows a schematic structural diagram of the resource mapping device provided by the embodiment of the present application.

[0023] Figure 6 Is a schematic hardware structure diagram of an electronic device for executing the resource mapping method provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To enable those skilled in the art to better understand the technical solutions in this application, the following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without making creative efforts shall fall within the protection scope of this application.

[0025] Figure 3 FIG. 4 shows a schematic flowchart of a resource mapping method 300 provided by an embodiment of this application. This method 300 can be executed by an electronic device, such as a terminal device or a server device. In other words, the method 300 can be executed by software or hardware installed on a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc. As Figure 3 shown, this method may include the following steps.

[0026] It should be noted that the electronic device may but is not limited to be configured with a P4 compiler, and the resource mapping method provided in this application may also be but is not limited to the resource mapping for a P4 compiler. For ease of understanding, the resource mapping process provided in this application will be described below by taking the P4 compiler as an example.

[0027] S310, perform a topological sort on each of the actions to be mapped according to the dependency relationship between the actions to be mapped and a meta-heuristic algorithm.

[0028] Among them, the dependency relationship between the actions to be mapped can be configured during P4 program development. In this embodiment, the dependency relationship between the actions to be mapped can be but is not limited to being represented by a dependency graph. Optionally, according to different application scenarios, the actions to be mapped can be actions for data processing, data forwarding, etc., which are not limited here.

[0029] The meta-heuristic algorithm includes but is not limited to single-agent intelligent algorithms and swarm intelligent algorithms, etc. The single-agent intelligent algorithms include but are not limited to simulated annealing algorithms, tabu search algorithms, etc.

[0030] The swarm intelligent algorithms include but are not limited to genetic algorithms, ant colony algorithms, particle swarm algorithms, etc.

[0031] It should be noted that when performing topological sorting on each of the to-be-mapped actions according to the dependencies between the to-be-mapped actions and the metaheuristic algorithm, the initialization parameters corresponding to different metaheuristic algorithms are different. For example, for the simulated annealing algorithm, the parameters that need to be initialized can include but are not limited to: the number of iterations per temperature, the number of repeated temperature drops, the temperature reduction coefficient, and the initial temperature; for another example, for the ant colony algorithm, the parameters that need to be initialized include: the number of ants, the visibility of pheromone concentration, the visibility of heuristic factor, the pheromone evaporation rate, the number of iterations, etc.

[0032] In addition, the selection of the metaheuristic algorithm can be determined according to the resource mapping requirements, and no limitation is imposed here.

[0033] In some embodiments, the process of "performing topological sorting on each of the to-be-mapped actions according to the dependencies between the to-be-mapped actions and the metaheuristic algorithm" in S310 may include: performing topological sorting on each of the to-be-mapped actions according to the dependencies between the to-be-mapped actions, the metaheuristic algorithm, and the path priority strategy. That is to say, when performing the topological sorting, it can be carried out according to the path priority principle, so as to improve the execution efficiency of subsequent resource mapping.

[0034] For example, in this embodiment, the path priority strategy may include but is not limited to the longest path first strategy or the shortest path first strategy, etc. When the dependencies between the to-be-mapped actions are represented by a dependency graph, the to-be-mapped actions on the longest path in the dependencies can be preferentially arranged during topological sorting.

[0035] S320, determine the total number of pipeline stages occupied by the to-be-mapped actions according to the topological sorting result.

[0036] Among them, the total number of pipeline stages can be understood as: the pipeline corresponding to each to-be-mapped action and the total number of pipelines occupied by all to-be-mapped actions. The pipeline corresponds to the logical states in the RMT architecture, and the RMT architecture includes a plurality of cascaded logical states. Please refer to again Figure 2 , in this embodiment, the to-be-mapped actions are mapped to different logical states in the RMT architecture in the way of resource mapping through the P4 compiler, so as to implement subsequent modification of packets, forwarding decisions, etc.

[0037] In this embodiment, by applying the metaheuristic algorithm for P4 compiler resource mapping, multiple topological sorting results of the dependencies of the to-be-mapped actions can be searched. Therefore, not only can the time complexity in the resource mapping process be effectively reduced to be applicable to large-scale problems, but also the resource utilization efficiency in the resource mapping process can be improved.

[0038] In some embodiments, there can be various processes for "determining the total number of pipeline stages occupied by the to-be-mapped action according to the topological sorting result" in S320. For example, each node corresponding to the to-be-mapped action can be traversed in sequence according to the topological sorting result. Then, during the traversal process, the pipeline stage number mapped by the second node is determined according to the pipeline stage number mapped by the first node, and when the pipeline stage number mapped by the second node meets the resource constraint conditions, the second node is added to the resource reservation list to complete the resource mapping of the second node; wherein, in the dependency relationship, the first node is adjacent to the second node and is the upstream node or the preceding node of the second node. The correspondence between the node and the to-be-mapped action can be understood as: when performing topological sorting, one to-be-mapped action corresponds to one node.

[0039] Alternatively, when the pipeline stage number mapped by the second node does not meet the resource constraint conditions, the second node is continuously mapped to the next-level pipeline until the pipeline stage number mapped by the second node meets the resource constraint conditions, and the second node that meets the resource constraint conditions is added to the resource reservation list.

[0040] For example, if the pipeline stage number (or logical state) mapped by the first node is n, then, the pipeline stage number mapped by the second node can be tentatively determined to be at least n + 1, and it is judged whether the pipeline stage number n + 1 mapped by the second node meets the resource constraint conditions. If it meets the resource constraint conditions, then, the pipeline stage number n + 1 mapped by the second node can be determined and added to the resource reservation list; if it does not meet the resource constraint conditions, then, it is continuously judged whether the pipeline stage number n + 2 mapped by the second node meets the resource constraint conditions. If it meets the resource constraint conditions, then, the pipeline stage number n + 2 mapped by the second node can be determined and added to the resource reservation list; if it does not meet the resource constraint conditions, then, it is continuously judged whether the pipeline stage number n + 3 mapped by the second node meets the resource constraint conditions. The foregoing steps are repeated until the pipeline stage number mapped by the second node meets the resource constraint conditions, and the second node that meets the resource constraint conditions is added to the resource reservation list.

[0041] Optionally, the foregoing resource constraint conditions are related to the resources in the RMT architecture. For example, the resource constraint conditions can include, but are not limited to, that the resource size and resource type of the pipeline stage number mapped by the second node meet the hardware resource conditions on the RMT architecture.

[0042] Exemplarily, the implementation process of "determining the total number of pipeline stages occupied by the action to be mapped according to the topological sorting result" is described exemplarily in the form of pseudocode as shown in 1)-7) below.

[0043] 1) Initialize an empty resource reservation list RT;

[0044] 2) Traverse each node n in sequence according to the topological sorting result; where the node corresponds to the action to be mapped.

[0045] 3) s = max e＝p→n∈E {S(p) + 1}; / * Determine at least which stage the second node n (or the current node or this node) is based on which stage the first node p in the dependency graph of the action to be mapped is in the pipeline. s is the pipeline stage corresponding to the second node n, S(p) is the pipeline stage corresponding to the first node n, e is the edge formed by the second node and the first node in the dependency graph, and E is the set of edges formed by different nodes in the dependency graph * /

[0046] 4) While adding the resources of the second node n to RT violates the resource constraint conditions, such as resource size and resource category.

[0047] 5) s = s + 1; / / Move backward by stages until the resource constraint conditions are met.

[0048] 6) S(n) = s; / / Map the second node n to the s-th stage.

[0049] 7) Add the resources of the second node n to RT[s].

[0050] It can be understood that the maximum number of stages of the mapping obtained by executing 1)-7) above is the total number of pipeline stages occupied.

[0051] Based on this, as a possible implementation, after determining the total number of pipeline stages occupied by the action to be mapped according to the topological sorting result, it is possible to continue to determine whether the end condition is met. In the case of meeting the end condition, determine the resource mapping result according to the total number of pipeline stages. That is to say, in the case of meeting the end condition, determine that the resource mapping process ends, and the total number of pipeline stages occupied by the action to be mapped can be used as the resource mapping result.

[0052] Alternatively, in the case of not meeting the end condition, update the topological sorting result according to the total number of pipeline stages, and continue to determine the total number of pipeline stages occupied by the action to be mapped based on the updated topological sorting result until the end condition is met.

[0053] That is to say, when the end condition is not met, the total number of pipeline stages occupied by the to-be-mapped action can be used as a cost to guide the update of the topological sorting result, and based on the updated topological sorting result, continue to determine the total number of pipeline stages occupied by the to-be-mapped action until the end condition is met.

[0054] Among them, for different metaheuristic algorithms, the process of updating the topological sorting result according to the total number of pipeline stages may be different. For example, for the simulated annealing algorithm, if the current cost function value is lower than the cost function value determined last time, directly accept the current cost function value; otherwise, accept the previous cost function value with a certain probability.

[0055] For another example, for the ant colony algorithm, increase the pheromone concentration inversely proportional to the previous cost function value on the path passed by the current ant individual, so that the pheromone concentration on the path with a lower cost function value is higher.

[0056] Optionally, the foregoing end condition may include but is not limited to at least one of the following a)-d).

[0057] a) The number of algorithm iterations reaches a first value.

[0058] b) The total number of pipeline stages meets the preset number of pipeline stages of the chip.

[0059] c) The number of algorithm iterations reaches a second value and no total number of pipeline stages with a cost function value meeting the predetermined requirements is found.

[0060] d) The number of algorithm iterations does not reach a third value, but the difference between the cost function values corresponding to the total number of pipeline stages in different iterations is less than a predetermined value.

[0061] Among them, the foregoing number of algorithm iterations can be understood as: the number of times of determining the total number of pipeline stages occupied by the to-be-mapped action according to the topological sorting result. In addition, the foregoing first value, second value, and third value may be the same or different, and are not limited herein.

[0062] Based on the description of the foregoing method embodiment 300, the implementation process of the foregoing resource mapping method is described below by way of Example 1 and Example 2, and the content is as follows.

[0063] Example 1

[0064] S411, as shown in 4a, initialize the parameters of the metaheuristic algorithm.

[0065] S412, perform topological sorting on each of the to-be-mapped actions according to the dependency relationship between the to-be-mapped actions and the metaheuristic algorithm.

[0066] S413. Determine the total number of pipeline stages occupied by the action to be mapped according to the topological sorting result.

[0067] S414. Determine whether the end condition is satisfied. If the end condition is satisfied, execute S415; otherwise, execute S416.

[0068] S415. Determine the resource mapping result according to the total number of pipeline stages.

[0069] S416. Update the topological sorting result according to the total number of pipeline stages, and continue to determine the total number of pipeline stages occupied by the action to be mapped based on the updated topological sorting result.

[0070] Example 2

[0071] In this Example 2, taking the meta - heuristic algorithm as the ant algorithm, the resource mapping method provided by this application is exemplarily described.

[0072] S421. As Figure 4b shown, initialize the parameters of the ant algorithm.

[0073] Among them, for the ant algorithm, the parameters that need to be initialized include constants such as the pheromone table, the number of ants, and the maximum number of iterations. In this Example 2, assuming the number of ants is M and the number of nodes to be arranged is N, the pheromone table is a two - dimensional matrix of N×N. The initial value of the pheromone table from node i to node j can be determined according to the following formula (1).

[0074]

[0075] Among them, S min represents the required shortest number of pipeline stages, which can be estimated by the greedy heuristic algorithm.

[0076] S422. Clear the path information of ant individuals.

[0077] Among them, during the iteration process, when starting a new iteration, it is necessary to clear the path information of the ants that have passed.

[0078] S423. Determine the topological sorting result.

[0079] Among them, when selecting the next node for each ant, first, the optional nodes need to be obtained. The optional nodes need to satisfy that all their direct predecessors (adjacent upstream nodes) in the dependency graph have been selected to ensure that the path sorting result is a topological sorting result with a dependency relationship. Then, the probability of each optional node being selected is obtained according to the following formula (2):

[0080]

[0081] Among them, in formula (2), represents the probability that the k-th ant selects node j at the i-th step, and τ ij (t) represents the pheromone intensity of selecting node j at the i-th step, and γ ij represents visibility, which is defined as γ ij = RD j / RD, where RD j is the reverse depth of the j-th node in the dependency graph, RD is the length of the longest path in the dependency graph, allowed is the set of optional nodes, and α and β are the weights of the pheromone concentration and visibility. After obtaining the probability of each node being selected, the roulette wheel method is used to select the final node. As can be seen from the above formula (2), the higher the pheromone concentration of a node, the greater the probability of being selected.

[0082] Based on this, when each ant has traversed all nodes, one iteration process ends. At this time, each ant has recorded the path it has walked, and a path is a topological sorting result of the nodes.

[0083] S424. Determine the total number of pipeline stages occupied by the action to be mapped.

[0084] Among them, the total number of pipeline stages occupied by the action to be mapped is determined based on each of the topological sorting results.

[0085] S425. Determine whether the termination condition is satisfied.

[0086] Among them, the termination condition adopted in this Example 2 can be that the number of algorithm iterations reaches a first value, that is, the termination condition is that the number of algorithm iterations reaches the maximum first value. Then, when the number of algorithm iterations reaches the first value, execute S426, otherwise execute S427.

[0087] S426. Output the total number of pipeline stages with the lowest cost as the final resource mapping result.

[0088] S427. Update the pheromone concentration at the cost of the total number of pipeline stages. Based on the updated pheromone concentration, re-execute S422 - S425 until the termination condition is satisfied. For example, after obtaining the total number of pipeline stages corresponding to the topological sorting results of each ant, the pheromone table can be updated according to the following formula (3).

[0089]

[0090] Among them, ρ in formula (3) represents the pheromone evaporation rate, which is defined as shown in the following formula (4).:

[0091]

[0092] S in formula (4) k is the total number of pipeline stages corresponding to the topological sorting result corresponding to the k-th ant.

[0093] It can be understood that the resource mapping method provided in the foregoing Examples 1-2 may include but is not limited to the foregoing steps, such as more or fewer steps than the foregoing, which are not limited herein.

[0094] In addition, the implementation process of the resource mapping method in the foregoing Examples 1-2 may refer to the relevant descriptions in the foregoing Method Embodiment 300 and achieve the same or corresponding technical effects, which are not limited herein.

[0095] The resource mapping method provided in this application searches for multiple topological sorting results of the dependency relationships of the actions to be mapped, and performs resource mapping based on the topological sorting results. Therefore, it can have higher resource utilization compared to the mapping algorithm based on the greedy strategy. At the same time, its complexity is polynomial time complexity, which can be applied to large-scale problems and also has high comprehensive performance.

[0096] Figure 5 The structural schematic diagram of the resource mapping device 500 provided in the embodiment of this application is shown. The device 500 includes: a sorting module 510, configured to perform topological sorting on each of the actions to be mapped according to the dependency relationships between the actions to be mapped and a metaheuristic algorithm; a determination module 520, configured to determine the total number of pipeline stages occupied by the actions to be mapped according to the topological sorting result; wherein, the pipeline corresponds to the logical states in the RMT architecture, and the RMT architecture includes a plurality of cascaded logical states.

[0097] Optionally, the determination module 520 determines the total number of pipeline stages occupied by the actions to be mapped according to the topological sorting result, including: traversing each node in sequence according to the topological sorting result, where the node corresponds to the action to be mapped; during the traversing process, determining the pipeline stage mapped by the second node according to the pipeline stage mapped by the first node, and when the pipeline stage mapped by the second node satisfies the resource constraint condition, adding the second node to the resource reservation list to complete the resource mapping of the second node; wherein, in the dependency relationship, the first node is adjacent to the second node and is the upstream node of the second node.

[0098] Optionally, the determination module 520 determining the total number of pipeline stages occupied by the actions to be mapped according to the topological sorting result further includes: when the pipeline stage mapped by the second node does not satisfy the resource constraint condition, continuing to map the second node to the next-level pipeline until the pipeline stage mapped by the second node satisfies the resource constraint condition, and adding the second node that satisfies the resource constraint condition to the resource reservation list.

[0099] Optionally, after determining the total number of pipeline stages occupied by the to-be-mapped action according to the topological sorting result, the determining module 520 is further configured to determine whether an end condition is satisfied; and in the case where the end condition is satisfied, determine a resource mapping result according to the total number of pipeline stages.

[0100] Optionally, the determining module 520 is further configured to, in the case where the end condition is not satisfied, update the topological sorting result according to the total number of pipeline stages; continue to determine the total number of pipeline stages occupied by the to-be-mapped action based on the updated topological sorting result until the end condition is satisfied.

[0101] Optionally, the end condition includes at least one of the following: the number of algorithm iterations reaches a first value; the total number of pipeline stages satisfies a preset chip pipeline stage number; the number of algorithm iterations reaches a second value and no total number of pipeline stages with a cost function value satisfying a predetermined requirement is found; the number of algorithm iterations does not reach a third value, but the difference between the cost function values corresponding to the total number of pipeline stages in different iterations is less than a predetermined value.

[0102] Optionally, the sorting module 510 performs topological sorting on each of the to-be-mapped actions according to the dependency relationship between the to-be-mapped actions and a metaheuristic algorithm, including: performing topological sorting according to the dependency relationship between the to-be-mapped actions, the metaheuristic algorithm, and a path priority strategy.

[0103] Optionally, the path priority strategy includes a longest path first strategy.

[0104] The apparatus 500 provided in the embodiments of the present application can execute the various methods described in the foregoing method embodiments, and implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.

[0105] Figure 6 FIG. shows a schematic hardware structure diagram of an electronic device provided in the embodiments of the present application. Referring to this figure, at the hardware level, the electronic device includes a processor, and optionally, an internal bus, a network interface, and a memory. Among them, the memory may include a memory, such as a high-speed random access memory (Random-Access Memory, RAM), and may also include a non-volatile memory, such as at least one disk memory, etc. Of course, the electronic device may also include other hardware required for other services.

[0106] The processor, network interface, and memory can be interconnected through an internal bus, which can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, only a bidirectional arrow is used in this figure, but it does not mean that there is only one bus or one type of bus.

[0107] A memory for storing programs. Specifically, the program can include program code, and the program code includes computer operation instructions. The memory can include a memory and a non-volatile memory, and provides instructions and data to the processor.

[0108] The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating a specified user at the logical level. The processor executes the program stored in the memory and is specifically used to execute: Figure 3 The methods disclosed in the illustrated embodiments and implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.

[0109] The above as in this application Figure 3The method disclosed in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0110] The electronic device can also execute the various methods described in the foregoing method embodiments and achieve the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.

[0111] Of course, in addition to the software implementation manner, the electronic device of the present application does not exclude other implementation manners, such as a logic device or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, and may also be hardware or a logic device.

[0112] The embodiments of the present application also propose a computer-readable storage medium. The computer-readable medium stores one or more programs. When the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to execute Figure 3 the method disclosed in the illustrated embodiment and achieve the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be elaborated herein.

[0113] Among them, the computer-readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disc, and the like.

[0114] Furthermore, an embodiment of the present application also provides a computer program product. The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the following process is implemented: Figures 1-3 The method disclosed in the illustrated embodiment realizes the functions and beneficial effects of each method described in the foregoing method embodiments, and will not be elaborated herein.

[0115] In summary, the above are only the preferred embodiments of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0116] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0117] Computer-readable media includes both permanent and non-permanent, removable and non-removable media and can be implemented by any method or technology for storing information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0118] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising said element.

[0119] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the relevant content.

Claims

1. A resource mapping method, characterized in that, it includes: Performing topological sorting on each of the to-be-mapped actions according to the dependency relationship between the to-be-mapped actions and a metaheuristic algorithm; Determining the total number of pipeline stages occupied by the to-be-mapped actions according to the topological sorting result; Wherein, the pipeline corresponds to the logical states in a reconfigurable matching table (RMT) architecture, and the RMT architecture includes a plurality of cascaded logical states.

2. The method according to claim 1, characterized in that, the determining the total number of pipeline stages occupied by the to-be-mapped actions according to the topological sorting result includes: Traversing each node in sequence according to the topological sorting result, where the node corresponds to the to-be-mapped action; During the traversing process, determining the pipeline stage mapped by a second node according to the pipeline stage mapped by a first node, and when the pipeline stage mapped by the second node satisfies the resource constraint condition, adding the second node to a resource reservation list to complete the resource mapping of the second node; Wherein, in the dependency relationship, the first node is adjacent to the second node and is the upstream node of the second node.

3. The method according to claim 2, characterized in that, the determining the total number of pipeline stages occupied by the to-be-mapped actions according to the topological sorting result further includes: When the pipeline stage mapped by the second node does not satisfy the resource constraint condition, continuing to map the second node to the next-level pipeline until the pipeline stage mapped by the second node satisfies the resource constraint condition, and adding the second node that satisfies the resource constraint condition to the resource reservation list.

4. The method according to any one of claims 1-3, characterized in that, after the determining the total number of pipeline stages occupied by the to-be-mapped actions according to the topological sorting result, the method further includes: Determining whether an end condition is satisfied; When the end condition is satisfied, determining a resource mapping result according to the total number of pipeline stages.

5. The method according to claim 4, characterized in that, the method further includes: When the end condition is not satisfied, updating the topological sorting result according to the total number of pipeline stages; Based on the updated topological sorting result, continuing to determine the total number of pipeline stages occupied by the to-be-mapped actions until the end condition is satisfied.

6. The method according to claim 4, characterized in that, the end condition includes at least one of the following: The number of algorithm iterations reaches a first value; The total number of pipeline stages satisfies a preset chip pipeline stage number; The number of algorithm iterations reaches a second value and no total number of pipeline stages with a cost function value satisfying a predetermined requirement is found; The number of algorithm iterations does not reach a third value, but the difference between the cost function values corresponding to the total number of pipeline stages in different iterations is less than a predetermined value.

7. The method according to claim 5, characterized in that, the performing topological sorting on each of the to-be-mapped actions according to the dependency relationship between the to-be-mapped actions and a metaheuristic algorithm includes: Performing topological sorting according to the dependency relationship between the to-be-mapped actions, the metaheuristic algorithm, and a path priority strategy.

8. The method according to claim 7, wherein, the path priority policy includes the longest path first policy.

9. An electronic device, wherein, it includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the computer program is executed by the processor, it implements the steps of the resource mapping method according to any one of claims 1-8.

10. A computer-readable medium, wherein, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the resource mapping method according to any one of claims 1-8.

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