A risc-v processor download debugging method and system based on an FPGA-JTAG interface

Abstract

The application provides a RISC-V processor download debugging method and system based on an FPGA-JTAG interface, and the method comprises the following steps: based on a boundary scan register address and a bit width, modifying boundary scan configuration code related to an FPGA chip in host computer source code; based on the boundary scan register, modifying the cfg configuration code of the host computer to be configured as a boundary scan mode; constructing a data packet containing a boundary scan register address, a debugging instruction and debugging data by the host computer, and transmitting the data packet to a data parsing module through an FPGA-JTAG interface; according to the data packet format, analyzing a TDI signal, and switching a TAP state machine state through a control TMS signal to realize the debugging of the RISC-V processor. The application realizes the debugging by multiplexing the FPGA-JTAG interface, improves the debugging efficiency and reliability, simplifies the hardware design, and reduces the system cost.

Description

Technical Field

[0001] This application belongs to the field of processor debugging design technology, and in particular relates to a RISC-V processor download and debugging method and system based on FPGA-JTAG interface. Background Technology

[0002] RISC-V, or Reduced Instruction Set Computer V, is an open instruction set architecture (ISA) proposed in 2010. Compared to traditional instruction sets such as ARM and x86, RISC-V's advantage lies in its royalty-free openness, which greatly lowers the barrier to processor innovation, allowing more developers to participate in processor design and application. Furthermore, RISC-V allows users to customize instruction set extensions according to specific needs, thus enabling processor customization for different application scenarios.

[0003] In the RISC-V ecosystem, debugging techniques are crucial for processor design and software development. Debugging systems empower developers with deep insight into and control over the processor's state, including but not limited to setting breakpoints, single-stepping, and viewing and modifying register and memory contents. These features greatly facilitate developers in discovering and fixing potential errors.

[0004] However, the debugging process for RISC-V processor soft cores currently running on FPGA (Field Programmable Gate Array) chips presents certain inconveniences. Specifically, existing download and debugging methods rely on external I / O connections, which necessitates frequent hot-swapping operations during debugging. This not only increases the complexity of debugging but may also damage the device. Therefore, a solution is needed to address these inconveniences and improve debugging efficiency.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] This application discloses a RISC-V processor download and debugging method system based on the FPGA-JTAG interface. By reusing the FPGA-JTAG interface, it can avoid the waste caused by using external IO resources and the complexity of the debugging process, thereby improving debugging efficiency and reliability.

[0007] Other objectives and advantages of this application can be further understood from the technical features disclosed herein.

[0008] To achieve one, some, or all of the above objectives or other objectives, in a first aspect, this application provides a method for downloading and debugging a RISC-V processor based on an FPGA-JTAG interface, the method comprising:

[0009] Based on the boundary scan register address and bit width of the FPGA chip, modify the boundary scan configuration code related to the FPGA chip in the host computer source code;

[0010] Based on the boundary scan register of the FPGA chip, modify the cfg configuration code of the host computer to configure the host computer into boundary scan mode;

[0011] The host computer structure contains a data packet containing the boundary scan register address, debugging instructions, and debugging data, which is then transmitted to the data parsing module via the FPGA-JTAG interface.

[0012] The TDI signal is parsed according to the format of the data packet to obtain the parsing result. The TMS signal is then controlled to switch the state of the TAP state machine according to the parsing result, thereby realizing the debugging of the RISC-V processor.

[0013] Furthermore, the modification of the host computer's cfg configuration code includes at least: defining the access mode of the boundary scan register, setting the chain order, and configuring the length of the scan chain in the cfg configuration code.

[0014] Furthermore, when the host computer is in boundary scan mode, it transmits data packets to the boundary scan register through the FPGA-JTAG interface, obtains the data type and bit width based on the TDI signal parsing, and controls the changes in the TMS signal to switch the state of the TAP state machine according to the data type and bit width.

[0015] Furthermore, when the TAP state machine is in the shift instruction register state, the boundary scan register address is input through the TDI signal and transmitted to the boundary scan register through the FPGA-JTAG interface.

[0016] Furthermore, when the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debugging instructions and the debugging data to the data parsing module through the FPGA-JTAG interface.

[0017] Furthermore, when the TAP state machine is in the shift instruction register state or the shift data register state, the TMS signal remains zero; the TDI signal is used to determine whether it is sent to the data register or the instruction register of the TAP state machine, and the number of clock cycles that the TMS signal needs to remain zero is calculated by obtaining the data bit width.

[0018] Furthermore, the data parsing module parses the debugging instructions according to the instruction register mode and the debugging data according to the data register mode.

[0019] In a second aspect, this application provides a RISC-V processor download and debugging system based on an FPGA-JTAG interface. The system includes at least a host computer, a boundary scan register, a data parsing module, a debugging module, and an FPGA-JTAG interface. The system is used to execute the RISC-V processor download and debugging method based on an FPGA-JTAG interface as described in any of the first aspects.

[0020] The host computer is used to modify the boundary scan configuration code related to the FPGA-JTAG interface in the source code based on the boundary scan register address and bit width of the FPGA chip; the host computer is used to modify the cfg configuration code of the host computer based on the boundary scan register of the FPGA chip to configure the host computer in boundary scan mode; the host computer generates a data packet containing the boundary scan register address, debugging instructions and debugging data, and transmits it to the data parsing module through the FPGA-JTAG interface;

[0021] The data parsing module parses the TDI signal according to the data packet format to obtain the parsing result; the data parsing module controls the TMS signal according to the parsing result to switch the state of the TAP state machine in the debugging module, thereby realizing the debugging of the RISC-V processor.

[0022] Thirdly, this application provides a computer-readable storage medium storing program code, which is called by a processor to execute any one of the methods for downloading and debugging a RISC-V processor based on an FPGA-JTAG interface.

[0023] Fourthly, this application also provides an electronic device, including one or more processors; a memory; and one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute a RISC-V processor download and debugging method based on an FPGA-JTAG interface as described in any of the first aspects.

[0024] The aforementioned RISC-V processor download and debugging method, system, computer-readable storage medium, and electronic device based on the FPGA-JTAG interface reuse the FPGA-JTAG interface as a dedicated test and debug pin, avoiding the need for additional hardware connections when using general-purpose I / O pins for debugging, thus saving valuable I / O resources. This application simplifies hardware design by reusing the FPGA-JTAG interface for debugging, eliminating the need for additional debug interfaces or hardware circuit changes. By reducing the introduction of additional debug lines, system noise and interference are reduced, improving data transmission stability and overall system reliability during debugging. This application enables processor debugging using only the FPGA-JTAG interface, simplifying board design and reducing testing or development overhead.

[0025] To make the above and other objects, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating the RISC-V processor download and debugging method based on the FPGA-JTAG interface of this application.

[0028] Figure 2 This is a timing diagram of the data parsing module in this application.

[0029] Figure 3 This is a schematic diagram of the TAP state machine of this application.

[0030] Figure 4 This is a system framework diagram of the RISC-V processor download and debugging system based on the FPGA-JTAG interface of this application. Detailed Implementation

[0031] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a method of distinguishing objects with the same attributes in the embodiments of this application.

[0032] refer to Figure 1 This application provides a RISC-V processor download and debugging method based on the FPGA-JTAG interface. The RISC-V debug system of this application conforms to the RISC-V External Debug Support Version 0.13 protocol. The method specifically includes the following steps:

[0033] Step S1: Based on the boundary scan register address and bit width of the FPGA chip, modify the boundary scan configuration code related to the FPGA chip in the host computer source code.

[0034] The JTAG interface (Joint Test Action Group) is a protocol used for internal chip testing. In this article, the FPGA-JTAG interface is also referred to simply as the JTAG interface.

[0035] Boundary scan (BSCAN) registers are special registers within the FPGA chip used for boundary scan testing. They reside in the FPGA chip's JTAG boundary scan chain, allowing access and control of the FPGA chip's boundary scan chain via the FPGA-JTAG interface. Each boundary scan register has a unique address used for identification and access within the JTAG protocol. The register bit width (e.g., 6-bit, 8-bit, and 32-bit) indicates the register's data width, determining the amount of data the register can store and transmit. The address and bit width of the FPGA chip's boundary scan registers can be obtained from the FPGA chip's datasheet and related technical documentation. Based on these parameters, the boundary scan configuration section related to the FPGA-JTAG interface in the host computer, such as the OpenOCD (Open On-Chip Debugger) source code, is modified accordingly to ensure correct recognition and processing by the host computer.

[0036] Step S2: Based on the boundary scan register of the FPGA chip, modify the cfg configuration code of the host computer accordingly to put it in boundary scan mode.

[0037] For example, boundary scan mode is an operating mode of an FPGA chip under the FPGA-JTAG interface. In this mode, the boundary scan chain of the FPGA chip is activated, allowing testing and debugging of the FPGA chip's input / output pins, internal signals, etc., through the FPGA-JTAG interface. The host computer communicates with the FPGA chip through the FPGA-JTAG interface, identifies the chip's IDCODE to confirm the type of target device, and configures, debugs, and tests the FPGA through JTAG protocol communication, including operations such as reading and writing registers and accessing memory.

[0038] Optionally, modifications to the host computer's cfg configuration code include defining the access method for the boundary scan registers, setting the chain order, and configuring the scan chain length. These modifications enable support for the FPGA chip's boundary scan mode, improving the accuracy of the host computer's identification and operation of the FPGA chip's boundary scan registers via the FPGA-JTAG interface, thus laying the foundation for subsequent debugging work.

[0039] Step S3: The host computer constructs a data packet containing the boundary scan register address, debugging instructions, and debugging data, and transmits it to the data parsing module through the FPGA-JTAG interface.

[0040] After configuring the host computer, the data packet containing the boundary scan register address, debugging instructions, and debugging data is transmitted to the data parsing module for processing via the FPGA-JTAG interface.

[0041] Optionally, after receiving debugging instructions from the host computer via the FPGA-JTAG interface, multiple tests can be performed to verify the stability of the communication connection and ensure error-free data transmission.

[0042] Step S4: Parse the TDI signal according to the data packet format to obtain the parsing result, and control the TMS signal to switch the state of the TAP state machine according to the parsing result, so as to realize the debugging of the RISC-V processor.

[0043] The data parsing module analyzes the TDI signal according to the data format and determines whether the data is sent to the data register or instruction register of the TAP state machine. Then, by obtaining the data bit width, it calculates the number of clock cycles the TMS signal needs to remain at zero to ensure accurate data reception. By controlling the TMS signal to switch the TAP state machine's state, debugging of the RISC-V processor is achieved.

[0044] The debug module is a core component for debugging RISC-V processors. It provides debug access and control over the CPU's running state, allowing the debugger to control the execution of the RISC-V processor, such as single-stepping, setting breakpoints, and reading / writing registers and memory, thereby enabling debugging of the RISC-V processor. In this embodiment, a data parsing module parses data packets, and then accurately transmits the debugging information from the parsing results to the debug transport module (DTM) within the debug module to achieve debugging of the RISC-V processor.

[0045] Step S5: After debugging is complete, disconnect the host computer from the FPGA-JTAG interface, restore the default configuration, and release the occupied resources.

[0046] Based on the above description, the RISC-V processor download and debugging method based on the FPGA-JTAG interface of this application, by modifying the source code and cfg configuration code of the host computer, reuses the FPGA-JTAG interface as a dedicated test and debugging pin, avoiding the need for additional hardware connections due to the use of general-purpose I / O pins, saving valuable I / O resources. It eliminates the inconvenience caused by frequent hot-swapping of external I / O pins in traditional debugging, significantly improving the stability and reliability of the debugging process. Simultaneously, by reusing the FPGA-JTAG interface for debugging, there is no need to add additional debugging interfaces or change hardware circuits, simplifying board design and reducing testing or development overhead. Moreover, by reducing the introduction of additional debugging lines, system noise and interference are reduced, achieving efficient debugging of the RISC-V processor, improving data transmission stability and overall system reliability during the debugging process.

[0047] In one implementation, refer to Figure 2 When the host computer is in boundary scan mode, it first sends the boundary scan register address. Once the FPGA-JTAG interface receives the boundary scan register address, it can establish communication with the RISC-V debugging system through the FPGA's boundary scan register. Debugging instructions and data related to RISC-V processor debugging are embedded in the data register. Since these instructions need to be parsed during debugging, the data parsing module of this application processes and extracts the debugging information and accurately transmits it to the debugging module. This method supports advanced debugging operations on the processor, such as batch read / write of registers, block operations on memory, and flexible breakpoint settings, enriching the debugging methods and functions.

[0048] Furthermore, the data parsing module analyzes the TDI signal transmitted through the boundary scan register to obtain the data type and bit width, and controls the changes in the TMS signal based on the parsing result. This ensures accurate switching of the TAP state machine between the instruction register (IR) and data register (DR) modes, thereby accurately parsing the debug instructions and debug data in the data packet and achieving precise debugging of the RISC-V processor. Specifically, refer to... Figure 2When the TAP state machine is in the shift instruction register state, the boundary scan register address is input via the TDI signal and transmitted to the boundary scan register through the FPGA-JTAG interface. When the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debug instructions and debug data to the data parsing module through the FPGA-JTAG interface. This simplifies hardware design by reusing the FPGA-JTAG interface, eliminating the need for additional debug interfaces or hardware circuit changes. Furthermore, it reduces the introduction of additional debug lines, lowers system noise and interference, and improves data transmission stability and overall system reliability during debugging.

[0049] As shown in Tables 1 and 2 below, Table 1 includes the data format for the execution instruction register mode, and Table 2 includes the data format for the execution data register mode.

[0050] Table 1

[0051]

[0052] Table 2

[0053]

[0054] Specifically, the TDI signal first sends a single bit ("0" or "1") to select whether to enter instruction register mode or data register mode. One bit of 0 indicates entry into instruction register mode for instruction transmission, while one bit of 1 indicates entry into data register mode for data transmission. After entering instruction register mode or data register mode, the instruction bit width and data information are then sent. Seven bits represent the corresponding bit width, with IR Width bits or DR Width bits representing the corresponding width. In shift instruction register or shift data register mode, the TMS signal remains 0 to ensure the TAP state machine can transmit instructions or data. The data parsing module parses the TDI signal according to the data packet format to determine whether the data is sent to the TAP state machine's data register or instruction register. Subsequently, by obtaining the data bit width, it calculates the number of clock cycles the TMS signal needs to remain zero to ensure accurate data reception. After transmission is complete, three consecutive bits of 0 are sent, causing the TAP state machine to re-enter the test run idle state, preparing for subsequent operations.

[0055] In summary, the RISC-V processor download and debugging method based on the FPGA-JTAG interface of this application can save external I / O resources, improve debugging efficiency and system stability, simplify test or application board design, and reduce costs. Specifically, this application reuses the FPGA-JTAG interface as dedicated test and debugging pins, instead of the FPGA's general-purpose I / O pins, avoiding the need to add extra hardware connections for debugging and saving valuable I / O resources. By reusing the FPGA-JTAG interface for debugging, this application simplifies hardware design, eliminating the need to add additional debugging interfaces or change hardware circuitry. By reducing the introduction of additional debugging lines, system noise and interference are reduced, improving data transmission stability and overall system reliability during debugging. This application can achieve processor debugging functionality using only the FPGA-JTAG interface, while simplifying board design and reducing testing or development overhead.

[0056] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0057] In one embodiment, reference Figure 4This application also provides a RISC-V processor download and debugging system framework based on an FPGA-JTAG interface. This system framework includes at least a host computer, a boundary scan register, a data parsing module, a debugging module, and an FPGA-JTAG interface. This system is used in any of the above embodiments for the RISC-V processor download and debugging method based on an FPGA-JTAG interface. Specifically, the host computer modifies the boundary scan configuration code related to the FPGA-JTAG interface in its source code based on the boundary scan register address and bit width of the FPGA chip; the host computer modifies its cfg configuration code based on the boundary scan register of the FPGA chip to put it in boundary scan mode; the host computer generates a data packet containing the boundary scan register address, debugging instructions, and debugging data, and transmits it to the data parsing module through the FPGA-JTAG interface; the data parsing module parses the TDI signal according to the data packet format to obtain the parsing result; the data parsing module controls the TMS signal according to the parsing result to switch the state of the TAP state machine in the debugging module, thereby realizing the debugging of the RISC-V processor.

[0058] In one embodiment, this application also provides a computer-readable storage medium storing program code, which is called by a processor to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface in any of the above embodiments.

[0059] In one embodiment, this application also provides an electronic device comprising one or more processors; a memory; and one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the FPGA-JTAG interface-based RISC-V processor download and debugging method described above.

[0060] It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles thereof, and such improvements and modifications also fall within the scope of protection of the claims of this application. It should be understood that certain features of this disclosure described in the context of individual embodiments for clarity may also be provided in combination in a single embodiment. Conversely, various features of this disclosure described in the context of individual embodiments for clarity may also be provided individually or in any suitable combination or as part of any other described embodiment of this disclosure.

Claims

1. A method for downloading and debugging a RISC-V processor based on an FPGA-JTAG interface, characterized in that, The method includes: Based on the boundary scan register address and bit width of the FPGA chip, modify the boundary scan configuration code related to the FPGA chip in the host computer source code; Based on the boundary scan register of the FPGA chip, modify the cfg configuration code of the host computer to configure the host computer into boundary scan mode; The host machine constructs a data packet containing the boundary scan register address, debugging instructions, and debugging data. This data packet is then transmitted to the boundary scan register via the FPGA-JTAG interface and finally to the data parsing module. Specifically, when the TAP state machine is in the shift instruction register state, the boundary scan register address is input via the TDI signal and transmitted to the boundary scan register via the FPGA-JTAG interface. When the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debugging instructions and debugging data to the data parsing module via the FPGA-JTAG interface. The data packet format is used to parse the TDI signal to obtain the data type and bit width. Based on the data type and bit width, the TMS signal is controlled to change, and the state of the TAP state machine in the debugging module is switched to achieve debugging of the RISC-V processor.

2. The RISC-V processor download and debugging method based on the FPGA-JTAG interface according to claim 1, characterized in that, The modification of the host computer's cfg configuration code includes at least: defining the access mode of the boundary scan register, setting the chain order, and configuring the length of the scan chain in the cfg configuration code.

3. The RISC-V processor download and debugging method based on the FPGA-JTAG interface according to claim 1, characterized in that, When the TAP state machine is in the shift instruction register state or the shift data register state, the TMS signal remains zero; the TDI signal determines whether it is sent to the data register or the instruction register of the TAP state machine, and the number of clock cycles that the TMS signal needs to remain zero is calculated by obtaining the data bit width.

4. The RISC-V processor download and debugging method based on the FPGA-JTAG interface according to claim 1, characterized in that, The data parsing module parses the debugging instructions according to the instruction register mode and the debugging data according to the data register mode.

5. A RISC-V processor download and debugging system based on an FPGA-JTAG interface, characterized in that, The system includes at least a host computer, a boundary scan register, a data parsing module, a debugging module, and an FPGA-JTAG interface. The system is used to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface as described in any one of claims 1 to 4. The host computer is used to modify the boundary scan configuration code related to the FPGA chip in the host computer source code based on the boundary scan register address and bit width of the FPGA chip; the host computer is used to modify the cfg configuration code of the host computer based on the boundary scan register of the FPGA chip to configure the host computer in boundary scan mode; the host computer constructs a data packet containing the boundary scan register address, debugging instructions and debugging data, and transmits it to the data parsing module through the FPGA-JTAG interface; wherein, when the TAP state machine is in the shift instruction register state, the boundary scan register address is input through the TDI signal and transmitted to the boundary scan register through the FPGA-JTAG interface; when the TAP state machine is in the shift data register state, the TDI signal transmits the configuration information of the debugging instructions and the debugging data to the data parsing module through the FPGA-JTAG interface; The data parsing module parses the TDI signal according to the data packet format to obtain the parsing result; the data parsing module controls the TMS signal according to the parsing result to switch the state of the TAP state machine in the debugging module, thereby realizing the debugging of the RISC-V processor.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code, which is invoked by a processor to execute the RISC-V processor download and debugging method based on the FPGA-JTAG interface as described in any one of claims 1 to 4.

7. An electronic device, characterized in that, Includes one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to perform the RISC-V processor download and debugging method based on the FPGA-JTAG interface as described in any one of claims 1 to 4.

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