Conversion circuit and method for 485 interface and UART (Universal Asynchronous Receiver / Transmitter) protocol interface using HDLC protocol
By designing a conversion circuit that uses the 485 interface and the UART protocol interface of the HDLC protocol, and using FPGA for data analysis and packaging, the baseband chip cannot meet the problem of using the 485 interface and the HDLC protocol communication on the bullet, and the compatibility and real-time response capabilities of different interfaces are achieved.
Patent Information
- Application Number
- CN202411936230.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-05-30
AI Technical Summary
The device's baseband chip uses the UART protocol to no longer meet the needs of using the 485 interface and HDLC protocol to communicate on the bullet.
A conversion circuit using the 485 interface and the UART protocol interface of the HDLC protocol is designed to realize data conversion through an isolation chip, interface chip and FPGA. Specifically, the FPGA includes an HDLC receiving module, an HDLC sending module, an instruction identification module, a UART receiving module and a UART sending module for parsing, encapsulating and forwarding data.
It solves the problem that the baseband chip cannot meet the communication using the UART protocol on the bullet by using the 485 interface and the HDLC protocol, improves the compatibility of different interfaces, and realizes real-time response when receiving the correct instructions, avoiding bus conflicts.
Smart Images
Figure CN120067006A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data communication, and in particular, to a conversion circuit and method for a 485 interface and a UART protocol interface using the HDLC protocol. Background Art
[0002] A satellite navigation receiver is an important part in the development process of an aircraft, responsible for communicating with the on-board computer and sending measurement information such as navigation solution results to the on-board computer. With the improvement of the information processing speed of the on-board computer and the increase in the number of communication devices, the use of the UART protocol by the baseband chip of the device no longer meets the communication requirements of the 485 interface and the HDLC protocol on the aircraft. Summary of the Invention
[0003] The present invention provides a conversion circuit and method for a 485 interface and a UART protocol interface using the HDLC protocol, so as to solve the problem that the use of the UART protocol by the baseband chip of the device no longer meets the communication requirements of the 485 interface and the HDLC protocol on the aircraft.
[0004] On the one hand, the present invention provides a conversion circuit for a 485 interface and a UART protocol interface using the HDLC protocol, including an isolation chip, an interface chip, and an FPGA connected in sequence. The isolation chip is used for electrically isolating the 485 interface, the interface chip is used for level conversion, and the FPGA includes an HDLC receiving module, an HDLC sending module, an instruction recognition module, a UART receiving module, and a UART sending module, wherein:
[0005] The HDLC receiving module is used for parsing the data from the interface chip according to the HDLC protocol and sending the parsed data to the instruction recognition module;
[0006] The HDLC sending module is used for encapsulating the data from the instruction recognition module according to the HDLC protocol and sending the encapsulated data to the interface chip;
[0007] The instruction recognition module is used for receiving the data from the HDLC receiving module, determining whether the received data is a correct instruction. If so, selecting the response data of the correct instruction from the pre-stored data and sending it to the HDLC sending module, and forwarding the correct instruction to the UART sending module, and continuing to receive the data from the HDLC receiving module. If not, continuing to receive the data from the HDLC receiving module, where the pre-stored data is the response data of all instructions; and is also used for receiving the data from the UART receiving module, updating the pre-stored data based on the received data, and continuing to receive the data from the UART receiving module;
[0008] The UART receiving module is used to parse the data sent through the UART protocol interface according to the UART protocol, and send the parsed data to the instruction recognition module;
[0009] The UART sending module is used to encapsulate the data from the instruction recognition module according to the UART protocol, and send the encapsulated data through the UART protocol interface.
[0010] Optionally, the isolation chip is an optocoupler or a magnetic coupler.
[0011] Optionally, the interface chip is a DS96F174 / 175 interface chip.
[0012] Optionally, the FPGA is a small FPGA.
[0013] Optionally, determining whether the received data is a correct instruction includes:
[0014] Determine whether the slave address in the received data is the address of the baseband chip. If so, it is a correct instruction. The baseband chip is connected to the FPGA through the UART protocol interface.
[0015] Optionally, the pre-stored data is stored in the RAM of the FPGA.
[0016] Optionally, the HDLC receiving module, the UART receiving module, and the instruction recognition module send data byte by byte.
[0017] On the other hand, the present invention provides a conversion method for a 485 interface and a UART protocol interface using the HDLC protocol, which is applied to any of the above circuits, including:
[0018] Receive data from the HDLC receiving module through the instruction recognition module, determine whether the received data is a correct instruction. If so, select the response data of the correct instruction from the pre-stored data and send it to the HDLC sending module, and forward the correct instruction to the UART sending module, and continue to receive data from the HDLC receiving module. If not, continue to receive data from the HDLC receiving module. The pre-stored data is the response data of all instructions;
[0019] At the same time, receive data from the UART receiving module through the instruction recognition module, update the pre-stored data based on the received data, and continue to receive data from the UART receiving module.
[0020] Optionally, determining whether the received data is a correct instruction includes:
[0021] Determine whether the slave address in the received data is the address of the baseband chip. If it is, it is a correct instruction. The baseband chip is connected to the FPGA through a UART protocol interface.
[0022] Optionally, the HDLC receiving module, the UART receiving module, and the instruction recognition module send data byte by byte.
[0023] The present invention realizes data conversion between a 485 interface using the HDLC protocol and a UART protocol interface through an isolation chip, an interface chip, and an FPGA, solves the problem that the baseband chip using the UART protocol no longer meets the communication requirements of the 485 interface and the HDLC protocol on the missile, and improves the compatibility of different interfaces. At the same time, when the FPGA receives a correct instruction, it immediately returns response data, which not only ensures real-time response but also avoids bus conflicts caused by simultaneous responses of multiple devices. Brief Description of the Drawings
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0025] Figure 1 It is a schematic design diagram of a conversion circuit for a 485 interface and a UART protocol interface using the HDLC protocol provided by an embodiment of the present invention;
[0026] Figure 2 It is a schematic architecture diagram of each module in the FPGA provided by an embodiment of the present invention;
[0027] Figure 3 It is a schematic flow diagram of a conversion method for a 485 interface and a UART protocol interface using the HDLC protocol provided by an embodiment of the present invention. Detailed Embodiments
[0028] In order to make the purpose, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0029] The following explains some terms in the embodiments to facilitate the understanding of those skilled in the art.
[0030] HDLC: HDLC stands for High-Level Data Link Control. It is a bit-oriented and transparent data transmission protocol with high data link transmission efficiency.
[0031] UART: UART stands for Universal Asynchronous Receiver / Transmitter. It is a serial communication protocol widely used for communication between microcontrollers, computers, and other electronic devices.
[0032] 485 interface: The RS-485 interface is a serial communication interface widely used in industrial control and automation systems, featuring long-distance transmission, multi-device connection, and anti-interference.
[0033] FPGA: Field-Programmable Gate Array. It is a programmable hardware device used to perform complex computing and control tasks in digital circuits.
[0034] Bus: In a computer system, the common path for transmitting information between various components is called a bus.
[0035] Figure 1 Specifically shows the design of a conversion circuit for a 485 interface using the HDLC protocol and a UART protocol interface provided by an embodiment of the present invention, including an isolation chip, an interface chip, and an FPGA connected in sequence.
[0036] The isolation chip is used to electrically isolate the 485 interface, and the other end of the 485 interface is connected to the HDLC bus. Through the electrical isolation between the pop-up machine and the satellite guidance, the influence of electromagnetic interference and noise on the signal can be reduced.
[0037] In one example, the isolation chip is an optocoupler or a magnetic coupler.
[0038] The interface chip is used for level conversion. Since the IO level of the FPGA is relatively low and does not meet the HDLC bus transmission requirements, it is necessary to convert the IO level of the FPGA to the 5V level of the 485 interface through level conversion to increase the driving ability.
[0039] In one example, the interface chip is a DS96F174 / 175 interface chip. This chip is a high-speed four-differential line transceiver, meeting the multi-point bus application requirements of the EIA-485 standard.
[0040] Figure 2 Shows the architecture of each module in the FPGA, including an HDLC receiving module, an HDLC transmitting module, an instruction recognition module, a UART receiving module, and a UART transmitting module.
[0041] In one example, the FPGA is a small FPGA. According to the resources occupied by the interface software, selecting a small FPGA can meet the usage requirements.
[0042] The HDLC receiving module is used to parse the data from the interface chip according to the HDLC protocol and send the parsed data to the instruction recognition module.
[0043] The HDLC sending module is used to encapsulate the data from the instruction recognition module according to the HDLC protocol and send the encapsulated data to the interface chip.
[0044] The instruction recognition module is used to receive the data from the HDLC receiving module, determine whether the received data is a correct instruction. If it is, select the response data of the correct instruction from the pre-stored data and send it to the HDLC sending module, and forward the correct instruction to the UART sending module, and continue to receive the data from the HDLC receiving module. If not, continue to receive the data from the HDLC receiving module.
[0045] In one example, determining whether the received data is a correct instruction includes:
[0046] Determine whether the slave address in the received data is the address of the baseband chip. If it is, it is a correct instruction. The baseband chip is connected to the FPGA through the UART protocol interface.
[0047] It should be noted that the data received by the instruction recognition module from the HDLC receiving module contains the master address and the slave address.
[0048] It should be noted that the baseband chip is at TTL / LVTTL level.
[0049] Specifically, the pre-stored data is the response data of all instructions.
[0050] It should be noted that all the instructions to be sent on the HDLC bus are known to the baseband chip. Therefore, the baseband chip can send the response data of all instructions to the FPGA.
[0051] In one example, the pre-stored data is stored in the RAM of the FPGA.
[0052] The instruction recognition module is also used to receive the data from the UART receiving module, update the pre-stored data based on the received data, and continue to receive the data from the UART receiving module.
[0053] The instruction recognition module continuously receives the response data of all instructions and updates it to the pre-stored data, which can ensure that the pre-stored data is the latest response data of all instructions.
[0054] The UART receiving module is used to parse the data sent through the UART protocol interface according to the UART protocol, and send the parsed data to the instruction recognition module.
[0055] The UART sending module is used to encapsulate the data from the instruction recognition module according to the UART protocol, and send the encapsulated data through the UART protocol interface.
[0056] In one example, the HDLC receiving module, the UART receiving module, and the instruction recognition module send data byte by byte.
[0057] The above solution realizes the data conversion between the 485 interface using the HDLC protocol and the UART protocol interface through an isolation chip, an interface chip, and an FPGA, solves the problem that the baseband chip using the UART protocol no longer meets the communication requirements of the 485 interface and the HDLC protocol on the missile, and improves the compatibility of different interfaces; at the same time, the FPGA immediately responds with response data when receiving a correct instruction, which not only ensures real-time response but also avoids bus conflicts caused by simultaneous responses of multiple devices.
[0058] Replacing the HDLC protocol with the SDLC protocol in the embodiments of the present invention is equally applicable.
[0059] Based on the same inventive concept, Figure 3 The flowchart of a conversion method for a 485 interface and a UART protocol interface using the HDLC protocol provided by the embodiments of the present invention is shown, including:
[0060] Receive the data from the HDLC receiving module through the instruction recognition module, determine whether the received data is a correct instruction. If so, select the response data of the correct instruction from the pre-stored data and send it to the HDLC sending module, and forward the correct instruction to the UART sending module, and continue to receive the data from the HDLC receiving module. If not, continue to receive the data from the HDLC receiving module, and the pre-stored data is the response data of all instructions;
[0061] At the same time, receive the data from the UART receiving module through the instruction recognition module, update the pre-stored data based on the received data, and continue to receive the data from the UART receiving module.
[0062] In one example, determining whether the received data is a correct instruction includes:
[0063] Determine whether the slave address in the received data is the address of the baseband chip. If so, it is a correct instruction, and the baseband chip is connected to the FPGA through the UART protocol interface.
[0064] In one example, the HDLC receiving module, the UART receiving module, and the instruction recognition module send data byte by byte.
[0065] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention.
[0066] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.
Claims
1. A conversion circuit using a 485 interface of HDLC protocol and a UART protocol interface, characterized in that: It includes an isolation chip, an interface chip and an FPGA connected in sequence, the isolation chip is used to electrically isolate the 485 interface, the interface chip is used to perform level conversion, and the FPGA includes an HDLC receiving module, an HDLC sending module, an instruction recognition module, a UART receiving module and a UART sending module, wherein: The HDLC receiving module is used to parse the data from the interface chip according to the HDLC protocol and send the parsed data to the instruction recognition module; The HDLC sending module is used to encapsulate the data from the instruction recognition module according to the HDLC protocol, and send the encapsulated data to the interface chip; The instruction recognition module is used to receive data from the HDLC receiving module, determine whether the received data is a correct instruction, if so, select the response data of the correct instruction from the pre-stored data and send it to the HDLC sending module, and forward the correct instruction to the UART sending module, and continue to receive data from the HDLC receiving module; if not, continue to receive data from the HDLC receiving module, and the pre-stored data is the response data of all instructions; it is also used to receive data from the UART receiving module, update the pre-stored data based on the received data, and continue to receive data from the UART receiving module; The UART receiving module is used to parse the data sent through the UART protocol interface according to the UART protocol, and send the parsed data to the instruction recognition module; The UART sending module is used to encapsulate the data from the instruction recognition module according to the UART protocol, and send the encapsulated data through the UART protocol interface.
2. The circuit according to claim 1, characterized in that: The isolation chip is an optical coupler or a magnetic coupler.
3. The circuit according to claim 1, characterized in that: The interface chip is a DS96F174 / 175 interface chip.
4. The circuit according to claim 1, characterized in that: The FPGA is a small FPGA.
5. The circuit according to claim 1, characterized in that: The step of determining whether the received data is a correct instruction comprises: Determine whether the slave station address in the received data is the address of the baseband chip. If so, it is a correct instruction. The baseband chip is connected to the FPGA through the UART protocol interface.
6. The circuit according to claim 1, characterized in that: The pre-stored data is stored in the RAM of the FPGA.
7. The circuit according to claim 1, characterized in that: The HDLC receiving module, the UART receiving module and the instruction recognition module send data per byte.
8. A method for converting a 485 interface using HDLC protocol and a UART protocol interface, applied to the circuit described in any one of claims 1 to 7, characterized in that: include: Receive data from the HDLC receiving module through the instruction recognition module, determine whether the received data is a correct instruction, if yes, select the response data of the correct instruction from the pre-stored data and send it to the HDLC sending module, and forward the correct instruction to the UART sending module, and continue to receive data from the HDLC receiving module, if no, continue to receive data from the HDLC receiving module, and the pre-stored data is the response data of all instructions; At the same time, the instruction recognition module receives data from the UART receiving module, updates the pre-stored data based on the received data, and continues to receive data from the UART receiving module.
9. The method according to claim 8, characterized in that: The step of determining whether the received data is a correct instruction comprises: It is determined whether the slave station address in the received data is the address of the baseband chip. If so, it is a correct instruction. The baseband chip is connected to the FPGA through a UART protocol interface.
10. The method according to claim 8, characterized in that: The HDLC receiving module, the UART receiving module and the instruction recognition module send data per byte.