PCIe Switch bifurcation characteristic verification system and method

Abstract

The invention provides a system and a method for verifying bifurcation characteristics of PCIe Switch, and relates to the technical field of PCIe. The forking characteristic verification system of the PCIe Switch comprises a DUT module, a first EP verification agent component, a second EP verification agent component, a first RC verification agent component, a second RC verification agent component, a first PHY verification agent component, a second PHY verification agent component and a configuration module. A configuration module, a first protocol comparator and a second protocol comparator, wherein the configuration module is used for configuring the bifurcation form of the uplink port and the downlink port and the behavior of each verification agent component; the first protocol comparator is used for verifying the bifurcation characteristic of the uplink port, and the second protocol comparator is used for synchronously verifying the bifurcation characteristic of the downlink port. The method has the advantages that the verification convergence speed is increased, and the verification rate is increased.

Description

Technical Field

[0001] This application relates to the field of PCIe technology. Specifically, it relates to a verification system and method for the bifurcation characteristics of a PCIe Switch. Background Art

[0002] PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) is widely used. A PCIe Switch (PCIe adapter device) is a hardware device that provides expansion or aggregation capabilities and allows more devices to be connected to a PCle port, thereby expanding the connectivity of the system.

[0003] PCIe device bifurcation means that a PCIe device can be connected to multiple different PCIe devices simultaneously. A PCIe device physically has multiple serial channels, and these channels can be bound together according to rules to connect to another PCIe device, helping the PCIe device achieve low-cost expansion. How these channels are bound corresponds to the bifurcation characteristics of the device. Since a PCIe switch needs to connect PCIe devices with various different channel widths, the bifurcation characteristic is one of the very important characteristics of a PCIe switch.

[0004] Generally, a PCIe Switch has multiple upstream ports and multiple downstream ports. The upstream ports can be connected to master devices such as CPUs, and the downstream ports are connected to terminal devices. The PCIe switch has bifurcation requirements for both upstream ports and downstream ports.

[0005] Most of the existing PCIe Switches support multiple bifurcation scenarios and can connect multiple devices with different channel widths according to different configurations. Facing complex bifurcation forms, it poses a great challenge to the verification of PCIe Switch chips.

[0006] Currently, common PCIe Switch bifurcation verification generally independently verifies the bifurcation characteristics of the upstream port or the downstream port on the PCIe Switch. However, it is necessary to build two sets of verification environments separately, consuming manpower and resources, and not being able to well cover the system configuration, resulting in low verification efficiency. Summary of the Invention

[0007] The purpose of this application is to provide a verification system and method for the bifurcation characteristics of a PCIe Switch to solve the problem of low verification efficiency of PCIe Switch bifurcation in the prior art.

[0008] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0009] On the one hand, an embodiment of the present application provides a PCIe Switch bifurcation characteristic verification system, and the PCIe Switch bifurcation characteristic verification system includes:

[0010] A DUT module, where the DUT module includes a plurality of upstream ports and a plurality of downstream ports;

[0011] A first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component; the first EP verification proxy component and the first PHY verification proxy component are both connected to the upstream port, and the first RC verification proxy component is connected to the first PHY verification proxy component; the second RC verification proxy component and the second PHY verification proxy component are both connected to the downstream port, and the second EP verification proxy component is connected to the second PHY verification proxy component; the first EP verification proxy component and the second EP verification proxy component are both used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are both used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are both used to simulate PCIe PHY behavior;

[0012] A configuration module, connected to the DUT module and each verification proxy component, and used to configure the bifurcation form of the upstream port and the downstream port and the behavior of each verification proxy component;

[0013] A first protocol comparator and a second protocol comparator, the first protocol comparator is connected to the first EP verification proxy component and the first RC verification proxy component, and the second protocol comparator is connected to the second EP verification proxy component and the second RC verification proxy component; the first protocol comparator is used to verify the bifurcation characteristics of the upstream port, and the second protocol comparator is used to synchronously verify the bifurcation characteristics of the downstream port.

[0014] Optionally, the first EP verification proxy component, the second EP verification proxy component, the first RC verification proxy component, the second RC verification proxy component, the first PHY verification proxy component, and the second PHY verification proxy component are all simulation models implemented by Verilog or Systerm Verilog code.

[0015] Optionally, the DUT module includes multiple physical links. The configuration module is configured to configure the number of the to-be-tested upstream ports and the to-be-tested downstream ports of the DUT module, and configure the number of physical links connected to each to-be-tested upstream port and to-be-tested downstream port, so as to implement the configuration of the forking form of the upstream port and the downstream port.

[0016] Optionally, each to-be-tested upstream port, the corresponding first RC verification agent component, the first PHY verification agent component, the first EP verification agent component, and the first protocol comparator form a first test unit, and multiple first test units are independent of each other;

[0017] Each to-be-tested downstream port, the corresponding second RC verification agent component, the second PHY verification agent component, the second EP verification agent component, and the second protocol comparator form a second test unit, and multiple second test units are independent of each other.

[0018] Optionally, when verifying the forking characteristics of the upstream port, the first EP verification agent component and the first RC verification agent component synchronously send test signals;

[0019] When verifying the forking characteristics of the downstream port, the second EP verification agent component and the second RC verification agent component synchronously send test signals.

[0020] Optionally, the DUT module provides multiple pipe bus interfaces and multiple serial interfaces. Each upstream port is connected to the first EP verification agent component through the pipe bus interface and is connected to the first PHY verification agent component through the serial interface;

[0021] Each downstream port is connected to the second RC verification agent component through the pipe bus interface and is connected to the second PHY verification agent component through the serial interface.

[0022] Optionally, when verifying the forking characteristics of the PCIe Switch, the verification test points include the low power consumption mode, clock reset, register access, PCIe enumeration process, various forking scenario configurations, pipe interface data transceiver path, and high-speed serial data transceiver path.

[0023] On the other hand, an embodiment of the present application further provides a method for verifying the forking characteristics of a PCIe Switch, which is applied to the above-mentioned system for verifying the forking characteristics of a PCIe Switch. The method includes:

[0024] Extract test points according to the protocol parameters of the DUT module and the forking form of the PCIe Switch, where the test points include test objects in different modes;

[0025] Generate a test sequence and test cases according to the test points; where each test case covers one or more function points, and all test cases cover all function points;

[0026] Configure the forking form of the DUT module and control the operation of each verification agent component;

[0027] Generate stimuli according to the test sequence and test cases, and send the stimuli to each verification agent component;

[0028] Use the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimuli, so as to realize the verification of the forking characteristics of the upstream port and the downstream port.

[0029] Optionally, after the step of using the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimuli, the method further includes:

[0030] Perform regression of all test cases with coverage, and collect code coverage and function coverage.

[0031] Optionally, the step of using the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimuli includes:

[0032] Compare the response data with the standard data. If the comparison fails, debug the configuration of each verification agent component, or debug the wiring of the PCIe Switch, or debug the code until all response data passes the comparison with the standard data.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] The embodiment of the present application provides a system and method for verifying the forking characteristics of a PCIe Switch. The system for verifying the forking characteristics of the PCIe Switch includes:

[0035] A DUT module, where the DUT module includes a plurality of upstream ports and a plurality of downstream ports;

[0036] The first EP verification agent component, the second EP verification agent component, the first RC verification agent component, the second RC verification agent component, the first PHY verification agent component, and the second PHY verification agent component; the first EP verification agent component and the first PHY verification agent component are both connected to the upstream port, and the first RC verification agent component is connected to the first PHY verification agent component; the second RC verification agent component and the second PHY verification agent component are both connected to the downstream port, and the second EP verification agent component is connected to the second PHY verification agent component; the first EP verification agent component and the second EP verification agent component are both used to simulate the terminal device controller, the first RC verification agent component and the second RC verification agent component are both used to simulate the master device controller, and the first PHY verification agent component and the second PHY verification agent component are both used to simulate the PCIe PHY behavior; a configuration module, connected to the DUT module and each verification agent component, and used to configure the forking form of the upstream port and the downstream port and the behavior of each verification agent component; a first protocol comparator and a second protocol comparator, the first protocol comparator is connected to the first EP verification agent component and the first RC verification agent component, and the second protocol comparator is connected to the second EP verification agent component and the second RC verification agent component; the first protocol comparator is used to verify the forking characteristics of the upstream port, and the second protocol comparator is used to synchronously verify the forking characteristics of the downstream port.

[0037] On the one hand, since the PCIe Switch forking characteristic verification system provided by the present application is provided with a first protocol comparator and a second protocol comparator, and the test unit composed of the first protocol comparator, the first EP verification agent component, the first PHY verification agent component, and the first RC verification agent component can implement the forking characteristic verification of the upstream port; while the test unit composed of the second protocol comparator, the second EP verification agent component, the second PHY verification agent component, and the second RC verification agent component can synchronously implement the forking characteristic verification of the downstream port. Therefore, in the entire verification system, the forking characteristic verification of the upstream port and the downstream port is simultaneously realized through a set of verification environments, reducing the consumption of manpower and resources, and at the same time improving the verification efficiency. On the other hand, since the first EP verification agent component and the second EP verification agent component are both used to simulate the terminal device controller, the first RC verification agent component and the second RC verification agent component are both used to simulate the master device controller, and the first PHY verification agent component and the second PHY verification agent component are both used to simulate the PCIe PHY behavior; therefore, each verification agent component is a virtual functional component, replacing the traditional physical controller, reducing the system construction cost, accelerating the verification convergence speed, and thus improving the verification efficiency of the entire system.

[0038] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Description of the Drawings

[0039] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0040] Figure 1 It is an interaction schematic diagram of the PCIe Switch fork characteristic verification system provided by the embodiments of the present application.

[0041] Figure 2 It is a module schematic diagram of the first test unit provided by the embodiments of the present application.

[0042] Figure 3 It is an exemplary flowchart of the PCIe Switch fork characteristic verification method provided by the embodiments of the application.

[0043] In the figure:

[0044] 110 - DUT module; 120 - First EP verification agent component; 130 - Second EP verification agent component; 140 - First RC verification agent component; 150 - Second RC verification agent component; 160 - First PHY verification agent component; 170 - Second PHY verification agent component; 180 - Configuration module; 190 - First protocol comparator; 200 - Second protocol comparator. Detailed Embodiments

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0048] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0049] The following will combine the drawings to elaborate on some embodiments of the present application. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0050] As described in the background art, currently, most PCIe Switches support multiple forking scenarios and can connect multiple devices with different channel widths according to different configurations. Facing complex forking topologies, it is necessary to verify the forking characteristics of the PCIe Switch chip.

[0051] A general PCIe Switch has multiple upstream ports and multiple downstream ports. The upstream ports can be connected to a master device such as a CPU (Root Complex, RC), and the downstream ports are connected to terminal devices (Endpoint, EP). The PCIe Switch has forking requirements for both upstream ports and downstream ports. Therefore, when verifying the forking characteristics of the PCIe Switch, it is necessary to verify the forking characteristics of the upstream ports of the PCIe Switch and also verify the forking characteristics of the downstream ports of the PCIe Switch.

[0052] In the prior art, there are usually two ways to verify the forking characteristics of the PCIe Switch chip:

[0053] One is that the PCIe Switch can independently verify the forking characteristics of the upstream port or the downstream port, but two sets of verification environments need to be built separately. One set of verification environment is used to verify the forking characteristics of the upstream port of the PCIe Switch, and the other set of verification environment is used to verify the forking characteristics of the downstream port of the PCIe Switch. Eventually, this verification method consumes manpower and resources, cannot well cover the system configuration, and has low verification efficiency.

[0054] Another is to perform verification at the SOC (System on Chip) level. This method is direct and effective, but it requires the entire PCIe Switch to be used as the DUT (Device Under Test). Since the SOC code volume is large, it causes problems such as low simulation speed and late defect exposure.

[0055] In view of this, to solve the above problems, the embodiments of the present application provide a PCIe Switch bifurcation characteristic verification system. By building a set of verification environments, it realizes the simultaneous verification of the bifurcation characteristics of the upstream port and the downstream port, shortens the simulation time, and speeds up the verification convergence.

[0056] The following provides an exemplary description of the PCIe Switch bifurcation characteristic verification system provided by the present application:

[0057] Please refer to Figure 1 , as an optional implementation manner, the PCIe Switch bifurcation characteristic verification system includes a DUT module 110, a first EP (endpoint) verification proxy component, a second EP verification proxy component 130, a first RC (root complex) verification proxy component, a second RC verification proxy component 150, a first PHY (Physical Layer) verification proxy component, a second PHY verification proxy component 170, a configuration module 180, a first protocol comparator 190, and a second protocol comparator 200.

[0058] The first EP verification proxy component 120 and the first PHY verification proxy component 160 are both connected to the upstream port, and the first RC verification proxy component 140 is connected to the first PHY verification proxy component 160; the second RC verification proxy component 150 and the second PHY verification proxy component 170 are both connected to the downstream port, and the second EP verification proxy component 130 is connected to the second PHY verification proxy component 170; the first EP verification proxy component 120 and the second EP verification proxy component 130 are both used to simulate the terminal device controller, the first RC verification proxy component 140 and the second RC verification proxy component 150 are both used to simulate the master device controller, and the first PHY verification proxy component 160 and the second PHY verification proxy component 170 are both used to simulate the PCIe PHY behavior;

[0059] The configuration module 180 is connected to the DUT module 110 and each verification proxy component, and is used to configure the bifurcation form of the upstream port and the downstream port and the behavior of each verification proxy component;

[0060] The first protocol comparator 190 is connected to the first EP verification agent component 120 and the first RC verification agent component 140, and the second protocol comparator 200 is connected to the second EP verification agent component 130 and the second RC verification agent component 150. The first protocol comparator 190 is used to verify the forking characteristics of the upstream ports, and the second protocol comparator 200 is used to synchronously verify the forking characteristics of the downstream ports.

[0061] Among them, the DUT module 110 is implemented by a PCIe Switch digital chip to be tested, which includes multiple upstream ports and multiple downstream ports, and can provide multiple pipe bus interfaces and multiple serial interfaces, and includes a configuration interface. Each upstream port is connected to the first EP verification agent component 120 through a pipe bus interface and connected to the first PHY verification agent component 160 through a serial interface; each downstream port is connected to the second RC verification agent component 150 through a pipe bus interface and connected to the second PHY verification agent component 170 through a serial interface.

[0062] Among them, the pipe bus interface is an interface signal of the PCIe controller. As an internal signal of the DUT, the simulation environment can connect the pipe interface to the verification component by means of forced assignment. The Pipe bus interface is defined in the physical layer, and the Pipe bus interface is a unified interface between the MAC (Media Access Layer) and the PCS (Physical Coding Sub-layer), aiming to provide a unified industry standard. The serial interface is a full-duplex extended interface commonly used for communication between electronic devices.

[0063] In the DUT module 110, the number of upstream ports and multiple downstream ports can be configured, and the link width of the pipe interfaces corresponding to the upstream ports and downstream ports and the number of serials can be flexibly configured. That is, the forking characteristics described in this application refer to the number of upstream ports and downstream ports configured and running in the current PCIe Switch, as well as information such as the link width corresponding to the ports.

[0064] As an implementation, the first EP verification agent component 120, the second EP verification agent component 130, the first RC verification agent component 140, the second RC verification agent component 150, the first PHY verification agent component 160, and the second PHY verification agent component 170 are all simulation models implemented by Verilog or Systerm Verilog code. Among them, the first PHY verification agent component 160 and the second PHY verification agent component 170 simulate the behavior of a real PCIe PHY. The first EP verification agent component 120 and the second EP verification agent component 130 are used to simulate the terminal device controller of the pipe interface. The first RC verification agent component 140 and the second RC verification agent component 150 are used to simulate the master device controller of the pipe interface. The first EP verification agent component 120, the second EP verification agent component 130, the first RC verification agent component 140, and the second RC verification agent component 150 can all generate and send stimuli and communicate with the upstream or downstream ports inside the DUT module 110 through the pipe interface or the serial interface. The master device described in this application can be a device such as a CPU. The terminal device described in this application can be a PCIe node device.

[0065] It can be understood that since the first EP verification agent component 120 and the second EP verification agent component 130 are both used to simulate the terminal device controller, the first RC verification agent component 140 and the second RC verification agent component 150 are both used to simulate the master device controller, and the first PHY verification agent component 160 and the second PHY verification agent component 170 are both used to simulate the PCIe PHY behavior; therefore, each verification agent component is a virtual functional component, replacing the traditional physical controller. On the basis of reducing the system construction cost, it speeds up the verification convergence speed, thereby improving the verification efficiency of the entire system.

[0066] Moreover, the upstream port is connected to the first EP verification agent component 120 through the pipe interface inside the DUT module 110 and to the first PHY verification agent component 160 through the serial interface externally. The first PHY verification agent component 160 is further connected to the first RC verification agent component 140. At the same time, the first protocol comparator 190 is respectively connected to the first EP verification agent component 120 and the first RC verification agent component 140, forming a basic test unit. Meanwhile, the downstream port is connected to the second RC verification agent component 150 through the pipe interface inside the DUT module 110 and to the second PHY verification agent component 170 through the serial interface externally. The second PHY verification agent component 170 is further connected to the second EP verification agent component 130. At the same time, the second protocol comparator 200 is respectively connected to the second EP verification agent component 130 and the second RC verification agent component 150, forming another basic test unit.

[0067] Understandably, through the two basic test units composed of the first protocol comparator 190 and the second protocol comparator 200, the bifurcation characteristics can be verified relatively independently. That is, the test unit composed of the first protocol comparator 190, the first EP verification agent component 120, the first PHY verification agent component 160, and the first RC verification agent component 140 can achieve the verification of the bifurcation characteristics of the upstream port; while the test unit composed of the second protocol comparator 200, the second EP verification agent component 130, the second PHY verification agent component 170, and the second RC verification agent component 150 can synchronously achieve the verification of the bifurcation characteristics of the downstream port. Therefore, in the entire verification system, the verification of the bifurcation characteristics of the upstream port and the downstream port is simultaneously achieved through a set of verification environments, reducing the consumption of manpower and resources and improving the verification efficiency at the same time.

[0068] Moreover, the DUT module 110 includes multiple physical links. The configuration module 180 is used to configure the number of upstream ports to be tested and downstream ports to be tested of the DUT module 110, and configure the number of physical links connected to each upstream port to be tested and downstream port to be tested, so as to realize the configuration of the bifurcation form of the upstream port and the downstream port. Specifically, the configuration module 180 can configure various PCIe Switch bifurcation forms, that is, it can configure the number of upstream ports or downstream ports, as well as the width of the pipe bus interface of each upstream port or downstream port and the number of differential pairs included in a group of serial interfaces.

[0069] For example, please combine Figure 1, for the uplink ports, when the number of uplink ports is 4 and the number of physical links is 16 (i.e., 16 pairs of differential lines), the number of the first EP verification agent components 120, the first PHY verification agent components 160, and the first RC verification agent components 140 is also 4, and the number of the uplink ports to be tested is configured to be three. For example, if the uplink ports are P1, P2, P3, and P4 respectively, the first EP verification agent components 120 are EP1, EP2, EP3, and EP4 respectively, and the first RC verification agent components 140 are RC1, RC2, RC3, and RC4 respectively. If the uplink ports to be tested are P1, P2, and P3, then the uplink port P4 is in the standby state; at this time, when the allocated physical links are X8 + 2X4, P1 is connected to EP1 through 8 physical links and is also connected to the corresponding first EP verification agent component 120 through 8 physical links; P2 is connected to EP2 through 4 physical links and is also connected to the corresponding first EP verification agent component 120 through 4 physical links; P3 is connected to EP3 through 4 physical links and is also connected to the corresponding first EP verification agent component 120 through 4 physical links.

[0070] Of course, the number of the uplink ports to be tested and the allocation of the physical links can also be configured according to actual requirements. For example, the number of the uplink ports to be tested can be 4, and the physical links of each uplink port to be tested are 4; or, the number of the uplink ports to be tested can be 2, and the physical links of each uplink port to be tested are 8; or, the number of the uplink ports to be tested can be 1, and the physical links of the uplink port to be tested are 16.

[0071] Moreover, each uplink port to be tested, the corresponding first RC verification agent component 140, the first PHY verification agent component 160, the first EP verification agent component 120, and the first protocol comparator 190 form a first test unit, and multiple first test units are independent of each other; at the same time, each downlink port to be tested, the corresponding second RC verification agent component 150, the second PHY verification agent component 170, the second EP verification agent component 130, and the second protocol comparator 200 form a second test unit, and multiple second test units are independent of each other.

[0072] Through the independent test units composed of the verification agent components and the protocol comparators, each test unit can perform independent simulation tests, thereby realizing parallel tests and greatly improving the verification efficiency of the forking characteristics.

[0073] Among them, when verifying the forking characteristics of the PCIe Switch, the verification test points include the low-power mode, clock reset, register access, PCIe enumeration process, various forking scenario configurations, pipe interface data transceiver path, and high-speed serial data transceiver path. Therefore, by setting up independent test units, different test units can perform different test point verifications, improving the flexibility of the operation of the forking characteristic verification system of the entire PCIe Switch.

[0074] For example, please refer to Figure 2 , the upstream ports are P1, P2, P3, and P4 respectively, the first EP verification proxy components 120 are EP1, EP2, EP3, and EP4 respectively, the first RC verification proxy components 140 are RC1, RC2, RC3, and RC4 respectively, and the first PHY verification proxy components 160 are PHY1, PHY2, PHY3, and PHY4 respectively. Then, during the verification process, P1, EP1, RC1, PHY1, and the first protocol comparator 190 form a first test unit, denoted as C1; P2, EP2, RC2, PHY2, and the first protocol comparator 190 form a first test unit, denoted as C2; P3, EP3, RC3, PHY3, and the first protocol comparator 190 form a first test unit, denoted as C3; P4, EP4, RC4, PHY4, and the first protocol comparator 190 form a first test unit, denoted as C4; then C1, C2, C3, and C4 can operate independently. For example, C1 can perform the low-power mode test, C2 can perform the register access test, C3 can perform the PCIe enumeration process test, and C4 can perform the clock reset test. Of course, the four first test units can also simultaneously perform tests on the same type of verification test points. For example, C1, C2, C3, and C4 all perform the PCIe enumeration process test, which is not limited here.

[0075] When conducting tests, the EP verification agent component and the RC verification agent component need to synchronously send test signals. That is, when verifying the forking characteristics of the upstream port, the first EP verification agent component 120 and the first RC verification agent component 140 synchronously send test signals. Among them, after the test signal sent by the first EP verification agent component 120 is processed by the upstream port, the processed signal is sent to the first PHY verification agent component 160, and then sent by the first PHY verification agent component 160 to the first RC verification agent component 140. At the same time, the test signal sent by the first RC verification agent component 140 is sent to the upstream port after passing through the first PHY verification agent component 160, and after being processed by the upstream port, the processed signal is sent to the first EP verification agent component 120. Similarly, when verifying the forking characteristics of the downstream port, the second EP verification agent component 130 and the second RC verification agent component 150 synchronously send test signals.

[0076] The first protocol comparator 190 and the second protocol comparator 200 detect the protocol behavior of the PCIe Switch by receiving the stimuli from the verification agent components and the responses of the internal upstream and downstream ports of the DUT module 110, compare it with the standard protocol specification, so as to complete the automatic check of the PCIe protocol. If there is any behavior that does not conform to the protocol, corresponding error messages will be printed, and at the same time, the forking characteristic verification system of the entire PCIe Switch will be debugged, such as debugging the configurations of each verification agent component, debugging environmental wiring problems or code problems, etc.

[0077] It can be seen that in the forking characteristic verification system of the PCIe Switch provided by this application, the verification of the upstream port and the downstream port is relatively independent. That is, each upstream port and downstream port are connected to relatively independent test units, and the tests between each upstream port and each downstream port are independent, and can independently determine the start and end of the test, getting rid of the unified control of the general verification framework. Through flexible configuration, the forking characteristics of both the upstream port and the downstream port can be configured at the same time, and the simulation cases run by each test unit can be different, making the verification of each forking scenario more sufficient. At the same time, the verification agent component is used to replace the real PCIe controller in the verification environment, which speeds up the verification convergence speed.

[0078] Based on the above implementation method, the embodiments of this application also provide a method for verifying the forking characteristics of a PCIe Switch. Please refer to Figure 3 and the method includes:

[0079] S102, extracting test points according to the protocol parameters of the DUT module and the forking form of the PCIe Switch, where the test points include test objects in different modes.

[0080] S104, generate test sequences and test cases based on test points; wherein, each test case covers one or more function points, and all test cases cover all function points.

[0081] S106, configure the forking form of the DUT module and control the operation of each verification agent component.

[0082] S108, generate stimuli based on the test sequences and test cases and send the stimuli to each verification agent component.

[0083] S110, use the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimuli, so as to implement the verification of the forking characteristics of the upstream port and the downstream port.

[0084] Among them, the protocol parameters of the DUT module 110 include the PCIe protocol and the PCIe interface protocol. The forking form of the PCIe Switch includes the forking specification of the to-be-tested PCIe Switch and the design scheme, and the design scheme includes the number of to-be-tested upstream ports and to-be-tested downstream ports.

[0085] In this application, according to the forking form of the PCIe Switch, the extracted test points include: low power consumption mode, clock reset, register access, PCIe enumeration process, configuration of each forking scenario, data transceiver path of the pipe interface, and data transceiver path of the high-speed serial.

[0086] After developing the test sequences and test cases, build a verification environment, instantiate each verification agent component, and verify the interfaces at the top level; connect each verification agent component to the DUT module 110.

[0087] Among them, the test sequence is a class library developed together with the test cases and is used to generate test stimuli. According to different verification function points, different test sequences are constructed to generate different stimuli to verify the to-be-tested design. A test case is a basic test scenario and is used to simulate the response of the DUT module 110 in a specific state. The test cases start the test sequences in the order required by the verification components. Each case covers one or more function points, and all test cases must cover all PCIe Switch forking function points to achieve the completeness of verification.

[0088] After completing the above configuration, the verification environment can be initialized. According to different configuration class information, configure the forking form of the DUT module 110 and control the operation of each verification agent component, that is, control the opening and closing of each verification agent component. Determine the number of downstram ports, determine the actual applied pipe width and serial width of each upstream port and downstream port, and the capabilities supported by each verification agent component.

[0089] After that, incentives are generated based on the test sequence and test cases, and the incentives are sent to each verification agent component. Among them, the test cases drive the verification agent components to complete PCIe enumeration and send PCIe data packet incentives. The data packets are processed by the DUT module 110, and the corresponding drive verification agent component will receive the incentives and send response data packets. It should be noted that the "corresponding end" mentioned in this application refers to the port opposite to the verification agent component that sends the incentives. For example, for the first EP verification agent component 120, its corresponding end is the first RC verification agent component 140; for the second RC verification agent component 150, its corresponding end is the second EP verification agent component 130.

[0090] Finally, the first protocol comparer 190 and the second protocol comparer are used to verify the response data generated based on the incentives, so as to realize the verification of the forking characteristics of the upstream port and the downstream port. Among them, the first protocol comparer 190 and the second protocol comparer debug each test case one by one to ensure that each test case truly covers the verification test points extracted in the above-mentioned step one. And, the first protocol comparer 190 and the second protocol comparer mainly compare the response data with the standard data. If the comparison fails, the configuration of each verification agent component is debugged, or the wiring of the PCIe Switch is debugged, or the code is debugged until all response data and standard data pass the comparison.

[0091] In addition, in one implementation manner, after the step of S110, the method further includes:

[0092] S112, perform regression with coverage for all test cases, and collect code coverage and functional coverage.

[0093] In actual processing, all test cases can be regressed with coverage, and code coverage and functional coverage can be collected. Coverage analysis is performed. For the uncovered points, new or modified test cases are added to cover them. Among them, code coverage refers to the ratio of the number of actually executed code lines to the total number of code lines during software testing, usually expressed as a percentage. It is calculated by tracking the execution situation during the test process with professional tools. Common calculation criteria include line coverage, function coverage, statement coverage, branch coverage, and condition coverage, etc., which are mainly used to measure the execution situation of the design code. Functional coverage is to write covergroup and coverpoint according to the verification plan to cover specific data, addresses, or other control signals. Its purpose is to ensure that the behavior of the design in the actual environment meets the expectations, and possible missing functions are discovered by artificially defining the coverage scenarios. By determining the code coverage and functional coverage and covering the uncovered points, the running performance of the forking characteristic verification system of the entire PCIe Switch can be improved.

[0094] In summary, the embodiments of the present application provide a system and method for verifying the forking characteristics of a PCIe Switch. The system for verifying the forking characteristics of the PCIe Switch includes: a DUT module, where the DUT module includes a plurality of upstream ports and a plurality of downstream ports; a first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component; the first EP verification proxy component and the first PHY verification proxy component are both connected to the upstream ports, and the first RC verification proxy component is connected to the first PHY verification proxy component; the second RC verification proxy component and the second PHY verification proxy component are both connected to the downstream ports, and the second EP verification proxy component is connected to the second PHY verification proxy component; the first EP verification proxy component and the second EP verification proxy component are both used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are both used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are both used to simulate PCIe PHY behavior; a configuration module, connected to the DUT module and each verification proxy component, and used to configure the forking form of the upstream ports and the downstream ports and the behavior of each verification proxy component; a first protocol comparator and a second protocol comparator, the first protocol comparator is connected to the first EP verification proxy component and the first RC verification proxy component, and the second protocol comparator is connected to the second EP verification proxy component and the second RC verification proxy component; the first protocol comparator is used to verify the forking characteristics of the upstream ports, and the second protocol comparator is used to synchronously verify the forking characteristics of the downstream ports.

[0095] On the one hand, since the PCIe Switch fork characteristic verification system provided by this application is provided with a first protocol comparator and a second protocol comparator, and the test unit composed of the first protocol comparator, the first EP verification agent component, the first PHY verification agent component, and the first RC verification agent component can implement the fork characteristic verification of the upstream port; while the test unit composed of the second protocol comparator, the second EP verification agent component, the second PHY verification agent component, and the second RC verification agent component can synchronously implement the fork characteristic verification of the downstream port. Therefore, in the entire verification system, the fork characteristic verification of the upstream port and the downstream port is simultaneously achieved through a set of verification environments, reducing the consumption of manpower and resources, and improving the verification efficiency at the same time. On the other hand, since the first EP verification agent component and the second EP verification agent component are both used to simulate the terminal device controller, the first RC verification agent component and the second RC verification agent component are both used to simulate the master device controller, and the first PHY verification agent component and the second PHY verification agent component are both used to simulate the PCIe PHY behavior; therefore, each verification agent component is a virtual functional component, replacing the traditional physical controller, reducing the system construction cost, accelerating the verification convergence speed, and thus improving the verification efficiency of the entire system.

[0096] The above are only the preferred embodiments of this application and are not intended to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

[0097] For those skilled in the art, it is obvious that this application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of this application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of this application is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in this application. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A PCIe Switch bifurcation characteristic verification system, characterized in that: The PCIe Switch bifurcation characteristic verification system includes: A DUT module, wherein the DUT module includes a plurality of uplink ports and a plurality of downlink ports; a first EP verification agent component, a second EP verification agent component, a first RC verification agent component, a second RC verification agent component, a first PHY verification agent component, and a second PHY verification agent component; the first EP verification agent component and the first PHY verification agent component are both connected to the upstream port, and the first RC verification agent component is connected to the first PHY verification agent component; the second RC verification agent component and the second PHY verification agent component are both connected to the downstream port, and the second EP verification agent component is connected to the second PHY verification agent component; the first EP verification agent component and the second EP verification agent component are both used to simulate a terminal device controller, the first RC verification agent component and the second RC verification agent component are both used to simulate a master device controller, and the first PHY verification agent component and the second PHY verification agent component are both used to simulate PCIe PHY behavior; A configuration module, connected to the DUT module and each verification agent component, and used to configure the bifurcation form of the upstream port and the downstream port and the behavior of each verification agent component; A first protocol comparator and a second protocol comparator, wherein the first protocol comparator is connected to the first EP verification agent component and the first RC verification agent component, and the second protocol comparator is connected to the second EP verification agent component and the second RC verification agent component; the first protocol comparator is used to verify the bifurcation characteristics of the upstream port, and the second protocol comparator is used to synchronously verify the bifurcation characteristics of the downstream port.

2. The PCIe Switch bifurcation characteristic verification system according to claim 1, characterized in that: The first EP verification agent component, the second EP verification agent component, the first RC verification agent component, the second RC verification agent component, the first PHY verification agent component and the second PHY verification agent component are all simulation models implemented by Verilog or SystermVerilog codes.

3. The PCIe Switch bifurcation characteristic verification system according to claim 1, characterized in that: The DUT module includes multiple physical links, and the configuration module is used to configure the number of upstream ports to be tested and downstream ports to be tested of the DUT module, and configure the number of physical links connecting each upstream port to be tested and the downstream port to be tested, so as to realize the configuration of the bifurcated form of the upstream port and the downstream port.

4. The PCIe Switch bifurcation characteristic verification system according to claim 3, characterized in that: Each of the uplink ports to be tested and the corresponding first RC verification agent component, the first PHY verification agent component, the first EP verification agent component and the first protocol comparer form a first test unit, and the plurality of first test units are independent of each other; Each of the downlink ports to be tested and the corresponding second RC verification agent component, the second PHY verification agent component, the second EP verification agent component and the second protocol comparator form a second test unit, and the multiple second test units are independent of each other.

5. The PCIe Switch bifurcation characteristic verification system according to claim 1, characterized in that: When verifying the bifurcation feature of the uplink port, the first EP verification agent component and the first RC verification agent component synchronously send a test signal; When verifying the bifurcation feature of the downstream port, the second EP verification agent component and the second RC verification agent component synchronously send a test signal.

6. The PCIe Switch bifurcation characteristic verification system according to claim 1, characterized in that: The DUT module provides a plurality of pipe bus interfaces and a plurality of serial interfaces, each of the uplink ports is connected to the first EP verification agent component through the pipe bus interface, and is connected to the first PHY verification agent component through the serial interface; Each of the downstream ports is connected to the second RC verification agent component via the pipe bus interface, and is connected to the second PHY verification agent component via the serial interface.

7. The PCIe Switch bifurcation characteristic verification system according to claim 1, characterized in that: When verifying the bifurcation characteristics of the PCIeSwitch, the verification test points include low power mode, clock reset, register access, PCIe enumeration process, various bifurcation scenario configurations, pipe interface data transceiver path, and high-speed serial data transceiver path.

8. A method for verifying the bifurcation characteristics of a PCIe Switch, characterized in that: A bifurcation characteristic verification system for a PCIe Switch as claimed in any one of claims 1 to 7, wherein the method comprises: Extracting test points according to the protocol parameters of the DUT module and the bifurcation form of the PCIe Switch, wherein the test points include test objects in different modes; Generate test sequences and test cases based on the test points; wherein each test case covers one or more functional points, and all test cases cover all functional points; Configure the fork form of the DUT module and control the operation of each verification agent component; Generate incentives based on the test sequence and test cases, and send the incentives to each verification agent component; The first protocol comparator and the second protocol comparator are used to perform verification based on the response data generated by the stimulus, so as to realize verification of the bifurcation characteristics of the upstream port and the downstream port.

9. The PCIe Switch bifurcation characteristic verification method according to claim 8, characterized in that: After the step of using the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimulus, the method further includes: Run all test cases with coverage regression and collect code coverage and functional coverage.

10. The PCIe Switch bifurcation characteristic verification method according to claim 8, characterized in that: The step of using the first protocol comparator and the second protocol comparator to verify the response data generated based on the stimulus includes: The response data is compared with the standard data. If the comparison fails, the configuration of each verification agent component is debugged or the wiring of the PCIe Switch is debugged or the code is debugged until all the response data are compared with the standard data.

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