Layered eSPI controller and implementation method thereof

Abstract

The invention discloses a layered eSPI controller and an implementation method thereof, a chip of the layered eSPI controller comprises two asynchronous clock domains, namely, an asynchronous main clock domain and an interface clock domain, the layered eSPI controller is classified according to the characteristics of each channel in an eSPI protocol specification and finally gathers into one path, the transmission sequence is determined through arbitration, the design level is clear, and the reliability is high. Decoupling is carried out between the modules, and the design is simplified to a great extent.

Description

Technical Field

[0001] The present invention relates to the fields of IC integrated circuit design and bus interfaces, and particularly to a hierarchical eSPI controller and an implementation method thereof. Background Art

[0002] With the continuous development of very large scale integrated circuits, the functions of chips have become more and more centralized and specialized. Various chips work together in the system of the entire electronic product, each performing its own functions. Therefore, the communication bus between chips is essential.

[0003] In response to different application requirements and scenarios, a series of bus interface standard specifications have emerged. Common bus interfaces in the embedded field include I2C (Inter-Integrated Circuit two-wire serial bus), SPI (Serial Peripheral interface full-duplex synchronous serial bus), UART (Universal Asynchronous Receiver / Transmitter universal asynchronous transceiver), USB (Universal Serial Bus universal serial bus), etc.

[0004] In the fields of laptops and servers, the current mainstream bus interfaces are LPC (Low Pin Count low-pin-count bus interface) and eSPI (Enhanced Serial Peripheral Interface enhanced serial peripheral interface), which are used for communication between the CPU (Central Processing Unit central processing unit) and the EC (Embedded Controller embedded controller) / BMC (Baseboard Management Controller baseboard management controller). Among them, the EC is a dedicated system-level chip, usually used in laptop computers to assist the CPU in managing some low-speed input devices, collecting battery parameters, and controlling the motherboard temperature. The BMC is applied in the server field and is more powerful than the EC, realizing functions such as autonomous monitoring, logging, recovery control, remote control, and power management.

[0005] Due to the LPC's small number of pins and high speed, it quickly became popular after the relevant specifications were released and has been used ever since. With the development of technology, LPC has gradually lost its advantages: (1) LPC requires at least 7 and a maximum of 13 signal lines; (2) 3.3V IO (Input / Output) introduces additional chip manufacturing costs; (3) LPC only supports 33MHz clock and the maximum bandwidth is only 133Mbps; (4) There are also several sideband signals transmitted between the CPU and EC / BMC, and LPC cannot receive them in-band.

[0006] Due to the many limitations of LPC, Intel launched the eSPI (Enhanced Serial Peripheral Interface) interface in 2016. Compared with LPC, it has the following advantages: (1) It fully reuses the timing and electrical characteristics of the SPI interface, and defines a protocol on this basis to meet the communication requirements between the CPU and the EC / BMC; (2) It defines four channels: peripheral channel / virtual wire interface channel / out of band message channel / run-time flash access channel, and receives all sideband signals in LPC into the band, requiring only 8 signal lines; (3) It supports a maximum clock of 66MHz and a maximum bandwidth of 264Mbps.

[0007] Since the eSPI interface specification was introduced relatively late, it has not yet completely replaced LPC. Today's mainstream EC / BMC supports both LPC and eSPI interfaces. If you want to implement the eSPI communication interface between the CPU and EC / BMC, you need to spend a lot of time and manpower on self-development, or purchase third-party IP at an expensive price. Summary of the invention

[0008] The object of the present invention is to provide a hierarchical eSPI controller and an implementation method thereof. The hierarchical eSPI controller chip includes two asynchronous clock domains, namely an asynchronous main clock domain and an interface clock domain. The hierarchical eSPI controller is classified according to the characteristics of each channel in the eSPI protocol specification, and finally converged into one channel. The transmission order is determined by arbitration. The design hierarchy is clear, and the modules are decoupled, which greatly simplifies the design.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] A hierarchical eSPI controller, characterized in that: it includes two clock domains, an independent main clock domain and an interface clock domain. Synchronization between the main clock domain and the interface clock domain is achieved through a cross-clock domain module. The main clock domain is used for the upper-layer AXI bus and APB bus interfaces, register configuration, data packing, and logic control. The interface clock domain is used for the eSPI bus interface, sending the upper-layer data according to the protocol specification, and processing the error response on one side of the eSPI interface.

[0011] Furthermore, the main clock domain includes

[0012] A register module, containing registers addressed by address, for the initialization of the eSPI controller, interrupt enable, and interrupt status acquisition, and also for initiating transmission requests, receiving data, configuration, and control of independent channels / virtual wire interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface information channels;

[0013] A peripheral device channel control module, for controlling the transmission of peripheral device channels;

[0014] An arbitration module, for priority arbitration of all transmission channels;

[0015] An APB slave interface, handling the transmission requests of the APB bus and implementing access to the register module addressed by address;

[0016] A clock and reset module, for generating the internal clock and reset of the main clock domain, controlled by the register module;

[0017] An interrupt generation module, for interrupt processing and generation, outputting to the CPU or other modules with interrupt processing capabilities;

[0018] An AXI slave interface, handling the transmission requests of the AXI bus descending from the chip side, docking with the peripheral device channel control module, and converting the requests into corresponding eSPI interface peripheral device channel transmissions;

[0019] An AXI master interface, handling the peripheral device channel requests ascending from the eSPI slave device side, docking with the peripheral device channel control module, and converting the requests into corresponding AXI interface transmissions;

[0020] An AXI interface detection module, for monitoring the transmissions on the AXI slave interface and the AXI master interface, to avoid the transmissions on the AXI master interface and the AXI slave interface from not ending normally due to the abnormality of the external eSPI slave device;

[0021] A status synchronization module, for updating the status returned by the eSPI slave signal, and responsible for handling the errors on the eSPI interface and updating them to the corresponding status registers;

[0022] An exception handling module, which is used to handle exception events that need to be returned, and returns an unsuccessful completion message to the eSPI slave device according to the type of the request.

[0023] Furthermore, the interface clock domain further includes

[0024] A serial deserialization module, which serializes the transmitted data and deserializes the received data according to the bus mode (1x / 2x / 4x) configured in the register;

[0025] A cyclic redundancy check module, which is used to generate the check code of the downstream message packet and check the requests and data returned by the eSPI slave device;

[0026] A sampling delay module, which adjusts the sampling edge of the received data by configuring the register, eliminates the delay introduced by the IO interface and wiring, etc., and ensures that the correct data is collected;

[0027] A clock stretching module, which stops the clock output of the eSPI interface when the RX FIFO is full, is used to reduce the required RX FIFO size, and eliminates the limitation that the main clock is greater than or equal to the interface clock domain.

[0028] A protocol state machine module, which is used to initiate and receive all transmissions and handle errors.

[0029] Furthermore, according to the initiator of the request, the transmission direction from the master device to the slave device is defined as the downstream direction, and the transmission direction from the slave device to the master device is defined as the upstream direction. The register module includes

[0030] An address addressing register, which is accessed through the APB bus interface, is used for the configuration of the entire eSPI controller, and is responsible for initiating transmissions of all channels except the peripheral device channels;

[0031] A TX FIFO, which is used to store the data to be transmitted in the downstream direction;

[0032] An RX FIFO, which is used to store the data to be received in the upstream direction;

[0033] A control logic state machine, which controls the initiation, arbitration, packet sending, response receiving, and RX data receiving of the configuration / status register transmission requests.

[0034] Furthermore, the peripheral device channel control module includes a downstream direction module and an upstream direction transmission module. The downstream direction module includes

[0035] A downstream state machine, which controls the initiation, arbitration, packet sending, response receiving, and RX data receiving of the downstream direction transmission requests;

[0036] A downstream TX FIFO, which is used to store the write transmission data of the AXI slave interface;

[0037] Downlink RX FIFO, which is used to store the data returned from the eSPI slave device for the read transfer of the AXI slave interface;

[0038] The uplink direction module includes

[0039] Uplink state machine, which controls the initiation, arbitration, packet sending, response receiving and RX data receiving of the uplink direction transfer request;

[0040] Uplink TX FIFO, which stores the data returned to the eSPI slave device according to the read transfer request initiated by the eSPI slave device;

[0041] Uplink RX FIFO, which is used to store the data corresponding to the write transfer initiated by the eSPI slave device.

[0042] Furthermore, the arbitration module includes the following four request inputs

[0043] Register request, which is used to transfer the transfer initiated by the register module;

[0044] Peripheral device interface request, which is used to transfer the transfer initiated by the peripheral device channel control module;

[0045] Exception handling request, which is used to transfer the transfer initiated by the exception handling module;

[0046] Prompt signal request, which is used to transfer the transfer initiated by the prompt signal in the eSPI slave signal;

[0047] The arbitration module determines the order of requests initiated on the eSPI interface according to the internal arbitration mechanism.

[0048] Furthermore, the cross-clock domain module includes

[0049] ASYNC TX FIFO. After the transfer request in the master clock domain is arbitrated in the downlink direction, the data packet is written into the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from it;

[0050] ASYNC RX FIFO. After the transfer request in the master clock domain is arbitrated in the uplink direction, the transfer on the eSPI bus is unpacked and verified. After verification, the corresponding data is written into the ASYNC RX FIFO, and the master clock domain obtains the data from it and distributes it to the corresponding processing module;

[0051] Synchronization module, which is used for the synchronization of control signals between the master clock domain and the interface clock domain.

[0052] A method for implementing a hierarchical eSPI controller chip includes the following steps:

[0053] The APB master is connected to the APB slave interface on the eSPI controller side, the AXI master is connected to the AXI slave interface on the eSPI controller side, the AXI slave is connected to the AXI master interface on the eSPI controller side, and the eSPI interface is connected to the off-chip eSPI bus slave device;

[0054] The transmission requests of the independent channel / virtual wire interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface message channel are initiated through the address addressing register configured by the APB slave interface; the transmission requests of the peripheral device channel enter the peripheral channel control module through the transmission requests of the AXI slave interface; the prompt signal initiated by the eSPI slave device is synchronized to the main clock domain of the eSPI controller, and a prompt signal transmission request is generated; for the upstream read request initiated by the eSPI slave device, after the protocol state machine module detects an error, it synchronizes the flag signal to the exception handling module, and the exception handling module forms a packet according to the current transmission and sends it to the exception handling path to initiate the exception handling module transmission request;

[0055] In the arbitration module, two-level cyclic arbitration is used for the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests. The arbitration module performs the first-level arbitration on the transmission requests initiated by the register module, and then performs the second-level arbitration with the prompt signal transmission requests initiated by the peripheral device channel control module, the exception handling module, and the eSPI slave device, and determines the transmission sequence through the arbitration result;

[0056] After the arbitration passes, the transmission starts. For the requests initiated by the eSPI controller side and the requests initiated by the eSPI slave device that require data to be returned, after obtaining the arbitration, the upper layer will write the data packet to the ASYNC TX FIFO, and the link layer will send it to the eSPI bus according to the protocol regulations, and set the corresponding status bit according to the response returned by the eSPI slave device; for the requests initiated by the eSPI slave device side and the requests initiated by the eSPI controller side that require data to be returned, after obtaining the arbitration, it will unpack and verify the transmission on the eSPI bus. If there is no error, it will be written to the ASYNC RX FIFO, and the upper layer will obtain the data and unpack it again, and store the data in the register module or the data memory in the peripheral device channel control module according to the transmission type and packet structure; for the exception handling transmission request, an unsuccessful completion message is returned to the eSPI slave device; for the prompt signal transmission request, a status command is initiated to obtain the status information on the eSPI slave device side.

[0057] Furthermore, the state transition relationship and conditions between the control logic state machines are as follows

[0058] (1) From IDLE state to Load_Data state: Since the virtual wire interface requests with modifiers and the peripheral device message requests are in the upstream direction, the parsing of packets is located in the upstream state machines of the protocol state machine module and the peripheral device channel control module respectively. After receiving the flag signal, the control logic state machine jumps to the load data state to receive data and the synchronization state;

[0059] (2) IDLE state and xxx_Req state: When a command other than those described in (1) is received in the IDLE state, it will enter the xxx_Req state. This state is for waiting for arbitration after receiving a request. If a transmission request as described in (1) is received in this state, indicating that the interface layer is performing the corresponding transmission, it will return to the IDLE state and then process the corresponding transmission according to (1). If a high-priority interrupts a low-priority event occurs in this state, it will jump back to the IDLE state and reprocess the high-priority request;

[0060] (3) xxx_Req state and xxx_Cmd_Send state: In the xxx_Req state, after receiving the arbitration obtained flag, it jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after sending. Otherwise, it enters the Wait_Rsp state and enters the Check_Rsp state after receiving the response;

[0061] (4) Check_Rsp state: If the received response is not accepted or there is no data transmission, the transmission ends and enters the CmdCpl state, waiting for state synchronization; For upstream out-of-band message channel and real-time storage access channel requests, it needs to enter the Checkt_Cycletype state for checking. If the CycleType is correct, it receives the data returned by the eSPI slave device like other commands;

[0062] (5) CmdCpl state: The data loading is completed, the Cycletype parsing is incorrect, a non-accepted response or no data transmission is received, and an in-band reset will all enter this state. This state waits for the state synchronization to be completed, then returns to the IDLE and generates the corresponding interrupt, waiting for the next transmission request.

[0063] Furthermore, the state transition relationships and conditions of the protocol state machine are as follows

[0064] (1) From PRO_IDLE state to PRO_CMD state: After the upper layer request obtains arbitration, the data is put into the Async TXFIFO. After receiving the non-empty signal, it is adjusted to the PRO_CMD state to start processing the command;

[0065] (2) PRO_CMD state: Parse the command, which is divided into three categories according to the command type

[0066] (a) Reset command (RESET CMD), which does not require the eSPI slave device to return a response and directly jumps to the PRO_CPL state;

[0067] (b) Commands without a packet structure directly enter the PRO_TXCRC state;

[0068] (c) Commands with a packet structure enter the PRO_TXPACKET state and continue to be processed until the Async TX FIFO is empty and then jump to the PRO_TXCRC state;

[0069] (3) PRO_TXCRC state: In this state, a cyclic redundancy check code is generated according to the sent command and packet, output to the serial module, and sent according to the mode configured in the register. After sending is completed, it enters the PRO_TAR state;

[0070] (4) PRO_RSP state: It enters the PRO_RSP state after two cycles in the PRO_TAR stage. This state is responsible for parsing the response signal of the eSPI slave device and jumping to the following corresponding states

[0071] (a) The response is legal and the command does not require a return packet;

[0072] (b) The response is legal and there is a return packet;

[0073] (c) The waiting period exceeds the set value, or the response is illegal;

[0074] (5) PRO_RXPACKET state: In this state, the returned packet is parsed according to the initiated command. If there is an error, it enters the RPO_ERR state, otherwise it enters the PRO_STS state;

[0075] (6) PRO_ERR state: Any error that occurs during the operation cycle of the protocol state machine will enter this state. The error reason will be recorded before entering. When entering this state, a stateless synchronization flag signal is generated to allow the upper-layer state machine to skip the process of obtaining the eSPI slave device state and then synchronize back to the interface domain to indicate that it can enter the next PRO_CPL state;

[0076] (7) PRO_STS state: Obtain the eSPI slave device state and write it into the Async RX FIFO;

[0077] (8) PRO_CPL: The protocol state machine finally converges to this state, which is responsible for integrating protocol errors and cyclic redundancy check errors during the transmission process, writing them into the Async RX FIFO according to the encoding, and returning to the PRO_IDLE state after completion.

[0078] Due to the above technical solutions, the present invention has the following beneficial effects:

[0079] 1. The eSPI controller chip design is divided into two asynchronous clock domains, namely the main clock domain and the interface clock domain, eliminating the clock dependence of different eSPI rate modes on the system bus side. The boundaries between the two clock domains are clear, and cross-clock domain processing is simple, avoiding the metastability risk introduced by different clock domains.

[0080] 2. The design adopts the mainstream AMBA bus, and selects the AXI4 and APB buses according to the traffic bandwidth and protocol requirements. Since there is no coupling between the bus interface module and the internal functional module, the interface is clear and the logic is simple. It can be easily replaced with other bus interfaces without modifying the underlying logic.

[0081] 3. Classification is carried out according to the characteristics of each channel in the eSPI protocol specification, and finally converged. The transmission sequence is determined through arbitration. The design hierarchy is clear, and the modules are decoupled, greatly simplifying the design. A feasible implementation scheme for the eSPI controller design is provided and is easy to implement.

[0082] 4. Two-level arbitration is adopted. Transmissions related to the register module share the same control logic state machine, and only one request can be sent at the same time. The paths related to the register module and the peripheral device interface are kept independent. The arbitration module structure is simpler and easier to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The present invention will be further described below with reference to the drawings.

[0084] Figure 1 It is a topology diagram of a hierarchical eSPI controller chip.

[0085] Figure 2 It is a state transition diagram of the control logic state machine.

[0086] Figure 3 It is a state transition diagram between states of the protocol state machine. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0087] The definitions of the technical terms recorded in the present invention are shown in Table 1.

[0088] Table 1: Definitions of Technical Terms

[0089]

[0090]

[0091] Such as Figure 1A hierarchical eSPI controller as shown includes two clock domains, an independent master clock domain and an interface clock domain. The master clock domain and the interface clock domain are synchronized through a cross-clock domain module. The master clock domain is used for the upper-layer AXI bus and APB bus interfaces, register configuration, data packing, and logic control. The interface clock domain is used for the eSPI bus interface to send the upper-layer data according to the protocol specification and process the error responses from the slave interface side.

[0092] The master clock domain includes

[0093] a register module containing address-addressed registers for the initialization of the eSPI controller, interrupt enabling, and interrupt status acquisition, and also for initiating transmission requests, receiving data, configuration, and control of independent channel / virtual wire interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface information channel.

[0094] a peripheral device channel control module for controlling the transmission of peripheral device channels.

[0095] an arbitration module for priority arbitration of all transmission channels.

[0096] an APB slave interface for handling the transmission requests of the APB bus and implementing access to the address-addressed register module.

[0097] a clock and reset module for generating the internal clock and reset of the master clock domain, controlled by the register module; an interrupt generation module for interrupt handling and generation, outputting to the CPU or other modules with interrupt handling capabilities.

[0098] an AXI slave interface for handling the transmission requests of the AXI bus descending from the chip side, docking with the peripheral device channel control module, and converting the requests into corresponding eSPI interface peripheral device channel transmissions.

[0099] an AXI master interface for handling the peripheral device channel requests ascending from the eSPI slave device side, docking with the peripheral device channel control module, and converting the requests into corresponding AXI interface transmissions.

[0100] an AXI interface detection module for monitoring the transmissions on the AXI slave interface and the AXI master interface to avoid abnormal transmissions on the AXI master interface and the AXI slave interface from not ending properly due to external eSPI slave devices.

[0101] a status synchronization module for updating the status returned by the eSPI slave signal and responsible for handling errors on the eSPI interface and updating them to the corresponding status registers.

[0102] an exception handling module for handling the exception events that need to be returned and returning an unsuccessful completion message to the eSPI slave device according to the type of the request.

[0103] The register module receives the signals from the upper-layer APB bus, and the peripheral device channel control module receives the signals from the upper-layer AXI bus. The data transmitted by the register module and the peripheral device channel control module is arbitrated in the arbitration module to determine the order of initiating the transmission. After arbitration, the protocol state machine module sends the received upper-layer data according to the installed protocol through the eSPI bus.

[0104] The interface clock domain includes

[0105] The serial deserialization module serializes the transmitted data and deserializes the received data according to the bus mode configured in the register.

[0106] The cyclic redundancy check module is used to generate the check code for the downstream message packet and verify the requests and data returned by the eSPI slave device.

[0107] The sampling delay module adjusts the sampling edge of the received data through the configuration register to eliminate the delay introduced by the IO interface and wiring, etc., and ensure that the correct data is acquired.

[0108] The clock stretching module stops the clock output of the eSPI interface when the RX FIFO is full, which is used to reduce the required RX FIFO size and eliminate the limitation that the main clock is greater than or equal to the interface clock domain.

[0109] The protocol state machine module is used to initiate and receive all transmissions and handle errors.

[0110] According to the initiator of the request, the transmission direction from the master device to the slave device is defined as the downstream direction, and the transmission direction from the slave device to the master device is defined as the upstream direction. The register module includes

[0111] The address addressing register is accessed through the APB bus interface, which is used for the configuration of the entire eSPI controller and is responsible for initiating the transmission of all channels except the peripheral device channel.

[0112] The TX FIFO is used to store the data to be transmitted in the downstream direction.

[0113] The RX FIFO is used to store the data to be received in the upstream direction.

[0114] The control logic state machine controls the initiation, arbitration, packet sending, response receiving, and RX data receiving of the configuration / status register transmission requests.

[0115] The peripheral device channel control module includes a downstream direction module and an upstream direction transmission module. The downstream direction module includes

[0116] The downstream state machine controls the initiation, arbitration, packet sending, response receiving, and RX data receiving of the downstream direction transmission requests.

[0117] A downlink TX FIFO for storing write transfer data from the AXI slave interface.

[0118] A downlink RX FIFO for storing data returned from the eSPI slave device during read transfer from the AXI slave interface.

[0119] The main mapping relationship between the AXI slave signal write path and the eSPI transfer can be described as follows:

[0120] (1) The signals awaddr and wstrb together determine the starting address of the write transfer.

[0121] (2) The signals awsize, awlen, and wstrb together determine the total amount of data to be written, and the written data is stored in the downlink TX FIFO.

[0122] (3) Based on the starting address and the quantity of data of the write transfer, the mapping of the PUT_PC, PUT_IOWR_SHORT, or PUTMEMWR32_SHORT command is determined.

[0123] (4) The PUT_IOWR_SHORT command needs to wait for the eSPI Slave response and then return the AXI interface response, while other commands can return the response after the downlink TX FIFO is empty.

[0124] The main mapping relationship between the AXI slave signal read path and the eSPI transfer can be described as follows:

[0125] (1) The signal araddr determines the starting address of the read transfer.

[0126] (2) The signals arsize and arlen together determine the total amount of data to be read.

[0127] (3) Based on the starting address and the quantity of data of the read transfer, the mapping of the PUT_NP, PUT_IORD_SHORT, or PUTMEMRD32_SHORT command is determined.

[0128] (4) After the eSPI interface responds and returns the data, it is stored in the downlink RX FIFO.

[0129] (5) Return the AXI slave interface response.

[0130] The upstream direction module includes

[0131] An upstream state machine that controls the initiation, arbitration, packet sending, response reception, and RX data reception of upstream direction transfer requests;

[0132] The upstream TX FIFO stores the data returned to the eSPI slave according to the read transfer request initiated by the eSPI slave.

[0133] The upstream RX FIFO is used to store the data corresponding to the write transfer initiated by the eSPI slave.

[0134] The main mapping relationship between the eSPI transfer and the AXI master interface write path can be described as follows:

[0135] 1. The eSPI interface initiates the prompt signals Alert + PC_AVAIL.

[0136] 2. The eSPI master interface obtains the requested address and data through GET_PC, and stores the data in the upstream RX FIFO.

[0137] 3. Generate the signals awaddr, awlen, and awstrb according to the address and data volume.

[0138] 4. After the data transmission of the AXI write channel is completed, a new eSPI transfer can be processed without waiting for the response channel to return.

[0139] The main mapping relationship between the eSPI transfer and the AXI master interface read path can be described as follows:

[0140] 1. The eSPI interface initiates the prompt signals Alert + NP_AVAIL.

[0141] 2. The eSPI master interface obtains the requested address and data volume through GET_NP.

[0142] 3. Generate the aligned signals araddr and arlen according to the address and data volume.

[0143] 4. After waiting for the data to return from the AXI read channel, intercept the data according to the requested starting address and data volume, pack it by byte and transmit it, and return the data through PUT_PC + Completion With Data.

[0144] The arbitration module includes the following four types of transfer requests

[0145] Register request, used to transfer the transfer initiated by the register module;

[0146] Peripheral device interface request, used to transfer the transfer initiated by the peripheral device channel control module;

[0147] Exception handling request, used to transfer the transfer initiated by the exception handling module;

[0148] Prompt signal request, used to transfer the transfer initiated by the prompt signal in the eSPI slave signal;

[0149] The arbitration module determines the order in which requests are initiated on the eSPI interface according to the internal arbitration mechanism.

[0150] The arbitration module first arbitrates the transmissions initiated by the register module, and then arbitrates the transmissions initiated by the register module, the peripheral device channel control module, the exception handling module, and the prompt signal.

[0151] The priority is encoded with 2 bits. The smaller the encoded value, the higher the priority. The priorities of various commands included in the first-level arbitration are shown in Table 2, and the priorities of various requests in the second-level arbitration are shown in Table 3.

[0152] Table 2: Priorities of various commands in the first-level arbitration.

[0153]

[0154] Table 3: Priorities of various requests in the second-level arbitration.

[0155]

[0156]

[0157] The reasons for priority allocation are as follows:

[0158] 1. Independent-related commands are global commands and have the highest priority of 2'b00.

[0159] 2. Requests of the downstream virtual wire interface class, which transmit in-band system events and GPIO downstream, have the highest priority of 2'b00.

[0160] 3. Requests of the upstream virtual wire interface class. The eSPI interface may have system events or interrupts that need to be processed in a timely manner on the eSPI master interface side, and a relatively high priority of 2'b01 is assigned to it.

[0161] 4. Exception handling belongs to error events. In order to be able to return errors to the eSPI interface in a timely manner, a relatively high priority of 2'b10 is assigned to it.

[0162] 5. Data transmission requests (including peripheral device channel class / out-of-band message class / running flash access class) maintain a lower priority of 2'b11.

[0163] In the arbitration module, two-level cyclic arbitration is used for the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests. The arbitration module performs the first-level arbitration on the transmission requests initiated by the register module, and then performs the second-level arbitration with the transmission requests of the peripheral device channel control module, the exception handling module, and the prompt signal initiated by the eSPI slave device, and determines the transmission order through the arbitration result.

[0164] Priority arbitration mechanism:

[0165] 1. Among different priorities, the one with higher priority is executed first.

[0166] 2. For the same priority, a cyclic arbitration method is adopted. That is, after a request is initiated and completed, it will be at a disadvantage when competing with other requests of the same priority, so as to avoid a certain type of request within the same priority being unable to obtain permission for a long time.

[0167] 3. Before the second-level arbitration gives a result, the high-priority first-level arbitration can interrupt the low-priority, and the priority order of the same level will not be affected after the interruption.

[0168] 4. After the second-level arbitration ends, the transmission will start directly, and no more arbitration and priority interruption requests will be received until the transmission is completed.

[0169] After the arbitration is passed, the transmission starts. For the requests initiated by the eSPI controller side and the requests initiated by the eSPI slave device that need to return data, after obtaining the arbitration, the upper layer will write the data packet to the ASYNC TX FIFO. The link layer will send it to the eSPI bus according to the protocol regulations, and set the corresponding status bits according to the response returned by the eSPI slave device; for the requests initiated by the eSPI slave device side and the requests initiated by the eSPI controller side that need to return data, after obtaining the arbitration, it will unpack and verify the transmission on the eSPI bus. If it is correct, it will be written to the ASYNC RX FIFO. The upper layer will obtain the data and unpack it again, and store the data in the data memory of the register module or the peripheral device channel control module according to the transmission type and packet structure; for the abnormal handling transmission request, an unsuccessful completion message will be returned to the eSPI slave device; for the prompt signal transmission request, a status command will be initiated to obtain the status information on the eSPI slave device side.

[0170] The cross-clock domain module includes

[0171] ASYNC TX FIFO. After the transmission request in the master clock domain obtains arbitration in the downstream direction, the data packet is written to the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from it;

[0172] ASYNC RX FIFO. After the transmission request in the master clock domain obtains arbitration in the upstream direction, it unpacks and verifies the transmission on the eSPI bus. If it is correct, the corresponding data is written to the ASYNC RX FIFO, and the master clock domain obtains the data from it and distributes it to the corresponding processing module;

[0173] Synchronization module, used for the synchronization of control signals between the master clock domain and the interface clock domain.

[0174] A method for implementing a hierarchical eSPI controller chip, comprising the following steps:

[0175] The APB slave interface is connected to the APB bus slave device on the eSPI controller side, the AXI slave interface is connected to the AXI bus slave device on the eSPI controller side, the AXI master interface on the eSPI controller side is connected to the AXI bus master device inside the chip, and the eSPI interface is connected to the off-chip eSPI bus slave device.

[0176] The transmission requests of the independent channel / virtual wire interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface message channel are initiated through the address addressing register configured by the APB slave interface; the transmission requests of the peripheral device channel enter the peripheral channel control module through the transmission requests of the AXI slave interface and are initiated; the prompt signal initiated by the eSPI slave device is synchronized to the main clock domain of the eSPI controller, and a prompt signal transmission request is generated; for the upstream read request initiated by the eSPI slave device, after the protocol state machine module detects an error, the flag signal is synchronized to the exception handling module, and the exception handling module forms a packet according to the current transmission and sends it to the exception handling path to initiate an exception handling module transmission request.

[0177] The jump relationship and conditions between the states of the control logic state machine are as Figure 2 shown. For the convenience of understanding the working principle of the state machine, English identifiers are used in the figure, and Table 4 explains each state.

[0178] Table 4 Explanation of the states in the control logic state machine.

[0179] English state Chinese state IDLE Idle state xxx_Req Waiting for arbitration status after receiving xxx request xxx_CmdSend Sending xxx command status Wait_Rsp Waiting for response status Check_Rsp Checking response status Load_data Loading data status Check_Cycletype Checking cycletype status CmdCpl Request completion status

[0180] (1) From the IDLE state to the Load_Data state: Since the virtual wire interface request with modifier (VW_modifier) and the peripheral device message request (PR_RxMsg) are in the upstream direction, the parsing of the packets is located in the upstream state machines of the protocol state machine module and the peripheral device channel control module respectively. After receiving the flag signal, the control logic state machine jumps to the load data state (Load_data) to receive data and synchronize the state;

[0181] (2) The IDLE state and the xxx_Req state: Any command (Any Req) received in the IDLE state other than those described in (1) will enter the xxx_Req state. This state is the state of waiting for arbitration after receiving a request. If a transmission request described in (1) is received in this state, indicating that the interface layer is performing the corresponding transmission, it will return to the IDLE state and then process the corresponding transmission according to (1). If a high-priority interrupts a low-priority event occurs in this state, it will jump back to the IDLE state and reprocess the high-priority request;

[0182] (3) xxx_Req State and xxx_Cmd_Send State: In the xxx_Req state, after receiving the arbitration flag (RG_Grant), it jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after sending. Otherwise (Other CMD), it enters the Wait_Rsp state and enters the Check_Rsp state after receiving the response (Response Received).

[0183] (4) Check_Rsp State: If the received response is not accepted or there is no data transfer (No Accept or NoData), the transmission ends and it enters the CmdCpl state, waiting for status synchronization. For the upstream out-of-band message channel and real-time storage access channel requests (Up OOB / Flash+Accept), it needs to enter the Checkt_Cycletype state for checking. If the CycleType is correct, it receives the data returned by the eSPI slave device like other commands.

[0184] (5) CmdCpl State: It enters this state when the data loading is completed (DataLoadDone), there is a Cycletype parsing error, a non-accepted response or no data transfer (No Accept or No Data) is received, and an in-band reset (InBandReset) occurs. This state waits for the status synchronization to be completed (StatusLdDone), then returns to IDLE and generates the corresponding interrupt, waiting for the next transfer request.

[0185] The state transition relationships and conditions of the protocol state machine are as Figure 3 shown. For the convenience of understanding the working principle of the state machine, English identifiers are used in the figure, and Table 5 explains each state.

[0186] Table 5 Explanation of States in the Protocol State Machine.

[0187]

[0188]

[0189] (1) From the PRO_IDLE state to the PRO_CMD state: After the upper layer requests arbitration and puts the data into the Async TXFIFO, after receiving the non-empty signal (TX FIFO Not Empty), it adjusts to the PRO_CMD state to start processing the command.

[0190] (2) PRO_CMD State: Parse the command, which is divided into three categories according to the command type

[0191] (a) Reset Command (RESET CMD), which does not require the eSPI slave device to return a response and directly jumps to the PRO_CPL state;

[0192] (b) Command without a packet structure (CMD without TX Packet), directly enters the PRO_TXCRC state;

[0193] (c) Command with a packet structure (CMD with TX Packet), enters the PRO_TXPACKET state and continues to process until the Async TX FIFO (TX FIFO Empty) is empty and then jumps to the PRO_TXCRC state;

[0194] (3) PRO_TXCRC state: In this state, a cyclic redundancy check code is generated based on the sent command and packet, output to the serial module, and sent according to the mode configured in the register. After the transmission is completed (8-bit CRC Finished), it enters the PRO_TAR state;

[0195] (4) PRO_RSP state: Enters the PRO_RSP state after two cycles in the PRO_TAR stage. This state is responsible for parsing the response signal of the eSPI slave device and jumping to the corresponding state as follows

[0196] (a) The response is valid and the command does not require a returned packet (Valid Response without RX Packet);

[0197] (b) The response is valid and there is a returned packet (Valid Response with RX Packet);

[0198] (c) The waiting period exceeds the set value, or the response is invalid (Wait Timeout or Invalid Response);

[0199] (5) PRO_RXPACKET state: In this state, the returned packet is parsed according to the initiated command. If there is an error (CycleType Error or Length Error), it enters the RPO_ERR state; otherwise (Receive Finish without Error), it enters the PRO_STS state;

[0200] (6) PRO_ERR Status: Any error occurring within the operation cycle of the protocol state machine will cause it to enter this state. The error cause will be recorded before entering. When entering this state, a stateless synchronization flag signal (NOSTS_SyncBack) is generated to allow the upper-layer state machine to skip the process of obtaining the eSPI slave device status, and then synchronized back to the interface domain to indicate that it can enter the next PRO_CPL state.

[0201] (7) PRO_STS Status: Obtain the eSPI slave device status and write it into the Async RX FIFO.

[0202] (8) PRO_CPL: The protocol state machine finally converges to this state, which is responsible for integrating protocol errors and cyclic redundancy check errors during the transmission process, writing them into the Async RX FIFO according to the encoding, and then returning to the PRO_IDLE state after completion.

[0203] An implementation method of a hierarchical eSPI controller includes an APB master device connected to the APB slave interface on the eSPI controller side, an AXI master device connected to the AXI slave interface on the eSPI controller side, an AXI slave device connected to the AXI master interface on the eSPI controller side, and an eSPI interface connected to an off-chip eSPI bus slave device.

[0204] The transmission requests of the independent channel / virtual wire interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface message channel are initiated through the address addressing register configured by the APB slave interface; the transmission requests of the peripheral device channel enter the peripheral channel control module through the transmission requests of the AXI slave interface; the prompt signal initiated by the eSPI slave device is synchronized to the main clock domain of the eSPI controller, and a prompt signal transmission request is generated; when the protocol state machine module detects an error in the upstream read request initiated by the eSPI slave device, the flag signal is synchronized to the exception handling module, and the exception handling module forms a packet according to the current transmission and sends it to the exception handling path to initiate an exception handling module transmission request.

[0205] In the arbitration module, a two-level cyclic arbitration is performed on the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests. The arbitration module performs the first-level arbitration on the transmission requests initiated by the register module, and then performs the second-level arbitration with the transmission requests of the peripheral device channel control module, the exception handling module, and the prompt signal initiated by the eSPI slave device, and determines the transmission order based on the arbitration result.

[0206] After arbitration is passed, the transmission starts. For requests initiated by the eSPI controller side and requests initiated by the eSPI slave device that require data to be returned, after obtaining arbitration, the upper layer will write the data packet to the ASYNC TX FIFO. The link layer will send it to the eSPI bus according to the protocol regulations, and set the corresponding status bit according to the response returned by the eSPI slave device; for requests initiated by the eSPI slave device side and requests initiated by the eSPI controller side that require data to be returned, after obtaining arbitration, the transmission on the eSPI bus will be unpacked and verified. If there is no error, it will be written to the ASYNC RX FIFO. The upper layer will obtain the data and unpack it again, and store the data in the data memory of the register module or the peripheral device channel control module according to the transmission type and packet structure; for abnormal handling transmission requests, an unsuccessful completion message will be returned to the eSPI slave device; for prompt signal transmission requests, a status command will be initiated to obtain the status information on the eSPI slave device side.

[0207] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements or modifications made based on the present invention to solve substantially the same technical problems and achieve substantially the same technical effects are all covered by the protection scope of the present invention.

Claims

1. A hierarchical eSPI controller, characterized in that: It includes two clock domains, an independent main clock domain and an interface clock domain. The main clock domain and the interface clock domain are synchronized through a cross-clock domain module. The main clock domain is used for the upper-layer AXI bus and APB bus interface, register configuration, data packaging, and logic control. The interface clock domain is used for the eSPI bus interface. The upper-layer data is sent according to the protocol specification, and the error response on one side of the eSPI interface is processed.

2. A hierarchical eSPI controller according to claim 1, characterized in that: The master clock domain includes Register module, including addressable registers, used for initialization, interrupt enable, and interrupt status acquisition of the eSPI controller, as well as transmission request initiation, data reception, configuration, and control of independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface information channels; A peripheral device channel control module is used to control the transmission of peripheral device channels; Arbitration module, used for priority arbitration of all transmission channels; APB slave interface, handles the transfer request of APB bus and implements the access to the address-addressed register module; The clock and reset module is used to generate the internal clock and reset of the main clock domain, which is controlled by the register module; the interrupt generation module is used for interrupt processing and generation, and outputs to the CPU or other modules with interrupt processing capabilities; The AXI slave interface processes the transmission request of the AXI bus on the downstream side of the chip, interfaces with the peripheral device channel control module, and converts the request into the corresponding eSPI interface peripheral device channel transmission; An AXI master interface processes the peripheral device channel request from the eSPI slave device, interfaces with the peripheral device channel control module, and converts the request into a corresponding AXI interface transmission; An AXI interface detection module, used for monitoring the transmission on the AXI slave interface and the AXI master interface, to prevent the transmission on the AXI master interface and the AXI slave interface from failing to terminate normally due to an abnormality of an external eSPI slave device; The status synchronization module is used to update the status returned by the eSPI slave signal, and is responsible for handling errors on the eSPI interface and updating the corresponding status registers.

3. A hierarchical eSPI controller according to claim 2, characterized in that: The interface clock domain includes The serial deserialization module serializes the transmitted data and deserializes the received data according to the bus mode configured by the register; The cyclic redundancy check module is used to generate the check code of the downlink message packet and check the request and data returned by the eSPI slave device; The sampling delay module adjusts the sampling edge of the received data by configuring the register, eliminating the delay introduced by the IO interface and wiring, and ensuring that the correct data is collected; Clock stretching module, which stops the clock output of the eSPI interface when the RX FIFO is full, is used to reduce the required RXFIFO size and eliminate the limitation that the main clock is greater than or equal to the interface clock domain; The protocol state machine module is used to initiate and receive all transmissions and handle errors; The exception handling module is used to handle the abnormal events that need to be returned and return an unsuccessful completion message to the eSPI slave device according to the type of request.

4. A hierarchical eSPI controller according to claim 2, characterized in that: According to the initiator of the request, the transmission direction from the master device to the slave device is defined as the downlink direction, and the transmission direction from the slave device to the master device is defined as the uplink direction. The register module includes The address register is accessed through the APB bus interface and is used to configure the entire eSPI controller and is responsible for initiating transmission of all channels except the peripheral device channel; TX FIFO, used to store data to be sent in the downlink direction; RX FIFO, used to store data to be received in the uplink direction; The control logic state machine controls the initiation, arbitration, packaging and sending, response reception and RX data reception of the configuration / status register transmission request.

5. A hierarchical eSPI controller according to claim 2, characterized in that: The peripheral device channel control module includes a downlink direction module and an uplink direction transmission module. The downlink direction module includes Downlink state machine, controls the initiation, arbitration, packaging and sending of transmission requests in the downlink direction, response reception and reception of RX data; Downstream TX FIFO, used to store write transfer data from the AXI slave interface; Downstream RX FIFO, used to store data returned from the eSPI slave device by read transfers from the AXI slave interface; The uplink direction module includes The uplink state machine controls the initiation, arbitration, packaging and sending of uplink transmission requests, response reception, and reception of RX data; The uplink TX FIFO stores the data returned to the eSPI slave device according to the read transfer request initiated by the eSPI slave device; Upstream RX FIFO, used to store data corresponding to write transfers initiated by the eSPI slave device.

6. A hierarchical eSPI controller according to claim 2, characterized in that: The arbitration module includes Register request, used to convey transfers initiated by the register module; Peripheral device interface request, used to transmit the transmission initiated by the peripheral device channel control module; Exception handling request, used to transmit the transmission initiated by the exception handling module; Prompt signal request, used to transmit the transmission initiated by the eSPI prompt signal from the signal; The arbitration module determines the order in which requests are initiated on the eSPI interface according to an internal arbitration mechanism.

7. The hierarchical eSPI controller according to claim 1, characterized in that: The cross-clock domain module includes ASYNC TX FIFO, after the transmission request of the master clock domain is arbitrated in the downstream direction, the data packet is written into the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from the ASYNC TX FIFO; ASYNC RX FIFO, after the transmission request of the master clock domain is arbitrated in the uplink direction, the transmission on the eSPI bus is unpacked and checked, and the corresponding data is written to the ASYNC RX FIFO, from which the master clock domain obtains data and distributes it to the corresponding processing module; A synchronization module is used for synchronizing control signals between the main clock domain and the interface clock domain.

8. A method for implementing a hierarchical eSPI controller as claimed in any one of claims 1 to 7, characterized in that: The steps include: The APB master device is connected to the APB slave interface on the eSPI controller side, and the AXI master device is connected to the eSPI controller side AXI slave interface, AXI slave device is connected to the AXI master interface on the eSPI controller side, and the eSPI interface is connected to the off-chip eSPI bus slave device; The transmission request of the independent channel / virtual line interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface message channel is initiated through the address addressing register configured by the APB slave interface; the transmission request of the peripheral device channel is initiated by entering the peripheral channel control module through the transmission request of the AXI slave interface; The prompt signal initiated by the eSPI slave device is synchronized to the master clock domain of the eSPI controller, and a prompt signal transmission request is generated; The eSPI slave device initiates an uplink read request. After the protocol state machine module detects an error, it synchronizes the flag signal to the exception handling module. The exception handling module forms a packet based on the current transmission and sends it to the exception handling channel to initiate the exception handling module transmission request. In the arbitration module, two-level circular arbitration is adopted for the input register transfer request, peripheral device interface transfer request, exception handling transfer request and prompt signal transfer request. The arbitration module conducts the first-level arbitration for the transfer request initiated by the register module, and then conducts the second-level arbitration with the prompt signal transfer request initiated by the peripheral device channel control module, the exception handling module and the eSPI slave device. The transmission order is determined by the arbitration result. After the arbitration is passed, the transmission starts. For the request initiated by the eSPI controller side and the request initiated by the eSPI slave device that needs to return data, the upper layer will write the data packet to the ASYNC TX FIFO after obtaining arbitration, and the link layer will send it to the eSPI bus according to the protocol, and set the corresponding status bit according to the response returned by the eSPI slave device; for the request initiated by the eSPI slave device side and the request initiated by the eSPI controller side that needs to return data, the transmission on the eSPI bus will be unpacked and checked after obtaining arbitration. If there is no error, it will be written to the ASYNC RX FIFO. The upper layer will obtain the data and unpack it again, and store the data in the register module or the data storage device in the peripheral device channel control module according to the transmission type and packet structure; for the exception handling transmission request, an unsuccessful completion message is returned to the eSPI slave device; for the prompt signal transmission request, a get status command is initiated to obtain the status information of the eSPI slave device side.

9. The method for implementing a hierarchical eSPI controller according to claim 8, characterized in that: The jump relationship and conditions between the control logic state machine states are as follows (1) From IDLE state to Load_Data state: Since the virtual line interface request with modifier and the peripheral device message request are in the uplink direction, the parsing of the packet is located in the uplink state machine of the protocol state machine module and the peripheral device channel control module respectively. The control logic state machine jumps to the load data state to receive data and synchronize after receiving the flag signal; (2) IDLE state and xxx_Req state: When the IDLE state receives any command other than the one described in (1), the state will enter the xxx_Req state, which is a state where requests are received and waiting for arbitration. If the state receives the transmission request described in (1), it means that the interface layer is currently performing the corresponding transmission. The state will return to the IDLE state and process the corresponding transmission according to (1). If a high-priority interruption of a low-priority event occurs in this state, the state will jump back to the IDLE state and reprocess the high-priority request. (3) xxx_Req state and xxx_Cmd_Send state: In the xxx_Req state, after receiving the arbitration flag, the state jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after the sending is completed. Otherwise, the state enters the Wait_Rsp state, and after receiving the response, the state enters the Check_Rsp state. (4) Check_Rsp state: If the received response is not an acceptance or there is no data transmission, the transmission ends and enters the CmdCpl state, waiting for state synchronization; for the uplink out-of-band message channel and real-time storage access channel request, it is necessary to enter the Checkt_Cycletype state check. If the CycleType is correct, the data returned by the eSPI slave device is received like other commands; (5) CmdCpl state: This state is entered when data loading is completed, Cycletype parsing error occurs, a non-acceptance response is received or no data is transmitted, or an in-band reset occurs. This state waits for state synchronization to complete, then returns to IDLE and generates a corresponding interrupt, waiting for the next transmission request.

10. The method for implementing a hierarchical eSPI controller according to claim 8, characterized in that: The jump relationship and conditions between the protocol state machine states are as follows (1) PRO_IDLE state to PRO_CMD state: After the upper layer requests arbitration, the data is placed in the Async TX FIFO. After receiving a non-empty signal, it is adjusted to the PRO_CMD state to start processing the command; (2) PRO_CMD status: Parse commands and divide them into three categories according to command types. (a) Reset command (RESET CMD), no need for eSPI slave device to return a response, jump directly to PRO_CPL state; (b) Commands without packet structure directly enter the PRO_TXCRC state; (c) For commands with packet structure, enter the PRO_TXPACKET state and continue processing until the Async TX FIFO is empty and jump to the PRO_TXCRC state; (3) PRO_TXCRC state: This state generates a cyclic redundancy check code based on the sent command and packet, outputs it to the serial module, and sends it out according to the mode configured by the register. After the transmission is completed, it enters the PRO_TAR state; (4) PRO_RSP state: After the PRO_TAR phase lasts for two cycles, the PRO_RSP state is entered. This state is responsible for parsing the response signal of the eSPI slave device and jumping to the following corresponding states (a) The response is legal and the command does not require a return packet; (b) respond to legitimate and returned packets; (c) The waiting period exceeds the set value, or the response is illegal; (5) PRO_RXPACKET state: This state parses the returned packet according to the initiated command. If there is an error, it enters the RPO_ERR state, otherwise it enters the PRO_STS state; (6) PRO_ERR state: This state is entered when an error occurs during the operation cycle of the protocol state machine. The cause of the error is recorded before entering the state. When entering this state, a stateless synchronization flag signal is generated for the upper-layer state machine to skip obtaining the process status of the eSPI slave device, and then synchronize back to the interface domain to indicate that the next PRO_CPL state can be entered. (7) PRO_STS status: Get the eSPI slave device status and write it to the Async RX FIFO; (8) PRO_CPL: The protocol state machine finally converges to this state, which is responsible for integrating the protocol errors and cyclic redundancy check errors in the transmission process, writing them into the Async RX FIFO according to the encoding, and returning to the PRO_IDLE state after completion.

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