Reading control method, device, chip and system of communication interface

Abstract

The invention relates to a reading control method, device, chip and system for a communication interface, and the method comprises the steps: obtaining a channel configuration parameter sent by an upper computer, carrying out the initialization according to the channel configuration parameter, and carrying out the communication with a target channel based on a reading triggering mode under the condition of determining that the reading triggering condition of the target channel is reached, and circularly reading the data returned by the target channel based on the cycle reading frequency threshold, recording the reading frequency, and returning a first response message to the upper computer under the condition of determining that the reading frequency reaches the cycle reading frequency threshold. According to the method and the device, the cyclic reading frequency threshold value of each channel is configured, so that data can be continuously read from the channel based on the cyclic reading frequency threshold value, frequent instruction sending is avoided, main control resources are saved, and the main control interruption frequency can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a method, apparatus, chip, and system for reading and controlling a communication interface. Background Art

[0002] In chip design, communication interfaces are essential. Commonly used communication interfaces include Serial Peripheral Interface (SPI for short, a synchronous peripheral interface), Inter-Integrated Circuit (IIC for short) bus interface, etc., which are often used for communication between a single host and multiple slaves.

[0003] In traditional technologies, the host and multiple slaves are respectively connected to a communication interface (such as SPI or IIC, etc.) bus, and the host accesses the slave registers through single read and write operations. During the communication process between the host and each slave, the host needs to initiate bus control rights to the corresponding slave through the bus every time it reads and writes.

[0004] However, for scenarios that require continuous parameter reading, the host needs to frequently send instructions through the bus, thus occupying a large amount of main control resources and having low reading efficiency. Summary of the Invention

[0005] Based on this, it is necessary to provide a method, apparatus, chip, and system for reading and controlling a communication interface that can improve reading efficiency for the above technical problems.

[0006] In a first aspect, this application provides a method for reading and controlling a communication interface, the method including:

[0007] Obtain channel configuration parameters sent by a host computer, and perform initialization according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cyclic read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger mode has a corresponding read trigger condition;

[0008] When it is determined that the read trigger condition of the target channel is reached, communicate with the target channel based on the read trigger mode, cyclically read the data returned by the target channel based on the communication and the cyclic read count threshold, and record the read count;

[0009] When it is determined that the read count reaches the cyclic read count threshold, return a first response message to the host computer.

[0010] In one embodiment, after cyclically reading the data returned by the target channel based on the communication and the cyclic read count threshold, the method further includes: storing the data read each time in a cache space corresponding to the target channel, where the cache space is a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other.

[0011] In one embodiment, the channel configuration parameters further include the data transfer conditions for each target channel; after storing the data read each time in the cache space corresponding to the target channel, the method further includes: when it is determined that the data transfer condition of the target channel is met, transferring the data in the cache space of the target channel to an external memory.

[0012] In one embodiment, when the read trigger mode is a timing trigger mode, the read trigger condition includes a corresponding trigger interval duration; the method further includes: when it is determined that the read count does not reach the cyclic read count threshold, starting to time; when the timing reaches the trigger interval duration, returning to execute the step of communicating with the target channel.

[0013] In one embodiment, when the read trigger mode is an interrupt trigger mode, the read trigger condition includes the condition of an external trigger interrupt signal; the method further includes: when it is determined that the read count does not reach the cyclic read count threshold, detecting whether an external interrupt signal is received; when it is determined that the external interrupt signal is received, returning to execute the step of communicating with the target channel.

[0014] In one embodiment, the read trigger condition further includes a first waiting duration, and the method further includes: when it is determined that the external interrupt signal is not received, detecting whether an external interrupt signal is received based on the first waiting duration; if the external interrupt signal is received within the first waiting duration, returning to execute the step of communicating with the target channel; if the external interrupt signal is not received within the first waiting duration, returning a second response message to the host computer.

[0015] In one embodiment, when the read trigger mode is a status polling trigger mode, the read trigger condition includes the condition of an externally triggered readable status; the method further includes: when it is determined that the read count does not reach the cyclic read count threshold, obtaining the status of the external register corresponding to the target channel; when it is determined that the status is a readable status, returning to execute the step of communicating with the target channel.

[0016] In one embodiment, the read trigger condition further includes a second waiting duration and a retry count threshold, and the method further includes: when determining that the state is an unreadable state, retrying to obtain the state of the external register corresponding to the target channel based on the second waiting duration, and recording the retry count; if the state obtained by the retry is a readable state, returning to execute the step of communicating with the target channel, and clearing the retry count; if the retry count reaches the retry count threshold and the state obtained by each retry is an unreadable state, returning a third response message to the host computer.

[0017] In a second aspect, the present application provides a read control device for a communication interface, and the device includes:

[0018] A configuration parameter acquisition module, configured to acquire channel configuration parameters sent by a host computer, and perform initialization according to the channel configuration parameters; the channel configuration parameters include read trigger modes and loop read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger mode has a corresponding read trigger condition;

[0019] A communication control module, configured to communicate with the target channel based on the read trigger mode when determining that the read trigger condition of the target channel is met, cyclically read the data returned by the target channel based on the communication and the loop read count threshold, and record the read count;

[0020] A response module, configured to return a first response message to the host computer when determining that the read count reaches the loop read count threshold.

[0021] In a third aspect, the present application provides a read control chip for a communication interface, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the above method are implemented.

[0022] In a fourth aspect, the present application provides a read control chip for a communication interface, including a register control module, a trigger mode module, and a main control module;

[0023] The register control module is configured to acquire channel configuration parameters sent by a host computer, and send the channel configuration parameters to the main control module and the trigger mode module; the channel configuration parameters include read trigger modes and loop read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger mode has a corresponding read trigger condition;

[0024] The trigger mode module is configured to perform parameter configuration according to the read trigger modes of at least two target channels in the channel configuration parameters, and feedback mode configuration information to the main control module;

[0025] The master control module is used to initialize according to the channel configuration parameters and the mode configuration information; and when it is determined that the read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read the data returned by the target channel based on the communication and the cyclic read count threshold, and record the read count; when it is determined that the read count reaches the cyclic read count threshold, return a first response message to the host computer.

[0026] In one embodiment, it further includes a storage management module, which is used to allocate storage space for each channel, and the cache spaces of different channels are independent of each other; the master control module is further used to send the data read each time to the storage management module; the storage management module is further used to store the data in the cache space corresponding to the target channel.

[0027] In one embodiment, the channel configuration parameters further include the data transfer conditions of each target channel; the register control module is further used to send the data transfer conditions of each target channel to the storage management module; the storage management module is further used to transfer the data in the cache space of the target channel to an external memory when it is determined that the data transfer condition of the target channel is met.

[0028] In a fifth aspect, the present application provides a read control system for a communication interface, including: the read control chip for the communication interface as described in the third aspect, a host computer, and at least two slave devices, where the host computer and the at least two slave devices are respectively connected to the read control chip for the communication interface.

[0029] In a sixth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0030] In a seventh aspect, the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0031] The above-mentioned read control method, device, chip, readable storage medium, and program product for a communication interface obtain channel configuration parameters sent by a host computer, perform initialization based on the channel configuration parameters, communicate with a target channel based on a read trigger mode when it is determined that the read trigger condition for the target channel is met, read the data returned by the target channel, and record the number of reads of the target channel. Then, when it is determined that the number of reads reaches the loop read count threshold, a first response message is returned to the host computer. By configuring the loop read count threshold for each channel, continuous data reading from the channel can be achieved based on this loop read count threshold, so as to avoid frequent instruction sending, save master control resources, and reduce the number of master control interrupts. Description of the Drawings

[0032] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0033] Figure 1 It is an application environment diagram of the read control method for a communication interface in an embodiment;

[0034] Figure 2 It is a flowchart of the read control method for a communication interface in an embodiment;

[0035] Figure 3 It is a control flowchart in the timing trigger mode in an embodiment;

[0036] Figure 4 It is a control flowchart in the interrupt trigger mode in another embodiment;

[0037] Figure 5 It is a control flowchart in the status polling trigger mode in an embodiment;

[0038] Figure 6 It is a structural block diagram of the read control device for a communication interface in an embodiment;

[0039] Figure 7 It is an internal structure diagram of the read control chip for a communication interface in an embodiment;

[0040] Figure 8 It is a structural schematic diagram of the read control system for a communication interface in an embodiment;

[0041] Figure 9 It is a schematic diagram of the DDR multi-channel storage structure in an embodiment;

[0042] Figure 10 Schematic diagram of a BRAM multi-channel storage structure in an embodiment;

[0043] Figure 11 Schematic diagram of a chip test scenario in an embodiment. Detailed implementation manners

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] In the traditional technology, during the communication process between the host and each slave, the host needs to initiate bus control rights to the corresponding slave through the bus every time it reads and writes. For scenarios that require continuous parameter reading, it is necessary to frequently send instructions through the bus, thereby occupying a large amount of main control resources and resulting in low reading efficiency. Moreover, for the data read each time, it needs to be processed immediately, which is likely to increase the CPU load and is difficult to apply to scenarios that require continuous observation of data changes.

[0046] In addition, the traditional solution is difficult to support parallel operations of a large number of channels (such as 64 slave devices). When multiple channels compete for the bus, frequent switching is required, resulting in bandwidth waste (such as the switching delay can reach dozens of microseconds). Moreover, each channel shares the storage space, and the mixed storage of data makes the parsing complexity high.

[0047] Based on this, the embodiment of the present application provides a reading control method for a communication interface. By obtaining the channel configuration parameters sent by the upper computer, initializing according to the channel configuration parameters, when it is determined that the read trigger condition of the target channel is reached, communicating with the target channel based on the read trigger mode, continuously reading the data returned by the target channel based on the loop read count threshold, and recording the read count. Then, when it is determined that the read count reaches the loop read count threshold, a first response message is returned to the upper computer. By configuring the loop read count threshold for each channel, continuous data reading from the channel can be achieved based on this loop read count threshold, which is particularly suitable for scenarios that require continuous parameter reading, so as to avoid frequent instruction sending, save main control resources, and reduce the number of main control interrupts.

[0048] The reading control method for the communication interface provided by the embodiment of the present application can be applied to, for example Figure 1In the application environment shown. Among them, the host computer 100 and multiple slave computers 200 are respectively connected to an FPGA (Field Programmable Gate Array) chip 300. Among them, the host computer 100 is responsible for data parsing and human-computer interaction, obtains the processed data by connecting to an external memory, analyzes and presents the results using software algorithms, and at the same time receives user instructions to realize the allocation of system operation parameters and working modes. The FPGA chip 300 is responsible for data processing (such as reading the data of the slave computer 200 and transferring the data to the external memory) and operation process scheduling, and can effectively handle complex computing and control tasks. The slave computer 200 returns data to it based on the instructions of the FPGA chip 300, and can achieve real-time return, periodic return, and polling return, etc. Specifically, the external memory can be integrated on the host computer 100, or placed on the cloud or other network servers. Among them, the host computer 100 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. The slave computer 200 can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Exemplarily, the slave computer 200 can be connected to the FPGA chip 300 based on the SPI interface, or based on the IIC interface, or based on other communication interfaces. This embodiment does not limit this.

[0049] In one embodiment, a method for reading and controlling a communication interface is provided. In this embodiment, this method is applied to an FPGA chip, and the slave computer is connected to the FPGA chip based on the IIC interface as an example (then the slave computer is referred to as an IIC slave computer). In this embodiment, as Figure 2 shown, the method may include the following steps:

[0050] Step 202, obtain the channel configuration parameters sent by the host computer, and perform initialization according to the channel configuration parameters.

[0051] Among them, the channel configuration parameters are used to determine the operating mechanism of the FPGA chip and the interaction logic with the IIC slave. The channel configuration parameters may include the read trigger mode and the cyclic read count threshold of at least two target channels, where the target channel refers to the communication channel between the FPGA chip and the target IIC slave. The read trigger mode has a corresponding read trigger condition, that is, the condition for triggering the reading of the data of the corresponding target channel. The cyclic read count threshold is the number of times of reading for triggering the reading of the data of the corresponding target channel. The cyclic read count threshold can be an integer greater than or equal to 2. Based on this cyclic read count threshold, continuous cyclic data reading can be achieved, thereby avoiding frequent instruction sending to save the master control resources.

[0052] Exemplarily, the read trigger modes of different target channels can be the same or different, and can be specifically determined based on the mode of the IIC slave corresponding to the channel. For each target channel, its corresponding read trigger mode may include any one of the timed trigger mode, the interrupt trigger mode, and the status polling trigger mode.

[0053] Exemplarily, the cyclic read count thresholds of different target channels can be the same or different, and can be specifically configured according to actual requirements, and this embodiment does not limit this.

[0054] In this embodiment, the FPGA chip initializes by obtaining the channel configuration parameters sent by the host computer and according to the channel configuration parameters. For example, the host computer can, based on the user instruction, write the channel configuration parameters of each IIC slave channel to the register control module of the FPGA chip through the master control interface (such as the AXI (Advanced eXtensible Interface, a bus protocol) bus). After the FPGA chip obtains the channel configuration parameters, it can enable the corresponding target channel to achieve initialization. The FPGA chip can also feedback a response message to the host computer through the Respond bus.

[0055] Step 204, in the case of determining that the read trigger condition of the target channel is reached, communicate with the target channel based on the read trigger mode, read the data returned by the target channel, and record the number of readings.

[0056] Among them, the communication is a communication protocol for interaction between devices. Taking the slave as the IIC slave as an example, the communication is IIC communication, that is, a serial synchronous half-duplex bus protocol for short-distance communication, which realizes data transmission between the master and slave devices through two signal lines (including SCL, that is, Serial Clock, the serial clock line, and SDA, that is, Serial Data Line, the serial data line). In this embodiment, the FPGA chip can trigger IIC communication with each target channel based on the above-obtained channel configuration parameters to read the data returned by each target channel.

[0057] Exemplarily, the FPGA chip can monitor whether each target channel reaches the corresponding read trigger condition based on the channel configuration parameters. When it is determined that there is a target channel reaching the corresponding read trigger condition, perform IIC communication with the corresponding target channel based on the read trigger mode, and cyclically read the data returned by the target channel based on the cyclic read count threshold, while recording the read count. It can be understood that this read count is used to represent the number of times of reading data from the corresponding target channel.

[0058] Step 206, when it is determined that the read count reaches the cyclic read count threshold, return a first response message to the host computer.

[0059] Among them, the first response message is used to represent that the data reading task of the corresponding target channel is completed. In this embodiment, when the FPGA chip determines that the read count of a certain target channel reaches the corresponding cyclic read count threshold, it means that the data reading task of the target channel is completed, and thus a first response message can be returned to the host computer to indicate that the host computer has completed the data reading task of the corresponding target channel.

[0060] In the above read control method of the communication interface, by obtaining the channel configuration parameters sent by the host computer, initializing according to the channel configuration parameters, when it is determined that the read trigger condition of the target channel is reached, communicate with the target channel based on the read trigger mode, read the data returned by the target channel, and record the read count of the target channel. Then, when it is determined that the read count reaches the cyclic read count threshold, return a first response message to the host computer. By configuring the cyclic read count threshold for each channel, continuous cyclic data reading from the channel can be achieved based on this cyclic read count threshold, so as to avoid frequent instruction sending, save the main control resources, and reduce the number of main control interrupts.

[0061] In an exemplary embodiment, in step 204, after reading the data returned by the target channel, the above method may further include: storing the data read each time in the cache space corresponding to the target channel. Among them, the cache space is the storage space pre-allocated by the FPGA chip for each channel, and the cache spaces of different channels are independent of each other. Each cache space also has a corresponding capacity size, such as 2MB DDR (Double Data Rate, double-speed synchronous dynamic random access memory) or 2KB BRAM (Block Random Access Memory, block random access memory) buffer, etc. Among them, both DDR and BRAM are random access memory resources in the FPGA chip.

[0062] In this embodiment, by allocating independent buffer spaces for each channel, the independence of data storage can be achieved. This not only avoids the problem of high parsing complexity caused by the mixed storage of data from each channel, but also enables parallel reading and writing of each channel to improve the reading and writing efficiency, and no multi-channel conflict will occur.

[0063] In an exemplary embodiment, the channel configuration parameters may further include the data transfer conditions of each target channel. After storing the data read each time in the buffer space corresponding to the target channel, the above method may further include: when it is determined that the data transfer conditions of the target channel are met, transferring the data in the buffer space of the target channel to an external memory.

[0064] Among them, the data transfer condition may be a condition for clearing the data stored in the buffer space of each channel. Exemplarily, the data transfer condition may be a condition for the capacity of the data stored in the buffer space. For example, it may be a capacity threshold of the buffer space (such as 80%). The data transfer condition may also be a condition for the number of times of storing data in the buffer space, such as 10 times. The data transfer condition may also be a time interval for clearing the data stored in the buffer space, such as 240 us (microseconds). It can be understood that the data transfer conditions of different target channels may be the same or different, and this embodiment does not limit this.

[0065] In this embodiment, by pre-configuring the data transfer conditions of each channel, when it is determined that the data transfer conditions of the target channel are met, the data in the buffer space of the target channel is automatically transferred to an external memory, thereby avoiding the risk of data overflow. Compared with the method of real-time processing of each read data, it can also reduce the number of interrupts, reduce the resource consumption of the FPGA chip, and is applicable to scenarios that require continuous observation of data changes.

[0066] In an exemplary embodiment, the channel configuration parameters may further include the data reading range of the corresponding channel. Then, in step 204, reading the data returned by the target channel may specifically include: reading the data returned by the target channel based on the data reading range.

[0067] Among them, the data reading range may include the start address and the reading length of the data read configured for each channel. For example, if the start address of the data read configured for a certain channel is 0x00 and the reading length is 8 bytes, when the FPGA chip reads the data of the target channel, it can read the data returned by the target channel based on the corresponding start address and reading length. This can not only improve the throughput, but also ensure the accuracy of continuously reading data subsequently.

[0068] In an exemplary embodiment, taking the read trigger mode as the timing trigger mode as an example, the above reading control method of the communication interface is further described. AsFigure 3 As shown in the figure, it may specifically include the following steps:

[0069] Step 302: Obtain the channel configuration parameters sent by the host computer.

[0070] Among them, the channel configuration parameters may include the read trigger mode, the threshold of the cyclic read times, and the data transfer conditions, etc. for the target channel, and the read trigger mode has corresponding read trigger conditions. When the read trigger mode is the timed trigger mode, the read trigger conditions include the trigger interval duration corresponding to each channel, that is, the interval duration of the timed trigger, such as 30 us. Specifically, it can be realized by timer timing.

[0071] Specifically, the host computer is responsible for configuring the parameters related to the timed trigger mode and transmitting them to the corresponding registers of the FPGA chip.

[0072] Step 304: Initialize according to the channel configuration parameters.

[0073] Initialization refers to the process of setting and configuring the various parameters of the FPGA chip based on the channel configuration parameters to ensure the normal operation of the FPGA chip. Specifically, the FPGA chip can select channels according to the obtained channel configuration parameters, that is, determine which channels to start, and start counters based on the trigger interval duration of each channel, and perform parallel processing after enabling the corresponding channels, thereby completing the initialization process.

[0074] Step 306: Monitor whether each target channel reaches the corresponding read trigger condition.

[0075] If it is monitored that a target channel reaches the corresponding read trigger condition, for example, when the timer of the target channel reaches the set time, then execute step 308, otherwise execute step 306 to continue monitoring.

[0076] Step 308: Perform IIC communication to read data and record the read times.

[0077] If it is monitored that a certain target channel reaches the corresponding read trigger condition, perform IIC communication with the target channel to read data and record the read times.

[0078] Step 310: Store the data read based on IIC communication in the corresponding cache space.

[0079] Read the data returned by the target channel based on IIC communication and store it in the cache space corresponding to the target channel.

[0080] Step 312: Perform data transfer when the data transfer condition is met.

[0081] When it is detected that the buffer space corresponding to a certain target channel reaches the data transfer condition, transfer the data in the buffer space to the external memory.

[0082] Step 314, determine whether the number of reads reaches the cyclic read count threshold.

[0083] After recording the number of reads in step 308, further determine whether the number of reads of the target channel reaches the cyclic read count threshold. If not, execute step 316; if so, execute step 318.

[0084] Step 316, start timing and wait for the trigger interval duration.

[0085] If the number of reads of a certain target channel does not reach the cyclic read count threshold, start timing and wait for the trigger interval duration, then return to execute step 308, that is, after waiting for the trigger interval duration, perform IIC communication with the target channel again, so as to achieve cyclic data reading.

[0086] Step 318, return a first response message to the host computer.

[0087] If the number of reads of a certain target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed, and thus a first response message can be returned to the host computer to indicate that the host computer has completed the data reading task for the corresponding target channel.

[0088] Exemplarily, if the trigger interval duration for a certain channel is 30 us, the cyclic read count threshold is 20 times, the length of each read is 8 bytes, and the data transfer condition is to perform data transfer after every 10 reads. It means that a read operation is triggered every 30 us for this channel, 8 bytes of data are continuously read each time and stored in the buffer space of the corresponding channel, the data in the buffer space is transferred to the external memory after every 10 reads, and the cyclic reading stops after 20 times. Thus, cyclic continuous data reading from the channel is achieved to avoid frequent sending of instructions and save the master control resources; and based on the independence of data storage for each channel, multi-channel conflicts can be avoided and the parallel read / write efficiency can be improved; through trigger automatic transfer, the risk of data overflow can also be avoided, the number of master control interrupts can be reduced, the resource consumption of the FPGA chip can be lowered, and the overall performance can be improved.

[0089] In an exemplary embodiment, taking the read trigger mode as the interrupt trigger mode as an example, the above-mentioned read control method of the communication interface is further described. As Figure 4 shown, it may specifically include the following steps:

[0090] Step 402, obtain the channel configuration parameters sent by the host computer.

[0091] Among them, the channel configuration parameters may include the read trigger mode of the target channel, the loop read count threshold, the data transfer condition, etc., and the read trigger mode has a corresponding read trigger condition. When the read trigger mode is the interrupt trigger mode, the read trigger condition includes the conditions of the external trigger interrupt signals corresponding to each channel, that is, the start condition of the interrupt mode, such as the low level of the INT pin.

[0092] Specifically, the host computer is responsible for configuring the parameters related to the interrupt trigger mode and transmitting them to the corresponding registers of the FPGA chip.

[0093] Step 404, perform initialization according to the channel configuration parameters.

[0094] Initialization refers to the process of setting and configuring the various parameters of the FPGA chip based on the channel configuration parameters to ensure the normal operation of the FPGA chip. Specifically, the FPGA chip can perform channel selection according to the obtained channel configuration parameters, such as the start conditions of the interrupt modes of each channel, and perform parallel processing after enabling the corresponding channels, thereby completing the initialization process.

[0095] Step 406, monitor whether each target channel triggers an interrupt signal.

[0096] If it is monitored that a target channel triggers an interrupt signal, it means that the corresponding target channel reaches the corresponding read trigger condition, and step 408 is executed; otherwise, step 414 is executed.

[0097] Step 408, perform IIC communication to read data and record the read count.

[0098] When it is monitored that a certain target channel reaches the corresponding read trigger condition, perform IIC communication with the target channel to read data and record the read count.

[0099] Step 410, store the read data in the corresponding buffer space.

[0100] Store the data returned by the target channel in the buffer space corresponding to the target channel.

[0101] Step 412, perform data transfer when the data transfer condition is reached.

[0102] When it is monitored that the buffer space corresponding to a certain target channel reaches the data transfer condition, transfer the data in the buffer space to the external memory.

[0103] Step 414, detect whether an external interrupt signal is received based on the first waiting duration.

[0104] Among them, the first waiting duration can be a relevant parameter configured in the read trigger condition, which is used to represent the maximum waiting duration of the corresponding channel in the interrupt trigger mode. If an external interrupt signal of the target channel is received within the first waiting duration, return to execute step 408 to perform IIC communication with the target channel. If the external interrupt signal of the target channel is not received within the first waiting duration, execute step 418 to return a response message to the host computer. It can be understood that in order to distinguish the response messages returned in different scenarios, the response message returned in this scenario can be called the second response message, and this second response message is used to represent that the corresponding target channel waits for an interrupt timeout.

[0105] Step 416, determine whether the number of reads has reached the cyclic read count threshold.

[0106] After recording the number of reads in step 408, further determine whether the number of reads has reached the cyclic read count threshold. If not, return to execute step 406 to continue monitoring whether each target channel triggers an interrupt signal. If so, execute step 418.

[0107] Step 418, return a response message to the host computer.

[0108] In one scenario, if the number of reads of a certain target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed, and thus a first response message can be returned to the host computer to indicate to the host computer that the data reading task for the corresponding target channel is completed.

[0109] In one scenario, if no external interrupt signal of a certain target channel is received within the first waiting duration, it means that the corresponding target channel waits for an interrupt timeout, and thus a second response message can be returned to the host computer to indicate to the host computer that the corresponding target channel waits for an interrupt timeout.

[0110] Exemplarily, if the condition for the external trigger interrupt signal of a certain channel is that the INT pin is at a low level, the first waiting duration is 100 us, the threshold of the cyclic read count is 20 times, the length of each read is 8 bytes, and the data transfer condition is to perform data transfer at intervals of 240 us. If it is detected that the INT pin of the IIC slave corresponding to a certain target channel is at a low level, it means that the read trigger condition for the corresponding target channel is reached, that is, the interrupt mode of the corresponding target channel can be started, triggering IIC communication to read data. Each time 8 bytes of data are continuously read and stored in the buffer space of the corresponding channel. After completion, wait for the next interruption (the maximum waiting duration is 100 us, that is, if no interruption is detected within 100 us, it ends). Data transfer is performed every 240 us, that is, data transfer is performed once every 240 us, and it stops after 20 cyclic reads. Thus, continuous data reading from the channel is achieved to avoid frequent instruction sending, saving the master control resources; and based on the independence of data storage for each channel, multi-channel conflicts can be avoided, improving the parallel read / write efficiency; through triggering automatic transfer, the risk of data overflow can also be avoided, and the number of master control interruptions is reduced, reducing the resource consumption of the FPGA chip and improving the overall performance.

[0111] In an exemplary embodiment, taking the read trigger mode as the status polling trigger mode as an example, the read control method of the above communication interface is further described. As Figure 5 shown, it may specifically include the following steps:

[0112] Step 502, obtain the channel configuration parameters sent by the host computer.

[0113] Among them, the channel configuration parameters may include the read trigger mode for the target channel, the threshold of the cyclic read count, the data transfer condition, etc., and the read trigger mode has corresponding read trigger conditions. In the case where the read trigger mode is the status polling trigger mode, the read trigger condition includes the conditions for the externally triggerable readable status corresponding to each channel, that is, the start condition of the status polling mode, such as the status register address and the determination condition.

[0114] Specifically, the host computer is responsible for configuring the parameters related to the status polling trigger mode and transmitting them to the corresponding registers of the FPGA chip.

[0115] Step 504, perform initialization according to the channel configuration parameters.

[0116] Initialization refers to the process of setting and configuring the various parameters of the FPGA chip based on the channel configuration parameters to ensure the normal operation of the FPGA chip. Specifically, the FPGA chip can perform channel selection, the start conditions of the status polling mode for each channel, etc. according to the obtained channel configuration parameters, and perform parallel processing after enabling the corresponding channels, thereby completing the initialization process.

[0117] Step 506: Obtain the status of the external register corresponding to the target channel.

[0118] Among them, the status is used to represent whether there is readable data in the IIC slave corresponding to the target channel. In this embodiment, the status of having readable data is defined as the readable state, and the status of not having readable data is defined as the unreadable state. Specifically, it can be determined based on the status bit flag of the external register. For example, if the status bit flag of the external register is 1, it indicates the readable state, and if it is 0, it indicates the unreadable state.

[0119] Step 508: Determine whether the status is the readable state.

[0120] In the case where it is determined that the status of the external register corresponding to the target channel is the readable state, execute Step 510. In the case where it is determined that the status of the external register corresponding to the target channel is the unreadable state, execute Step 516.

[0121] Step 510: Perform IIC communication to read data and record the number of reads.

[0122] If it is monitored that the status of the external register corresponding to a certain target channel is the readable state, it means that when the corresponding read trigger condition is reached. Therefore, perform IIC communication with the target channel to read data and record the number of reads.

[0123] Step 512: Store the read data in the corresponding cache space.

[0124] Store the data returned by the target channel read by IIC communication in the cache space corresponding to the target channel.

[0125] Step 514: When the data transfer condition is reached, perform data transfer.

[0126] When it is monitored that the cache space corresponding to a certain target channel reaches the data transfer condition, transfer the data in the cache space to the external memory.

[0127] Step 516: Start timing and wait for the second waiting duration.

[0128] Among them, the second waiting duration can be the pre-configured interval duration for reading the status of the external register corresponding to the target channel. For example, 10 us, which means reading the status of the external register corresponding to the target channel every 10 us.

[0129] If in Step 508, it is monitored that the status of the external register corresponding to a certain target channel is the unreadable state, it means that the corresponding read trigger condition is not reached. Therefore, start timing and after waiting for the second waiting duration, return to execute Step 506 to retry reading the status of the external register corresponding to the target channel.

[0130] Step 518, determine whether the number of reads has reached the cyclic read count threshold.

[0131] After recording the number of reads in step 510, further determine whether the number of reads of the target channel has reached the cyclic read count threshold. If not, return to step 506 to continue reading the status of the external register corresponding to the target channel. If so, execute step 520.

[0132] Step 520, return a response message to the host computer.

[0133] In one scenario, if the number of reads of a certain target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed. Thus, a first response message can be returned to the host computer to indicate that the host computer has completed the data reading task for the corresponding target channel.

[0134] In one scenario, to avoid deadlock caused by the status of the external register corresponding to the target channel always being unreadable, the maximum number of retries (i.e., the retry count threshold) for each channel can also be set. That is, when it is determined that the status of the external register corresponding to the target channel is unreadable, the status of the external register corresponding to the target channel can be retried based on the second waiting duration, and the number of retries is recorded. If the status obtained after the retry is readable, return to execute the step of communicating with the target channel and clear the number of retries; if the number of retries reaches the retry count threshold and the status obtained each time after the retry is unreadable, return a third response message to the host computer. This third response message is used to indicate that the retry for the corresponding target channel has timed out. Thus, the occurrence of deadlock can be avoided.

[0135] Exemplarily, if the status register address in the conditions for the externally triggerable readable state of a certain channel is 0x10, the second waiting duration is 10 us, the maximum number of retries is 10 times, the threshold of the cyclic read count is 20 times, the length of each read is 8 bytes, and the data transfer condition is to perform data transfer at intervals of 240 us. If it is detected that the status bit of the external status register (the register with the address of 0x10) corresponding to a certain target channel is in the readable state, it means that the read trigger condition for the corresponding target channel is met, that is, the polling mode of the corresponding target channel can be started, triggering communication to read data. Each time, 8 bytes of data are continuously read and stored in the buffer space of the corresponding channel. After completion, the next status read is performed (that is, after a 10 us interval, continue to read the status bit of the external register of the corresponding channel). Data transfer is performed every 240 us, that is, data transfer is performed once every 240 us. After 20 cyclic reads, it stops. If the status bits of the external status register corresponding to a certain target channel are all in the unreadable state for 10 consecutive reads, the loop is exited to avoid deadlock. Thus, continuous data reading from the channel is achieved to avoid frequent instruction sending and save the master control resources; and based on the independence of data storage for each channel, multi-channel conflicts can be avoided and the parallel read / write efficiency can be improved; by triggering automatic transfer, the risk of data overflow can also be avoided, and the number of master control interrupts can be reduced, the resource consumption of the FPGA chip can be reduced, and the overall performance can be improved.

[0136] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the indication of the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same moment, but can be executed at different moments. The execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0137] Based on the same inventive concept, the embodiments of the present application also provide a read control device for a communication interface for implementing the read control method of the communication interface involved above. The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the read control device for the communication interface provided below can refer to the limitations on the read control method of the communication interface in the above text, and will not be repeated here.

[0138] In an exemplary embodiment, as Figure 6As shown, a read control device for a communication interface is provided, including: a configuration parameter acquisition module 602, a communication control module 604, and a response module 606, where:

[0139] The configuration parameter acquisition module 602 is configured to acquire channel configuration parameters sent by a host computer and initialize according to the channel configuration parameters; at least two read trigger modes and a cyclic read count threshold of target channels are included in the channel configuration parameters, and the read trigger modes of different target channels are the same or different, and the read trigger mode has a corresponding read trigger condition;

[0140] The communication control module 604 is configured to communicate with the target channel based on the read trigger mode when it is determined that the read trigger condition of the target channel is met, cyclically read the data returned by the target channel based on the communication and the cyclic read count threshold, and record the read count;

[0141] The response module 606 is configured to return a first response message to the host computer when it is determined that the read count reaches the cyclic read count threshold.

[0142] In an exemplary embodiment, the device further includes a storage module configured to store the data read each time in a cache space corresponding to the target channel, and the cache space is a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other.

[0143] In an exemplary embodiment, data transfer conditions of each target channel are further included in the channel configuration parameters; the device further includes a data transfer module configured to, after storing the data read each time in the cache space corresponding to the target channel, transfer the data in the cache space of the target channel to an external memory when it is determined that the data transfer condition of the target channel is met.

[0144] In an exemplary embodiment, when the read trigger mode is a timing trigger mode, the read trigger condition includes a corresponding trigger interval duration; the communication control module is further configured to: start timing when it is determined that the read count does not reach the cyclic read count threshold; and return to execute the step of communicating with the target channel when the timing reaches the trigger interval duration.

[0145] In an exemplary embodiment, when the read trigger mode is an interrupt trigger mode, the read trigger condition includes a condition of an external trigger interrupt signal; the communication control module is further configured to: detect whether an external interrupt signal is received when it is determined that the read count does not reach the cyclic read count threshold; and return to execute the step of communicating with the target channel when it is determined that the external interrupt signal is received.

[0146] In an exemplary embodiment, the read trigger condition further includes a first waiting duration, and the communication control module is further configured to: when it is determined that the external interrupt signal has not been received, detect whether the external interrupt signal is received based on the first waiting duration; if the external interrupt signal is received within the first waiting duration, return to execute the step of communicating with the target channel; if the external interrupt signal is not received within the first waiting duration, return a second response message to the host computer.

[0147] In an exemplary embodiment, when the read trigger mode is the status polling trigger mode, the read trigger condition includes the condition for the external trigger to be in a readable state; the communication control module is further configured to: when it is determined that the number of reads has not reached the cyclic read number threshold, obtain the status of the external register corresponding to the target channel; when it is determined that the status is a readable state, return to execute the step of communicating with the target channel.

[0148] In an exemplary embodiment, the read trigger condition further includes a second waiting duration and a number threshold, and the communication control module is further configured to: when it is determined that the status is an unreadable state, retry to obtain the status of the external register corresponding to the target channel based on the second waiting duration and record the number of retries; if the status obtained by the retry is a readable state, return to execute the step of communicating with the target channel and clear the number of retries; if the number of retries reaches the retry number threshold and the status obtained by each retry is an unreadable state, return a third response message to the host computer.

[0149] Each module in the above read control device of the communication interface can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in the form of hardware or be independent of the processor, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0150] In an exemplary embodiment, a read control chip for a communication interface is provided. The read control chip for the communication interface can be an FPGA chip. Its internal structure diagram can be as Figure 7As shown in the figure. The read control chip of the communication interface includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the read control chip of the communication interface is used to provide computing and control capabilities. The memory of the read control chip of the communication interface includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the read control chip of the communication interface is used to store the configuration parameter data of each channel. The input / output interface of the read control chip of the communication interface is used to exchange information between the processor and external devices. The communication interface of the read control chip of the communication interface is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it realizes a method for reading and controlling a communication interface.

[0151] Those skilled in the art can understand that Figure 7 the structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the read control chip of the communication interface to which the solution of the present application is applied. The specific read control chip of the communication interface may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0152] In an exemplary embodiment, a communication interface read control system is further provided, and its internal structure diagram may be as Figure 8 shown in the figure. The connection relationship between the internal modules of the FPGA chip (including the main control module, register control module, trigger mode module, storage management module, parallel processing module, etc.) and external slave devices (in this embodiment, an IIC slave device is taken as an example) and the host computer is shown. It can be understood that there may be multiple IIC slave devices. Among them, 116 is the host computer, which is responsible for assigning parameter values to the register control module of the FPGA chip. The host computer 116 communicates with the register control module of the FPGA chip through the AXI bus and the Respond bus. 117 is the slave device, which may specifically be an IIC slave device, and interacts with the main control module of the FPGA chip through the SDA and SCL signal lines to implement read and write functions.

[0153] Among them, the register control module in the FPGA chip 101 is used to obtain the channel configuration parameters sent by the host computer and send the channel configuration parameters to the main control module, the trigger mode module, and the parallel processing module; the channel configuration parameters include the read trigger mode and the cyclic read count threshold of at least two target channels. The read trigger modes of different target channels may be the same or different, and the read trigger mode has a corresponding read trigger condition;

[0154] A trigger mode module, configured to perform parameter configuration according to the read trigger modes of at least two target channels in the channel configuration parameters, and feedback mode configuration information to the main control module;

[0155] A parallel processing module, configured to perform parallel configuration according to the read trigger modes of at least two target channels in the channel configuration parameters, and feedback parallel configuration information to the main control module;

[0156] A main control module, configured to perform initialization according to the channel configuration parameters, the mode configuration information, and the parallel configuration information; and when it is determined that the read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read the data returned by the target channel based on the communication and the cyclic read count threshold, and record the read count; when it is determined that the read count reaches the cyclic read count threshold, return a first response message to the host computer.

[0157] Exemplarily, a storage management module is configured to allocate storage space for each channel, and the cache spaces of different channels are independent of each other; then the main control module is further configured to send the data read each time to the storage management module; the storage management module is further configured to store the data in the cache space corresponding to the target channel.

[0158] Exemplarily, the channel configuration parameters further include the data transfer conditions of each target channel; then the register control module is further configured to send the data transfer conditions of each target channel to the storage management module; the storage management module is further configured to, when it is determined that the data transfer condition of the target channel is met, transfer the data in the cache space of the target channel to an external memory.

[0159] Specifically, 101 is the clock division unit in the main control module of the FPGA chip, providing clock frequencies of 100 kHz, 200 kHz, 400 kHz, 1 MHz, and 3.4 MHz, and outputting them to the IIC timing control module 102. 102 is the IIC timing control module in the main control module, responsible for receiving the data to be sent, performing timing processing, and sending the data to the slave device according to the IIC data structure. At the same time, it receives the data returned by the slave device, parses and frames it, and temporarily stores the parsed data into the read / write data transfer module 103. 103 is the read / write data transfer module in the main control module, responsible for interacting with the IIC timing control module 102 and forwarding the data to be stored to the storage management module. 104 is the channel mode parameter register group in the register control module, responsible for receiving the channel-related parameters configured by the host computer and forwarding them to the main control module, the trigger mode module, and the parallel processing module. 105 is the transfer control parameter register group in the register control module, responsible for receiving the parameters of the trigger transfer control configured by the host computer and forwarding them to the storage management module. 106 is the read operation parameter register group in the register control module, responsible for receiving the read operation parameters configured by the host computer and forwarding them to the main control module. 107, 108, and 109 are the timing trigger unit, the interrupt trigger unit, and the status polling trigger unit in the trigger mode module respectively, responsible for receiving the mode selection parameters of the register control module and forwarding the processed relevant parameters to the main control module. 110 and 111 are the BRAM storage unit and the DDR storage unit in the storage management module, responsible for receiving the data transmitted by the main control module for storage. 112 is the transfer controller in the storage management module, responsible for receiving the transfer control parameters of the register control module and generating a transfer signal when the specified parameters are met. 113 is the DMA (Direct Memory Access, also known as the block data transfer method, sometimes also known as direct memory operation) transfer module, which transfers the data in the BRAM or DDR to the external memory 114 after receiving the transfer signal generated by the transfer controller. 114 is the external memory module connected to the FPGA, responsible for receiving the data transferred by the DMA. 115 is the parallel processing module, responsible for multi-channel parallel communication.

[0160] In an exemplary embodiment, the DDR multi-channel storage structure is as Figure 9 shown. Among them, 901 shows the storage space allocated for each channel in the DDR. For example, each channel is allocated 2 MB of storage space, with a total of 64 channels (such as CH0, CH1,..., CH63). 902 shows the specific space allocation for continuously reading back data in the timing trigger mode. After storing to the specified address, the address will be automatically cleared and start storing from address 0 again. At the same time, a certain amount of storage space will be reserved for other functions, and the reserved storage space can be adjusted in real time according to the usage situation.

[0161] In an exemplary embodiment, the BRAM multi-channel storage structure is as Figure 10 shown. Among them, 1001 shows the storage space allocated for each channel in the BRAM. For example, 2KB of storage space is allocated for each channel, with a total of 64 channels (such as CH0, CH1, ……, CH63). 1002 shows the specific space allocation for continuous read operations to read back data in the timing trigger mode. After storing to the specified address, the address will be automatically cleared and start storing from address 0 again. At the same time, a certain amount of storage space will be reserved for other functions, and the reserved storage space can be adjusted in real time according to the usage situation.

[0162] Based on the above multi-channel storage structure, each channel can operate independently, without interference between channels, and each channel can execute simultaneously in different read modes (such as channels 1 - 32 in the timing trigger mode, and channels 33 - 64 in the interrupt trigger mode), thereby maximizing the throughput, reducing the risk of master control interruption, and avoiding data overflow.

[0163] In an exemplary embodiment, taking the above-mentioned read control system of the communication interface applied to the chip test scenario as an example, its corresponding system architecture can be in the form as Figure 11 shown, including an FPGA communication board (i.e., the above-mentioned FPGA chip), a Cable connection line, a circuit board of the chip under test (where the chip under test is equivalent to an IIC slave), and a host computer.

[0164] Specifically, the FPGA communication board, as the core of the system, is responsible for a large amount of data processing and operation process scheduling. Different models can be selected according to different application scenarios. Its parallel processing ability and logical configuration flexibility can effectively handle complex arithmetic and control tasks.

[0165] The Cable connection line undertakes the data transmission and communication connection work between hardware devices, ensuring smooth information interaction between components, and has a significant impact on the stability and speed of data transmission.

[0166] The circuit board of the chip under test, one of the data sources, bears the chip to be detected and analyzed. Its data characteristics and interface specifications determine the data acquisition method and scope of the system.

[0167] The host computer is responsible for data parsing and human-computer interaction. It obtains the processed data by connecting to an external memory, analyzes and presents the results using software algorithms, and at the same time receives user instructions to adjust the system operation parameters and working modes. Its parameterized configuration supports dynamic adjustment of the number of channels and modes.

[0168] Its working processes in different modes can refer to the above Figure 3 、 Figure 4 andFigure 5 For the embodiments shown, this embodiment will not be elaborated herein.

[0169] In an exemplary embodiment, a read control chip for a communication interface is provided, which includes a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0170] In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0171] In an embodiment, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0172] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0173] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0174] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0175] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A communication interface reading control method, characterized in that: The method comprises: Acquire channel configuration parameters sent by the host computer, and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger modes have corresponding read trigger conditions; In the case of determining that the read trigger condition of the target channel is met, communicating with the target channel based on the read trigger mode, cyclically reading the data returned by the target channel based on the communication and the cyclic read number threshold, and recording the number of reads; When it is determined that the number of reads reaches the cyclic read number threshold, a first response message is returned to the host computer.

2. The method according to claim 1, characterized in that: After cyclically reading the data returned by the target channel based on the communication and the cyclic read number threshold, the method further includes: The data read each time is stored in a cache space corresponding to the target channel, wherein the cache space is a storage space allocated in advance for each channel, and the cache spaces of different channels are independent of each other.

3. The method according to claim 2, characterized in that The channel configuration parameters also include data handling conditions for each target channel; After storing the data read each time in the cache space corresponding to the target channel, the method further includes: When it is determined that the data transfer condition of the target channel is met, the data in the cache space of the target channel is transferred to an external memory.

4. The method according to any one of claims 1 to 3, characterized in that: In the case where the read trigger mode is a timing trigger mode, the read trigger condition includes a corresponding trigger interval duration; The method further comprises: When it is determined that the number of reads does not reach the cyclic read number threshold, starting timing; When the timing reaches the trigger interval, the step of communicating with the target channel is returned to be executed.

5. The method according to any one of claims 1 to 3, characterized in that: In the case where the read trigger mode is an interrupt trigger mode, the read trigger condition includes a condition of an external trigger interrupt signal; the method further includes: In the case where it is determined that the number of reads does not reach the cyclic read number threshold, detecting whether an external interrupt signal is received; In the case where it is determined that the external interrupt signal is received, the process returns to executing the step of communicating with the target channel.

6. The method according to claim 5, characterized in that The read trigger condition further includes a first waiting time, and the method further includes: In a case where it is determined that the external interrupt signal is not received, detecting whether the external interrupt signal is received based on the first waiting time; If the external interrupt signal is received within the first waiting time, returning to execute the step of communicating with the target channel; If the external interrupt signal is not received within the first waiting period, a second response message is returned to the host computer.

7. The method according to any one of claims 1 to 3, characterized in that: In the case where the read trigger mode is a state polling trigger mode, the read trigger condition includes a condition of an externally triggered readable state; the method further includes: When it is determined that the number of reads does not reach the cyclic read number threshold, obtaining a state of an external register corresponding to the target channel; If it is determined that the state is a readable state, returning to execute the step of communicating with the target channel.

8. The method according to claim 7, characterized in that The read trigger condition also includes a second waiting time and a retry number threshold, and the method also includes: In the case where it is determined that the state is an unreadable state, retrying to obtain the state of the external register corresponding to the target channel based on the second waiting time, and recording the number of retries; If the state obtained by retrying is a readable state, returning to the step of communicating with the target channel and clearing the number of retries; If the number of retries reaches the retry number threshold, and the status obtained in each retry is an unreadable status, a third response message is returned to the host computer.

9. A reading control device for a communication interface, characterized in that: The device comprises: A configuration parameter acquisition module is used to acquire channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger modes have corresponding read trigger conditions; A communication control module, configured to communicate with the target channel based on the read trigger mode when it is determined that the read trigger condition of the target channel is met, cyclically read the data returned by the target channel based on the communication and the cyclic read number threshold, and record the number of reads; The response module is used to return a first response message to the host computer when it is determined that the number of reads reaches the cyclic read number threshold.

10. A read control chip for a communication interface, characterized in that: The chip includes a register control module, a trigger mode module and a main control module; The register control module is used to obtain the channel configuration parameters sent by the host computer, and send the channel configuration parameters to the main control module and the trigger mode module; the channel configuration parameters include the read trigger mode and the cycle read number threshold of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger mode has a corresponding read trigger condition; A trigger mode module, used to perform parameter configuration according to the read trigger modes of at least two target channels in the channel configuration parameters, and to feed back mode configuration information to the main control module; The main control module is used to initialize according to the channel configuration parameters and the mode configuration information; and, when it is determined that the read trigger condition of the target channel is met, communicating with the target channel based on the read trigger mode, cyclically reading the data returned by the target channel based on the communication and the cyclic read number threshold, and recording the number of reads; When it is determined that the number of reads reaches the cyclic read number threshold, a first response message is returned to the host computer.

11. The chip according to claim 10, characterized in that: The chip also includes a storage management module for allocating storage space to each channel, and the cache spaces of different channels are independent of each other; The main control module is also used to send the data read each time to the storage management module; The storage management module is further used to store the data in a cache space corresponding to the target channel.

12. The chip according to claim 11, characterized in that: The channel configuration parameters also include data handling conditions for each target channel; The register control module is also used to send the data handling conditions of each target channel to the storage management module; The storage management module is further configured to transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer condition of the target channel is met.

13. A communication interface reading control system, characterized in that: include: The reading control chip of the communication interface, the host computer and at least two slaves according to any one of claims 10 to 12, wherein the host computer and the at least two slaves are respectively connected to the reading control chip of the communication interface.

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