Data encryption method and system based on wafer-level chip heterogeneous platform

Abstract

The embodiments of the present invention relate to the technical field of wafer-level chip heterogeneous computing for cryptographic algorithms, and provide a data encryption method and system based on a wafer-level chip heterogeneous platform, including: obtaining multiple groups of original data to be encrypted and original keys; generating multiple data encryption subtasks based on the multiple groups of original data, and performing key expansion on the original keys to generate expanded keys; scheduling the multiple data encryption subtasks in parallel to the corresponding hardware backend based on the task scheduling mechanism of the multi-level intermediate representation framework, performing data encryption processing on the multiple groups of original data according to the expanded keys and the corresponding data encryption subtasks to obtain multiple encrypted data; and merging the multiple encrypted data to obtain target encrypted data. Thus, encryption throughput is improved, memory overhead is reduced, and efficient collaborative computing across CPUs, GPUs, and FPGAs on wafer-level chips is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer-level chip heterogeneous computing of cryptographic algorithms, and in particular to a data encryption method and system based on a wafer-level chip heterogeneous platform. Background Art

[0002] The current mainstream Advanced Encryption Standard (AES) algorithm primarily relies on software implementation on general-purpose CPUs, and its efficiency is limited by the following factors:

[0003] 1. Performance bottlenecks in software implementations and insufficient vectorization and instruction-level parallelism: Traditional software implementations typically use byte-by-byte processing logic and fail to fully utilize the SIMD (Single Instruction, Multiple Data) instruction set, resulting in limited performance. Because these implementations rely on general-purpose instruction sets (such as x86 or ARM), they struggle to fully exploit the parallel computing capabilities of modern hardware. For example, while OpenSSL's AES implementation supports Intel AES-NI instruction acceleration, performance degrades significantly on platforms without dedicated instruction sets (such as low-end embedded devices), and parallelization efficiency is limited on multi-core CPUs. While SIMD instructions (such as SSE and AVX) are partially used, the full potential of vectorization for the AES process is not fully utilized. For example, row shifts and column shuffles still rely on byte-by-byte operations and are not fully converted to vector instructions, resulting in limited instruction throughput.

[0004] 2. Redundancy in key expansion, resource contention, and memory inefficiency: Traditional implementations can suffer from redundant memory access and multi-thread contention during the key expansion phase during multiple encryption and decryption tasks. For example, when encrypting multiple data blocks with the same key, round keys must be regenerated for each encryption, without reusing existing results. This repetitive operation significantly increases computational overhead in batch encryption scenarios, especially in the long-key AES-256 mode. Furthermore, traditional implementations lack optimized memory alignment and sharing strategies, leading to memory resource contention between multiple threads or hardware units.

[0005] 3. Inadequate adaptability to heterogeneous hardware: Traditional solutions cannot dynamically adapt to multiple hardware backends. For example, GPU implementations typically require specialized code (such as CUDA or OpenCL), which is costly and difficult to coordinate with CPU tasks. FPGA implementations typically use fixed pipeline designs, making them difficult to flexibly adapt to different encryption modes. The high parallel potential of wafer-level chips has not been fully exploited, and traditional code cannot be automatically mapped to their distributed computing units. Summary of the Invention

[0006] The present invention provides a data encryption method and system based on a wafer-level chip heterogeneous platform, which is used to solve the performance bottlenecks of software implementation and the defects of insufficient vectorization and instruction-level parallelism, redundancy defects of key expansion, resource competition and memory inefficiency, and insufficient heterogeneous hardware adaptability in the prior art, thereby improving encryption throughput, reducing memory overhead, and realizing efficient collaborative computing across CPU, GPU, and FPGA on wafer-level chips.

[0007] The present invention provides a data encryption method based on a wafer-level chip heterogeneous platform, comprising:

[0008] Obtain multiple sets of original data to be encrypted and original keys;

[0009] Generating a plurality of data encryption subtasks based on the plurality of groups of original data, and performing key expansion on the original key to generate an expanded key;

[0010] Based on the task scheduling mechanism of the multi-level intermediate representation framework, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend, and the multiple groups of original data are encrypted by the hardware backend according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of a heterogeneous hardware platform of a wafer-level chip;

[0011] The multiple encrypted data are merged to obtain target encrypted data.

[0012] In one possible implementation, the method further includes:

[0013] Adapting a symmetric encryption algorithm to a heterogeneous hardware platform of a wafer-level chip using a multi-level intermediate representation framework, wherein the heterogeneous hardware platform includes multiple heterogeneous hardware computing units;

[0014] Converting data processing operations of the symmetric encryption algorithm into vector instructions through the vectorized dialect of the multi-level intermediate representation framework;

[0015] The symmetric encryption algorithm is memory managed based on a memory management optimization strategy, wherein the memory management optimization strategy includes a data flattening strategy, a shared memory strategy for an extended key and a T table, a data alignment optimization strategy, and a dynamic memory allocation strategy.

[0016] In one possible implementation, the method further includes:

[0017] The byte substitution operation, row shift operation, and round key addition operation of the symmetric encryption algorithm are vectorized and converted into vector instructions through the vectorization dialect of the multi-level intermediate representation framework.

[0018] In one possible implementation, the method further includes:

[0019] Flattening the high-dimensional data in the symmetric encryption algorithm into one-dimensional data;

[0020] Storing the extended key and the T-table in the static shared memory of the wafer-level chip for access by the multiple heterogeneous hardware computing units;

[0021] The S-box of the symmetric encryption algorithm and every four I8 entries of the T-table are pre-calculated and merged into an I32 value.

[0022] In one possible implementation, the method further includes:

[0023] Based on the task scheduling mechanism of the multi-level intermediate representation framework and the properties of each of the hardware backends, generating corresponding target task partitioning codes;

[0024] Based on the target task division code, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend.

[0025] In one possible implementation, the method further includes:

[0026] Based on the data length requirement of the symmetric encryption algorithm, each set of original data is divided into data blocks, and the last data block is padded with data to obtain multiple target data blocks;

[0027] Performing data encryption processing on the multiple target data blocks of each group of original data according to the extended key and the symmetric encryption algorithm through the hardware backend;

[0028] The target data blocks of each group of original data after data encryption are merged to obtain a plurality of encrypted data.

[0029] The present invention also provides a data encryption system based on a wafer-level chip heterogeneous platform, comprising the following modules:

[0030] A front-end module is configured to obtain multiple sets of original data to be encrypted and an original key; generate multiple data encryption subtasks based on the multiple sets of original data; and perform key expansion on the original key to generate an expanded key;

[0031] A parallel module is used to schedule the multiple data encryption subtasks in parallel to the corresponding hardware backend based on the task scheduling mechanism of the multi-level intermediate representation framework; through the hardware backend, the multiple groups of original data are encrypted according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of a heterogeneous hardware platform of a wafer-level chip; the multiple encrypted data are merged to obtain target encrypted data.

[0032] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the computer program, it implements any of the above-described data encryption methods based on a wafer-level chip heterogeneous platform.

[0033] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the data encryption method based on a wafer-level chip heterogeneous platform as described above is implemented.

[0034] The present invention also provides a computer program product, comprising a computer program, which, when executed by a processor, implements any of the above-described data encryption methods based on a wafer-level chip heterogeneous platform.

[0035] The present invention provides a data encryption method and system based on a wafer-level chip heterogeneous platform, which obtains multiple sets of original data and original keys to be encrypted; generates multiple data encryption subtasks based on the multiple sets of original data, and performs key expansion on the original keys to generate expanded keys; based on the task scheduling mechanism of a multi-level intermediate representation framework, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend, and the hardware backend performs data encryption processing on the multiple sets of original data according to the expanded keys and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of the heterogeneous hardware platform of the wafer-level chip; and the multiple encrypted data are merged to obtain target encrypted data. Compared with the performance bottleneck of software implementation in the prior art, as well as the defects of insufficient vectorization and instruction-level parallelism, redundancy defects of key expansion, resource competition and memory inefficiency, and insufficient heterogeneous hardware adaptation, this solution realizes efficient multi-hardware backend parallelization of symmetric encryption algorithms on wafer-level chips through a multi-level intermediate representation framework, and combines vectorization optimization and memory management strategies to significantly improve algorithm performance and resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 It is a flow chart of the data encryption method based on the wafer-level chip heterogeneous platform provided by the present invention.

[0038] Figure 2This is a data flow diagram of the data encryption method based on the wafer-level chip heterogeneous platform provided by the present invention.

[0039] Figure 3 It is a structural diagram of the data encryption system based on the wafer-level chip heterogeneous platform provided by the present invention.

[0040] Figure 4 This is a parallel module flow chart of the data encryption system based on the wafer-level chip heterogeneous platform provided by the present invention.

[0041] Figure 5 This is a key expansion flow chart provided by the present invention.

[0042] Figure 6 This is a schematic diagram of the T-table generation principle provided by the present invention.

[0043] Figure 7 This is a schematic diagram of the parallel scheduling principle provided by the present invention.

[0044] Figure 8 This is a schematic diagram of table lookup encryption optimization provided by the present invention.

[0045] Figure 9 This is a schematic diagram of table lookup method decryption optimization provided by the present invention.

[0046] Figure 10 This is a table lookup column hybrid principle diagram provided by the present invention.

[0047] Figure 11 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0049] To facilitate understanding of the embodiments of the present invention, specific embodiments will be further explained below with reference to the accompanying drawings. The embodiments do not limit the embodiments of the present invention.

[0050] Figure 1 This is one of the flow charts of the data encryption method based on the wafer-level chip heterogeneous platform provided by the present invention, such as Figure 1 As shown, the method includes the following:

[0051] S11. Obtain multiple groups of original data to be encrypted and original keys.

[0052] This embodiment of the present invention adapts the Advanced Encryption Standard (AES) symmetric encryption algorithm to wafer-level chips through the Multi-Level Intermediate Representation (MLIR) framework. The AES algorithm, a symmetric encryption algorithm of the Advanced Encryption Standard, is dynamically generated using the MLIR framework's hardware dialect support and vectorization optimization capabilities to efficiently generate code for the distributed computing units within the wafer-level chip. Specifically, this includes: MLIR-based full-process vectorized instruction conversion of AES core operations (such as byte substitution, row shift, and column mixing); optimized key and table lookup data access through a shared memory strategy to reduce resource contention among multiple cores; and dynamically allocating encryption tasks to heterogeneous computing units within the wafer-level chip in conjunction with the MLIR task scheduling mechanism. This embodiment of the present invention significantly improves encryption throughput, reduces memory overhead, and enables efficient collaborative computing across CPUs, GPUs, and FPGAs within the wafer-level chip.

[0053] Specific, combined Figure 2 As shown in the data flow diagram, in the initial stage of the encryption process, the system first needs to obtain the data to be encrypted and the original encryption key from the user to the front-end module. This data can be any binary data format, such as file contents, network data packets, or other information to be protected. The size of each data set can vary, but for ease of subsequent processing, the data is typically divided into fixed-size blocks (for example, 16 bytes, as required by the AES algorithm).

[0054] Furthermore, the system receives the original key, which is the initial key provided by the user for encryption. The AES algorithm supports various key lengths, such as 128 bits, 192 bits, or 256 bits. The length of the original key determines the security of the encryption and the complexity of subsequent key expansion.

[0055] For example, if the system needs to encrypt the contents of a text file and the user provides a 128-bit raw key, the system reads the contents of the text file as binary data and divides it into multiple 16-byte data blocks.

[0056] S12: Generate multiple data encryption subtasks based on the multiple groups of original data, and perform key expansion on the original key to generate an expanded key.

[0057] After receiving multiple sets of source data, the system divides them into multiple subtasks to improve processing efficiency. Each subtask contains one or more data blocks, which are then distributed to different hardware backends for processing through parallel scheduling. The specific division method depends on the system's parallel processing capabilities and hardware resources. For example, if the system supports multithreading or multiple hardware backends, the source data can be divided into multiple parallel processing subtasks to improve encryption efficiency.

[0058] Furthermore, the original key needs to undergo a key expansion operation to generate the expanded key required for multiple rounds of encryption. Figure 5 The key expansion flow chart shown in the figure shows that key expansion is the core process of the AES algorithm. The original 16-byte key is expanded to a 176-byte key through multiple rounds of parallel XOR, word rotation, byte substitution, and round coefficient XOR operations. Whether it is encryption or decryption, the implementation of key expansion is exactly the same. The specific implementation of the embodiment of the present invention is as follows:

[0059] During the initialization phase of key expansion, runtime overhead is reduced by precalculating the round constant (Rcon) and vectorizing constant loading. Rcon is a crucial parameter in AES key expansion, and the code predefines it as a constant array to avoid repeated calculations during each round of key expansion. Furthermore, a mask of vector<4xI1> is created via vector::CreateMaskOp to control the range of subsequent vector operations.

[0060] A normal round of key expansion involves only one parallel XOR operation, which simultaneously XORs every byte in the two vectors using the arith::XOrIOp operation. A special round of key expansion requires three additional operations:

[0061] First, word rotation is implemented using a vectorized byte shuffle operation called vector::ShuffleOp. This shuffles four bytes left by one byte. Using a shuffle index vector of the form inv4 = {1, 2, 3, 0}, the bytes in the vector are shifted left by one bit. This shuffle is performed with a single instruction, avoiding the multiple shifts and concatenations required in traditional implementations and significantly improving efficiency.

[0062] Byte substitution is then performed (this byte substitution is consistent with the byte substitution steps in the core AES encryption and decryption algorithms, so it is briefly outlined here). This involves using a vectorized table lookup to collect data non-contiguously from the S-box. Specifically, the 4-byte index is first expanded to 32 bits, and the 4-byte replacement result is collected from the S-box all at once using vector::GatherOp, avoiding the byte-by-byte table lookup required in traditional implementations. Furthermore, the S-box is preloaded into static memory before key expansion begins, further reducing memory access latency during the table lookup.

[0063] Finally, the round coefficient XOR is performed using the vectorized XOR operation arith::XOrIOp to XOR the Rcon value with the key byte. The Rcon value is directly obtained from a precomputed constant array. This parallel XOR operation fully utilizes the multiple execution units of the backend hardware, reducing the number of instructions and increasing instruction-level parallelism.

[0064] Data reading and writing also require vectorization optimization. Key expansion requires loading four consecutive bytes from memory into a vector register (vectorI8x4) using the vectorized load operation vector::LoadOp. After the key is calculated, the system uses the vector::StoreOp operation to perform vectorized storage of the expanded key and store it in static memory, making it easily accessible to multiple parallel module threads. Vectorized reading and writing significantly improves the efficiency of key expansion.

[0065] The theoretical performance improvements of AES key expansion are as follows: pre-calculated Rcon and vectorized constant loading reduce runtime overhead; vectorized loading and byte reordering optimize memory access and word loop operations; vectorized table lookup and pre-loaded S-boxes accelerate byte substitution operations; vectorized XOR operations and branchless design improve instruction-level parallelism; and vectorized read and write reduce the number of memory accesses.

[0066] S13. Based on the task scheduling mechanism of the multi-level intermediate representation framework, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend. Through the hardware backend, the multiple groups of original data are encrypted according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data.

[0067] S14: Merge the multiple encrypted data to obtain target encrypted data.

[0068] In this embodiment of the present invention, the hardware backend is a heterogeneous hardware computing unit on a heterogeneous hardware platform based on wafer-level chips. Based on the task scheduling mechanism of the multi-level intermediate representation framework and the properties of each hardware backend, a corresponding target task partitioning code is generated. Based on the target task partitioning code, multiple data encryption subtasks are dispatched in parallel to the corresponding hardware backend.

[0069] Furthermore, based on the data length requirement of the symmetric encryption algorithm, each group of original data is divided into data blocks, and the last data block is padded with data to obtain multiple target data blocks; the multiple target data blocks of each group of original data are encrypted according to the extended key and the symmetric encryption algorithm through the hardware backend; the target data blocks of each group of original data after the data encryption processing are merged to obtain multiple encrypted data.

[0070] It should be noted that the front-end module also needs to pre-allocate static memory space for the extended key, S-box, inverse S-box, and T-table so that the parallel modules can share memory data. Each set of original data after scheduling grouping (a set of original data corresponding to a data encryption subtask) will be divided into multiple 16-byte data blocks, and then used as the input of the parallel module in units of data blocks. After the parallel module operation is completed, all data blocks will be merged in sequence to form the final result, and the data block at the end of each set of original data will also be filled; the output of this module is the result after encryption and decryption of multiple sets of original data.

[0071] like Figure 6 The present invention provides a schematic diagram of the T-table generation principle. T-table generation involves precalculating polynomial multiplication over the finite field GF(2^8) and then loading the results into static memory. All I8 values ​​(0x00-0xFF) are modularly multiplied with the column-mixing matrix coefficients to obtain the calculation results for 256 input values, which are then stored in the corresponding locations in the T-table. This optimizes the column-mixing matrix multiplication into a fast bitwise operation involving table lookup and exclusive-or. If the system performs AES encryption, the T-table contains only four index tables related to 0x01 / 0x01 / 0x02 / 0x03; if AES decryption is performed, the T-table contains only four index tables related to 0x09 / 0x0B / 0x0D / 0x0E, ensuring the reusability of the T-table. Similar to key expansion, T-table generation is performed only once across multiple parallel AES tasks, avoiding redundant T-table calculations in parallel modules.

[0072] The specific implementation of modular multiplication: The algorithm examines the lowest bit of the second multiplier bit by bit to determine whether to perform an XOR operation on the intermediate result with the temporary value temp. Furthermore, by examining the highest bit of temp, it determines whether to perform finite field reduction with the irreducible polynomial 0x1b, ensuring that the result remains within GF(2^8). The system utilizes MLIR arithmetic operations such as arith::ShLIOp, arith::ShRUIOp, arith::AndIOp, and arith::XOrIOp to implement efficient computation logic, significantly improving the performance of the column mix step.

[0073] The calculation results of T table are loaded into continuous static memory (4 256 bytes), the system further improves performance through T-table alignment optimization and memory sharing. Like S-boxes, T-table storage is compressed from a two-dimensional structure into a contiguous one-dimensional array. For T-table entry storage, the system aligns memory accesses by concatenating four consecutive I8 bytes into a single I32 value. This allows vector::LoadOp to load four bytes at once, rather than loading them one by one, reducing memory access latency. Furthermore, multiple parallel tasks access shared T-table memory, eliminating the overhead of repeated T-table loading and improving cache hit rates during parallel execution. Furthermore, vector::CreateMaskOp is used to create masks to control the scope of vector operations and avoid unnecessary memory accesses.

[0074] like Figure 7 The parallel scheduling principle diagram provided by this invention demonstrates that, in the specific implementation of multi-group task partitioning, the system dynamically allocates multiple groups of AES tasks to different hardware backends based on the parallel loop operation hyper::ForOp in the heterogeneous scheduling dialect and a hardware information library, supporting parallel computing across devices. First, the system obtains the current system hardware configuration (such as the number of devices and computing power) from the hardware information library and divides the hardware resources into multiple groups, each containing one or more devices. Next, the system dynamically allocates AES tasks based on the load ratio of each group. The system calculates the load ratio of each group and determines the number of tasks to be processed by each group based on the total number of tasks and the load ratio, thereby maximizing hardware resource utilization. After task allocation, the system uses hyper::ForOp to use each group of tasks as input to a parallel module. The system then executes the tasks in parallel on the heterogeneous devices using the computational logic described by its subregions. Each device independently processes the assigned task and simultaneously reduces the computation results using a reduction operator, ultimately achieving efficient load balancing and parallel computing. This design not only fully utilizes the computing power of heterogeneous hardware, but also optimizes overall performance through task partitioning and dynamic scheduling, ensuring efficient parallel execution across the assigned devices.

[0075] Before encryption, the original text in each task is divided into 16-byte blocks. The last block is padded according to the PKCS #7 standard to ensure that the data length meets the AES algorithm's block length requirements (16-byte alignment). For decryption, after all calculations are completed, the padded data is removed according to the PKCS #7 standard to restore the original data. Specifically, the system first calculates the number of remaining bytes in the input data and generates a padding value. The padding value is 16 minus the number of remaining bytes, and the padding content is the byte representation of the padding value. The system uses the dynamic masking operation vector::CreateMaskOp to determine whether to pad the current block. If padding is required, the system uses the vector::MaskedLoadOp operation to load the original data and insert the padding bytes; otherwise, the original data is loaded directly. Padding utilizes vectorized masking operations and conditional branch optimizations to avoid multiple memory accesses and branch prediction failures in traditional implementations, improving padding efficiency. Furthermore, the system uses vector::SplatOp to broadcast the padding value to the entire vector, ensuring uniformity and efficiency of the padding operation.

[0076] The core concept of the AES algorithm is to obfuscate and diffuse data through multiple rounds of encryption operations (including byte substitution, row shifting, column mixing, and round key addition) to ensure encryption strength. AES supports key lengths of 128, 192, and 256 bits, with each round operating on a 16-byte data block. The encryption process includes an initial round key addition, multiple rounds of encryption (10, 12, or 14 rounds, depending on the key length), and a final round of encryption. The decryption process is the inverse of encryption, recovering the original data by reversing the steps.

[0077] Specifically, round key addition involves performing a byte-by-byte XOR on the round key and the data block. Traditional implementations typically employ a byte-by-byte XOR approach, which is inefficient. This system leverages MLIR's vectorized XOR operation to implement efficient vectorized XOR operations. The system first loads the 16-byte key fragment of the current round from the extended key using vector::LoadOp. Since the total length of the AES-128 extended key is 176 bytes, the system locates the key fragment for each round using index calculation. The loaded key fragment is then XORed byte-by-byte with the data block using arith::XOrIOp to generate an encrypted intermediate result. This vectorized XOR operation not only reduces the number of instructions but also fully utilizes the hardware's parallel computing units, significantly improving computational efficiency. Furthermore, the system uses loop unrolling technology to combine multiple rounds of key addition operations into a single vectorized operation, reducing loop control overhead.

[0078] Byte substitution is a nonlinear transformation in the AES encryption algorithm. It replaces each byte by querying an S-box to enhance the algorithm's obfuscation and security. The S-box is queried during encryption, while the inverse S-box is queried during decryption. Traditional byte-by-byte table lookups are inefficient. This system utilizes MLIR's vector::GatherOp to implement vectorized table lookups, processing 16 bytes of input data at a time, significantly reducing table lookups and memory access latency. The implementation is as follows: First, the system uses arith::ExtUIOp to expand the 16-byte original text into a 32-bit index to ensure alignment with the S-box memory address. Next, vector::GatherOp is used to collect the 16-byte substitution results from a preloaded S-box at once, using a mask (maskI1x16) to control the location of valid data. Finally, vector::StoreOp is used to write the replaced data to the output buffer for efficient storage. This vectorized table lookup significantly improves the efficiency of byte substitution.

[0079] Row shifting cyclically left-shifts each row of the state matrix by a different offset, enhancing data diffusion and algorithm security. Traditional implementations of byte-by-byte shifting are inefficient. This system uses vector::ShuffleOp and a predefined index vector inv16 to shuffle the 16-byte vector, directly completing all row shifts. For example, during encryption, inv16 = {0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11}; during decryption, inv = {0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3}. This efficient shuffling is achieved with a single vector instruction. This optimization avoids row-by-row shifting and concatenation operations, fully leveraging hardware vectorization support and significantly improving efficiency. At the same time, combined with mask operations (vector::CreateMaskOp) to ensure the accuracy and consistency of data processing.

[0080] The table lookup column mixing mixes each column of the state matrix through finite field multiplication to enhance the diffusion of data. However, its traditional implementation relies on complex finite field multiplication operations and is inefficient. The embodiment of the present invention uses a table lookup method to replace the two steps of byte substitution and column mixing in the main round, such as Figure 8This is a schematic diagram of the optimization of the table lookup encryption method provided by the present invention, that is, replacing the finite field multiplication operation with higher complexity by querying the pre-calculated T table. In order to meet the correctness of the table lookup method, it is necessary to swap the order of byte substitution and row shift in the main round of the AES algorithm, so that the two steps of byte substitution and column mixing are performed adjacently, which facilitates the direct merging of the two steps. The correctness of this operation lies in that the order of byte substitution and row shift in the main round will not affect the result of the AES algorithm. For AES encryption, it is necessary to advance the row shift in the main round, that is, perform table lookup and column mixing after the row shift; for AES decryption, it is necessary to post-position the reverse row shift in the main round, that is, perform reverse row shift after the reverse table lookup and column mixing, such as Figure 9 This is a schematic diagram of table lookup method decryption optimization provided by the present invention.

[0081] Figure 10 This is a hybrid principle diagram of the table lookup provided by the present invention, such as Figure 10 As shown, a column-by-column lookup requires extracting the original 16-byte text into four vector<4x18> segments using the vector::ExtractStridedSliceOp operation. A vectorized table lookup is then performed on each segment using a vector::GatherOp operation similar to byte substitution. Four different vectorized table lookups are performed on each segment, corresponding to the four finite field matrix multiplications in the column-by-column mix. The resulting 16 vector segments are then XOR-reduced using vector::ReductionOp to produce a vector<16xI8> result. Finally, the result is written back to contiguous memory using vector.store.

[0082] The present invention provides a data encryption method based on a wafer-level chip heterogeneous platform, which obtains multiple sets of original data and original keys to be encrypted; generates multiple data encryption subtasks based on the multiple sets of original data, and performs key expansion on the original keys to generate expanded keys; based on the task scheduling mechanism of a multi-level intermediate representation framework, the multiple data encryption subtasks are parallelly scheduled to corresponding hardware backends, and the hardware backends encrypt the multiple sets of original data according to the expanded keys and corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of the heterogeneous hardware platform of the wafer-level chip; and the multiple encrypted data are merged to obtain target encrypted data. Compared with the performance bottlenecks of software implementation in the prior art, as well as the defects of insufficient vectorization and instruction-level parallelism, redundancy defects of key expansion, resource competition and memory inefficiency, and insufficient heterogeneous hardware adaptation, the present method realizes efficient multi-hardware backend parallelization of symmetric encryption algorithms on wafer-level chips through a multi-level intermediate representation framework, and combines vectorization optimization and memory management strategies to significantly improve algorithm performance and resource utilization.

[0083] The data encryption system based on the wafer-level chip heterogeneous platform provided by the present invention is described below. The data encryption system based on the wafer-level chip heterogeneous platform described below and the data encryption method based on the wafer-level chip heterogeneous platform described above can be referenced to each other.

[0084] Figure 3 This is a schematic diagram of the structure of the data encryption system based on the wafer-level chip heterogeneous platform provided by the present invention, which specifically includes:

[0085] The front-end module 301 is configured to obtain multiple sets of original data to be encrypted and an original key; generate multiple data encryption subtasks based on the multiple sets of original data; and perform key expansion on the original key to generate an expanded key;

[0086] The parallel module 302 is used to schedule the multiple data encryption subtasks in parallel to the corresponding hardware backend based on the task scheduling mechanism of the multi-level intermediate representation framework; through the hardware backend, the multiple groups of original data are encrypted according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of a heterogeneous hardware platform of a wafer-level chip; the multiple encrypted data are merged to obtain target encrypted data.

[0087] Specifically, the front-end module 301 includes: a parallel scheduling unit, which is used to divide multiple groups of original data into multiple subtasks and assign them to the designated hardware back-end; a key expansion unit, which is used to expand the original key and generate an expanded key; a memory management unit, which is used to pre-allocate static memory space and optimize the memory management.

[0088] The parallel module 302 includes: a data block processing unit for dividing the original data into multiple 16-byte data blocks and padding the last data block; an encryption and decryption execution unit for performing AES encryption and decryption operations, including byte substitution, row shift, column mixing and round key addition.

[0089] Multiple heterogeneous computing units can be deployed on a single chip, offering high-throughput parallel computing capabilities, making them ideal for group-parallel execution of multiple AES encryption and decryption operations. Leveraging the cross-architecture support provided by MLIR, compilation to multiple hardware backends can be completed simply by calling the MLIR framework's libraries and descending to a unified intermediate MLIR IR. This eliminates the need to write independent operator cores for multiple parallel backends or port operator libraries on a large scale. Chips typically include powerful vectorized instruction sets, and the vectorized instructions provided by MLIR can fully leverage the performance of vector hardware, directly optimizing key encryption steps.

[0090] Leveraging MLIR's vectorized dialects (such as the vector dialect), core AES operations (such as byte substitution, row shifts, and column shuffles) are converted into efficient vector instructions, enabling full-process vectorization. For example, vector::GatherOp enables batch processing of S-box table lookups, while vector::ShuffleOp performs single-instruction rearrangement of row shifts, significantly reducing the number of instructions and memory accesses. MLIR's automatic vectorization further reduces the cost of manual optimization while ensuring instruction-level parallelism across hardware platforms.

[0091] The memory management unit is used to pre-allocate static memory space and optimize memory management, including:

[0092] Data flattening: Traditional AES algorithm implementations are based on byte-by-byte calculations of two-dimensional data. This system flattens all high-dimensional data in traditional AES implementations into one dimension, making it easier to load into vector registers and supporting batch processing of SIMD instructions.

[0093] The extended key and T-table use shared memory: key expansion and T-table generation are completed in the front-end module, and the extended key and generated T-table are stored in the static shared memory of the wafer-level chip for direct access by all parallel computing units, without the need for repeated calculations in parallel modules.

[0094] Data alignment optimization: For the S-box and T-table index tables, every four I8 entries are pre-computed and merged into a single I32 value, leveraging the atomic read and write properties of 32-bit integers to improve memory access locality.

[0095] Dynamic memory allocation: Combined with the memory management dialect of the MLIR framework, intermediate vectors are loaded and stored in a vectorized manner, and temporary memory is dynamically allocated on demand to reduce memory usage.

[0096] Based on MLIR's automatic adaptation to multiple hardware backends, the system adapts the AES algorithm to various hardware backends on wafer-level chips (such as CPUs, GPUs, and FPGAs), enabling dynamic task allocation and parallel computing. MLIR's hardware dialect support enables the algorithm to generate optimal code based on the characteristics of different hardware, maximizing the utilization of heterogeneous computing resources. For example, hyper::ForOp enables multi-backend task partitioning, dynamically allocating encryption tasks to different hardware units, avoiding idle resources and improving overall throughput.

[0097] Before using this system to optimize the AES algorithm on a wafer-level chip or simulator, pre-configuration is required, including:

[0098] Build environment configuration: Users need to specify the build directory and compilation toolchain directory in the Linux environment to ensure that the files and tools required for the build process (g++, make, llvm, etc.) can be correctly found and used;

[0099] Configure AES algorithm parameters: Users need to specify the original text / ciphertext data for encryption and decryption, original text / ciphertext length, number of original text / ciphertext groups, key data, key length, key type, and output address in the front-end module.

[0100] Compilation: The user compiles the MLIR project with the help of the Makefile file, and the intermediate files and target files will be generated in the directory specified by the user.

[0101] Execute the AES encryption and decryption program: After executing the compiled executable program, the terminal will output the AES encryption and decryption results of each set of data.

[0102] The embodiment of the present invention was also tested on a wafer-level chip system simulation platform, using AES-128 as the test algorithm, ECB mode for encryption and decryption, and PKCS#7 as the padding mechanism. Multiple AES tasks in the experiment used the same key.

[0103] The configuration of the wafer-level chip system simulation platform is as follows:

[0104] CPU (Ariel): Main frequency: 2660 MHz, single core, maximum number of requests per cycle: 3, network bandwidth: 96 GB / s.

[0105] GPU (NVIDIA GTX 480): Video memory: 1024 KB stack, 8 MB heap, bandwidth: 96 GB / s, latency: 300 ps.

[0106] Memory: Main frequency: 800 MHz, bandwidth: 96 GB / s, latency: 1000 ps, ​​capacity: 4 GB.

[0107] Network: Latency: 25 ps, Bandwidth: 96 GB / s, Flit size: 8 B.

[0108] Compiler: MLIR based on LLVM, LLVM version: 17.0.6.

[0109] Experiment 1: Performance Comparison

[0110] Experimental description: Under the same configuration of the wafer-level chip system simulation platform, the execution time of different algorithms to complete 100 sets of AES encryption and decryption tasks is tested.

[0111] Objective: To verify the performance advantages of the AES algorithm optimization method based on a wafer-level chip heterogeneous platform compared with traditional methods.

[0112] The experimental results are shown in Table 1:

[0113] Table 1

[0114]

[0115] Conclusion: The AES optimization method based on wafer-level chips significantly outperforms traditional implementations in terms of throughput. Its high parallel computing capability and MLIR optimization capabilities (such as vectorization and memory optimization) are the key to the performance improvement.

[0116] Experiment 2: Vectorization Optimization Performance Analysis

[0117] Experimental description: Under the same configuration of the wafer-level chip system simulation platform, the execution time and the length of the generated intermediate LLVM code of different implementation methods to complete 100 groups of AES encryption and decryption tasks are tested.

[0118] Objective: To verify the acceleration effect of MLIR vectorization on key steps.

[0119] The experimental results are shown in Table 2:

[0120] Table 2

[0121]

[0122] Conclusion: Vectorization optimization is crucial for improving the performance of the AES algorithm, especially for table lookup and XOR operations. Removing vectorized operations significantly increases execution time and the length of the LLVM intermediate code.

[0123] Experiment 3: Verification of memory optimization effect

[0124] Experimental description: Under the same configuration of the wafer-level chip system simulation platform, test the memory usage of different implementation methods to complete 100 sets of AES encryption and decryption tasks.

[0125] Objective: To verify the impact of various memory optimization strategies on performance.

[0126] The experimental results are shown in Table 3:

[0127] Table 3

[0128]

[0129] Conclusion: The memory optimization strategy significantly reduces memory usage, especially the memory sharing strategy for the extended key and T table. Without this optimization, memory usage increases significantly.

[0130] Experiment 4: Heterogeneous Hardware Co-scheduling Test

[0131] Experimental description: Under different configurations of the wafer-level chip system simulation platform, the hardware resource utilization is tested to complete 100 sets of AES encryption and decryption tasks when the CPU and GPU task loads are 1:0, 1:1, and 0:1 respectively.

[0132] Objective: To verify whether the system can achieve cross-hardware task distribution.

[0133] The experimental results are shown in Table 4:

[0134] Table 4

[0135]

[0136] Conclusion: The experimental results show that the system can dynamically allocate tasks according to the load ratio, and the system's parallel scheduling mechanism performs well in cross-hardware parallelism and resource utilization optimization.

[0137] This system adapts the AES algorithm to wafer-level chips using the MLIR framework. Leveraging MLIR's hardware dialect support and vectorization optimization capabilities, it dynamically generates efficient code for the wafer-level chip's distributed computing units. Specifically, this includes: MLIR-based full-process vectorized instruction conversion of AES core operations (such as byte substitution, row shift, and column mix); optimized key and table lookup data access through a shared memory strategy to reduce resource contention among multiple cores; and dynamically assigning encryption tasks to the wafer-level chip's heterogeneous computing units using the MLIR task scheduling mechanism. This significantly improves encryption throughput, reduces memory overhead, and enables efficient collaborative computing across CPUs, GPUs, and FPGAs on the wafer-level chip.

[0138] Figure 8 An example of a physical structure diagram of an electronic device is shown below. Figure 8As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communications bus 840. The processor 810 may call logic instructions in the memory 830 to execute a data encryption method based on a wafer-level chip heterogeneous platform, the method comprising: obtaining multiple sets of original data to be encrypted and an original key; generating multiple data encryption subtasks based on the multiple sets of original data, and performing key expansion on the original key to generate an expanded key; scheduling the multiple data encryption subtasks in parallel to corresponding hardware backends based on a task scheduling mechanism of a multi-level intermediate representation framework, wherein the hardware backend performs data encryption processing on the multiple sets of original data according to the expanded key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of the heterogeneous hardware platform of the wafer-level chip; and merging the multiple encrypted data to obtain target encrypted data.

[0139] Furthermore, the logic instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0140] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the data encryption method based on the wafer-level chip heterogeneous platform provided by the above methods, the method including: obtaining multiple groups of original data and original keys to be encrypted; generating multiple data encryption subtasks based on the multiple groups of original data, and performing key expansion on the original key to generate an expanded key; based on the task scheduling mechanism of the multi-level intermediate representation framework, scheduling the multiple data encryption subtasks in parallel to the corresponding hardware backend, and through the hardware backend, performing data encryption processing on the multiple groups of original data according to the expanded key and the corresponding data encryption subtask to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of the heterogeneous hardware platform of the wafer-level chip; merging the multiple encrypted data to obtain target encrypted data.

[0141] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the data encryption method based on a wafer-level chip heterogeneous platform provided by the above-mentioned methods, the method comprising: obtaining multiple groups of original data and original keys to be encrypted; generating multiple data encryption subtasks based on the multiple groups of original data, and performing key expansion on the original keys to generate expanded keys; scheduling the multiple data encryption subtasks in parallel to the corresponding hardware backend based on the task scheduling mechanism of the multi-level intermediate representation framework, and performing data encryption processing on the multiple groups of original data according to the expanded keys and the corresponding data encryption subtasks through the hardware backend to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of the heterogeneous hardware platform of the wafer-level chip; merging the multiple encrypted data to obtain target encrypted data.

[0142] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0143] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A data encryption method based on a wafer-level chip heterogeneous platform, characterized in that: include: Obtain multiple sets of original data to be encrypted and original keys; Generating a plurality of data encryption subtasks based on the plurality of groups of original data, and performing key expansion on the original key to generate an expanded key; Obtain the hardware backend configuration of the current system through the hardware information library, wherein the hardware backend configuration includes the number of devices and computing power; Dividing the hardware backend into multiple groups based on the number of devices and computing capabilities, each group including one or more devices; Dynamically allocate data encryption subtasks based on the load ratio of each group and the total number of tasks to maximize hardware resource utilization; Based on the task scheduling mechanism of the multi-level intermediate representation framework, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend, and the multiple groups of original data are encrypted by the hardware backend according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of a heterogeneous hardware platform of a wafer-level chip; The multiple encrypted data are merged to obtain target encrypted data.

2. The method according to claim 1, characterized in that Before obtaining the multiple groups of original data to be encrypted and the original key, the method includes: Adapting a symmetric encryption algorithm to a heterogeneous hardware platform of a wafer-level chip using a multi-level intermediate representation framework, wherein the heterogeneous hardware platform includes multiple heterogeneous hardware computing units; Converting data processing operations of the symmetric encryption algorithm into vector instructions through the vectorized dialect of the multi-level intermediate representation framework; The symmetric encryption algorithm is memory managed based on a memory management optimization strategy, wherein the memory management optimization strategy includes a data flattening strategy, a shared memory strategy for an extended key and a T table, a data alignment optimization strategy, and a dynamic memory allocation strategy.

3. The method according to claim 2, characterized in that The step of converting the data processing operations of the symmetric encryption algorithm into vector instructions using the vectorized dialect of the multi-level intermediate representation framework comprises: The byte substitution operation, row shift operation, and round key addition operation of the symmetric encryption algorithm are vectorized and converted into vector instructions through the vectorization dialect of the multi-level intermediate representation framework.

4. The method according to claim 2, characterized in that The memory management of the symmetric encryption algorithm based on the memory management optimization strategy includes: Flattening the high-dimensional data in the symmetric encryption algorithm into one-dimensional data; Storing the extended key and the T-table in the static shared memory of the wafer-level chip for access by the multiple heterogeneous hardware computing units; The S-box of the symmetric encryption algorithm and every four I8 entries of the T-table are pre-calculated and merged into an I32 value.

5. The method according to claim 1, wherein The task scheduling mechanism based on the multi-level intermediate representation framework schedules the multiple data encryption subtasks in parallel to the corresponding hardware backend, including: Based on the task scheduling mechanism of the multi-level intermediate representation framework and the properties of each of the hardware backends, generating corresponding target task partitioning codes; Based on the target task division code, the multiple data encryption subtasks are scheduled in parallel to the corresponding hardware backend.

6. The method according to claim 5, characterized in that The hardware backend performs data encryption processing on the multiple groups of original data according to the extended key and the corresponding data encryption subtask to obtain multiple encrypted data, including: Based on the data length requirement of the symmetric encryption algorithm, each set of original data is divided into data blocks, and the last data block is padded with data to obtain multiple target data blocks; Performing data encryption processing on the multiple target data blocks of each group of original data according to the extended key and the symmetric encryption algorithm through the hardware backend; The target data blocks of each group of original data after data encryption are merged to obtain a plurality of encrypted data.

7. A data encryption system based on a wafer-level chip heterogeneous platform, characterized in that: The system comprises: A front-end module is configured to obtain multiple sets of original data to be encrypted and original keys; generate multiple data encryption subtasks based on the multiple sets of original data, and perform key expansion on the original keys to generate expanded keys; obtain the hardware back-end configuration of the current system from a hardware information library, the hardware back-end configuration including the number of devices and computing power; divide the hardware back-end into multiple groups based on the number of devices and computing power, each group containing one or more devices; and dynamically allocate data encryption subtasks based on the load ratio and total number of tasks of each group to maximize hardware resource utilization; A parallel module is used to schedule the multiple data encryption subtasks in parallel to the corresponding hardware backend based on the task scheduling mechanism of the multi-level intermediate representation framework; through the hardware backend, the multiple groups of original data are encrypted according to the extended key and the corresponding data encryption subtasks to obtain multiple encrypted data, wherein the hardware backend is a heterogeneous hardware computing unit of a heterogeneous hardware platform of a wafer-level chip; the multiple encrypted data are merged to obtain target encrypted data.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the data encryption method based on the wafer-level chip heterogeneous platform is implemented as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data encryption method based on a wafer-level chip heterogeneous platform is implemented as described in any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the data encryption method based on a wafer-level chip heterogeneous platform is implemented as described in any one of claims 1 to 6.

Images