Method and device for predicting bridging structure of chip, medium and equipment

Abstract

The invention discloses a method and a device for predicting a bridging structure of a chip, a medium and equipment, and relates to the technical field of finite element numerical simulation of semiconductor packaging. Analyzing the distance between adjacent welding spots when a bridging structure is formed according to the welding spot density and the warping degree of the chip, and constructing a function relation expression; the function relation expression comprises the relation among the chip warping degree, the welding spot density and the shortest distance between the adjacent welding spots; obtaining the welding spot density and the warping degree of the to-be-predicted chip; substituting the welding spot density and the warping degree of the to-be-predicted chip into the function relation expression, and determining the shortest distance between adjacent welding spots in the to-be-predicted chip; and if the shortest spacing is smaller than a preset spacing threshold, determining that the to-be-predicted chip has a bridging structure. The method can accurately predict the bridging structure of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of "finite element numerical simulation" of semiconductor packaging, and particularly relates to a method, device, medium and equipment for predicting the bridging structure of a chip. Background Art

[0002] Currently, as an advanced packaging technology, 2.5D packaging has been widely used in the electronics industry in recent years. It combines the advantages of two-dimensional planar packaging and three-dimensional stacking technology, and can achieve higher integration and better performance.

[0003] In 2.5D packaging, the formation of the ball bridge structure is a key issue. Its occurrence will cause a decrease in the conductivity of the entire packaging or even short circuit, which has an important impact on the performance of the entire packaging. Therefore, accurately predicting whether there is a bridging structure in the chip can help engineers identify potential risks at the design stage and take measures in advance to avoid the occurrence of bridging problems.

[0004] However, there is a lack of a method for predicting the bridging structure of a chip in the prior art. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, device, medium and equipment for predicting the bridging structure of a chip, which can accurately predict the bridging structure of the chip.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides a method for predicting the bridging structure of a chip, including:

[0008] Analyze the solder joint density and warpage degree of the chip to the spacing between adjacent solder joints when forming a bridging structure, and construct a functional relationship expression; the functional relationship expression includes the relationship between the chip warpage degree, solder joint density and the shortest spacing between adjacent solder joints;

[0009] Obtain the solder joint density and warpage degree of the chip to be predicted;

[0010] Substitute the solder joint density and warpage degree of the chip to be predicted into the functional relationship expression to determine the shortest spacing between adjacent solder joints in the chip to be predicted;

[0011] If the shortest spacing is less than the preset spacing threshold, it is determined that the chip to be predicted has a bridging structure.

[0012] Optionally, the functional relationship expression is:

[0013]

[0014] where z is the shortest spacing, z0 A, B, C, D, E, and F are constant terms, x is the degree of chip warpage, and y is the solder joint density.

[0015] Optionally, analyze the solder joint density and warpage degree of the chip to the spacing between adjacent solder joints when forming a bridging structure, and construct a functional relationship expression, including:

[0016] Establish an initial chip model with different solder joint densities in finite element numerical simulation software;

[0017] For any initial chip model, apply a stress load to the initial chip model, determine the degree of warpage of the initial chip model under different stress loads, and calculate the shortest spacing between adjacent solder joints of the initial chip model under different stress loads;

[0018] Determine the functional relationship expression according to the shortest spacing corresponding to the initial chip model with different degrees of warpage under different solder joint densities.

[0019] Optionally, calculate the shortest spacing between adjacent solder joints of the initial chip model under different stress loads, including:

[0020] For any stress load, obtain the spacing between all adjacent solder joints in the initial chip model;

[0021] Determine the shortest spacing from all the spacings.

[0022] Optionally, calculate the shortest spacing between adjacent solder joints of the initial chip model under different stress loads, including:

[0023] For any stress load, the spacing between the solder joint at the center of the chip and the adjacent solder joint in the initial chip model under the stress load;

[0024] Determine the spacing between the solder joint at the center of the chip and the adjacent solder joint as the shortest spacing.

[0025] Optionally, the method further includes:

[0026] After establishing the initial chip model, mark the center points of any two adjacent solder joints in the initial chip model;

[0027] After applying the stress load to the initial chip model, select the marked center points through a probe to determine the coordinates of the centers of any two adjacent solder joints;

[0028] Determine the spacing between any two adjacent solder joints according to the difference between the coordinates of the centers of any two adjacent solder joints.

[0029] Optionally, the calculation formula for the solder joint density is:

[0030]

[0031] The present invention provides a prediction device for the bridging structure of a chip, comprising:

[0032] A construction module, configured to analyze the pitch between adjacent solder joints when forming a bridging structure based on the solder joint density and warpage degree of the chip, and construct a functional relation expression; the functional relation expression includes the relationship between the chip warpage degree, solder joint density and the shortest pitch between adjacent solder joints;

[0033] An acquisition module, configured to acquire the solder joint density and warpage degree of the chip to be predicted;

[0034] A calculation module, configured to substitute the solder joint density and warpage degree of the chip to be predicted into the functional relation expression to determine the shortest pitch between adjacent solder joints in the chip to be predicted;

[0035] A prediction module, configured to determine that there is a bridging structure in the chip to be predicted if the shortest pitch is less than a preset pitch threshold.

[0036] The present invention provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the above-mentioned method for predicting the bridging structure of a chip is implemented.

[0037] The present invention provides a computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the above-mentioned method for predicting the bridging structure of a chip is implemented.

[0038] The above at least one technical solution adopted by the present invention can achieve the following beneficial effects:

[0039] In the present invention, by analyzing the influence of the solder joint density and warpage degree of the chip on the formation of the bridging structure, a functional relation expression is constructed; the functional relation expression includes the relationship between the chip warpage degree, solder joint density and the shortest pitch between adjacent solder joints. Therefore, the functional relation expression represents the functional relationship between the solder joint density and warpage degree of the chip and the formation of the bridging structure, so that it is possible to accurately determine whether there is a bridging structure in the chip to be predicted according to the functional relation expression. Description of the Drawings

[0040] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0041] Figure 1 is a schematic flow chart of a method for predicting the bridging structure of a chip provided by the present invention;

[0042] Figure 2A geometric schematic diagram of C4 bump provided by the present invention;

[0043] Figure 3 A geometric schematic diagram of Model 1 provided by the present invention;

[0044] Figure 4 A geometric schematic diagram of Model 2 provided by the present invention;

[0045] Figure 5 A geometric schematic diagram of Model 3 provided by the present invention;

[0046] Figure 6 A schematic diagram of the pitch of C4 bump provided by the present invention;

[0047] Figure 7 A schematic diagram of the center point marking of C4 bump provided by the present invention;

[0048] Figure 8 A schematic diagram of adding a probe after deformation provided by the present invention;

[0049] Figure 9 A display diagram of the initial condition setting provided by the present invention;

[0050] Figure 10 A deformation schematic diagram of Model 1 provided by the present invention;

[0051] Figure 11 A deformation schematic diagram of Model 2 provided by the present invention;

[0052] Figure 12 A deformation schematic diagram of Model 2 provided by the present invention;

[0053] Figure 13 A scatter plot of simulation data provided by the present invention;

[0054] Figure 14 A fitting effect diagram of sample points provided by the present invention;

[0055] Figure 15 A schematic diagram of a device for predicting the bridging structure of a chip provided by the present invention;

[0056] Figure 16 A schematic diagram of a computer device for implementing a method for predicting the bridging structure of a chip provided by the present invention. Detailed implementation manners

[0057] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0058] In modern electronic devices, such as smartphones, tablets, servers, etc., any failure or malfunction may cause damage to the device or loss of data, bringing inconvenience and losses to users. Therefore, in 2.5D packaging, the formation of BallBridge must be avoided to ensure the long-term stable operation of electronic products.

[0059] During the 2.5D packaging process, warping of the chip is a common problem. Chip warping can lead to poor connection between C4 bumps (solder joints) and chip pins, thereby causing the formation of Ball Bridge. In addition, the change in the density of C4 bumps on the chip will affect the magnitude of the stress on the chip and thus form Ball Bridge.

[0060] The present invention aims to find a functional relationship between chip warping and C4 bump density for the formation of Ball Bridge, so that the formation of Ball Bridge can be controlled and circuit failures caused by Ball Bridge problems can be avoided.

[0061] Based on this, the present invention provides a method for predicting the bridging structure of a chip, which can accurately predict whether there is a bridging structure in the chip.

[0062] The following will detail the technical solutions provided by each embodiment of the present invention in conjunction with the drawings.

[0063] Figure 1 It is a schematic flowchart of a method for predicting the bridging structure of a chip in the present invention, which specifically includes the following steps:

[0064] S101, analyze the pitch between adjacent solder joints when forming a bridging structure based on the solder joint density and warping degree of the chip, and construct a functional relationship expression; the functional relationship expression includes the relationship between the chip warping degree, solder joint density and the shortest pitch between adjacent solder joints.

[0065] Among them, the solder joint density and warpage degree of the chip are analyzed for the spacing between adjacent solder joints when forming a bridging structure, and a functional relationship expression is constructed, including: establishing an initial chip model with different solder joint densities in a finite element numerical simulation software; for any initial chip model, applying a stress load to the initial chip model, determining the warpage degree of the initial chip model under different stress loads, and calculating the shortest spacing between adjacent solder joints of the initial chip model under different stress loads; determining the functional relationship expression according to the shortest spacing corresponding to the initial chip models with different warpage degrees under different solder joint densities.

[0066] Optionally, calculating the shortest spacing between adjacent solder joints of the initial chip model under different stress loads includes: for any stress load, obtaining the spacing between all adjacent solder joints in the initial chip model; determining the shortest spacing from all the spacings. Or, since the warpage of the middle part of the chip will reach the maximum, after deformation, the spacing between the C4 bump at the center of the chip and its adjacent C4 bump is calculated using a probe. Therefore, another way to calculate the shortest spacing between adjacent solder joints of the initial chip model under different stress loads is: for any stress load, taking the spacing between the solder joint at the center of the chip and its adjacent solder joint in the initial chip model under the stress load; taking the spacing between the solder joint at the center of the chip and its adjacent solder joint as the shortest spacing.

[0067] After establishing the initial chip model, mark the center points of any two adjacent solder joints in the initial chip model; after applying a stress load to the initial chip model, select the marked center points through a probe to determine the coordinates of the centers of any two adjacent solder joints; determine the spacing between any two adjacent solder joints according to the difference between the coordinates of the centers of any two adjacent solder joints. It should be noted that the coordinates of the solder joints are the coordinates on the x, y, and z axes. Among them, the y-axis represents the height of the solder joint, and the x-axis and z-axis represent the position distribution of the solder joints. Therefore, the spacing between adjacent solder joints can be the difference between the x-axes of adjacent solder joints on the same z-axis, or the difference between the z-axes of adjacent solder joints on the same x-axis. The spacing can represent the absolute value of the difference.

[0068] Among them, the calculation formula for the solder joint density is:

[0069]

[0070] Fitting the shortest spacing corresponding to the initial chip models with different solder joint densities and different warpage degrees, the determined functional relationship expression is:

[0071]

[0072] Among them, z is the shortest spacing, z 0, B, C, D, E, and F are constant terms, x is the degree of chip warping, and y is the solder joint density. Different chip types correspond to different values of the constant terms in the function relationship expression.

[0073] S102, obtain the solder joint density and warping degree of the chip to be predicted.

[0074] The chip to be predicted can be a chip after packaging on a simulation software, and directly obtain the solder joint density and warping degree of the chip to be predicted from the simulation software.

[0075] S103, substitute the solder joint density and warping degree of the chip to be predicted into the function relationship expression to determine the shortest distance between adjacent solder joints in the chip to be predicted.

[0076] Substitute the solder joint density and warping degree of the chip to be predicted into the function relationship expression to obtain the shortest distance between adjacent solder joints in the chip to be predicted, where the shortest distance is the shortest distance between all solder joints in the chip to be predicted.

[0077] S104, if the shortest distance is less than the preset distance threshold, determine that the chip to be predicted has a bridging structure.

[0078] The preset distance threshold can be the safe distance between solder joints, and the preset distance threshold can be 0.3 mm.

[0079] If the shortest distance is less than the preset distance threshold, it means that there is a distance exceeding the preset distance threshold between all solder joints in the chip to be predicted, and it is determined that the chip to be predicted has a bridging structure. If the shortest distance is greater than or equal to the preset distance threshold, it means that the distances between all solder joints in the chip to be predicted are not less than the preset distance threshold, and it is determined that the chip to be predicted does not have a bridging structure.

[0080] In an exemplary embodiment, establish an initial model: establish an initial chip model with different C4 bump densities in the simulation software ANSYS. The geometric model of the C4 bump is a drum shape, the upper and lower planes are circles with a diameter of 0.2 mm, and the maximum diameter of the middle circle is 0.3 mm, as Figure 2 shown. Model 1 includes a main chip (5 mm × 5 mm × 3 mm) and 225 C4 bumps, and the distance between two adjacent C4 bumps is 0.02 mm, as Figure 3 shown; Model 2 includes a main chip and 169 C4 bumps, and the distance between two adjacent C4 bumps is 0.05 mm, as Figure 4 shown; Model 3 includes a main chip and 121 C4 bumps, and the distance between two adjacent C4 bumps is 0.1 mm, as Figure 5 shown; Different models correspond to different C4 bump densities.

[0081] Define the pitch between C4 bumps: The pitch between C4 bumps is the center distance between two adjacent C4 bumps. Taking the C4 bump pitch diagram of Model 1 as an example, as Figure 6 shown.

[0082] Calculation method for the C4 bump pitch after model deformation: For the initial model, the center distance between C4 bumps can be measured in the sketch. After deformation, the probe in ANSYS is used to calculate the pitch between C4 bumps. Taking Model 1 as an example, first mark the center points of two adjacent C4 bumps, as Figure 7 shown; after applying stress to deform the model, then select the probe to select these two centers to obtain the coordinate values of the two centers. By subtracting the x-axis coordinate values, the pitch between the two C4 bumps after deformation can be obtained, as Figure 8 shown.

[0083] Define the C4 bump density of the model: The C4 bump density is defined as the total area of C4 bumps divided by the area of the main chip.

[0084] Define Ball Bridge: If, after subtracting the corresponding coordinate components of the center points of adjacent C4 bumps and adding the absolute values of the three resulting values, at least one value is less than 0.3 mm (the maximum circle diameter of the C4 bump), it is in the Ball Bridge state.

[0085] First, apply a fixed constraint to the main chip to ensure the stability of the simulation results. Subsequently, simulate the working environment of the chip, apply a stress load, and perform simulation deformation. Continuously change the stress load and extract the warpage degree of the chip under different stress loads. Since the warpage of the middle part of the chip reaches the maximum, after deformation, use the probe to calculate the pitch between the central C4 bump of the chip and its adjacent C4 bump. Finally, record the data of each group of warpage and C4 bump pitch.

[0086] Establish a functional relationship: In the present invention, the prediction of forming Ball Bridge by the chip warpage and C4 bump density in 2.5D packaging is used, and the functional relationship is: z = f(x, y). Where z is the shortest pitch between C4 bumps after model deformation, x is the chip warpage degree, and y is the C4 bump density. Table 1 shows the values of various material parameters of the model.

[0087] Table 1

[0088]

[0089] Simulation results: The environmental temperature of the simulation deformation is uniformly set to 60 °C, the displacement is at the four lower corner points of the bottom of the chip, and the fixed support is the bottom surface of the central C4 bump of the chip. The conditions are setFigure 9 As shown. Simulations are performed on each model to obtain simulation results, such as Figures 10 - 12 shown, Figure 10 is a schematic diagram of the deformation of Model 1, Figure 11 is a schematic diagram of the deformation of Model 2, Figure 12 is a schematic diagram of the deformation of Model 2.

[0090] Simulation data display: Eight sets of simulation data are obtained by applying different stresses to three groups of models respectively, with a total of 24 sets of simulation data, as shown in Table 2.

[0091] Table 2

[0092]

[0093]

[0094] Function fitting: The above simulation data is imported into Origin, and surface fitting is performed on the sample points. The results are as Figure 13 and Figure 14 shown.

[0095] Function relationship expression of chip warpage and C4 bump density on the formation of Ball Bridge: The values of each constant term are shown in Table 3.

[0096] Table 3

[0097] Constant term Value Z0 59.4 B -213 C 1463 D 1529 E -0.56 F 0.11

[0098] From Figure 14 it can be seen that R2 = 0.9963, indicating that the difference between the predicted value of the surface fitting model and the simulation value is relatively small, and the model can well predict the law of the formation of Ball Bridge.

[0099] When applying the method for predicting the bridging structure of the chip provided by the present invention, it is not necessary to execute according to the order of the steps Figure 1 shown. The specific execution order of each step can be determined according to needs, and the present invention does not limit this.

[0100] The above is the method for predicting the bridging structure of the chip provided by one or more embodiments of the present invention. Based on the same idea, the present invention also provides a corresponding device for predicting the bridging structure of the chip, such as Figure 15 shown.

[0101] Figure 15 is a schematic diagram of a device for predicting the bridging structure of a chip provided by the present invention. The device 1500 includes:

[0102] A construction module 1501 is used to analyze the solder joint density and warping degree of a chip to obtain the spacing between adjacent solder joints when forming a bridging structure, and construct a functional relationship expression; the functional relationship expression includes the relationship between the chip warping degree, solder joint density, and the shortest spacing between adjacent solder joints.

[0103] An acquisition module 1502 is used to acquire the solder joint density and warping degree of a chip to be predicted.

[0104] A calculation module 1503 is used to substitute the solder joint density and warping degree of the chip to be predicted into the functional relationship expression to determine the shortest spacing between adjacent solder joints in the chip to be predicted.

[0105] A prediction module 1504 is used to determine that there is a bridging structure in the chip to be predicted if the shortest spacing is less than a preset spacing threshold.

[0106] For the specific limitations of the device for predicting the bridging structure of a chip, reference can be made to the limitations of the method for predicting the bridging structure of a chip in the above text, which will not be elaborated here. Each module in the above device for predicting the bridging structure of a chip can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of a computer device in hardware form or be independent of it, or be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0107] The present invention also provides a computer-readable storage medium, which stores a computer program that can be used to execute the above Figure 1 provided method for predicting the bridging structure of a chip.

[0108] The present invention also provides Figure 16 a schematic structural diagram of the computer device as shown in Figure 16 shown. At the hardware level, the computer device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory. Of course, it may also include other hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the above Figure 1 provided method for predicting the bridging structure of a chip.

[0109] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above various methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided by the present invention can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0110] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded by the present invention.

Claims

1. A method for predicting a chip's bridging structure, characterized in that: include: The density of solder joints and the degree of warpage of the chip are analyzed to determine the distance between adjacent solder joints when forming a bridge structure, and a functional relationship expression is constructed; The functional relationship expression includes the relationship between the chip warpage degree, the solder joint density and the shortest distance between adjacent solder joints; Obtain the solder joint density and warpage degree of the chip to be predicted; Substituting the solder joint density and the warpage degree of the chip to be predicted into the functional relationship expression to determine the shortest distance between adjacent solder joints in the chip to be predicted; If the shortest distance is less than a preset distance threshold, it is determined that a bridge structure exists in the chip to be predicted.

2. The method according to claim 1, characterized in that The functional relationship expression is: Among them, z is the shortest spacing, z0, B, C, D, E, and F are constant terms, x is the degree of chip warpage, and y is the solder joint density.

3. The method according to claim 1, characterized in that The effect of the density of solder joints and the warpage degree of the chip on the spacing between adjacent solder joints when forming a bridge structure is analyzed, and a functional relationship expression is constructed, including: Establishing initial chip models with different solder joint densities in finite element numerical simulation software; For any initial chip model, applying stress load to the initial chip model, determining the warping degree of the initial chip model under different stress loads, and calculating the shortest spacing between adjacent solder joints of the initial chip model under different stress loads; The functional relationship expression is determined according to the shortest spacing corresponding to the initial chip model with different warping degrees under different solder joint densities.

4. The method according to claim 3, characterized in that The calculating the shortest spacing between adjacent solder joints of the initial chip model under different stress loads includes: For any stress load, obtaining the spacing between all adjacent solder joints in the initial chip model; The shortest distance is determined from all the distances.

5. The method according to claim 3, characterized in that: The calculating the shortest spacing between adjacent solder joints of the initial chip model under different stress loads includes: For any stress load, the distance between the most central solder joint of the chip and the adjacent solder joints in the initial chip model under the stress load; The distance between the solder joint at the center of the chip and the adjacent solder joint is determined as the shortest distance.

6. The method according to claim 3, characterized in that The method further comprises: After establishing the initial chip model, marking the center points of any two adjacent solder joints in the initial chip model; After applying stress load to the initial chip model, the coordinates of the centers of any two adjacent solder joints are determined by selecting the center points of the marks through a probe; The distance between the two adjacent welding spots is determined according to the difference between the coordinates of the centers of the two adjacent welding spots.

7. The method according to claim 1, characterized in that The calculation formula of the solder joint density is:

8. A chip bridge structure prediction device, characterized in that: include: A construction module is used to analyze the effect of the solder joint density and the warpage degree of the chip on the spacing between adjacent solder joints when forming a bridge structure, and to construct a functional relationship expression; The functional relationship expression includes the relationship between the chip warpage degree, the solder joint density and the shortest distance between adjacent solder joints; An acquisition module is used to obtain the solder joint density and warpage degree of the chip to be predicted; A calculation module, used for substituting the solder joint density and the warpage degree of the chip to be predicted into the functional relationship expression to determine the shortest distance between adjacent solder joints in the chip to be predicted; The prediction module is used to determine that the chip to be predicted has a bridge structure if the shortest distance is less than a preset distance threshold.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

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