High-frequency digital information transmission method and system

Abstract

The invention provides a high-frequency digital information transmission method and system. The method comprises the following steps: performing histogram equalization quantization processing on a high-frequency digital signal through a logic gating residual neural network to generate a quantized signal; processing the quantized signal by adopting quick reading and recovery of stress sensing to form a recovery signal; and performing transaction level hierarchical structure verification and optimization processing on the recovery signal to obtain a high-reliability transmission signal. According to the method, the quantization precision is improved through histogram equalization quantization, the signal recovery accuracy is improved in combination with stress sensing, the transmission quality is ensured by adopting multi-level verification, and the problem of signal integrity in high-frequency digital signal transmission is effectively solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and particularly to a high-frequency digital information transmission method and system. Background Art

[0002] With the continuous development of the integrated circuit manufacturing process, chip design is moving towards smaller size and faster transmission speed. In the field of high-frequency digital information transmission, ensuring signal integrity and transmission quality is particularly important, which directly affects the optimization of PCB design and system performance.

[0003] Currently, common high-frequency digital signal transmission technologies mainly include differential signal transmission and multi-layer PCB wiring and other solutions. Among them, differential signal transmission uses an inverting signal pair to cancel common-mode noise and improve the reliability of signal transmission; multi-layer PCB wiring optimizes signal integrity by reasonably allocating signal layers and power layers.

[0004] An existing technical solution uses a neural network combined with quantization processing to optimize high-frequency signal transmission. This solution establishes a signal transmission model, performs signal processing in combination with a residual network structure, and uses an adaptive quantization algorithm to reduce signal distortion.

[0005] However, this technical solution has the following problems: First, traditional quantization methods do not fully consider the signal histogram distribution characteristics, resulting in less than ideal quantization accuracy; second, during the high-frequency signal reading process, the system stress state is not effectively considered, affecting the accuracy of signal recovery; in addition, there is a lack of an effective verification mechanism to ensure the reliability of signal transmission. Summary of the Invention

[0006] In view of this, this application provides a high-frequency digital information transmission method and system, which solves the problems of less than ideal accuracy of traditional quantization methods, limited accuracy of signal recovery, and lack of an effective verification mechanism in the prior art.

[0007] An embodiment of this application provides a high-frequency digital signal transmission method, including:

[0008] Performing histogram equalization quantization processing on a high-frequency digital signal through a logic-gated residual neural network to generate a quantized signal;

[0009] Performing stress-aware fast reading and recovery on the quantized signal to form a recovered signal;

[0010] Obtaining a highly reliable transmission signal by performing transaction-level hierarchical structure verification and optimization processing on the recovered signal.

[0011] The performing histogram equalization quantization processing on a high-frequency digital signal through a logic-gated residual neural network to generate a quantized signal includes:

[0012] Using a logic gating mechanism, extract the features of the high-frequency digital signal and output the initial signal features;

[0013] Adopt a residual neural network model to analyze the initial signal features and generate a signal histogram distribution;

[0014] Apply an adaptive threshold algorithm to design the signal histogram distribution and form quantization parameters;

[0015] Generate the quantization signal by performing equalization quantization processing on the quantization parameters.

[0016] The generating the quantization signal by performing equalization quantization processing on the quantization parameters includes:

[0017] According to the quantization parameters, map the amplitude of the signal histogram distribution to the standard range and perform normalization processing to obtain a normalized signal;

[0018] Adopt probability density matching to perform non-linear mapping on the normalized signal to form the quantization signal.

[0019] The processing the quantization signal by adopting stress-aware fast reading and recovery to form a recovery signal includes:

[0020] Output a stress feature matrix by performing stress modeling analysis on the quantization signal;

[0021] Design a fast reading strategy for the stress feature matrix to generate a reading timing sequence;

[0022] According to the reading timing sequence, perform sampling and recovery modeling through the quantization signal to obtain a signal recovery model;

[0023] Use the signal recovery model to perform signal recovery and reconstruction processing on the quantization signal to generate the recovery signal.

[0024] The outputting a stress feature matrix by performing stress modeling analysis on the quantization signal includes:

[0025] Based on a pre-established thermal-electrical coupling model, perform an analysis on the influence of temperature changes on the quantization signal to form temperature stress characteristics;

[0026] According to the temperature stress characteristics, adopt load stress and power supply noise analysis to obtain the stress feature matrix.

[0027] The using the signal recovery model to perform signal recovery and reconstruction processing on the quantization signal to generate the recovery signal includes:

[0028] According to the signal recovery model, an adaptive algorithm is applied to preliminarily recover the quantized signal to generate a preliminarily recovered signal;

[0029] Perform stress compensation optimization on the preliminarily recovered signal to generate the recovered signal.

[0030] The high-reliability transmission signal is obtained by performing transaction-level hierarchical structure verification and optimization processing on the recovered signal, including:

[0031] Use the transaction-level hierarchical structure to analyze the recovered signal and output a functional coverage rate index;

[0032] Obtain a verification strategy through deductive form verification design of the functional coverage rate index;

[0033] Apply the verification strategy to generate a verification result through verification execution and data collection;

[0034] Perform signal optimization processing on the verification result to form the high-reliability transmission signal.

[0035] The use of the transaction-level hierarchical structure to analyze the recovered signal and output a functional coverage rate index includes:

[0036] Perform underlying signal characteristic verification and middle-layer protocol consistency verification on the recovered signal to generate first verification data;

[0037] Perform top-level functional integrity verification on the first verification data to obtain the functional coverage rate index.

[0038] The performing of signal optimization processing on the verification result to form the high-reliability transmission signal includes:

[0039] Use timing parameters and signal integrity parameters to classify and grade the verification result to generate an optimization strategy;

[0040] Adjust and optimize the timing parameters and signal integrity parameters according to the optimization strategy to form the high-reliability transmission signal.

[0041] This application embodiment also provides a high-frequency digital information transmission device, including:

[0042] A histogram equalization quantization processing module, configured to perform histogram equalization quantization processing on a high-frequency digital signal via a logic-gated residual neural network to generate a quantized signal;

[0043] A stress perception processing module, which uses stress perception for fast reading and recovery to process the quantized signal to form a recovered signal;

[0044] A verification and optimization processing module, configured to obtain a highly reliable transmission signal by performing transaction-level hierarchical verification and optimization processing on the recovery signal.

[0045] An embodiment of this application also provides a computer device, which includes:

[0046] At least one processor; and,

[0047] A memory communicatively connected to the at least one processor; wherein,

[0048] The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the above-mentioned high-frequency digital signal transmission method.

[0049] An embodiment of this application also provides a computer-readable storage medium, which stores computer instructions for causing a computer to execute the above-mentioned high-frequency digital signal transmission method.

[0050] An embodiment of this application also provides a computer program product, including computer instructions, and when the computer instructions are executed by a processor, the steps of the above-mentioned high-frequency digital signal transmission method are implemented.

[0051] This application has the following technical effects:

[0052] 1. By performing histogram equalization quantization processing through a logic-gated residual neural network, fully considering the signal histogram distribution characteristics, the quantization accuracy is improved;

[0053] 2. By adopting a stress-aware fast reading and recycling mechanism, effectively considering the influence of the system stress state on signal recovery, the accuracy of signal recovery is improved;

[0054] 3. By introducing transaction-level hierarchical verification and optimization processing, a complete signal verification mechanism is established, ensuring the reliability of high-frequency digital signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. The drawings herein are incorporated into the specification and constitute a part of this specification. These drawings show embodiments that conform to the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0056] Figure 1Schematic diagram of the high-frequency digital signal transmission method provided by the embodiment of the present application;

[0057] Figure 2 Schematic diagram of the histogram equalization quantization processing flow provided by the embodiment of the present application;

[0058] Figure 3 Schematic diagram of the stress sensing fast read and recycle processing flow provided by the embodiment of the present application;

[0059] Figure 4 Schematic diagram of the transaction level verification and optimization processing flow provided by the embodiment of the present application;

[0060] Figure 5 Schematic diagram of the structure of the high-frequency digital information transmission system provided by the embodiment of the present application. Detailed implementation manners

[0061] The following will refer to the case of writing the specification to elaborate on the detailed implementation manners of the embodiment of the present application.

[0062] As Figure 1 shown, the embodiment of the present application provides a high-frequency digital signal transmission method, including:

[0063] S1: Perform histogram equalization quantization processing on the high-frequency digital signal through a logic-gated residual neural network to generate a quantization signal;

[0064] As Figure 2 shown, step S1 specifically includes:

[0065] S1.1: Use a logic gating mechanism to extract features from the high-frequency digital signal and output initial signal features.

[0066] Receive the high-frequency digital signals to be processed, which usually come from the test points on the PCB board, and the signal frequency range is usually in the MHz to GHz level.

[0067] Secondly, establish a logic gating mechanism, which mainly includes two key parts: a timing control unit and a feature extraction unit.

[0068] Specifically, the timing control unit is responsible for controlling the sampling timing of the signal to ensure that the signal is acquired within an appropriate time window; the feature extraction unit extracts features such as the amplitude, rise time, and fall time of the signal by setting multiple logic threshold values.

[0069] Finally, output an initial signal feature set containing the time domain and frequency domain features of the signal.

[0070] S1.2: Use a residual neural network model to analyze the initial signal features and generate a signal histogram distribution.

[0071] After obtaining the initial signal features, first construct a residual neural network model, which contains multiple residual blocks, and each residual block consists of a convolutional layer, a batch normalization layer, and an activation function. Then, input the initial signal features into the residual neural network for processing. The network retains the original feature information through skip connections while extracting deep features. In addition, the model will count the distribution of the signal within different value ranges to generate a frequency statistics of the signal amplitude. Finally, output the histogram data reflecting the signal distribution characteristics.

[0072] Exemplarily, when processing a high-frequency digital signal of 1 GHz, the network can effectively extract key feature information such as the relatively dense distribution of the signal within the range of 0.3 - 0.7 V.

[0073] Exemplarily, construct a residual neural network model:

[0074] First, the basic structure design of the residual neural network. The network is constructed by connecting multiple residual blocks in series, and each residual block contains the following hierarchical structure:

[0075] Input layer: Receive the initial signal features, with a dimension of 1×N, where N is the number of sampling points;

[0076] First convolutional layer: Use 64 3×1 convolutional kernels for feature extraction, with a stride of 1, and the output dimension is 64×N;

[0077] Batch normalization layer: Normalize the output of the convolutional layer to maintain the stability of the data distribution;

[0078] ReLU activation layer: Introduce non-linearity to enhance the expression ability of the network;

[0079] Second convolutional layer: Use 64 3×1 convolutional kernels for further feature extraction;

[0080] Skip connection: Directly add the input signal to the output of the second convolutional layer to form a residual structure.

[0081] Second, the stacking design of the residual blocks. The network contains a total of 5 residual blocks, and the specific configuration is as follows:

[0082] The 1st - 2nd residual blocks: Keep the number of channels at 64, mainly used for extracting low-level features;

[0083] The 3rd - 4th residual blocks: Increase the number of channels to 128, used for extracting middle-level features;

[0084] The 5th residual block: Increase the number of channels to 256, used for extracting high-level features.

[0085] Third, the training strategy of the network includes the following key points:

[0086] Loss function: The mean squared error (MSE) loss is adopted to evaluate the difference between the network output and the target histogram distribution.

[0087] Optimizer: The Adam optimizer is used, and the initial learning rate is set to 0.001.

[0088] Learning rate scheduling: The learning rate is reduced to 0.1 times the original every 50 epochs.

[0089] Batch size: It is set to 64 to balance training efficiency and memory usage.

[0090] For example, when processing a high-frequency digital signal of 1 GHz, the specific application process of this residual neural network model is as follows:

[0091] Input processing:

[0092] The signal sampling data (sampling rate 10 GSa / s) within a 1 ms time window is used as the input.

[0093] The input data is normalized so that its mean is 0 and variance is 1.

[0094] Feature extraction:

[0095] The first residual block extracts basic waveform features, such as rise / fall time features.

[0096] The second residual block identifies the periodic pattern of the signal.

[0097] The third and fourth residual blocks extract the modulation features of the signal.

[0098] The fifth residual block generates the final histogram distribution features.

[0099] Network output:

[0100] The histogram distribution of 256 bins is output.

[0101] Each bin represents a voltage range of 0.1 V.

[0102] The distribution shows that the signal proportion within the range of 0.3 - 0.7 V reaches 80%.

[0103] This residual neural network structure can effectively extract the features of high-frequency digital signals and accurately reflect the amplitude distribution characteristics of the signals, providing a reliable basis for subsequent quantization processing.

[0104] S1.3: Apply the adaptive threshold algorithm to design the signal histogram distribution to form quantization parameters.

[0105] The system first receives the signal histogram distribution data output from the previous step and analyzes the probability density distribution characteristics of the signal. Then, it adopts an adaptive threshold algorithm, which dynamically adjusts the division of the quantization interval by calculating the entropy value and variance of the signal.

[0106] Specifically, a smaller quantization step is used in the region where the signal values are densely distributed, and a larger quantization step is used in the region where the distribution is sparse, so as to achieve a reasonable allocation of quantization resources. In addition, the algorithm will also adaptively adjust the quantization bits according to the dynamic range of the signal.

[0107] Finally, a quantization parameter set including parameters such as quantization step and quantization bits is output. It should be noted that, for example, for the signal distribution range of 0.3 - 0.7V which is dense, 8-bit quantization may be used with a step of 0.001V; while in other intervals, 6-bit quantization may be used with a step of 0.005V, so as to achieve the optimal allocation of resources.

[0108] Among them, the adaptive threshold algorithm dynamically adjusts the division of the quantization interval by calculating the entropy value and variance of the signal. Specifically, it includes:

[0109] The basic principle design of the algorithm.

[0110] The adaptive threshold algorithm mainly makes dynamic adjustments based on the statistical characteristics of the signal. The core includes two key steps: entropy value calculation and variance analysis. The entropy value is used to evaluate the uncertainty of the signal distribution, and the variance reflects the degree of dispersion of the signal. Specifically, for each interval in the histogram distribution, calculate its normalized probability pi, and then calculate the information entropy through the formula H = -Σ(pi * log2(pi)). At the same time, calculate the signal variance through the standard deviation formula σ = (Σ(xi - μ)2 / N), where xi is the signal value, μ is the mean value, and N is the number of sampling points.

[0111] Second, the adaptive division strategy of the quantization interval specifically includes the following steps:

[0112] Initial partition:

[0113] First, evenly divide the signal range into M initial intervals (the typical value of M = 256);

[0114] Calculate the probability density and cumulative distribution function of each interval;

[0115] Preliminarily evaluate the signal distribution in each interval;

[0116] Entropy value analysis:

[0117] Calculate the change in the local entropy value of adjacent intervals;

[0118] When the change in the entropy value exceeds a preset threshold (such as 0.1), it is marked as a possible segmentation point;

[0119] Determine the necessity of interval subdivision according to the entropy change rate;

[0120] Variance evaluation:

[0121] Analyze the variance distribution of signals in each interval;

[0122] Further subdivide the intervals with larger variances (such as exceeding 1.5 times the average variance);

[0123] Consider merging adjacent intervals with smaller variances;

[0124] Third, the specific implementation of the dynamic adjustment mechanism includes:

[0125] Adaptive step size control:

[0126] Adopt a smaller quantization step size (such as 0.001V) in the dense signal distribution area;

[0127] Adopt a larger quantization step size (such as 0.005V) in the sparse signal distribution area;

[0128] The step size range is automatically adjusted according to the dynamic range of the signal;

[0129] Threshold update strategy:

[0130] Update the statistical parameters once every 1000 sampling points;

[0131] Trigger the recalculation of the threshold when the entropy change exceeds 5%;

[0132] Keep the minimum interval between adjacent thresholds not less than 0.1 times the signal standard deviation;

[0133] Fourth, an example of the actual application effect of the algorithm is illustrated:

[0134] For a typical high-speed digital signal (such as 10Gbps data transmission), the specific performance is as follows: in the area where the signal conversion is frequent (such as 0.4V - 0.6V):

[0135] The entropy value is relatively high (usually greater than 0.8);

[0136] Adopt 8-bit quantization accuracy;

[0137] Set the quantization step size to 0.001V;

[0138] In the relatively stable signal area (such as 0 - 0.3V and 0.7 - 1.0V):

[0139] The entropy value is relatively low (usually less than 0.3);

[0140] Adopt 6-bit quantization accuracy;

[0141] The quantization step can be relaxed to 0.005V;

[0142] Dynamic adjustment effect:

[0143] When the signal mutates, the algorithm can complete the threshold adjustment within 2 - 3 clock cycles;

[0144] The quantization error is controlled within ±0.1% of the full scale;

[0145] The resource utilization rate is increased by about 30%;

[0146] Through this adaptive threshold algorithm, the system can dynamically optimize the quantization parameters according to the actual characteristics of the signal, improving the system efficiency while ensuring the signal quality. This algorithm is particularly suitable for processing high-frequency digital signals with uneven distribution characteristics, and can effectively balance the quantization accuracy and system resource consumption.

[0147] S1.4: Generate the quantization signal by performing equalization quantization processing on the quantization parameters.

[0148] Based on the quantization parameter set obtained in the previous step, first establish an equalization quantization processing module, which includes a preprocessing unit and a quantization execution unit.

[0149] Among them, the preprocessing unit normalizes the signal according to the quantization parameters, mapping the signal amplitude to the standard range. In addition, the quantization execution unit performs quantization coding on the processed signal according to the quantization step and the number of bits, and ensures the uniform distribution of the quantization error through equalization processing. It should be noted that the equalization processing adopts the method of probability density matching, and realizes the equalization of the signal distribution through nonlinear mapping. Finally, an optimized quantization signal is output, which has high quantization accuracy and good signal fidelity.

[0150] Among them, the equalization processing adopts the method of probability density matching, and realizes the equalization of the signal distribution through nonlinear mapping, specifically including:

[0151] The equalization processing adopts the method of probability density matching for nonlinear mapping, and its core principle is to realize the uniformization of the signal through probability distribution conversion. This method is mainly based on the statistical characteristics of the signal, and realizes the optimization of the signal distribution by establishing the mapping relationship between the probability density function (PDF) of the input signal and the target uniform distribution. In practical applications, the system first calculates the cumulative distribution function (CDF) F(x) of the input signal x, and then maps the uniform distribution back to the required signal space through the inverse function G(y), thus completing the entire equalization process.

[0152] In the specific implementation process, the system first uses the kernel density estimation method to calculate the probability density function of the signal. This step selects the Gaussian kernel function as the basis, and its bandwidth parameter is determined by the cross-validation method. To ensure the reliability of the estimation results, the system will smooth the initially obtained probability density function to effectively reduce the impact of noise on the system. On this basis, the cumulative distribution function is calculated by the numerical integration method, and the piecewise linear interpolation technique is used to improve the calculation efficiency while ensuring the monotonicity and continuity of the CDF.

[0153] For the specific application scenario of high-speed data transmission, the system implements a dynamic range adjustment mechanism. For example, when processing data transmission at 10 Gbps, the system will dynamically map the signal to the standardized interval of [-1, 1], and at the same time, by increasing the mapping point density at the places where the signal changes violently, effective non-linear compensation is achieved. In addition, the system also establishes an adaptive adjustment mechanism, which can monitor the signal distribution change in real time and dynamically update the mapping function parameters to ensure the real-time response of the system.

[0154] In terms of the optimization effect, this method significantly improves the distribution characteristics of the signal. Taking the actual application as an example, the signal that was originally unevenly distributed in the range of 0.3 - 0.7 V achieves uniform distribution after non-linear mapping, and the signal density difference is significantly reduced from the original 5:1 to 1.2:1. At the same time, the dynamic response characteristics of the system are also guaranteed. When the signal jumps, the mapping process can be completed within 100 ps, and the non-linear error in the transition region is controlled within 1%.

[0155] At the system implementation level, this method adopts a fine precision control strategy. 16-bit precision is used for calculation in the area where the signal distribution is dense, while it can be appropriately reduced to 12-bit precision in the sparse distribution area. This differential precision control strategy ensures that the average calculation error can be controlled within 0.1%. At the same time, through optimizing the implementation method, the system realizes significant resource savings. The compression ratio of the lookup table reaches 75%, the calculation delay is controlled within 2 clock cycles, and the overall power consumption is reduced by 40% compared with the traditional method.

[0156] This equalization processing method based on probability density matching not only effectively improves the distribution characteristics of the signal, but also significantly improves the quality and reliability of signal transmission. Especially when processing unevenly distributed high-frequency digital signals, this method shows excellent performance, and can optimize the utilization of system resources while ensuring signal integrity. Through actual application verification, this method has achieved significant effects in improving signal equalization, improving eye diagram opening, and reducing inter-symbol interference, and has high engineering application value.

[0157] Among them, step S1.4 specifically includes:

[0158] S1.4.1: According to the quantization parameters, map the amplitudes of the signal histogram distribution to the standard range and perform normalization processing to obtain a normalized signal.

[0159] First, determine the target range of signal mapping based on the quantization step and bit information in the quantization parameters. Then, for signals in different value ranges, use piecewise linear mapping to project the signal amplitudes into the standard range.

[0160] Specifically, the system first divides the signal amplitudes into multiple intervals according to the distribution characteristics of the quantization parameters. For example, the signal range of 0 - 1V can be divided into three intervals: [0, 0.3V), [0.3, 0.7V), and [0.7V, 1V]. Then, for each interval, use the corresponding mapping function to map the signal values into the standard range of [0, 1]. In addition, to eliminate the sudden changes between different intervals, the system uses a smooth transition function at the interval boundaries for processing. Finally, perform normalization processing on the mapped signal to ensure the uniformity of the overall signal distribution, thereby obtaining a normalized signal. It should be noted that this way of piecewise mapping and normalization can effectively maintain the relative distribution characteristics of the signal and provide a good basis for subsequent non - linear mapping.

[0161] S1.4.2: Use probability density matching to perform non - linear mapping on the normalized signal to form the quantization signal.

[0162] Perform non - linear mapping on the normalized signal using the method of probability density matching.

[0163] First, the system establishes the cumulative distribution function of the signal according to the probability distribution characteristics of the normalized signal. Then, by comparing with the ideal uniform distribution of the target quantization levels, construct a non - linear mapping function.

[0164] Specifically, this mapping function adjusts the distribution density of the signal in different value ranges so that the finally quantized signal has a similar probability distribution at each quantization level.

[0165] Exemplarily, if it is found that the signals in a certain quantization interval are too dense, the mapping function will appropriately widen the numerical range of this interval; conversely, if the signals in an interval are too sparse, the numerical range of this interval will be appropriately compressed. In addition, the system will also dynamically adjust the non - linear characteristics of the mapping function according to different types of signal characteristics (such as periodic signals, mutation signals, etc.) to obtain the optimal quantization effect. For example, for periodic signals, a period compensation term can be introduced into the mapping function; for signals with mutations, the local linearity can be increased near the mutation points. Finally, through this adaptive non - linear mapping process, a quantization signal with uniform distribution characteristics is formed, effectively improving the accuracy and reliability of subsequent signal processing.

[0166] Among them, the mapping function makes the finally quantized signal have a similar probability distribution at each quantization level by adjusting the distribution density of the signal in different value ranges, including:

[0167] The core objective of the mapping function is to achieve the equalization of signal distribution. Its basic principle is to dynamically adjust the signal distribution density in different value ranges so that the finally quantized signal shows a uniform distribution characteristic at each quantization level. This adjustment process needs to consider multiple factors such as the statistical characteristics of the signal, the quantization accuracy requirements of the system, and the hardware resource constraints. In practical applications, the system first conducts a statistical analysis on the input signal to determine the distribution characteristics of the signal in different value ranges, and then designs corresponding mapping strategies based on these characteristics.

[0168] In the specific design of the mapping function, the system uses a piecewise mapping method for processing. For high-frequency digital signals, usually the entire signal range can be divided into multiple sub-intervals. Taking a signal with a full scale of 1V as an example, it can be divided into three main intervals: [0, 0.3V), [0.3V, 0.7V], and (0.7V, 1V]. Within each interval, the system will design a corresponding mapping function according to the signal distribution characteristics of that interval. For example, in the interval [0.3V, 0.7V] where the signal distribution is relatively dense, a smaller mapping step size, such as 0.01V, is used; while in the two end intervals where the signal distribution is relatively sparse, a larger mapping step size, such as 0.05V, can be used.

[0169] To ensure the smoothness and continuity of the mapping process, the system uses a transition function to process at the interval boundaries. These transition functions are usually constructed using cubic spline interpolation methods to ensure that the function values and derivatives are continuous at the interval connections. Specifically, the system sets a transition region within ±5% of each interval boundary, and within these regions, the slope of the mapping function is adjusted to achieve a smooth transition. This processing method can effectively avoid sudden changes during the quantization process and improve the quality of the signal.

[0170] In terms of the dynamic adjustment mechanism, the system implements feedback-based adaptive control. By real-time monitoring the probability distribution of the quantized signal, the system can dynamically evaluate the effect of the current mapping function. When it detects that there are obvious deviations in the probability distribution at certain quantization levels (for example, the probability of a certain level exceeds 1.5 times the average value), the system will automatically adjust the mapping parameters of the corresponding interval. This adjustment process is usually completed within 100 clock cycles to ensure that the system can quickly respond to changes in signal characteristics.

[0171] The actual application effect shows that this mapping method can significantly improve the distribution uniformity of the signal. Taking the data transmission of 10Gbps as an example, after applying this mapping function, the probability distribution difference at different quantization levels is reduced from the original maximum of 3:1 to within 1.2:1. At the same time, the dynamic performance of the system is also guaranteed. In the case of signal mutation, the mapping function can complete the adjustment within 200ps to ensure the real-time response ability of the system.

[0172] In terms of resource optimization, the system realizes the mapping function by combining a look-up table with linear interpolation. By optimizing the distribution density of the look-up table, the system achieves a balance between resource occupancy and accuracy. Specifically, a denser look-up table point interval (such as 0.005V) is adopted in the area where the signal changes violently, while a sparser point interval (such as 0.02V) is used in the area where the signal changes gently. This differential storage strategy enables the system to control the size of the look-up table within 60% of the original implementation while ensuring accuracy.

[0173] Through this carefully designed mapping function, the system has successfully achieved the equalization of signal distribution, providing a good foundation for subsequent quantization processing. Actual tests show that this method not only improves the quantization uniformity but also enhances the overall performance of the system, including reducing the quantization error (the average error is reduced by 40%), increasing the dynamic range of the signal (increased by 25%), and improving the resource utilization efficiency of the system (saving 35% of the storage resources). These advantages make this method have broad application prospects in the field of high-speed digital signal processing.

[0174] S2: Adopt stress-aware fast reading and recycling to process the quantization signal to form a recovery signal.

[0175] As Figure 3 shown, step S2 specifically includes:

[0176] S2.1: Output a stress feature matrix by performing stress modeling and analysis on the quantization signal.

[0177] First, it is necessary to obtain the stress state parameters of the system, including key parameters such as power supply voltage fluctuation, temperature change, and signal load. Then, establish a stress modeling and analysis system, which adopts a multi-dimensional modeling method to map various stress parameters into a unified feature space.

[0178] Specifically, the system analyzes the impact of temperature changes on signal transmission characteristics by establishing a thermal-electric coupling model. Meanwhile, a load stress model is constructed to evaluate the signal integrity performance under different load conditions. In addition, the system also needs to consider the impact of power supply noise on the system and establish a power supply stress model. Finally, these analysis results are integrated to output a characteristic matrix containing the influence of various stress factors. Exemplarily, when the system operates under the conditions of a temperature of 75°C, a power supply ripple of 100 mV, and a load capacitance of 10 pF, the system can accurately model the comprehensive impact of these parameters on signal transmission.

[0179] The primary task of stress modeling analysis is to establish a complete stress feature extraction framework. This framework mainly considers three key stress factors: temperature stress, power supply stress, and load stress. In practical applications, the system first collects temperature data at each key point of the chip through a distributed temperature sensor network. These sensors are usually evenly distributed on the signal transmission path at intervals of 100 μm. Meanwhile, the system also collects the fluctuations of the power supply voltage in real-time through a power supply monitoring unit and obtains the change characteristics of the output load through a load detection circuit. These raw data constitute the basic input for stress modeling.

[0180] In terms of temperature stress modeling, the system adopts a thermal-electric coupling analysis method.

[0181] Specifically, a heat conduction model is first established. This model divides the chip into multiple tiny units (typical size: 10 μm × 10 μm), and calculates the heat transfer process between these units through the finite element method. For example, when the temperature of a certain unit rises to 85°C, the system will evaluate the impact of this temperature change on the surrounding units and calculate the resulting change in signal transmission characteristics. In particular, for high-speed signals (such as 10 Gbps), a temperature increase may cause the transmission delay to increase by 15 - 20 ps, and these impacts will be accurately quantified and recorded in the stress characteristic matrix.

[0182] The modeling process of power supply stress focuses on the impact of power supply noise on signal integrity. The system establishes a detailed power supply distribution network model, which includes the parasitic resistance and inductance effects of the power supply traces. Through this model, the system can evaluate the impact of power supply ripple (typical value: 50 - 100 mV) and ground bounce noise on signal quality. At the same time, considering the transient response characteristics during high-speed switching, the system also establishes a dynamic power consumption model to predict the power supply fluctuations under different data patterns.

[0183] Load stress analysis mainly considers the impact of the output load on signal transmission. The system analyzes the signal response characteristics under different load conditions (such as the input capacitance varying in the range of 5 - 15 pF) by establishing an accurate equivalent circuit model. This model pays particular attention to impedance matching issues because impedance mismatch may cause severe signal reflection and distortion during high-speed transmission. All these analysis results are organized into a standardized stress characteristic matrix, and each element of the matrix contains stress parameters under specific conditions.

[0184] S2.2: Design a fast reading strategy for the stress characteristic matrix to generate a reading timing sequence.

[0185] After obtaining the stress characteristic matrix, it is first necessary to design an adaptive fast reading strategy.

[0186] Specifically, the system dynamically adjusts the timing parameters of signal sampling according to the parameters in the stress characteristic matrix. Then, through a timing optimization algorithm, the optimal sampling moment and sampling window width are determined to avoid the time interval with the greatest stress impact. In addition, the system also designs a buffering strategy, adopting a more conservative reading method in the high-stress interval and a more aggressive reading method in the low-stress interval. It should be noted that the system can dynamically adjust the sampling timing according to the actual situation. For example, when it detects that the signal delay increases due to a temperature rise, it automatically shifts the sampling moment backward, sets the sampling window at 0.2 ns after the clock rising edge, and adjusts the sampling window width to 0.1 ns to ensure the accuracy of sampling.

[0187] Based on the obtained stress characteristic matrix, the system further designs a fast reading strategy. The core of this strategy is to establish an adaptive timing control mechanism to dynamically adjust the reading timing according to different stress conditions. Specifically, the system first divides the stress characteristic matrix into multiple sub-regions, and each region corresponds to a specific stress combination. For example, when the temperature is in the range of 75 - 85 °C, the power supply ripple is within 80 mV, and the load capacitance is 10 pF, the system will select the corresponding optimal reading timing parameters.

[0188] In the specific design of the reading timing, the system adopts a predictive compensation mechanism. By analyzing the trend information in the stress characteristic matrix, the system can predict the signal behavior under specific stress conditions and adjust the sampling moment in advance. For example, when it detects a rapid temperature rise, the system will appropriately delay the sampling moment (typical value is 5 - 10 ps) to compensate for the increased signal delay caused by the temperature rise. This predictive compensation can significantly improve the system's response speed and usually complete the timing adjustment within one clock cycle.

[0189] To ensure the reliability of the reading strategy, the system also implements a multi-level protection mechanism. Under normal working conditions, the system uses optimized timing parameters for data reading; but when an abnormal stress condition is detected (such as the temperature suddenly exceeding 90°C), the system will immediately switch to the conservative mode, increasing the setup time margin to ensure the reliability of data reading. This adaptive protection mechanism can effectively balance the performance and reliability requirements of the system.

[0190] The actual application effect shows that this stress-aware fast reading strategy can significantly improve the reliability of the system. In typical application scenarios, the bit error rate (BER) of the system can be maintained below 10^-12. Even in the case of large stress fluctuations (such as a temperature change of ±20°C and a power supply ripple reaching 100 mV), the system can still maintain stable performance. At the same time, the additional power consumption overhead of this method is small, usually only increasing the system power consumption by 5-8%, which is completely acceptable in high-speed digital systems.

[0191] S2.3: According to the reading timing, perform sampling and recovery modeling through the quantization signal to obtain a signal recovery model.

[0192] Execute the signal sampling process according to the reading timing. Secondly, establish a signal recovery modeling system, which includes a signal feature extraction module and a recovery strategy generation module. Specifically, the feature extraction module performs time-domain and frequency-domain analysis on the sampled signal to extract the key feature parameters of the signal; the recovery strategy generation module constructs an adaptive signal recovery algorithm based on these features. In addition, the system also considers the influence of sampling noise and establishes a noise suppression model. Finally, integrate these models and output a complete signal recovery model. In summary, this step provides a reliable basis for subsequent signal recovery through a systematic modeling process.

[0193] In addition, the core goal of the signal recovery model is to achieve efficient and accurate signal reconstruction. This model mainly includes three key components: signal feature extraction, distortion compensation, and reconstruction optimization. In practical applications, the system first establishes an accurate model of the signal transmission channel, including the frequency response characteristics of the transmission line, crosstalk effects, and reflections caused by impedance mismatches. For example, in a 10Gbps high-speed transmission system, a typical transmission channel will cause a signal attenuation of 20-30% and introduce a frequency-dependent loss of 2-3 dB.

[0194] In the signal feature extraction stage, the system uses adaptive sampling technology for processing.

[0195] Specifically, the system sets multiple sampling points (usually 8 - 16) within each bit period, and the timing intervals of these sampling points are dynamically adjusted according to the rise / fall time of the signal. Taking a signal with a 2ns bit width as an example, the system uses a relatively dense sampling interval (such as 20ps) in the signal transition region (about 20% of the bit width), while the sampling interval can be appropriately increased in the signal steady region (such as 50ps). This differential sampling strategy not only ensures the capture of key features but also optimizes the use of system resources.

[0196] For the distortion compensation section, the system implements a predictive compensation mechanism based on historical data. This mechanism analyzes the signal characteristics of consecutive multiple bit periods to establish a pattern library of signal distortion. For example, when a specific bit sequence (such as the "1010" pattern) is detected, the system predicts the possible inter-symbol interference effect and prepares the corresponding compensation parameters in advance. Typical compensation parameters include: amplitude compensation factor (range 0.8 - 1.2), phase compensation amount (range ±15ps), and equalizer coefficients (3 - 5 orders).

[0197] The reconstruction optimization stage is processed using an iterative optimization algorithm. The system first constructs a rough profile of the signal based on the initial sampling data, and then gradually optimizes the reconstruction result through the least mean square error criterion. In each iteration, the system evaluates the error between the reconstructed signal and the ideal waveform and adjusts the reconstruction parameters accordingly. Specifically, the optimization accuracy in the amplitude direction is usually controlled within 1% of the full scale, and the optimization accuracy in the timing direction is controlled within 5% of the unit interval.

[0198] In response to the special requirements of high-speed digital signals, the system also implements an adaptive threshold adjustment mechanism. This mechanism dynamically optimizes the decision threshold by real-time monitoring the eye diagram characteristics of the signal. For example, when it is detected that the eye opening degree drops below a preset threshold (usually 60%), the system automatically adjusts the sampling moment and the decision threshold to maintain reliable signal decision. Typically, the range of threshold adjustment is ±15% of the nominal value, and the adjustment step is 1%.

[0199] To handle complex noise environments, the system adopts a multi-stage filtering strategy. The first stage uses an analog band-pass filter to suppress out-of-band noise, and the bandwidth range is usually set to 0.75 times the signal rate; the second stage uses a digital equalizer to compensate for channel losses, and the equalizer generally adopts a 5th-order FIR structure; the third stage improves the noise resistance of the signal through the maximum likelihood detection algorithm. This multi-stage processing strategy can increase the signal-to-noise ratio of the signal by 15 - 20dB.

[0200] In terms of actual application effects, the signal recovery model exhibits excellent performance. Taking a 10Gbps transmission system as an example, at a transmission distance of 1 meter on a printed circuit board, the system can increase the original eye opening of 30% to more than 85%, reduce inter-symbol interference by 40%, and control the peak-to-peak jitter within 0.2UI. At the same time, the implementation complexity of this model is relatively low, occupying only about 8% of the logic resources and 12% of the DSP resources on a typical FPGA platform.

[0201] Particularly noteworthy is that the model also has good scalability. By adjusting the sampling parameters and compensation algorithms, the system can adapt to different transmission rates (from 5Gbps to 25Gbps) and different transmission media (including PCB traces, coaxial cables, and differential pairs, etc.). This flexibility enables the model to be widely applied in various high-speed digital systems, providing strong support for ensuring signal integrity.

[0202] S2.4: Use the signal recovery model to perform signal recovery and reconstruction processing on the quantized signal to generate the recovered signal.

[0203] For step S2.4, based on the established signal recovery model, first start the signal recovery processing unit, which uses an adaptive algorithm to preliminarily recover the sampled signal. Then, perform fine processing through the signal reconstruction module, which combines stress characteristic information to optimize and reconstruct the timing characteristics and amplitude characteristics of the signal.

[0204] Specifically, the system will adopt corresponding compensation strategies to correct the signal according to the signal distortion characteristics under different stress conditions.

[0205] Exemplarily, when the system detects a 15% overshoot in the signal in the continuous 1010 pattern, the overshoot can be controlled within 5% by adjusting the equalizer parameters, while ensuring that the eye opening meets the specification requirements. It should be noted that the system can restore a signal that was originally distorted by stress (such as a 50% increase in the rise time) to a state close to the ideal state (such as only a 10% increase in the rise time). In addition, the system will continuously monitor various indicators of the signal to ensure the stability of the optimization effect. Finally, output a high-quality signal that has been recovered and reconstructed.

[0206] Among them, step S2.1 specifically includes:

[0207] S2.1.1: Based on the pre-established thermal-electrical coupling modeling, analyze the influence of temperature change on the quantized signal to form temperature stress characteristics.

[0208] Establish a thermal-electrical coupling model, which includes two core parts: temperature distribution modeling and electrical characteristic response analysis.

[0209] Specifically, for temperature distribution modeling, the finite element analysis method is adopted. The PCB board and the signal transmission path are divided into multiple tiny units, and the temperature distribution of each unit is accurately calculated. Then, based on the temperature data of each unit, a temperature gradient field is constructed to analyze the heat propagation law in the system.

[0210] In addition, the system also establishes a dynamic temperature response model to predict the transient impact of temperature changes on signal transmission characteristics.

[0211] For example, when the system temperature rises from the standard operating temperature of 25°C to 75°C, the model can accurately calculate the temperature distribution at each point on the signal transmission path and evaluate the impacts such as the increase in signal delay and impedance change caused by the temperature change.

[0212] It should be noted that the system dynamically updates the temperature stress characteristics by real-time monitoring the temperature data of key points to ensure the accuracy and real-time nature of the model.

[0213] S2.1.2: According to the described temperature stress characteristics, load stress and power supply noise analysis are adopted to obtain the stress characteristic matrix.

[0214] Based on the obtained temperature stress characteristics, the impacts of load stress and power supply noise are further analyzed. First, the system establishes a load stress analysis model, which considers various loads on the signal transmission path, including input capacitance, parasitic capacitance, termination matching resistors, etc.

[0215] Specifically, the system calculates the signal reflection, crosstalk, and attenuation characteristics under different load conditions by establishing an equivalent circuit model. Then, the system analyzes the impact of power supply noise, focusing on factors such as power supply ripple, ground bounce noise, and switching noise. In addition, the system also establishes a comprehensive stress assessment mechanism, which integrates the impacts of temperature stress, load stress, and power supply noise through weight allocation. Exemplarily, when the system detects that the power supply ripple reaches 100 mV and the load capacitance is 10 pF, the model can calculate the coupling effect of these factors with temperature changes, such as evaluating the amplitude amplification effect of the power supply ripple at high temperatures, or the impedance mismatch caused by the change of the load capacitance with temperature. Finally, the system outputs a complete stress characteristic matrix, which contains the influence degree and interaction relationship of various stress factors, providing comprehensive stress characteristic information for subsequent signal processing.

[0216] Among them, step S2.4 specifically includes:

[0217] S2.4.1: According to the signal recovery model, an adaptive algorithm is applied to preliminarily recover the quantized signal to generate a preliminary recovery signal.

[0218] Based on the signal recovery model, an adaptive algorithm is implemented to preliminarily recover the quantized signal. First, the system constructs an adaptive filter bank, including a feedforward equalizer and a decision feedback equalizer, to compensate for various distortions introduced by the channel.

[0219] Specifically, the feedforward equalizer pre-compensates the frequency response of the signal by adjusting the tap coefficients; the decision feedback equalizer eliminates inter-symbol interference using the recovered signal symbols. Then, the system adopts the least mean square error criterion to dynamically update the equalizer parameters. In addition, the system also introduces an adaptive step size control mechanism, using a larger step size during rapid signal changes to accelerate the convergence speed, and a smaller step size in the steady state to improve accuracy.

[0220] It should be noted that the system automatically adjusts the algorithm parameters according to the signal characteristics under different data patterns, such as continuous 1010 patterns or long periods of the same level, etc. For example, when a 15% overshoot is detected in the signal, the system will promptly adjust the equalizer parameters to achieve fast response and precise compensation. Finally, through this adaptive recovery process, the preliminarily recovered signal is output.

[0221] S2.4.2: Perform stress compensation optimization on the preliminarily recovered signal to generate the recovered signal.

[0222] Perform stress compensation optimization processing on the preliminarily recovered signal.

[0223] First, the system establishes a stress compensation model, which is based on the stress characteristic matrix obtained previously and designs corresponding compensation strategies for different types of stress effects.

[0224] Specifically, for the influence caused by temperature stress, the system compensates by adjusting the timing parameters of the signal, such as automatically adjusting the sampling moment according to temperature changes; for the influence of load stress, it is optimized through impedance matching and pre-emphasis techniques. Second, the system adopts a hierarchical compensation strategy, first performing a large-scale compensation for the main stress effects and then making fine adjustments for the secondary effects. In addition, the system also establishes a compensation effect evaluation mechanism, which monitors key indicators such as eye diagram opening, jitter, and signal integrity, and evaluates the compensation effect in real time and performs dynamic optimization. Exemplarily, when the operating temperature of the system increases and the signal delay increases by 50%, through temperature compensation and timing optimization, the increase in delay can be controlled within 10%; when the load conditions change and signal reflection occurs, the pre-emphasis technique can effectively suppress the influence of the reflected wave. In summary, through this multi-dimensional stress compensation optimization, a high-quality recovered signal is finally output.

[0225] S3: Obtain a highly reliable transmission signal by performing transaction-level hierarchical structure verification and optimization processing on the recovered signal.

[0226] Such asFigure 4 As shown, step S3 specifically includes:

[0227] S3.1: Analyze the restoration signal using the transaction-level hierarchy and output a functional coverage metric.

[0228] Establish a transaction-level hierarchy analysis framework and divide signal verification into multiple levels: bottom-level signal characteristic verification, middle-level protocol consistency verification, and top-level functional integrity verification.

[0229] Specifically, bottom-level verification mainly focuses on the basic characteristics of the signal, such as timing parameters, amplitude characteristics, and jitter metrics, etc.; middle-level verification focuses on checking whether the signal transmission conforms to the preset protocol specifications, including the timing relationship of handshake signals, the format requirements of data packets, etc.; top-level verification evaluates the integrity of the signal at the functional level to ensure the correctness and reliability of data transmission.

[0230] In addition, the system also establishes a coverage statistics model, which calculates and updates the coverage metric in real time by hierarchically recording the coverage of each verification item.

[0231] Exemplarily, when the system is at a data transmission rate of 10 Gbps, the model can identify that the coverage of some complex data patterns is only 85%, thus providing a clear optimization direction for subsequent verification.

[0232] Bottom-level signal characteristic verification mainly focuses on the basic electrical characteristics of the signal, including timing characteristics, level characteristics, and integrity characteristics, etc.

[0233] In the specific implementation process, the system adopts a hierarchical testing strategy. First, verify the timing characteristics of the signal, including key parameters such as setup time, hold time, and propagation delay. For example, in a 10 Gbps transmission system, the typical setup time requirement is 50 ps, and the hold time requirement is 30 ps. The system uses a high-precision oscilloscope (bandwidth not less than 40 GHz) to collect the signal waveform and analyze whether these timing parameters meet the design specifications.

[0234] In terms of level characteristic verification, the system focuses on the amplitude, swing, and noise characteristics of the signal. Specific verification metrics include: high level (VOH), low level (VOL), signal swing, and common-mode voltage, etc. For example, for differential signals, the system will verify the differential swing (usually required to be 800 mV ± 10%) and the common-mode level (usually required to be within the range of 0.9 V ± 5%). At the same time, the noise tolerance of the signal also needs to be evaluated to ensure that under the maximum noise interference (usually 15% of the signal swing), the system can still correctly identify the signal level.

[0235] Signal integrity verification includes eye diagram analysis, jitter analysis, crosstalk analysis, etc. The system constructs a statistical eye diagram by collecting data of no less than 1 million symbols in real time. In eye diagram analysis, the following parameters are mainly verified: eye opening degree (required ≥ 65%), eye height (required ≥ 400 mV), jitter characteristics (periodic jitter ≤ 0.1 UI, random jitter RMS value ≤ 2 ps). For crosstalk analysis, the system evaluates the coupling effect between the nearest neighbor signals, and requires the near-end crosstalk (NEXT) to be controlled below -20 dB.

[0236] The middle-layer protocol consistency verification mainly focuses on the correct execution of the data transmission protocol. The system first establishes a complete protocol state machine model, which contains all possible protocol states and state transitions. For example, for the transmission protocol based on 8b / 10b coding, the system needs to verify the correctness of the coding rules, including: the recognition accuracy of running codes (K codes), code distance control, DC balance maintenance, etc. Specifically, the system will generate a test sequence containing all possible coding combinations to verify the correctness of the encoding and decoding processes.

[0237] In terms of protocol handshake and flow control, the system verifies the timing relationship of various control signals. For example, in a full-duplex communication system, it is necessary to verify whether the handshake signals (such as Ready, Valid signals) between the transmitter and the receiver meet the timing requirements specified by the protocol. The system usually uses a protocol analyzer to capture the complete handshake process and analyze the relative relationship and timing margin between the signals. For the handling of abnormal situations, the system also needs to verify the correctness of the timeout mechanism and the retransmission mechanism.

[0238] The top-layer function integrity verification focuses on the end-to-end function implementation of the entire system. This layer of verification uses a scenario-based testing method to verify the system functions by constructing various actual application scenarios. For example, in a data transmission system, the following test scenarios will be designed: continuous large-volume data transmission (testing the stability of the system), burst data transmission (testing the dynamic response ability of the system), error injection testing (verifying the fault tolerance ability of the system), etc. Each scenario needs to define clear acceptance criteria, such as transmission success rate ≥ 99.999%, error recovery time ≤ 100 μs, etc.

[0239] In the specific implementation of function verification, the system adopts a hierarchical coverage analysis method. First is the function coverage to ensure that all function modules are fully tested; second is the code coverage, requiring the statement coverage to reach 100% and the branch coverage to reach over 95%; finally is the scenario coverage to ensure that all possible usage scenarios are verified. The system uses a dedicated coverage collection tool to monitor the integrity of the verification in real time.

[0240] For complex verification requirements, the system also establishes an automated verification platform. This platform can automatically generate test vectors, execute test cases, and collect test results.

[0241] For example, in protocol compliance verification, the platform can automatically generate test sequences containing various boundary conditions and quickly execute these tests through a hardware accelerator (such as an FPGA). The test results will be automatically compared with the expected results to generate a detailed verification report.

[0242] In practical applications, this multi-level verification method significantly improves the reliability of the system. Statistical data shows that after adopting this verification method, the early fault detection rate of the system has increased by 80%, and the on-site failure rate of the final product has decreased by 90%. At the same time, due to the high degree of automation in the verification process, the entire verification cycle has been shortened by 40% compared with traditional methods, and the verification cost has been reduced by 35%. These advantages have enabled this verification method to be widely used in the development of high-speed digital systems.

[0243] S3.2: Obtain a verification strategy by performing deductive formal verification design on the functional coverage metrics.

[0244] Based on the functional coverage metrics, construct a deductive formal verification system. First, this system transforms the verification requirements into an executable set of verification rules through formal methods. Then, for the function points with low coverage, the system automatically generates targeted verification cases, such as designing specialized test sequences for high-speed switching scenarios and boundary conditions of the same level for a long time.

[0245] Specifically, the system adopts a top-down verification strategy design method to ensure the systematicness and integrity of the verification. In addition, the verification system will also formulate differentiated verification depth requirements according to the importance of different functions, and adopt more stringent verification standards for key function points. It should be noted that the system ensures the correctness of the verification rules through formal proof methods to avoid missing key verification scenarios.

[0246] S3.3: Apply the verification strategy to generate verification results through verification execution and data collection.

[0247] Start the automated verification process according to the verification strategy. This process includes three main links: test case execution, result collection, and data analysis.

[0248] First, various verification test cases are executed through an automated testing platform to monitor key metrics during the verification process in real time. Secondly, the system comprehensively collects data during the verification process, including various performance parameters of the signal, such as signal integrity metrics, timing margins, power consumption, etc., while recording the handling results of abnormal situations and boundary conditions. In addition, the system also uses data visualization technology to generate intuitive analysis results such as trend charts and distribution charts. For example, through automated testing, it may be found that in the continuous 1010 pattern, the signal will have a 15% overshoot, and all these data will be detailedly recorded for subsequent optimization.

[0249] S3.4: Perform signal optimization processing on the verification results to form the highly reliable transmission signal.

[0250] Establish a signal optimization processing module, which includes a problem analysis unit and an optimization execution unit.

[0251] First, the problem analysis unit classifies and grades various problems found during the verification process to determine the priority order of optimization.

[0252] Then, the system adopts corresponding optimization strategies for different types of problems: for timing problems, it is optimized by adjusting clock parameters and jitter compensation; for signal integrity problems, it is improved by adjusting equalizer parameters and pre-emphasis technology.

[0253] Specifically, the system will monitor various metrics during the optimization process in real time to ensure that the optimization effect reaches the expected goal.

[0254] Exemplarily, by adjusting the equalizer parameters, the signal overshoot can be controlled within 5% from 15%, while ensuring that the eye diagram opening meets the specification requirements. In addition, the system has also established a long-term tracking mechanism for the optimization effect to continuously evaluate the stability of the signal quality. Finally, through this systematic optimization processing, a highly reliable transmission signal is output.

[0255] Among them, step S3.1 specifically includes:

[0256] S3.1.1: Perform underlying signal characteristic verification and middle-layer protocol consistency verification on the restored signal to generate the first verification data.

[0257] The system first conducts underlying signal characteristic verification.

[0258] Specifically, the underlying verification mainly includes three aspects: timing characteristic verification, electrical characteristic verification, and signal integrity verification. The timing characteristic verification focuses on checking key parameters such as the setup time, hold time, and transmission delay of signals. For example, it verifies whether the setup time of a signal meets the design requirement of 100 ps at a transmission rate of 10 Gbps. The electrical characteristic verification mainly focuses on parameters such as the voltage swing, threshold level, and input / output impedance of signals. For example, it verifies whether the signal swing is maintained within the standard range. The signal integrity verification checks characteristics such as signal overshoot, undershoot, ringing, and crosstalk.

[0259] Then, the system conducts middle-layer protocol consistency verification, which mainly includes: protocol timing verification, data format verification, and state transition verification. Among them, the protocol timing verification ensures that the timing relationships of various control signals and data signals conform to the protocol specifications. The data format verification checks the structural integrity of data frames. The state transition verification ensures that the switching of the system between different working states meets expectations. In addition, the system has also established an anomaly detection mechanism for capturing and recording anomaly phenomena during the verification process.

[0260] Finally, the results of the underlying and middle-layer verifications are integrated to generate the first verification data containing various parameters and indicators.

[0261] S3.1.2: Conduct top-layer functional integrity verification on the first verification data to obtain the functional coverage rate indicator.

[0262] Based on the first verification data, conduct top-layer functional integrity verification. First, the system establishes a functional integrity evaluation model, which analyzes from three dimensions: the correctness of data transmission, the stability of the system, and performance indicators.

[0263] Specifically, the verification of the correctness of data transmission mainly focuses on end-to-end data consistency, which is verified by sending specific test sequences and comparing the received data. The verification of system stability focuses on checking the system's performance under extreme conditions such as long-term operation and rapid data switching. The verification of performance indicators evaluates key performance indicators such as the throughput, latency, and bit error rate of the system.

[0264] In addition, the system has also established a hierarchical coverage rate statistical mechanism, which comprehensively evaluates the coverage of each layer of verification through weight assignment.

[0265] Exemplarily, the system may assign a higher weight to key function points such as high-speed data transmission scenarios and a lower weight to non-critical functions such as transmissions in low-speed modes. It should be noted that the system dynamically updates the coverage rate calculation method through an adaptive adjustment mechanism to ensure that the coverage rate indicator can accurately reflect the verification status of the system. Finally, based on the complete verification data, the system outputs a comprehensive functional coverage rate indicator, providing a basis for subsequent verification strategy design.

[0266] Among them, step S3.4 specifically includes:

[0267] S3.4.1: Classify and grade the verification results using timing parameters and signal integrity parameters to generate an optimization strategy.

[0268] Establish a classification and grading framework, which includes three core modules: problem feature extraction, impact assessment, and priority ranking.

[0269] Specifically, the problem feature extraction module classifies the anomalies in the verification results, mainly divided into timing problems and signal integrity problems. Timing problems include clock jitter exceeding the standard, transmission delay offset, setup and hold time violations, etc.; signal integrity problems include signal overshoot and undershoot, crosstalk interference, impedance mismatch, etc. Then, the system analyzes the impact degree of various problems on the system performance through the impact assessment module.

[0270] For example, when it is detected that the jitter of a certain data channel exceeds 80% of the design margin, the system will mark it as a high-priority problem; while for minor crosstalk that only affects signal quality but does not cause bit errors, it will be marked as a low-priority problem.

[0271] In addition, the system also establishes a dynamic priority adjustment mechanism to update the priority of problems in real time according to the occurrence frequency of problems and the system operating status. Finally, based on the complete problem analysis, the system outputs an optimization strategy with clear priorities.

[0272] S3.4.2: Adjust and optimize the timing parameters and signal integrity parameters according to the optimization strategy to form the high-reliability transmission signal.

[0273] Based on the optimization strategy, perform parameter adjustment and optimization processing. First, the system constructs a parameter optimization model, which includes a timing parameter optimization unit and a signal integrity parameter optimization unit.

[0274] The optimization of timing parameters focuses on aspects such as clock setting, delay compensation, and jitter control. For example, optimize the clock quality by adjusting the multiplication factor and phase compensation parameters of the PLL; when it is found that the jitter of a certain data channel exceeds the standard, the system will automatically adjust the pre-emphasis level and tap coefficients of the equalizer to effectively suppress the jitter.

[0275] Secondly, the optimization of signal integrity parameters focuses on improving the signal waveform, including impedance matching optimization, crosstalk suppression, and equalizer parameter adjustment, etc.

[0276] Specifically, when a signal reflection causes an overshoot of 15%, the system controls the overshoot within 5% by adjusting the resistance value of the terminal matching network and the compensation coefficient of the equalizer. In addition, the system has established an optimization effect evaluation mechanism to ensure that the optimized signal quality meets the system requirements by real-time monitoring of key indicators such as eye opening and bit error rate. It should be noted that the system adopts an iterative optimization strategy, evaluating the optimization effect after each parameter adjustment and deciding whether to perform the next round of optimization based on the evaluation results. Finally, through this systematic parameter optimization process, a stable and reliable high-speed signal transmission system is output.

[0277] Taking the intelligent verification of a high-speed serial data transmission system as a specific example:

[0278] Step 3.1 (Basic data collection) First, a complete data collection framework is established. In this example, the main data collected by the system includes: signal waveform data, protocol status data, and system operation data. Specifically, a high-speed oscilloscope with a 40 GHz bandwidth is used to collect signal waveforms at a sampling rate of 40 GSa / s; at the same time, a protocol analyzer is used to collect 8b / 10b encoded protocol data streams; system operation data is obtained through built-in performance counters. For example, at a transmission rate of 10 Gbps, the system collects 400 MB of waveform data, 2 MB of protocol status data, and 500 KB of system operation parameters per second.

[0279] Step 3.2 (Feature extraction and analysis) Feature extraction is performed on the collected raw data. In terms of waveform data, the system extracts the following key features: signal rise time (typical value 35 ps), fall time (typical value 40 ps), overshoot amount (required ≤ 15%), eye diagram parameters (opening, height, width), etc. For protocol data, information such as code pattern distribution characteristics, running code usage frequency, and discontinuous transmission mode is extracted. System operation data focuses on features such as resource utilization rate, power consumption change, and temperature distribution. These feature data are organized into standardized feature vectors for subsequent analysis.

[0280] Step 3.3 (Intelligent classification processing) A multi-layer neural network is used for data classification. The network includes an input layer (128 nodes, corresponding to the extracted features), two hidden layers (64 and 32 nodes respectively), and an output layer (16 nodes, corresponding to different system states). The network is trained with a large amount of historical data and can accurately identify the working state of the system. For example, when it is detected that the eye opening of the signal drops below 70% and at the same time the bit error rate in the protocol data rises to the 10^-9 level, the system will classify it as the "channel quality degradation" state.

[0281] In specific implementations, the classification algorithm adopts a weighted voting mechanism. The system assigns different weights to different features. For example, the weight of the eye diagram parameter is 0.4, the weight of the protocol state parameter is 0.3, and the weight of the system operation parameter is 0.3. Through this weighted method, the system can more accurately judge the current state. In practical applications, the accuracy rate of this classification algorithm reaches more than 95%, and the recognition sensitivity for abnormal states exceeds 90%.

[0282] Step 3.4 (Adaptive Optimization Strategy) Based on the classification result, the system implements corresponding optimization strategies. Taking the "channel quality degradation" state as an example, the system will initiate a three-level optimization strategy: First, adjust the equalizer parameters and increase the high-frequency compensation (typical value: +3dB@5GHz); Second, appropriately increase the signal swing (increase by 10%); Finally, if the signal quality cannot be effectively improved by the first two steps, reduce the transmission rate to 8Gbps and simultaneously initiate the error correction coding mechanism.

[0283] During the execution of the optimization strategy, the system adopts a progressive adjustment method. The step size of each parameter adjustment is strictly controlled. For example, the equalizer parameters are adjusted by no more than 0.5dB each time, and the signal swing is adjusted by no more than 5% each time. After each adjustment, the system will wait for at least 1000 symbol times to evaluate the adjustment effect. If the expected effect cannot be achieved after three consecutive adjustments, the system will switch to the next-level optimization strategy.

[0284] To verify the optimization effect, the system has established a complete evaluation system. The main evaluation indicators include: signal quality improvement degree (required to increase the eye diagram opening degree by ≥20%), system stability (error-free operation for 24 consecutive hours), resource overhead (increase in additional power consumption ≤10%), etc. Practical application data shows that this optimization strategy can successfully restore the system performance in 90% of cases, and the average recovery time is less than 1ms.

[0285] It is particularly worth noting that the system has also established a self-learning mechanism for the optimization strategy. By recording the process and effect of each optimization, the system continuously updates and improves the optimization strategy library. For example, if it is found that a certain parameter combination has particularly good effects under specific conditions, the system will increase the usage priority of this combination in similar situations. This self-learning mechanism enables the optimization effect of the system to continuously improve with the increase in operation time.

[0286] The actual application effect shows that this optimization method based on intelligent verification significantly improves the reliability of the system. During the six-month on-site test, the mean time between failures (MTBF) of the system increased by 200% and reached more than 50000 hours; the dynamic adaptation ability of the system was significantly enhanced, and it could automatically recover to the normal working state in 95% of abnormal situations; at the same time, the maintenance cost was reduced by 60%. These advantages have enabled this method to be widely applied in high-speed digital systems.

[0287] As Figure 5 shown, an embodiment of the present application further provides a high-frequency digital information transmission device, including:

[0288] A histogram equalization quantization processing module, configured to perform histogram equalization quantization processing on a high-frequency digital signal via a logic-gated residual neural network to generate a quantization signal;

[0289] A stress sensing processing module, which uses fast reading and recycling of stress sensing to process the quantization signal to form a recovery signal;

[0290] A verification and optimization processing module, configured to obtain a highly reliable transmission signal by performing transaction-level hierarchical structure verification and optimization processing on the recovery signal.

Claims

1. A high-frequency digital signal transmission method, characterized in that: include: Through the logic gated residual neural network, the high-frequency digital signal is subjected to histogram equalization quantization processing to generate a quantized signal; The quantized signal is processed to form a recovery signal by using stress-aware fast reading and recovery; By performing transaction level hierarchy verification and optimization processing on the recovery signal, a high reliability transmission signal is obtained.

2. The method according to claim 1, characterized in that The method of performing histogram equalization quantization processing on the high-frequency digital signal through the logic-gated residual neural network to generate a quantized signal includes: Using a logic gating mechanism, extracting features from the high-frequency digital signal and outputting initial signal features; Using a residual neural network model, the initial signal characteristics are analyzed to generate a signal histogram distribution; Applying an adaptive threshold algorithm to design the signal histogram distribution to form a quantization parameter; The quantized signal is generated by performing balanced quantization processing on the quantization parameter.

3. The method according to claim 2, characterized in that The generating the quantized signal by performing balanced quantization processing on the quantization parameter comprises: According to the quantization parameter, the amplitude of the signal histogram distribution is mapped into a standard range, and normalized to obtain a normalized signal; Probability density matching is adopted to perform nonlinear mapping on the normalized signal to form the quantized signal.

4. The method according to claim 1, characterized in that: The method of using stress-aware fast reading and recycling to process the quantized signal to form a recovery signal includes: Outputting a stress characteristic matrix by performing stress modeling analysis on the quantized signal; Designing a fast reading strategy for the stress characteristic matrix to generate a reading timing; According to the read timing, sampling and recovery modeling are performed by the quantized signal to obtain a signal recovery model; The signal recovery model is used to perform signal recovery and reconstruction processing on the quantized signal to generate the recovered signal.

5. The method according to claim 4, characterized in that The step of performing stress modeling analysis on the quantized signal to output a stress characteristic moment includes: Based on the pre-established thermal-electric coupling modeling, the temperature change impact analysis is performed on the quantized signal to form a temperature stress characteristic; According to the temperature stress characteristics, load stress and power supply noise analysis are adopted to obtain the stress characteristic matrix.

6. The method according to claim 4, characterized in that The using the signal recovery model to perform signal recovery and reconstruction processing on the quantized signal to generate the recovered signal includes: According to the signal recovery model, an adaptive algorithm is applied to perform preliminary recovery on the quantized signal to generate a preliminary recovery signal; The preliminary recovery signal is subjected to stress compensation optimization to generate the recovery signal.

7. The method according to claim 1, characterized in that The method of obtaining a high-reliability transmission signal by performing transaction level hierarchy verification and optimization processing on the recovery signal includes: Analyzing the recovery signal using a transaction level hierarchy and outputting a functional coverage indicator; By performing deductive formal verification design on the functional coverage indicators, a verification strategy is obtained; Apply the verification strategy to generate verification results through verification execution and data collection; The verification result is subjected to signal optimization processing to form the high-reliability transmission signal.

8. The method according to claim 7, characterized in that The transaction level hierarchy is used to analyze the recovery signal and output functional coverage indicators, including: Performing bottom-layer signal characteristic verification and middle-layer protocol consistency verification on the recovery signal to generate first verification data; Perform top-level functional integrity verification on the first verification data to obtain the functional coverage index.

9. The method according to claim 7, characterized in that: The performing signal optimization processing on the verification result to form the high-reliability transmission signal includes: Using timing parameters and signal integrity parameters, classifying and grading the verification results to generate an optimization strategy; According to the optimization strategy, the timing parameters and signal integrity parameters are adjusted and optimized to form the high-reliability transmission signal.

10. A high-frequency digital information transmission device, characterized in that: include: A histogram equalization quantization processing module is used to perform histogram equalization quantization processing on high-frequency digital signals through a logic-gated residual neural network to generate a quantized signal; A stress sensing processing module processes the quantized signal using stress sensing fast reading and recovery to form a recovery signal; The verification and optimization processing module is used to obtain a high-reliability transmission signal by performing transaction level hierarchy verification and optimization processing on the recovery signal.

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