Chip verification method based on multi-core constraint solution, electronic equipment and medium

Abstract

The invention relates to the technical field of computers, in particular to a chip verification method based on multi-core constraint solving, electronic equipment and a medium, and the method comprises the following steps: S1, a main thread obtains a candidate solver core set of a target constraint problem; s2, the main thread obtains M sub-threads; s3, the main thread copies the target constraint problem into M copies and sends the M copies to each Wm, and each Wm executes the target constraint problem in parallel; s4, returning a solving result of the optimal Cm by the main thread, and generating a target solver core set; s5, when the target constraint problem is obtained again, D1 is selected to solve the target constraint problem; s6, monitoring the function coverage rate increasing speed, and if the coverage rate increasing speed meets a preset coverage rate increasing speed reducing condition, executing S7; and S7, selecting a target Di, switching to the target Di to solve the target constraint problem, and returning to execute the step S6. According to the invention, the convergence speed of the chip function coverage rate is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a chip verification method, an electronic device, and a medium based on multi-core constraint solving. Background Art

[0002] The technology of constraint problem solving has a wide range of applications in hardware verification, software automated testing, and a series of common programming problems. Many problems can be transformed into constraint problems and solved using a constraint solver. There are various types of solver cores applied to constraint problem solving, and a constraint solver can contain different types of solver cores. Different types of constraint solver cores are usually very different in the types of problems they are good at solving, and different types of solver cores will show completely different random distributions of solutions for the same constraint problem. Functional coverage is a very important indicator in the chip verification process. Verification engineers need to write functional coverage to count the coverage of data, addresses, control signals, etc. to verify whether the stimuli achieve the purpose, and use it to quantify the completeness of the entire verification process. Therefore, the convergence of the functional coverage indicator plays a crucial role in the convergence of the entire verification process.

[0003] Usually, in a hardware verification project, it is necessary to run enough test iterations on the same random test case. Therefore, the same constraint problem will be solved repeatedly, and the distribution quality of random values often determines the improvement speed of functional coverage and plays a key role in the convergence of the entire verification process. If only one type of solver core is selected for solving, it will bring a distribution bias problem. It can be seen from this that how to combine solver cores with different distribution characteristics to generate a richer stimulus distribution, cover more stimulus solution spaces, make the random variable distribution more uniform, and improve the convergence speed of chip functional coverage has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip verification method, an electronic device, and a medium based on multi-core constraint solving, which improve the convergence speed of chip functional coverage.

[0005] According to the first aspect of the present invention, there is provided a chip verification method based on multi-core constraint solving, including:

[0006] Step S1, the main thread obtains a candidate solver core set {C 1 , C 2 ,..., C m ,..., C M} of the target constraint problem, where C m is the m-th candidate solver core of the constraint problem to be solved, the value range of m is from 1 to M, M is the total number of candidate solver cores of the target constraint problem, and M≥2;

[0007] Step S2, the main thread obtains M child threads {W 1 ,W 2 ,...,W m ,...,W M} from the thread pool, and establishes a one-to-one correspondence between each child thread and the candidate solver core. W m is the m-th child thread, and W m corresponds to C m ;

[0008] Step S3, the main thread copies the target constraint problem M times and sends them to each W m , and each W m executes the target constraint problem in parallel;

[0009] Step S4, the main thread returns the solution result of the optimal C m , and generates a set of target solver cores {D 1 ,D 2 ,...,D i ,...,D I}. D i is the i-th target solver core, where the value range of i is from 1 to I. D i is the solver core whose running time for solving the target constraint problem is less than or equal to the preset waiting time threshold of the target constraint problem. {D 1 ,D 2 ,...,D i ,...,D I} is a subset of {C 1 ,C 2 ,...,C m ,...,C M}, and D 1 is the optimal C m ;

[0010] Step S5, when obtaining the target constraint problem again, the main thread first selects D 1 to solve the target constraint problem;

[0011] Step S6, monitor the function coverage improvement speed. If the coverage improvement speed meets the preset coverage improvement speed reduction condition, then execute Step S7;

[0012] Step S7, select a target D 1 ,D 2 ,...,D i ,...,D I from {D i}, switch to the target D i to solve the target constraint problem, and return to execute Step S6.

[0013] According to a second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the first aspect of the present invention.

[0014] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for executing the method described in the first aspect of the present invention.

[0015] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solutions, a chip verification method, an electronic device, and a medium based on multi-core constraint solving provided by the present invention can achieve considerable technological progress and practicality, and have broad industrial utilization value. It has at least the following beneficial effects:

[0016] The present invention can combine solver cores with different distribution characteristics to generate a richer excitation distribution, cover more excitation solution spaces, make the random variable distribution more uniform, and improve the convergence speed of the new chip function coverage rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a flowchart of a chip verification method based on multi-core constraint solving provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0020] An embodiment of the present invention provides a chip verification method based on multi-core constraint solving, as Figure 1 shown, including:

[0021] Step S1, the main thread obtains a candidate solver core set {C 1 , C 2,..., C m ,..., C M},C m is the m-th candidate solver core for the constraint problem to be solved, where m ranges from 1 to M, M is the total number of candidate solver cores for the target constraint problem, and M ≥ 2.

[0022] Among them, different C m may have the same or different solver core types, and the solver core types include SAT (Boolean satisfiability problem) solvers, SMT (Satisfiability modulo theories) solvers, CSP (Constraint satisfaction problem) solvers, and BDD (Binary decision diagram) solvers.

[0023] Step S2, the main thread obtains M child threads {W 1 , W 2 ,..., W m ,..., W M} from the thread pool, and establishes a one-to-one correspondence between each child thread and the candidate solver core. W m is the m-th child thread, and W m corresponds to C m .

[0024] Step S3, the main thread copies the target constraint problem M times and sends them to each W m , and each W m executes the target constraint problem in parallel.

[0025] Step S4, the main thread returns the solution result of the optimal C m , and generates a set of target solver cores {D 1 , D 2 ,..., D i ,..., D I}, where D i is the i-th target solver core, i ranges from 1 to I, I is the total number of target solver cores, and D i is the solver core whose running time for solving the target constraint problem is less than or equal to the preset waiting time threshold of the target constraint problem. {D 1 , D 2 ,..., D i ,..., D I} is {C 1 , C 2 ,..., C m ,..., C Msubset of}, D 1 is the optimal C m .

[0026] Step S5: When the target constraint problem is obtained again, the main thread first selects D 1 to solve the target constraint problem.

[0027] Step S6: Monitor the function coverage rate improvement speed. If the coverage rate improvement speed meets the preset coverage rate improvement speed reduction condition, then execute Step S7.

[0028] Among them, the preset coverage rate improvement speed reduction condition can specifically be set as the coverage rate improvement speed being less than the preset speed threshold, or the coverage rate improvement speed starting to decrease, or the coverage rate improvement speed continuously decreasing within the preset time period, and it can be flexibly set according to application requirements.

[0029] Step S7: Select a target D from {D 1 , D 2 ,..., D i ,..., D I}, switch to the target D i , and solve the target constraint problem, then return to execute Step S6. i It should be noted that through Steps S5 - S6, when the same target constraint problem is randomly obtained again, the main thread defaults to preferably using the optimal C

[0030] for solution. The main thread continuously monitors the function coverage rate improvement speed. When the preset coverage rate improvement speed reduction condition is met, it enters the adaptive scheduling mode, and randomly selects a different D from {D m , D 1 ,..., D 2 ,..., D i ,..., D I} to call for solution. When it is monitored that the function coverage rate improvement is effective, D 1 will continue to be used. Otherwise, continue to switch. When the preset coverage rate improvement speed reduction condition is met, continue to switch different solver cores for calling until the chip verification ends. i By combining solvers with different distribution characteristics and superimposing the final random value distribution, it can make the excitation distribution generated by the constraint solver more abundant, make the random variable distribution more uniform, cover more random solution spaces, and avoid the distribution bias problem caused by only using one solver. In addition, it can also generate more abundant test scenarios to help the function coverage converge faster. i As an embodiment, the said Step S1 includes:

[0031]

[0032]

[0032]

[0032]

[0033] Step S11: The main thread extracts feature information from the target constraint problem; the feature information includes the number of variables, the number of bits of variables, the number of expressions, and the types of expressions.

[0034] Among them, the target constraint problem consists of variables, constants, and expressions. A variable is a signed or unsigned bit-vector with a fixed bit-width. An expression consists of operands and operators. The operands can be constants or variables, and the operators can include the following 6 categories: logical operators, bit operators, arithmetic operators, relational operators, If-then-else operators, and set relational operators. Among them, the logical operators include &&, ||,!. The bit operators include &, |, ^, ~... The arithmetic operators include +, -, *, / , %. The relational operators include >, <, >=, <=, ==,!=. The set relational operators include inside, dist.

[0035] Step S12: Determine the solver cores in the corresponding solver core of the solver that can match the feature information corresponding to the target constraint problem and are not marked with the disabled flag of the target constraint problem as candidate solver cores, and generate a set of candidate solver cores.

[0036] It should be noted that the solver core marked with the disabled flag of the target constraint problem refers to the solver core that is not applicable to the target constraint problem, specifically, the solver core whose solving time for the target constraint problem exceeds the preset waiting time threshold.

[0037] As an embodiment, the step S4 includes:

[0038] Step S41: The main thread determines the earliest obtained C m as the current optimal C m , and returns the solution result of the current optimal C m .

[0039] Step S42: Continue to run the W m corresponding to the C m other than the current optimal C m in the background, and determine the optimal C m and the C m that returns the solution result within the preset waiting time threshold other than the current optimal C m as the target solver cores, and generate {D 1 , D 2 ,..., D i ,..., D I}.

[0040] As an embodiment, step S41 includes:

[0041] Step S411: For each W m Perform preprocessing modeling adaptation for the target constraint problem with respect to C m to generate the corresponding intermediate-state constraint problem P m for C m .

[0042] Among them, preprocessing modeling adaptation is a process of performing a series of adjustments and optimizations on the original constraint model according to the characteristics of the specific problem, the environment it is in, and specific requirements, etc., before formally applying a solving algorithm to find a solution that meets the constraint conditions. The intermediate-state constraint problem is a transitional problem form formed after preprocessing modeling adaptation in the process of solving the original constraint problem. Step S411 can be directly implemented based on the existing preprocessing modeling adaptation process and will not be elaborated here.

[0043] Step S412: Start each C m to solve the corresponding P m in combination with the shared inference constraint library, and the initial state of the shared inference constraint library is empty.

[0044] Step S413: If C m generates an inference constraint, return the corresponding inference constraint of C m to the main thread, and the main thread stores the corresponding inference constraint of C m in the shared inference constraint library.

[0045] Among them, the inference constraint refers to the additional constraint information deduced through an inference mechanism based on the existing constraint conditions of the target constraint problem, relevant knowledge in the problem domain, and logical rules, etc. These information help to further limit the solution space of the problem and help to find a feasible solution that meets all constraints more efficiently and accurately. By setting up the shared inference constraint library, each C m interacts with the shared inference constraint library to jointly solve the corresponding P m , thus accelerating the solving process.

[0046] Step S414: Determine the C m that obtains the solution result earliest as the current optimal C m .

[0047] As an embodiment, after step S42, it further includes:

[0048] Step S43: Mark the target constraint problem disable flag on the C m for which the solution result has not been returned after exceeding the preset waiting time threshold.

[0049] It should be noted that by marking the target constraint problem disabling identifier in step S43, the speed and accuracy of obtaining the candidate solver core set when step S1 is executed again can be improved.

[0050] Suppose a random integer variable x is defined in a target constraint problem, and there is a defined functional coverage associated with this x. The solution space of x is [a:b], [c:d], [e:f]. Different solver cores are called to generate different random value distributions for x. C 1 Cannot generate solutions within the range of [e:f] or the probability is very low. C 2 Cannot generate solutions within the range of [a:b] or the probability is very low. C 3 The generated solutions mainly fall within the interval [c:d]. Using the method described in the embodiments of the present invention can superimpose multiple distributions, so that x can be more uniform and cover more solution values, generate richer test scenarios, and improve the relevant coverage rate.

[0051] The following is an example of a target constraint problem:

[0052]

[0053] For the SAT type solver core, the distribution of the generated random solutions on x shows that the highest bit is always 0, and the 0 and 1 probabilities of each of the 7 bits from low to high are the same. For the CSP type solver core, it shows that x uniformly takes values within the range of [1:99]. And the BDD type solver core also shows that it uniformly takes values between [1:99] in this case. When the number of variables increases, the BDD type solver core will follow a strict uniform joint probability distribution. The distribution of other types of solver cores will become more complex and unpredictable. Using only one solver core will bring the problem of distribution bias, while the present invention combines solver cores with different distribution characteristics to superimpose the final random value distribution, which can make the excitation distribution generated by the constraint solver core more abundant, make the random variable distribution more uniform, and cover more random solution spaces.

[0054] As an embodiment, in step S7, a target D can be directly randomly selected from {D 1 , D 2 ,..., D i ,..., D I}, or a strategy adjustment module can be set up to select the target D from {D i , D 1 ,..., D 2 ,..., D i ,..., D I} through the strategy adjustment module. i. The input of the policy adjustment module may specifically include the association relationship between random constraint variables and coverage variables, the statistical distribution data of the current random constraint variables, and the current coverage rate trend, etc. The output of the policy adjustment module may specifically include the target D i and the key parameters of the corresponding adjusted solver core. The policy adjustment module may specifically be implemented based on algorithms such as AI (Artificial Intelligence) algorithms. It should be noted that the above is only an example, and other algorithms that can select the target D 1 , D 2 ,..., D i ,..., D I from {D i} are also applicable here.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0056] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method of the embodiment of the present invention.

[0057] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method of the embodiment of the present invention.

[0058] The embodiment of the present invention can combine solver cores with different distribution characteristics to generate a richer excitation distribution, cover more excitation solution spaces, make the random variable distribution more uniform, and improve the convergence speed of the new chip function coverage rate.

[0059] The above is only a preferred embodiment of the present invention, and it is not intended to limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to be equivalent embodiments within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A chip verification method based on multi-core constraint solving, characterized in that: include: Step S1: The main thread obtains a core set of candidate solvers {C1, C2, ..., C m ,...,C M }, C m is the mth candidate solver core of the constraint problem to be solved, the value of m ranges from 1 to M, M is the total number of candidate solver cores of the target constraint problem, M≥2; Step S2: The main thread obtains M child threads {W1, W2, ..., W m ,...,W M }, and establish a one-to-one correspondence between each subthread and the candidate solver core, W m is the mth child thread, W m With C m corresponding; Step S3: The main thread copies the target constraint problem into M copies and sends them to each W m , every W m Parallel execution of goal-constrained problems; Step S4: The main thread returns the optimal C m The solution result of the target solver core set {D1,D2,...,D i ,...,D I }, D i is the i-th target solver core, i ranges from 1 to I, D i The solver core {D1,D2,...,D i ,...,D I } is {C1,C2,...,C m ,...,C M }, D1 is the optimal C m ; Step S5: When the target constraint problem is obtained again, the main thread first selects D1 to solve the target constraint problem; Step S6, monitoring the coverage rate improvement speed, if the coverage rate improvement speed meets the preset coverage rate improvement speed reduction condition, executing step S7; Step S7: From {D1, D2, ..., D i ,...,D I }Select a target D i , switch to target D i Solve the target constraint problem and return to execute step S6.

2. The method according to claim 1, characterized in that: The step S1 comprises: Step S11, the main thread extracts feature information from the target constraint problem; Step S12: Determine the solver cores corresponding to the solver cores that can match the characteristic information corresponding to the target constraint problem and are not marked with a disabled flag of the target constraint problem as candidate solver cores, and generate a set of candidate solver cores.

3. The method according to claim 2, characterized in that: The characteristic information includes the number of variables, the number of variable bits, the number of expressions and the type of expression.

4. The method according to claim 1, characterized in that: The step S4 comprises: Step S41: The main thread obtains the solution result first. m Determined as the current optimal C m , returns the current optimal C m The solution result of ; Step S42: Remove the current optimal C m C m The corresponding W m Continue to run in the background, the optimal C m And except for the current optimal C m In addition, C returns the solution result within the preset waiting time threshold m are all determined as the target solver core, generating {D1,D2,...,D i ,...,D I }.

5. The method according to claim 4, characterized in that: The step S41 comprises: Step S411: Each W m For the target constraint problem, m Preprocessing modeling adaptation to generate C m The corresponding intermediate state constraint problem P m ; Step S412: Start each C m Combine the shared reasoning constraint library to the corresponding P m Solving, the shared reasoning constraint library is initially empty; Step S413: If C m Generate inference constraints, then C m The corresponding inference constraints are returned to the main thread, and the main thread converts C m The corresponding reasoning constraints are stored in the shared reasoning constraint library; Step S414: The C that obtains the solution result earliest m Determined as the current optimal C m .

6. The method according to claim 4, characterized in that: After step S42, the following steps are also included: Step S43: If the C that does not return the solution result exceeds the preset waiting time threshold, m The upper annotation target constraint problem disables the flag.

7. The method according to claim 1, characterized in that: Different C m The solver core types are the same or different, and the solver core types include SAT solver, SMT solver, CSP solver and BDD solver.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-7.

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