Quantum state control circuit of radio frequency digital-to-analog converter and control method thereof

Abstract

The invention discloses a radio frequency digital-to-analog converter quantum state control circuit and a control method thereof.The radio frequency digital-to-analog converter quantum state control circuit comprises a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module and a mixer, the clock management module is used for generating clock signals, and the low-frequency clock domain module is used for generating baseband data according to the clock signals; the calibration logic module is used for performing current compensation on the current mirror to be calibrated according to a clock signal and an absolute average error algorithm to obtain a calibration current, and the high-frequency clock domain module is used for obtaining a radio frequency phase signal and a radio frequency amplitude signal according to baseband data and the calibration current; the mixer is used for mixing the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal, and the output frequency of the high-frequency clock domain module covers any frequency point of the second Nyquist region and the third Nyquist region. According to the invention, integrated control of multiple quantum bits can be realized, the fidelity of quantum state control can be improved, and the method can be widely applied to the technical field of quantum control.

Description

Technical Field

[0001] The present invention relates to the field of quantum control technology, and in particular to a quantum state control circuit for a radio frequency digital-to-analog converter and a control method therefor. Background Art

[0002] A radio frequency digital-to-analog converter is an electronic device that converts digital signals into analog radio frequency signals. For a current-steering radio frequency digital-to-analog converter (RF-DAC), the current mirror is a key component in the RF-DAC, and its accuracy directly affects the accuracy and stability of the output signal. However, due to factors such as process deviation and temperature change, there are often mismatches between current mirrors, resulting in the deterioration of the spurious-free dynamic range (SFDR) of the output signal, thereby affecting the fidelity of quantum state control. In addition, for a practical quantum computer, the number of controllable qubits in the system is crucial for the performance of the quantum computer. However, there are problems of limited controllable qubits and difficulty in integration in existing quantum control systems. Summary of the Invention

[0003] To solve the above technical problems, an object of the present invention is to provide a quantum state control circuit for a radio frequency digital-to-analog converter and a control method therefor, which can achieve integrated control of multiple qubits.

[0004] To achieve the above object, one aspect of the embodiments of the present application provides a quantum state control circuit for a radio frequency digital-to-analog converter, including a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module, and a mixer. The input ends of the low-frequency clock domain module and the calibration logic module are both connected to the output end of the clock management module. The output ends of the low-frequency clock domain module and the calibration logic module are both connected to the input end of the high-frequency clock domain module. The output end of the high-frequency clock domain module is connected to the input end of the mixer. The clock management module is used to generate clock signals with different frequencies. The low-frequency clock domain module is used to generate baseband data according to the clock signals. The calibration logic module is used to perform current compensation on the current mirror to be calibrated according to the clock signals and the absolute average error algorithm to obtain a calibrated current. The high-frequency clock domain module is used to obtain a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibrated current. The mixer is used to mix the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal, wherein the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist region and the third Nyquist region.

[0005] In some embodiments, the low-frequency clock domain module includes a serial communication module and a main control module. The output end of the serial communication module is connected to the input end of the main control module. The serial communication module is configured to receive the baseband data and send the baseband data to the main control module, and the main control module is configured to output a control instruction.

[0006] In some embodiments, the low-frequency clock domain module further includes a register and a state machine. Both the register and the state machine are connected to the main control module. The register is configured to cache the baseband data in the main control module, and the state machine is configured to control the quantum measurement and control pulse time according to the control instruction.

[0007] In some embodiments, the high-frequency clock domain module includes a parallel-to-serial conversion module. The output ends of the low-frequency clock domain module and the clock management module are both connected to the input end of the parallel-to-serial conversion module. The parallel-to-serial conversion module is configured to increase the rate of the baseband data according to the clock signal to obtain a baseband signal.

[0008] In some embodiments, the high-frequency clock domain module further includes a radio frequency digital-to-analog converter. The input end of the radio frequency digital-to-analog converter is connected to the output end of the parallel-to-serial conversion module, and the output end of the radio frequency digital-to-analog converter is connected to the input end of the mixer. The radio frequency digital-to-analog converter is configured to modulate the baseband signal according to the calibration current to obtain the radio frequency phase signal and the radio frequency amplitude signal.

[0009] In some embodiments, the calibration logic module includes a current mirror to be calibrated, a comparator, a calibration logic module, and a calibration digital-to-analog converter. The output end of the current mirror to be calibrated is connected to the input end of the comparator, the output end of the comparator is connected to the input end of the calibration logic module, the output end of the calibration logic module is connected to the input end of the calibration digital-to-analog converter, the output end of the calibration digital-to-analog converter is connected to the input end of the current mirror to be calibrated, and the input end of the calibration logic module is further connected to the output end of the clock management module. The current mirror to be calibrated is configured to output a reference current and an output current. The comparator is configured to compare the output current and the reference current to obtain a comparison result. The calibration logic module is configured to generate a control signal according to the comparison result and the clock signal. The calibration digital-to-analog converter is configured to perform current compensation on the output current according to the control signal and the absolute average error algorithm to obtain the calibration current.

[0010] To achieve the above object, another aspect of the embodiments of the present application provides a control method for a radio frequency digital-to-analog converter quantum state control circuit, including the following steps:

[0011] Generating clock signals with different frequencies through a clock management module;

[0012] The baseband data is generated by the low-frequency clock domain module according to the clock signal;

[0013] The current mirror to be calibrated is compensated for current according to the clock signal and the absolute mean error algorithm by the calibration logic module to obtain a calibrated current;

[0014] The radio frequency phase signal and the radio frequency amplitude signal are obtained by the high-frequency clock domain module according to the baseband data and the calibrated current;

[0015] The radio frequency phase signal and the radio frequency amplitude signal are mixed by a mixer to obtain a control signal;

[0016] Wherein, the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist region and the third Nyquist region.

[0017] In some embodiments, the current mirror to be calibrated is compensated for current according to the clock signal and the absolute mean error algorithm by the calibration logic module to obtain a calibrated current, which specifically includes:

[0018] The reference current and the output current are output by the current mirror to be calibrated;

[0019] The output current and the reference current are compared by a comparator to obtain a comparison result;

[0020] The calibration logic module generates a control signal according to the comparison result and the clock signal;

[0021] The output current is compensated for current according to the control signal and the absolute mean error algorithm by a calibration digital-to-analog converter to obtain the calibrated current.

[0022] In some embodiments, the output current is compensated for current according to the control signal by a calibration digital-to-analog converter to obtain the calibrated current, which specifically includes:

[0023] The total number of current mirrors and the current values corresponding to each current mirror are obtained;

[0024] According to the total number of current mirrors and the current values, the calibrated current corresponding to the current mirror to be calibrated is calculated by the absolute mean error algorithm;

[0025] The output current corresponding to the current mirror to be calibrated is compensated to the calibrated current by successive approximation logic.

[0026] In some embodiments, the calibrated current corresponding to the current mirror to be calibrated is calculated by the following formula:

[0027]

[0028] Among them, i cal represents the calibration current corresponding to the current mirror to be calibrated, n represents the total number of current mirrors, and i k represents the current value of the k-th current mirror.

[0029] The beneficial effects of the present invention are as follows: A quantum state control circuit and its control method for a radio frequency digital-to-analog converter of the present invention include a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module, and a mixer. The clock management module is used to generate clock signals of different frequencies. The low-frequency clock domain module is used to generate baseband data according to the clock signal. The calibration logic module is used to perform current compensation on the current mirror to be calibrated according to the clock signal and the absolute average error algorithm to obtain the calibration current. The high-frequency clock domain module is used to obtain a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibration current. The mixer is used to mix the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal. Among them, the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist region and the third Nyquist region. On the one hand, the present invention uses two-way quadrature mixed radio frequency phase signals and radio frequency amplitude signals to be superimposed and output to the next-stage mixer, and the output frequency can cover any frequency point in the second and third Nyquist regions. Therefore, a larger baseband bandwidth can be provided to generate more different qubits to achieve the integrated control of multiple qubits. On the other hand, the current mirror calibration algorithm of absolute average error is introduced, which can effectively reduce the deterioration of the spurious-free dynamic range of the output control signal caused by current mirror mismatch, thereby improving the fidelity of quantum state control. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following introduces the drawings required to be used in the embodiments of the present invention. It should be understood that the drawings introduced below only conveniently and clearly express some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a structural block diagram of a quantum state control circuit for a radio frequency digital-to-analog converter provided by an embodiment of the present invention;

[0032] Figure 2 It is a circuit structural block diagram of a quantum state control circuit for a radio frequency digital-to-analog converter provided by an embodiment of the present invention;

[0033] Figure 3 It is a circuit structural block diagram of the calibration logic module provided by an embodiment of the present invention;

[0034] Figure 4It is a flowchart of steps of a control method for a quantum state control circuit of a radio frequency digital-to-analog converter provided by an embodiment of the present invention;

[0035] Figure 5 It is a schematic diagram of current mirror calibration control logic provided by an embodiment of the present invention;

[0036] Figure 6 It is a schematic diagram of the simulation result of current mirror calibration provided by an embodiment of the present invention.

[0037] Reference numerals: S1, output control switch transistor; S2, reference control switch transistor; S3, calibration control switch transistor. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0039] It can be understood that the terms "first", "second", etc. used in the present application can be used in this document to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be called the second information, and similarly, the second information can also be called the first information. Depending on the context, the words "if", "when" as used herein can be interpreted as "when...", "when...", or "in response to a determination".

[0040] The terms "at least one", "a plurality", "each", "any one", etc. used in the present application, at least one includes one, two or more, a plurality includes two or more, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0041] A radio frequency digital-to-analog converter is an electronic device that converts digital signals into analog radio frequency signals. For a current-steering radio frequency digital-to-analog converter (RF-DAC), the current mirror is a key component in the RF-DAC, and its accuracy directly affects the accuracy and stability of the output signal. However, due to factors such as process variations and temperature changes, there are often mismatches between current mirrors, resulting in the deterioration of the spurious-free dynamic range (SFDR) of the output signal, which in turn affects the fidelity of quantum state control. In addition, for a practical quantum computer, the number of controllable qubits in the system is crucial for the performance of the quantum computer. However, there are problems of limited controllable qubits and difficulty in integration in existing quantum control systems.

[0042] To this end, an embodiment of the present invention proposes a quantum state control circuit for a radio frequency digital-to-analog converter, including a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module, and a mixer. The clock management module is used to generate clock signals of different frequencies. The low-frequency clock domain module is used to generate baseband data according to the clock signal. The calibration logic module is used to perform current compensation on the current mirror to be calibrated according to the clock signal and the absolute mean error algorithm to obtain a calibrated current. The high-frequency clock domain module is used to obtain a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibrated current. The mixer is used to mix the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal, wherein the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist region and the third Nyquist region. On the one hand, the present invention uses two orthogonally mixed radio frequency phase signals and radio frequency amplitude signals to be superimposed and output to the next-stage mixer, and the output frequency can cover any frequency point in the second and third Nyquist regions, so it can provide a larger baseband bandwidth for generating more different qubits and realize the integrated control of multiple qubits. On the other hand, an absolute mean error current mirror calibration algorithm is introduced, which can effectively reduce the deterioration of the spurious-free dynamic range of the output control signal caused by current mirror mismatch, thereby improving the fidelity of quantum state control.

[0043] Refer to Figure 1 , Figure 1It is a structural block diagram of a quantum state control circuit for a radio frequency digital-to-analog converter provided by an embodiment of the present invention. An embodiment of the present invention proposes a quantum state control circuit for a radio frequency digital-to-analog converter, including a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module, and a mixer. The input ends of the low-frequency clock domain module and the calibration logic module are both connected to the output end of the clock management module. The output ends of the low-frequency clock domain module and the calibration logic module are both connected to the input end of the high-frequency clock domain module. The output end of the high-frequency clock domain module is connected to the input end of the mixer. The clock management module is used to generate clock signals of different frequencies. The low-frequency clock domain module is used to generate baseband data according to the clock signals. The calibration logic module is used to perform current compensation on the current mirror to be calibrated according to the clock signals and the absolute average error algorithm to obtain a calibrated current. The high-frequency clock domain module is used to obtain a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibrated current. The mixer is used to mix the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal. Among them, the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist region and the third Nyquist region.

[0044] Referring to Figure 2 , Figure 2 It is a circuit structural block diagram of a quantum state control circuit for a radio frequency digital-to-analog converter provided by an embodiment of the present invention. Further as an optional implementation manner, the high-frequency clock domain module further includes a radio frequency digital-to-analog converter. The input end of the radio frequency digital-to-analog converter is connected to the output end of the parallel-to-serial module. The output end of the radio frequency digital-to-analog converter is connected to the input end of the mixer. The radio frequency digital-to-analog converter is used to modulate the baseband signal according to the calibrated current to obtain a radio frequency phase signal and a radio frequency amplitude signal.

[0045] Specifically, the radio frequency digital-to-analog converter in the quantum state control circuit of the embodiment of the present invention operates in the mixing mode (MIX mode) and uses the frequency band signals in the second Nyquist and third Nyquist domains. In the embodiment of the present invention, because two orthogonal RF-DAC signals (radio frequency phase signal and radio frequency amplitude signal) are used to be superimposed and output to the next-stage mixer. At the RF-DAC end, by changing the relative phase of the target frequency point frequency, it can be determined to suppress the upper sideband or the lower sideband frequency point, so as to change the position where the target frequency point appears in the second Nyquist region or the third Nyquist region. Theoretically, the embodiment of the present invention can obtain a 2GHz baseband frequency band width by using a 2GHz clock, and then use a mixer to shift the control baseband frequency to the characteristic frequency of a superconducting qubit of 4 to 8GHz, and then filter out the lower sideband mixed by the mixer through an off-chip filter to obtain the final control signal, realizing the integrated control of multiple qubits.

[0046] Among them, the Nyquist region refers to a specific range of the sampled signal in the frequency domain. The second Nyquist region and the third Nyquist region are extended parts of the Nyquist region, which are used to describe the spectral characteristics of the signal.

[0047] It should be noted that for a practical quantum computer, the number of controllable qubits in the system is crucial for the performance of the quantum computer. For a computer with multiple qubits, in order to ensure that the interference between each qubit is small enough, generally the control characteristic frequency interval of each qubit is set above 50 MHz, and the characteristic frequency of superconducting qubits is generally between 4 and 8 GHz. If simultaneous control of 8 qubits is to be achieved, at least 400 MHz of baseband bandwidth is required, which requires that the multi-qubit control system has a sufficiently large bandwidth to accommodate the quantum characteristic frequencies to be controlled. The embodiment of the present invention uses a radio frequency control framework based on a radio frequency digital-to-analog converter, which has higher cost performance and flexibility compared to traditional mixing schemes.

[0048] Refer to Figure 2 , further as an optional implementation manner, the low-frequency clock domain module includes a serial communication module and a main control module. The output end of the serial communication module is connected to the input end of the main control module. The serial communication module is used to receive baseband data and send the baseband data to the main control module, and the main control module is used to output control instructions.

[0049] Specifically, the baseband data is generated by the digital circuit in the system, which includes information such as amplitude, frequency, and phase modulation. The serial communication module is mainly responsible for the communication between the main control module and the outside, and is used to load the baseband data into the memory of the main control module and receive instructions, etc.

[0050] Refer to Figure 2 , further as an optional implementation manner, the low-frequency clock domain module further includes a register and a state machine. Both the register and the state machine are connected to the main control module. The register is used to cache the baseband data in the main control module, and the state machine is used to control the quantum measurement and control pulse time according to the control instructions.

[0051] Specifically, the register is used to cache the baseband data of the part to be played, and the state machine is used to control information such as the time and type of the quantum measurement and control pulse.

[0052] Refer to Figure 2 , further as an optional implementation manner, the high-frequency clock domain module includes a parallel-to-serial conversion module. The output ends of the low-frequency clock domain module and the clock management module are both connected to the input end of the parallel-to-serial conversion module. The parallel-to-serial conversion module is used to increase the rate of the baseband data according to the clock signal to obtain a baseband signal.

[0053] It should be noted that in the generation part of the baseband data, the quantum state control circuit in the embodiment of the present invention is divided into a high-speed part and a low-speed part for processing. Since the sampling frequency of the radio frequency digital-to-analog converter (RF-DAC) is very high, operating the entire circuit at such a high sampling frequency will generate high power consumption. Therefore, the serial-to-parallel module is used to gradually increase the data rate of the baseband data in the low-speed part, thereby saving the power consumption of the digital part of the control circuit.

[0054] Specifically, the serial-to-parallel module is implemented by a data selector and a flip-flop. When multiple data bits are input to the data selector simultaneously, the data selector has multiple input terminals. The data selector sequentially selects one data bit for output according to the clock signal. In each clock cycle, the data selector selects a different input terminal, outputs one data bit, and then latches and outputs it through a D flip-flop.

[0055] Refer to Figure 3 As Figure 3 is the circuit structure block diagram of the calibration logic module provided by the embodiment of the present invention. Further, as an optional implementation manner, the calibration logic module includes a current mirror to be calibrated, a comparator, a calibration logic module, and a calibration digital-to-analog converter. The output terminal of the current mirror to be calibrated is connected to the input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the calibration logic module, the output terminal of the calibration logic module is connected to the input terminal of the calibration digital-to-analog converter, the output terminal of the calibration digital-to-analog converter is connected to the input terminal of the current mirror to be calibrated, and the input terminal of the calibration logic module is also connected to the output terminal of the clock management module. The current mirror to be calibrated is used to output a reference current and an output current, the comparator is used to compare the output current and the reference current to obtain a comparison result, the calibration logic module is used to generate a control signal according to the comparison result and the clock signal, and the calibration digital-to-analog converter is used to perform current compensation on the output current according to the control signal and the absolute mean error algorithm to obtain a calibrated current.

[0056] It should be noted that in order to reduce the current mirror mismatch of the current-steering radio frequency digital-to-analog converter (RF-DAC), the embodiment of the present invention introduces an absolute mean error current mirror calibration algorithm, which can effectively reduce the deterioration of the spurious-free dynamic range of the output control signal caused by the current mirror mismatch, thereby improving the fidelity of the quantum state control.

[0057] The structure and working principle of the quantum state control circuit of the RF-DAC in the embodiments of the present invention have been described above. It can be recognized that, compared with the traditional quantum state controller in the direct up-conversion mode, the proposed quadrature mixer RF-DAC in the embodiments of the present invention has an output frequency that can cover any frequency point in the second and third Nyquist regions. Therefore, it can provide a larger baseband bandwidth for generating more different qubits and realize the integrated control of multiple qubits. At the same time, in order to reduce the current mirror mismatch of the current-steering RF-DAC, an absolute average error current mirror calibration algorithm is introduced, which can effectively reduce the deterioration of the spurious-free dynamic range of the output control signal caused by the current mirror mismatch, thereby improving the fidelity of quantum state control.

[0058] Referring Figure 4 , the embodiments of the present invention provide a control method for a quantum state control circuit of an RF-DAC, which is used to control through the above-mentioned quantum state control circuit of the RF-DAC, and includes the following steps S101 to S105:

[0059] S101. Generate clock signals with different frequencies through a clock management module;

[0060] S102. Generate baseband data through a low-frequency clock domain module according to the clock signal;

[0061] S103. Perform current compensation on the current mirror to be calibrated through a calibration logic module according to the clock signal and the absolute average error algorithm to obtain a calibrated current;

[0062] S104. Obtain an RF phase signal and an RF amplitude signal through a high-frequency clock domain module according to the baseband data and the calibrated current;

[0063] S105. Mix the RF phase signal and the RF amplitude signal through a mixer to obtain a control signal;

[0064] Among them, the output frequency of the high-frequency clock domain module covers any frequency point in the second and third Nyquist regions.

[0065] The content in the above embodiments of the quantum state control circuit of the RF-DAC is applicable to the embodiments of the control method of the quantum state control circuit of the RF-DAC. The functions specifically implemented in the embodiments of the control method of the quantum state control circuit of the RF-DAC are the same as those in the above embodiments of the quantum state control circuit of the RF-DAC, and the beneficial effects achieved are also the same as those in the above embodiments of the quantum state control circuit of the RF-DAC.

[0066] As a further optional implementation, the step of obtaining a calibrated current by compensating the current of the current mirror to be calibrated according to the clock signal and the absolute average error algorithm by the calibration logic module can be further divided into the following steps S1031 to S1034 specifically:

[0067] S1031. Output a reference current and an output current through the current mirror to be calibrated;

[0068] S1032. Compare the output current with the reference current through a comparator to obtain a comparison result;

[0069] S1033. Generate a control signal by the calibration logic module according to the comparison result and the clock signal;

[0070] S1034. Compensate the output current according to the control signal and the absolute average error algorithm through a calibration digital-to-analog converter to obtain a calibrated current.

[0071] As a further optional implementation, the step of obtaining a calibrated current by compensating the output current according to the control signal and the absolute average error algorithm through a calibration digital-to-analog converter can be further divided into the following steps S10341 to S10343 specifically:

[0072] S10341. Obtain the total number of current mirrors and the current values corresponding to each current mirror;

[0073] S10342. Calculate the calibrated current corresponding to the current mirror to be calibrated through the absolute average error algorithm according to the total number of current mirrors and the current values;

[0074] S10343. Compensate the output current corresponding to the current mirror to be calibrated to the calibrated current through successive approximation logic.

[0075] In some optional embodiments, such as Figure 5The figure shows a schematic diagram of the current mirror calibration control logic. In the embodiments of the present invention, the current mirror to be calibrated is compensated for current through successive approximation logic, and finally the calibrated current is achieved. A switching selection control method is adopted for the output currents of the current mirror and the reference current. During the calibration process, the digital logic is used to select the turn-on of the output control switch tube S1, the reference control switch tube S2, and the calibration control switch tube S3 to implement the comparison logic of the comparator. Specifically, during normal operation, the reference control switch tube S2 and the calibration control switch tube S3 are both in the off state, and the output control switch tube S1 is in the on state, and the calibration digital-to-analog converter works normally; in the calibration mode, when the current mirror is calibrated, the calibration control switch tube S3 is turned on to allow calibration modulation of the current mirror, the reference control switch tube S2 is turned off, and the reference control switch tubes S2 of the remaining current mirrors are turned on to provide a reference current for the current mirror to be calibrated. The calibration control of the current mirror is achieved by alternately controlling the turn-on of the current mirror switch tubes.

[0076] Further as an optional implementation manner, the calibrated current corresponding to the current mirror to be calibrated is calculated by the following formula:

[0077]

[0078] where, i cal represents the calibrated current corresponding to the current mirror to be calibrated, n represents the total number of current mirrors, and i k represents the current value of the kth current mirror.

[0079] Specifically, in the embodiments of the present invention, the absolute average error algorithm is used to average and calibrate the errors of the current mirrors. Assuming that there are n current mirrors in the circuit, when calibrating the mth current mirror, the currents of the remaining n - 1 current mirrors are added and averaged as the calibrated current, and the expression of the calibrated current is as shown in the above formula.

[0080] In summary, as Figure 6 shown in the schematic diagram of the simulation result of current mirror calibration, as can be seen from Figure 6 , in the embodiments of the present invention, the current mirror to be calibrated is compensated to the average calibrated current through successive approximation logic by the calibration digital-to-analog converter to achieve the calibration of a single current mirror, and through the iteration of the absolute average error algorithm, the errors between the current mirrors can be averaged, thereby obtaining higher current consistency. When the mismatch of the current mirrors follows a Gaussian distribution, the errors between the current mirrors can be effectively reduced through a finite number of iterations of the algorithm.

[0081] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The above methods can be implemented in a computer program using standard programming techniques—including a non-transitory computer-readable storage medium configured with the computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Additionally, for this purpose the program is capable of running on a programmed application-specific integrated circuit.

[0082] In addition, the operations of the processes described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions and can be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) executed jointly on one or more processors, by hardware, or by a combination thereof. The above computer programs include a plurality of instructions executable by one or more processors.

[0083] Furthermore, the above methods can be implemented in any type of computing platform operably connected, including but not limited to personal computers, minicomputers, mainframes, workstations, network or distributed computing environments, standalone or integrated computer platforms, or communicating with charged particle tools or other imaging devices, etc. Aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into the computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer and, when the storage medium or device is read by the computer, can be used to configure and operate the computer to perform the processes described herein. Additionally, the machine-readable code, or portions thereof, can be transmitted via a wired or wireless network. When such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the inventions described herein include these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques described in the present invention, the present invention also includes the computer itself.

[0084] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0085] In the foregoing description of the present specification, descriptions with reference to the terms "one embodiment / implementation", "another embodiment / implementation", or "certain embodiments / implementations", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0086] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.

[0087] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A radio frequency digital-to-analog converter quantum state control circuit, characterized in that: It includes a low-frequency clock domain module, a high-frequency clock domain module, a clock management module, a calibration logic module and a mixer, wherein the input ends of the low-frequency clock domain module and the calibration logic module are connected to the output end of the clock management module, the output ends of the low-frequency clock domain module and the calibration logic module are connected to the input end of the high-frequency clock domain module, the output end of the high-frequency clock domain module is connected to the input end of the mixer, the clock management module is used to generate clock signals of different frequencies, the low-frequency clock domain module is used to generate baseband data according to the clock signal, the calibration logic module is used to perform current compensation on the current mirror to be calibrated according to the clock signal and the absolute mean error algorithm to obtain a calibration current, the high-frequency clock domain module is used to obtain a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibration current, and the mixer is used to mix the radio frequency phase signal and the radio frequency amplitude signal to obtain a control signal, wherein the output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist zone and the third Nyquist zone.

2. The RF digital-to-analog converter quantum state control circuit according to claim 1, characterized in that: The low-frequency clock domain module includes a serial communication module and a main control module. The output end of the serial communication module is connected to the input end of the main control module. The serial communication module is used to receive the baseband data and send the baseband data to the main control module. The main control module is used to output control instructions.

3. The RF digital-to-analog converter quantum state control circuit according to claim 2, characterized in that: The low-frequency clock domain module also includes a register and a state machine, both of which are connected to the main control module, the register is used to cache the baseband data in the main control module, and the state machine is used to control the quantum measurement and control pulse time according to the control instruction.

4. The RF digital-to-analog converter quantum state control circuit according to claim 1, characterized in that: The high-frequency clock domain module includes a parallel-to-serial module. The output ends of the low-frequency clock domain module and the clock management module are connected to the input end of the parallel-to-serial module. The parallel-to-serial module is used to increase the rate of the baseband data according to the clock signal to obtain a baseband signal.

5. The RF digital-to-analog converter quantum state control circuit according to claim 4, characterized in that: The high-frequency clock domain module also includes a radio frequency digital-to-analog converter, the input end of the radio frequency digital-to-analog converter is connected to the output end of the parallel-to-serial module, the output end of the radio frequency digital-to-analog converter is connected to the input end of the mixer, and the radio frequency digital-to-analog converter is used to modulate the baseband signal according to the calibration current to obtain the radio frequency phase signal and the radio frequency amplitude signal.

6. The RF digital-to-analog converter quantum state control circuit according to claim 1, characterized in that: The calibration logic module includes a current mirror to be calibrated, a comparator, a calibration logic module and a calibration digital-to-analog converter. The output end of the current mirror to be calibrated is connected to the input end of the comparator, the output end of the comparator is connected to the input end of the calibration logic module, the output end of the calibration logic module is connected to the input end of the calibration digital-to-analog converter, the output end of the calibration digital-to-analog converter is connected to the input end of the current mirror to be calibrated, and the input end of the calibration logic module is also connected to the output end of the clock management module. The current mirror to be calibrated is used to output a reference current and an output current. The comparator is used to compare the output current and the reference current to obtain a comparison result. The calibration logic module is used to generate a control signal according to the comparison result and the clock signal. The calibration digital-to-analog converter is used to perform current compensation on the output current according to the control signal and the absolute mean error algorithm to obtain the calibration current.

7. A control method for a radio frequency digital-to-analog converter quantum state control circuit, used for controlling the radio frequency digital-to-analog converter quantum state control circuit according to any one of claims 1 to 6, characterized in that: The following steps are involved: Generate clock signals of different frequencies through the clock management module; Generate baseband data according to the clock signal through a low-frequency clock domain module; Performing current compensation on the current mirror to be calibrated according to the clock signal and an absolute mean error algorithm through a calibration logic module to obtain a calibration current; Obtaining a radio frequency phase signal and a radio frequency amplitude signal according to the baseband data and the calibration current through a high frequency clock domain module; Mixing the radio frequency phase signal and the radio frequency amplitude signal by a mixer to obtain a control signal; The output frequency of the high-frequency clock domain module covers any frequency point in the second Nyquist zone and the third Nyquist zone.

8. The control method of a radio frequency digital-to-analog converter quantum state control circuit according to claim 7, characterized in that: The calibration logic module performs current compensation on the current mirror to be calibrated according to the clock signal and the absolute mean error algorithm to obtain the calibration current, which specifically includes: Outputting a reference current and an output current through a current mirror to be calibrated; Comparing the output current with a reference current by a comparator to obtain a comparison result; Generate a control signal according to the comparison result and the clock signal by a calibration logic module; The calibration current is obtained by performing current compensation on the output current according to the control signal and the absolute average error algorithm through a calibration digital-to-analog converter.

9. The control method of a radio frequency digital-to-analog converter quantum state control circuit according to claim 8, characterized in that: The step of performing current compensation on the output current according to the control signal and the absolute mean error algorithm by calibrating the digital-to-analog converter to obtain the calibration current specifically includes: Obtain the total number of current mirrors and the current value corresponding to each current mirror; According to the total number of the current mirrors and the current value, the calibration current corresponding to the current mirror to be calibrated is calculated by the absolute mean error algorithm; The output current corresponding to the current mirror to be calibrated is compensated to the calibration current through successive approximation logic.

10. The control method of a radio frequency digital-to-analog converter quantum state control circuit according to claim 9, characterized in that: The calibration current corresponding to the current mirror to be calibrated is calculated by the following formula: Among them, i cal represents the calibration current corresponding to the current mirror to be calibrated, n represents the total number of current mirrors, i k Represents the current value of the kth current mirror.

Images