Image splicing method and system, computer equipment and storage medium

Abstract

The invention provides an image splicing method and system, computer equipment and a storage medium, and the method comprises the steps: writing a plurality of to-be-spliced images into an image memory in rows, each image comprising a plurality of first sub-images in rows; acquiring a head address of each image written into an image memory and a row span of each image; determining the arrangement of each image in the splicing direction according to a target spliced image, wherein the target spliced image comprises a plurality of second sub-images in rows; determining an initial address of the first sub-image contained in each second sub-image in the storage space of the image memory; and sequentially reading the first sub-images included in the second sub-images in rows according to the splicing direction, and mapping the address read each time as the initial address of the current first sub-image. According to the scheme, the higher image splicing speed can be achieved, the data transmission amount on the bus is smaller, the occupied bandwidth is lower, and the system performance can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to an image stitching method, system, computer device, and storage medium. Background Art

[0002] The existing image stitching device usually includes an image collector, an image memory, and a subsequent system. The image collector is used to capture image data and may include one or more image capture devices, and write the captured image data into the image memory; the image memory is used to store the original image and the stitched image data; the image stitching device is used to complete image stitching and store the stitched image into the image memory; the stitched image data can be output to the subsequent system.

[0003] However, during the entire image stitching and output process, there are at least two read operations and two write operations, resulting in a large amount of data transmitted on the memory bus during the image stitching process, a large occupancy of the bus bandwidth, and a long stitching time, which affects the system performance. Therefore, there is an urgent need for an image stitching method with a faster image stitching speed, less data transmitted on the bus, and lower bandwidth occupancy. Summary of the Invention

[0004] The purpose of the present invention is to provide an image stitching method, system, computer device, and storage medium, which can achieve a faster image stitching speed, reduce the amount of data transmitted on the bus, and lower the bandwidth occupancy, thereby improving the system performance.

[0005] The technical solution provided by the present invention is as follows:

[0006] The present invention provides an image stitching method, including the steps of:

[0007] Writing a plurality of images to be stitched into the image memory row by row, and each image includes a plurality of first sub-images row by row;

[0008] Obtaining the starting address of each image written into the storage space of the image memory, and the row span of the first sub-images of each image in the storage space of the image memory;

[0009] Determining the arrangement of each image or at least a part of each image in the stitching direction according to the target stitched image, where the target stitched image includes a plurality of second sub-images row by row, and each second sub-image includes at least one of the first sub-images or a part of the first sub-image;

[0010] Determine the initial address in the storage space of the image memory for the first sub-image included in each of the second sub-images or a part of the first sub-image according to the starting address at which each image is written into the storage space of the image memory and the row span of the first sub-image of each image in the storage space of the image memory;

[0011] Read in sequence by rows the first sub-image included in each of the second sub-images or a part of the first sub-image according to the splicing direction, and map the address read each time to the initial address of the current first sub-image or a part of the first sub-image.

[0012] In this solution, by converting the read and write operations of the image splicing device and the memory into a flexible address mapping for reading the memory, the image data read from the image memory can be directly output to the subsequent system, eliminating the process of the image splicing device writing data to the memory and the subsequent system reading data from the memory, reducing the original two reads and two writes to one read and one write. Thereby, the occupancy of the memory bus bandwidth during the image splicing process is reduced, less data is transmitted on the bus, and a faster image splicing speed can be achieved, which is beneficial to improving the system performance.

[0013] In some embodiments, the row span of the first sub-image of each image in the storage space of the image memory is not less than the width of the first sub-image.

[0014] In some embodiments, the splicing direction is the width direction of the image, and the target spliced image is the splicing of at least two images in the splicing direction.

[0015] In some embodiments, the target spliced image is the splicing of two images in the splicing direction, both images are rectangles, and the number of the first sub-images included in the two images is the same;

[0016] The starting address at which the first image is written into the storage space of the image memory is the first starting address, the row span of the first image in the storage space of the image memory is the first row span, the width of the first image is the first image width, the starting address at which the second image is written into the storage space of the image memory is the second starting address, the row span of the second image in the storage space of the image memory is the second row span, and the width of the second image is the second image width;

[0017] During reading, the first address read is the first starting address, and the first sub-image of the first row of the first image is continuously read out from the image memory;

[0018] When the width to be read reaches the width of the first image, map the read address to the second starting address, and continuously read the first sub-image of the first row of the second image from the image memory;

[0019] When the width to be read reaches the width of the second image, map the read address to the second address, where the second address is the first starting address plus the span of the first row, and continuously read the first sub-image of the second row of the first image from the image memory;

[0020] When the width to be read reaches the width of the first image, map the read address to the third address, where the third address is the second starting address plus the span of the second row, and continuously read the first sub-image of the second row of the second image from the image memory;

[0021] And so on. Until the last row of the first image is read, map the read address to the fourth address, where the fourth address = the first starting address + (N - 1) the span of the first row, N is the number of rows of the first image, and continuously read the first sub-image of the last row of the first image from the image memory;

[0022] When the width to be read reaches the width of the first image, map the read address to the fifth address, where the fifth address = the second starting address + (N - 1) the span of the second row, N is the number of rows of the second image, and continuously read the first sub-image of the last row of the second image from the image memory.

[0023] In some embodiments, the splicing direction is the width direction of the image, and the target spliced image is the splicing of a part inside at least two images in the splicing direction.

[0024] In some embodiments, the target spliced image is the splicing of two image segments with the same height inside two images in the splicing direction. The two images are both rectangles, and the number of the first sub-images included in the two images is the same. The two image segments are also rectangles;

[0025] The starting address where the first image segment is written into the storage space of the image memory is the third starting address. The row span of the first image in the storage space of the image memory is the first row span, and the width of the first image segment is the width of the third image; The starting address where the second image segment is written into the storage space of the image memory is the fourth starting address. The row span of the second image in the storage space of the image memory is the second row span, and the span of the second image segment is the width of the fourth image;

[0026] During reading, the first address read is the third starting address, and the first sub-image of the first row of the first image segment is continuously read out from the image memory;

[0027] When the width to be read reaches the width of the third image, the read address is mapped to the fourth starting address, and the first sub-image of the first row of the second image segment is continuously read out from the image memory;

[0028] When the width to be read reaches the width of the fourth image, the read address is mapped to the sixth address, and the sixth address is the third starting address plus the span of the first row. Then the first sub-image of the second row of the first image segment is continuously read out from the image memory;

[0029] When the width to be read reaches the width of the third image, the read address is mapped to the seventh address, and the seventh address is the fourth starting address plus the span of the second row. Then the first sub-image of the second row of the second image segment is continuously read out from the image memory;

[0030] And so on. Until the last row of the first image segment is read, the read address is mapped to the eighth address, and the eighth address = the third starting address + (N - 1) the span of the first row, where N is the number of rows of the first image segment. Then the first sub-image of the last row of the first image segment is continuously read out from the image memory;

[0031] When the width to be read reaches the width of the third image, the read address is mapped to the ninth address, and the ninth address = the fourth starting address + (N - 1) the span of the second row, where N is the number of rows of the second image segment. Then the first sub-image of the last row of the second image segment is continuously read out from the image memory.

[0032] In some embodiments, the splicing direction is the height direction of the image, which is used to realize the splicing of at least two rectangular images with the same width in the height direction; or,

[0033] The splicing direction is the height direction of the image, which is used to realize the splicing of rectangular image segments with the same width inside at least two images in the height direction; or,

[0034] The splicing direction is the width direction and the height direction of the image, which is used to realize the splicing of multiple rectangular images or rectangular image segments inside multiple images, and the widths of the rectangular images or rectangular image segments spliced in the height direction are the same, and the heights of the rectangular images or rectangular image segments spliced in the width direction are the same; or,

[0035] The splicing direction is the width direction and height direction of the image, which is used to realize the splicing of multiple rectangular images or rectangular image segments inside multiple images, and the target spliced image after splicing can form a complete rectangular picture.

[0036] In a second aspect, the present application provides an image splicing system, including:

[0037] An image collector, configured to capture a plurality of images to be spliced and write the plurality of images to be spliced into an image memory row by row respectively;

[0038] An image memory, connected to the image collector, for storing the plurality of images to be spliced;

[0039] An image splicing device, connected to the image memory, includes a processor, and the processor is configured to execute a computer program to implement the steps of the image splicing method described in the first aspect;

[0040] A subsequent system, connected to the image splicing device, for receiving the image spliced by the image splicing device.

[0041] In a third aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the image splicing method described in the first aspect.

[0042] In a fourth aspect, the present application provides a computer storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by a processor, the steps of the image splicing method described in the first aspect are implemented.

[0043] According to an image splicing method, system, computer device, and storage medium provided by the present invention, by converting the read and write operations of the image splicing device and the memory into a flexible address mapping for reading the memory, the image data read from the image memory can be directly output to the subsequent system, omitting the process of the image splicing device writing data to the memory and the subsequent system reading memory data, reducing the original two reads and two writes to one read and one write, thereby reducing the occupancy of the memory bus bandwidth during the image splicing process, making the amount of data transmitted on the bus less, and enabling a faster image splicing speed, which is beneficial to improving system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The following will further illustrate the above characteristics, technical features, advantages, and their implementation manners of the solution in a clear and understandable manner in combination with the drawings of the preferred embodiments.

[0045] Figure 1 is a schematic structural diagram of an image splicing system in the prior art;

[0046] Figure 2 It is a schematic diagram of writing an image into an image memory by rows respectively;

[0047] Figure 3 It is a schematic diagram of an image stitching process in the prior art;

[0048] Figure 4 It is another schematic diagram of an image stitching process in the prior art;

[0049] Figure 5 It is yet another schematic diagram of an image stitching process in the prior art;

[0050] Figure 6 It is a schematic diagram of the structure of an image stitching system according to an embodiment of the present invention;

[0051] Figure 7 It is a schematic diagram of the flowchart of an image stitching method according to an embodiment of the present invention;

[0052] Figure 8 It is a schematic diagram of an image stitching method according to an embodiment of the present invention;

[0053] Figure 9 It is a schematic diagram of another image stitching method according to an embodiment of the present invention;

[0054] Figure 10 It is a schematic diagram of yet another image stitching method according to an embodiment of the present invention. Detailed implementation manners

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will describe the specific implementation manners of the present invention with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings, and other implementation manners can be obtained.

[0056] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent the actual structure of the product. Additionally, to make the drawings concise and easy to understand, in some drawings, for components with the same structure or function, only one of them is schematically shown, or only one of them is marked. In this document, "one" not only means "only this one", but also can mean "more than one" situation.

[0057] Refer to the attached Figure 1, the system where the existing image stitching device is located usually consists of an image collector, an image memory, and a subsequent system. The image collector is used to capture image data and may include one or more image acquisition devices, and write the acquired image data into the image memory; the image memory is used to store the original image and the stitched image data; the image stitching device is used to complete image stitching and store the stitched image into the image memory; the stitched image data can be output to the subsequent system.

[0058] However, during the entire image stitching and output process, there are at least two read operations and two write operations, resulting in a relatively large amount of data transmitted on the memory bus during the image stitching process, a large occupancy of the bus bandwidth, and a long stitching time, which affects the system performance. Specifically, refer to the appendix Figures 2 to 5 , taking the example of stitching 2 1080p resolution (1920*1080, about 2M pixel points) images P1 and P2 in the width direction. The width of the image is 1920, and the height of the image is 1080. The storage space occupied by each row of the image in the image memory is the row stride, and the stride should be greater than or equal to the image width. The order of image acquisition and storage is row-by-row processing, that is, the first row line1, the second row line2, until the last row lineN.

[0059] First, the image collector acquires images P1 and P2 and writes them into the image memory. As Figure 2 shown, W1 = W2 = 1920, H1 = H2 = 1080, where the starting address of P1 in the memory is addr1, the stride is P1_stride, the starting address of P2 is addr2, and the stride is P2_stride. To save storage space and meet the system alignment requirements, let the values of P1_stride and P2_stride be the minimum value that satisfies 64B alignment and is greater than or equal to the image width, that is, 1920 (the stride in the figure is slightly larger than the image width, just for illustration). Then the writing process of P1 is: write P1line1, P1line2 until P1lineN, and the total amount of data on the bus during the writing process is about 2M; similarly, the writing process of P2 is similar to that of P1, and the total amount of data on the bus is about 2M.

[0060] The existing image stitching method needs to arrange two images P1 and P2 row by row and then write them into the memory and output image P3 to the subsequent device, involving a process of reading and writing a relatively large amount of data into the memory. Assume that the address of the output image P3 in the memory after stitching is addr3, the image width is W3, the image height is H3, and the stride is P3_stride.

[0061] The specific stitching process is as follows:

[0062] The processing part of P1: Refer to the appendixFigure 3 , first read P1line1, then write it into the memory with the starting address being addr3. Then read P1line2, and write it into the memory with the starting address being addr3 + P3_stride. This process continues until the reading and writing of lineN are completed. The stride during the reading process is P1_stride, and the stride during the writing process is P3_stride. After the reading and writing are completed, the distribution in the memory is as shown in the figure. Therefore, the data volume on the P1 image bus during reading is approximately 2M, and the data volume on the P1 image bus during writing is approximately 2M.

[0063] The processing part of P2: Refer to the appendix Figure 4 , first read P2line1, then write it into the memory with the starting address being addr4 (addr4 = addr3 + W1). Then read P2line2, and write it into the memory with the starting address being addr4 + P3_stride. This process continues until the reading and writing of lineN are completed. The stride during the reading process is P2_stride, and the stride during the writing process is P3_stride. After the reading and writing are completed, the distribution in the memory is as shown in the figure. Therefore, the data volume on the P2 image bus during reading is approximately 2M, and the data volume on the P2 image bus during writing is approximately 2M.

[0064] The processing part of P3: Refer to the appendix Figure 5 , after the processing of the previous two steps, the image stitching is completed. The stitched image P3 is as shown in the figure. Read image P3line1, P3line2, until P3lineN with the starting address addr3. The stride during the reading process is P3_stride. Therefore, the data volume on the P3 image bus during reading is approximately 4M.

[0065] In summary, during the process of image stitching and outputting the stitched image data in the prior art, the total data volume of reading images on the bus is 8M, and the total data volume of writing images is 8M. During the image stitching process, the data volume transmitted on the memory bus is relatively large, occupying a large bus bandwidth, and the stitching time is relatively long, affecting the system performance. Therefore, there is an urgent need for an image stitching method with a faster image stitching speed, less data volume transmitted on the bus, and lower occupied bandwidth.

[0066] Refer to the appendix Figure 6 , this application designs a brand-new image stitching device. By optimizing the stitching method, the image stitching device reads image data from the image memory and directly outputs it to the subsequent system, eliminating the process of the image stitching device writing data to the memory and the subsequent system reading data from the memory. The original two reads and two writes are reduced to one read and one write, thereby reducing the occupation of the memory bus bandwidth during the image stitching process. The optimized stitching method will be described in detail below with reference to the accompanying drawings:

[0067] In one embodiment, referring to the appended drawings of the specification Figure 7 , the present application provides an image stitching method, including the steps of:

[0068] S100. Write a plurality of images to be stitched into an image memory row by row, and each image includes a plurality of first sub-images row by row; the present application does not limit the number of images for stitching, nor does it limit whether a complete image or a part of an image is used for stitching.

[0069] S200. Obtain the starting address of each image written into the storage space of the image memory, and the row stride of the first sub-images of each image in the storage space of the image memory; as Figure 2 shown, when an image is written into the image memory, each image is written independently, and each image writes the respective first sub-images row by row. The row stride of the first sub-images of each image in the storage space of the image memory is not less than the width of the first sub-image, that is, when the image is written row by row, the row stride is not less than the width of the first sub-image.

[0070] S300. Determine the arrangement of each image or at least a part of each image in the stitching direction according to the target stitched image. The target stitched image includes a plurality of second sub-images row by row, and each second sub-image includes at least one first sub-image or a part of a first sub-image.

[0071] S400. Determine the initial address of the first sub-image or the part of the first sub-image included in each second sub-image in the storage space of the image memory according to the starting address of each image written into the storage space of the image memory and the row stride of the first sub-images of each image in the storage space of the image memory; for example, when a complete image is used for stitching, the initial address of the first sub-image in the first row is addr1, and the initial address of the first sub-image in the second row is addr1 + P1_stride, and so on. Another example is that when a part of an image is used for stitching, the row stride of the image is P1_stride, and the initial address of the image segment used for stitching is addr1p, then the initial address of the next row of the image segment is addr1p + P1_stride. This is because each image is written into the image memory row by row, and the row stride is generally not less than the width of the image. Therefore, after determining the stitched image, the initial address of the first sub-image or the part of the first sub-image included in each second sub-image in the storage space of the image memory can be determined according to the starting address and the row stride of the image.

[0072] S500. Read the first sub-image or the part of the first sub-image included in each second sub-image row by row according to the stitching direction, and map the address read each time to the initial address of the current first sub-image or the part of the first sub-image.

[0073] This solution converts the read and write operations of the image stitching device and the memory into a flexible address mapping for reading the memory, enabling the image data read from the image memory to be directly output to the subsequent system, eliminating the processes of the image stitching device writing data to the memory and the subsequent system reading data from the memory, reducing the original two reads and two writes to one read and one write. This reduces the occupancy of the memory bus bandwidth during the image stitching process, resulting in less data transferred on the bus and enabling a faster image stitching speed, which is beneficial for improving system performance.

[0074] In one embodiment, the stitching direction is the width direction of the image, and the target stitched image is the stitching of at least two images in the stitching direction. For example, in a specific implementation, the target stitched image is the stitching of two images in the stitching direction. Both images are rectangular, and the number of first sub-images included in the two images is the same. The first address written into the storage space of the image memory for the first image is the first start address, the row stride of the first image in the storage space of the image memory is the first row stride, the width of the first image is the first image width, the first address written into the storage space of the image memory for the second image is the second start address, the row stride of the second image in the storage space of the image memory is the second row stride, and the width of the second image is the second image width.

[0075] During reading, the first address read is the first start address, and the first sub-images of the first row of the first image are continuously read from the image memory. When the read width reaches the first image width, the read address is mapped to the second start address, and the first sub-images of the first row of the second image are continuously read from the image memory. When the read width reaches the second image width, the read address is mapped to the second address, where the second address is the first start address plus the first row stride, and the first sub-images of the second row of the first image are continuously read from the image memory. When the read width reaches the first image width, the read address is mapped to the third address, where the third address is the second start address plus the second row stride, and the first sub-images of the second row of the second image are continuously read from the image memory. And so on, until the last row of the first image is read, the read address is mapped to the fourth address, where the fourth address = the first start address + (N - 1) the first row stride, N is the number of rows of the first image, and the first sub-images of the last row of the first image are continuously read from the image memory. When the read width reaches the first image width, the read address is mapped to the fifth address, where the fifth address = the second start address + (N - 1) the second row stride, N is the number of rows of the second image, and the first sub-images of the last row of the second image are continuously read from the image memory.

[0076] Also Figure 2Take the stitching of the two images shown as an example. The starting address of image P1 in the image memory is addr1, the image width is W1, the image height is H1, and the stride of the image is W1_stride; similarly, the starting address of image P2 in the memory is addr2, the image width is W2, the image height is H2, and the stride of the image is W2_stride. Taking stitching in the width W direction as an example, usually the heights are equal, H1 = H2, W1_stride is the minimum value greater than or equal to W1 and meeting the alignment requirements of the storage system, and W2_stride is the minimum value greater than or equal to W2 and meeting the alignment requirements of the storage system. When writing P1 and P2, both are written into the image memory row by row, in the order of line1, line2 to lineN. The image stitching is completed by alternately reading row by row, and the process of the image stitching device reading and writing the memory during stitching is converted into an address mapping of reading the memory address. First, the starting address of the memory read is addr1, and image P1_line1 is continuously read out from the image memory. When the read length reaches W1, P1_line1 is read out completely, and the starting address of the memory read is mapped to addr2, and image P2_line1 starts to be continuously read out. When the read length reaches W2, P2_line1 is read out completely, and the starting address of the memory read is mapped to addr1 + P1_stride, and image P1_line2 starts to be continuously read out. When the read length reaches W1, P1_line2 is read out completely, and the starting address of the memory read is mapped to addr2 + P2_stride, and image P2_line2 starts to be continuously read out. Until the last line lineN is read, the starting address of the memory read is mapped to addr1 + (N - 1)*P1_stride, and image P1_lineN starts to be continuously read out; when the read length reaches W1, P1_lineN is read out completely, and the starting address of the memory read is mapped to addr2 + (N - 1)*P2_stride, and P2_lineN starts to be continuously read out. When the read length reaches W2, image P2_lineN is read out completely.

[0077] By comparison, the image data output by this method is exactly the same as the P3 image data after stitching by the traditional scheme. However, when this scheme runs, the data volumes of images P1 and P2 that need to be written are 2M respectively, and the total data volume of the written images is 4M; the data volumes of images P1 and P2 that need to be read are 2M respectively, and the total data volume of the read images is 4M; therefore, the data volume on the bus during the operation of this scheme is half of that of the traditional scheme, effectively reducing the bandwidth requirement of the image stitching device for the system and improving the performance of image stitching.

[0078] In addition, this has strong flexibility and can achieve, in the splicing direction, the splicing of any two image segments with the same height inside images P1 and P2, that is, it can complete cutout splicing.

[0079] In one embodiment, the splicing direction is the width direction of the image, and the target spliced image is the splicing of a part inside at least two images in the splicing direction. In a specific implementation, the target spliced image is the splicing of two image segments with the same height inside two images in the splicing direction. The two images are both rectangles, and the number of first sub-images included in the two images is the same. The two image segments are also rectangles. The first address where the first image segment is written into the storage space of the image memory is the third first address, the row span of the first image in the storage space of the image memory is the first row span, and the width of the first image segment is the third image width; the first address where the second image segment is written into the storage space of the image memory is the fourth first address, the row span of the second image in the storage space of the image memory is the second row span, and the width of the second image segment is the fourth image width.

[0080] When reading, the first address to be read is the third first address, and the first sub-images of the first row of the first image segment are continuously read out from the image memory; when the width to be read reaches the third image width, the read address is mapped to the fourth first address, and the first sub-images of the first row of the second image segment are continuously read out from the image memory; when the width to be read reaches the fourth image width, the read address is mapped to the sixth address, and the sixth address is the third first address plus the first row span, and the first sub-images of the second row of the first image segment are continuously read out from the image memory; when the width to be read reaches the third image width, the read address is mapped to the seventh address, and the seventh address is the fourth first address plus the second row span, and the first sub-images of the second row of the second image segment are continuously read out from the image memory; and so on. Until the last row of the first image segment is read, the read address is mapped to the eighth address, and the eighth address = the third first address + (N - 1) the first row span, where N is the number of rows of the first image segment, and the first sub-images of the last row of the first image segment are continuously read out from the image memory; when the width to be read reaches the third image width, the read address is mapped to the ninth address, and the ninth address = the fourth first address + (N - 1) the second row span, where N is the number of rows of the second image segment, and the first sub-images of the last row of the second image segment are continuously read out from the image memory.

[0081] Specifically, refer to the attached instructions Figure 8, there is an image segment P1_p in the image P1, with a height of Hp, a width of W1p, and a starting address in the memory of addr1p; there is an image segment P2_p in the image P2, with a height of Hp, a width of W2p, and a starting address in the memory of addr2p. When reading, first map the first address of the read memory to addr1p, and start to read out the image P1_p_line1 continuously from the image memory. When the read length reaches W1p, P1_p_line1 is read, and the first address of the read memory is mapped to addr2p, and the image P2_p_line1 is read continuously. When the read length reaches W2p, P2_p_line1 is read, and the first address of the read memory is mapped to addr1p+P1_stride, and the image P1_p_line2 is read continuously. When the read length reaches W1p, P1_p_line2 is read, and the first address of the read memory is mapped to addr2p+P2_stride, and the image P2_p_line2 is read continuously. Until the last line lineN is read, the first address of the read memory is mapped to addr1p+(N-1)*P1_stride, and P1_p_lineN is read continuously. When the read length reaches W1p, P1_p_lineN is read. The first address of the read memory is mapped to addr2p+(N-1)*P2_stride, and P2_p_lineN is read continuously. When the read length reaches W2p, the image P2_p_lineN is read. At this point, the image stitching is completed in the original image.

[0082] The above-mentioned embodiments illustrate that the image stitching device of the present scheme realizes the stitching of images P1 and P2 with the same height in the width W direction, or any two image fragments with the same height within images P1 and P2. However, the present device is very flexible, and can adapt to a variety of situations while maintaining the advantages of low bus data volume and low system bandwidth occupancy. For example, in a specific implementation, the stitching direction is the height direction of the image, which is used to stitch at least two rectangular images with the same width in the height direction; for another example, in a specific implementation, the stitching direction is the height direction of the image, which is used to stitch at least two rectangular image fragments with the same width within the image in the height direction; for another example, in a specific implementation, as shown in the attached Figure 9As shown, the splicing directions are the width direction and the height direction of the image, which are used to implement the splicing of multiple rectangular images or rectangular image segments inside multiple images. Moreover, the widths of the rectangular images or rectangular image segments spliced in the height direction are the same, and the heights of the rectangular images or rectangular image segments spliced in the width direction are the same. That is, P1 and P2 have the same height, P3 and P4 have the same height, P1 and P3 have the same width, and P2 and P4 have the same width. For another example, in a specific implementation, as shown in the appendix Figure 10 As shown, the splicing directions are the height direction and the height direction of the image, which are used to implement the splicing of multiple rectangular images or rectangular image segments inside multiple images. Moreover, the target spliced image after splicing can form a complete rectangular picture. That is, the requirements for the widths and heights of the images P1, P2,... PN or the N image segments inside the images P1, P2,... PN are more flexible, and it is only necessary to be able to form a rectangular picture that meets the output resolution requirements.

[0083] In one embodiment, as Figure 6 As shown, the present application provides an image splicing system, including: an image collector, which is used to capture a plurality of images to be spliced and write the plurality of images to be spliced into an image memory row by row respectively; an image memory, which is connected to the image collector and is used to store the plurality of images to be spliced; an image splicing device, which is connected to the image memory and includes a processor, and the processor is used to execute a computer program to implement the steps of the image splicing method in the foregoing embodiment; a subsequent system, which is connected to the image splicing device and is used to receive the image spliced by the image splicing device.

[0084] In one embodiment, the present application further provides a computer device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the image splicing method in the foregoing embodiment.

[0085] In one embodiment, the present application further provides a computer storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the image splicing method in the foregoing embodiment are implemented.

[0086] In one embodiment, the present application further provides a computer program product, including a computer program or instruction. When the computer program or instruction is executed by a processor, the steps of the image splicing method in the foregoing embodiment are implemented.

[0087] In the foregoing embodiments, the processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0088] The memory may be an internal storage unit of the simulation system, such as: the hard disk or memory of the intelligent device. The memory may also be an external storage device of the intelligent device, such as: the plug-in hard disk equipped on the intelligent device, SmartMedia Card (SMC), Secure Digital (SD) card, Flash Card, etc. Further, the memory is used to store the computer program and other programs and data required for the verification method of the FPGA. The memory may also be used to temporarily store the data that has been output or is to be output.

[0089] A communication bus is a circuit that connects the described elements and enables transmission between these elements. For example, a central processing unit receives commands from other elements via the communication bus, decrypts the received commands, and performs calculations or data processing based on the decrypted commands. The memory may include program modules, such as a kernel, middleware, an Application Programming Interface (API), and applications. These program modules can be composed of software, firmware, hardware, or at least two of them. The input / output interface forwards commands or data input by the user through the input / output interface (such as sensors, keyboards, touchscreens). The communication interface connects the rotational speed measurement device of this artificial heart to other network devices, user devices, and networks. For example, the communication interface can be connected to a network through a wired or wireless connection to connect to other external network devices or user devices. Wireless communication can include at least one of the following sparse matrix solution methods, computer devices, storage media, and program products: Wi-Fi (Wireless Fidelity), Bluetooth (BT), Near Field Communication (NFC), Global Positioning System (GPS), and cellular communication, etc. Wired communication can include at least one of the following sparse matrix solution methods, computer devices, storage media, and program products: Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Asynchronous Transmission Standard Interface (RS-232), etc. The network can be a telecommunications network and a communication network. The communication network can be a computer network, the Internet, the Internet of Things, or a telephone network. The verification device of the FPGA can be connected to the network through the communication interface, and the protocol used for communication between the rotational speed measurement device of the artificial heart and other network devices can be supported by at least one of the application, the Application Programming Interface (API), middleware, the kernel, and the communication interface.

[0090] The image stitching method of this application can be implemented with program codes executable by a computing device. Thus, they can be stored in a storage device for execution by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

[0091] It should be noted that the above-mentioned embodiments can be freely combined as needed. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An image stitching method, characterized in that: Includes steps: Writing a plurality of images to be spliced ​​into an image memory row by row, each image including a plurality of first sub-images row by row; Acquire the first address of each image written into the storage space of the image memory, and the row span of the first sub-image of each image in the storage space of the image memory; Determining the arrangement of each image or at least a part of each image in a stitching direction according to a target stitching image, wherein the target stitching image includes a plurality of second sub-images in a row, and each of the second sub-images includes at least one of the first sub-images or a part of the first sub-image; Determine, according to the first address of each image written into the storage space of the image memory and the row span of the first sub-image of each image in the storage space of the image memory, the initial address of the first sub-image or a part of the first sub-image included in each second sub-image in the storage space of the image memory; The first sub-image or a part of the first sub-image contained in each second sub-image is read row by row in sequence according to the stitching direction, and the address read each time is mapped to the initial address of the current first sub-image or a part of the first sub-image.

2. The image stitching method according to claim 1, characterized in that: The row span of the first sub-image of each image in the storage space of the image memory is not less than the width of the first sub-image.

3. The image stitching method according to claim 1, characterized in that: The stitching direction is the width direction of the image, and the target stitching image is the stitching of at least two images in the stitching direction.

4. The image stitching method according to claim 3, characterized in that: The target stitching image is a stitching of two images in the stitching direction, both images are rectangular, and the two images include the same number of the first sub-images; The first address of the first image written into the storage space of the image memory is the first first address, the row span of the first image in the storage space of the image memory is the first row span, and the width of the first image is the first image width; the first address of the second image written into the storage space of the image memory is the second first address, the row span of the second image in the storage space of the image memory is the second row span, and the width of the second image is the second image width; When reading, the first address read is the first first address, and the first sub-image of the first row of the first image is continuously read out from the image memory; When the read width reaches the first image width, mapping the read address to the second first address, and continuously reading out the first sub-image of the first row of the second image from the image memory; When the read width reaches the second image width, mapping the read address to a second address, the second address being the first first address plus the first row span, and continuously reading out the first sub-image of the second row of the first image from the image memory; When the read width reaches the first image width, mapping the read address to a third address, the third address being the second first address plus the second row span, and continuously reading out the first sub-image of the second row of the second image from the image memory; And so on, until the last line of the first image is read, the read address is mapped to a fourth address, the fourth address = the first first address + (N-1) the first line span, N is the number of lines of the first image, and the first sub-image of the last line of the first image is continuously read out from the image memory; When the read width reaches the width of the first image, the read address is mapped to the fifth address, the fifth address = the second first address + (N-1) the second row span, N is the number of rows of the second image, and the first sub-image of the last row of the second image is continuously read out from the image memory.

5. The image stitching method according to claim 1, characterized in that: The stitching direction is the width direction of the image, and the target stitching image is the stitching of a portion of at least two images in the stitching direction.

6. The image stitching method according to claim 5, characterized in that: The target stitched image is a stitching of two image segments with the same internal height in two images in the stitching direction, both images are rectangular, and the two images include the same number of the first sub-images, and the two image segments are also rectangular; The first address at which the first image fragment is written into the storage space of the image memory is the third first address, the row span of the first image in the storage space of the image memory is the first row span, and the width of the first image fragment is the third image width; the first address at which the second image fragment is written into the storage space of the image memory is the fourth first address, the row span of the second image in the storage space of the image memory is the second row span, and the width of the second image fragment is the fourth image width; When reading, the first address read is the third first address, and the first sub-image of the first row of the first image segment is continuously read out from the image memory; When the read width reaches the third image width, mapping the read address to the fourth first address, and continuously reading out the first sub-image of the first row of the second image segment from the image memory; When the read width reaches the fourth image width, mapping the read address to a sixth address, the sixth address being the third first address plus the first row span, and continuously reading out the first sub-image of the second row of the first image segment from the image memory; When the read width reaches the third image width, mapping the read address to a seventh address, the seventh address being the fourth first address plus the second row span, and continuously reading out the first sub-image of the second row of the second image segment from the image memory; And so on, until the last row of the first image segment is read, the read address is mapped to the eighth address, the eighth address = the third first address + (N-1) the first row span, N is the number of rows of the first image segment, and the first sub-image of the last row of the first image segment is continuously read out from the image memory; When the read width reaches the third image width, the read address is mapped to the ninth address, the ninth address = the fourth first address + (N-1) the second row span, N is the number of rows of the second image fragment, and the first sub-image of the last row of the second image fragment is continuously read out from the image memory.

7. The image stitching method according to claim 1, characterized in that: The stitching direction is the height direction of the image, which is used to stitch at least two rectangular images with the same width in the height direction; or, The stitching direction is the height direction of the image, and is used to stitch rectangular image segments with the same width inside at least two images in the height direction; or, The stitching direction is the width direction and the height direction of the image, and is used to stitch multiple rectangular images or rectangular image fragments within multiple images, and the widths of the rectangular images or rectangular image fragments stitched in the height direction are the same, and the heights of the rectangular images or rectangular image fragments stitched in the width direction are the same; or, The stitching direction is the width direction and the height direction of the image, and is used to stitch multiple rectangular images or rectangular image fragments within multiple images, and the target stitched image after stitching can form a complete rectangular picture.

8. An image stitching system, characterized in that: include: An image collector is used to capture a plurality of images to be spliced, and write the plurality of images to be spliced ​​into an image memory row by row; An image storage device connected to the image collector and used for storing a plurality of images to be spliced; An image stitching device, connected to the image memory, comprising a processor, wherein the processor is used to execute a computer program to implement the steps of the image stitching method according to any one of claims 1 to 7; The post-stage system is connected to the image stitching device and is used to receive the images stitched by the image stitching device.

9. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the image stitching method according to any one of claims 1 to 7.

10. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the image stitching method according to any one of claims 1 to 7 are implemented.

Images