Pixel unit, display panel, and display device

Abstract

The present invention proposes a pixel unit, a display panel and a display device, wherein the pixel unit includes a pixel electrode, a storage capacitor, a first switching circuit, a switching output circuit and a flip circuit. During the line-by-line scanning of the previous frame, the pixel unit of the current row can receive a line start signal and a data signal, and the flip circuit can switch to output a first level signal. At this time, the first switching circuit and the switching output circuit are switched accordingly and output a first drive signal to the pixel electrode. During the line-by-line scanning of the next frame, the flip circuit switches to output a second level signal. At this time, the first switching circuit and the switching output circuit are switched accordingly and output a second drive signal with a polarity opposite to the first drive signal to the pixel electrode. The pixel electrode can form a drive voltage with a polarity opposite to that of the common electrode layer on the color film substrate to drive the liquid crystal layer in the previous and next frames. Polarity switching is achieved through switch switching, thereby reducing the charging and discharging power consumption of the storage capacitor.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a pixel unit, a display panel and a display device. Background Art

[0002] Liquid crystal display panels have the advantages of high resolution, accurate color reproduction, simple structure, and high stability. Traditional liquid crystal display panels achieve different grayscale displays by controlling the deflection of liquid crystal molecules to control the amount of polarized light passing through.

[0003] In a liquid crystal display panel, a voltage is applied across the liquid crystal layer to drive the liquid crystal molecules to rotate. If a single electric field is applied to the liquid crystal molecules for a long time, the molecules will polarize. This polarization can cause changes in the liquid crystal's response characteristics, such as slower response speed and uneven display. Therefore, polarity switching is necessary to prevent polarization of the liquid crystal molecules.

[0004] When switching polarity, the storage capacitor in the pixel unit needs to perform a large-amplitude charge and discharge operation to ensure that the liquid crystal pixel displays according to the correct polarity. The large-amplitude charge and discharge operation increases circuit power consumption. Summary of the Invention

[0005] An object of the present invention is to provide a pixel unit, aiming to solve the problem of high power consumption of traditional pixel units when switching polarity.

[0006] A first aspect of an embodiment of the present invention provides a pixel unit, including:

[0007] pixel electrode;

[0008] Storage capacitor;

[0009] a first switching circuit, connected to the data line and the storage capacitor, respectively, the first switching circuit being configured to transmit the data signal on the data line to the second end of the storage capacitor upon receiving a first level signal, or to transmit the data signal to the first end of the storage capacitor upon receiving a second level signal, or to trigger shutdown upon receiving a row-off signal;

[0010] a switching output circuit, connected to the common electrode terminal, the storage capacitor, and the pixel electrode, respectively, the switching output circuit being configured to transmit the common electrode voltage at the common electrode terminal to the first terminal of the storage capacitor when receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor and output the voltage of the first terminal of the storage capacitor to the pixel electrode when receiving the second level signal or the row off signal;

[0011] A flip circuit is respectively connected to the scan line, the first switching circuit and the switching output circuit. The flip circuit is used to output the first level signal or the second level signal when receiving the row start signal transmitted by the scan line, and switch the polarity of the output level when receiving the row start signal again, or output the row close signal when receiving the row close signal transmitted by the scan line.

[0012] Optionally, the first switching circuit includes a first transistor and a second transistor;

[0013] The first end of the first transistor, the first end of the second transistor and the data line are connected, the second end of the first transistor is connected to the first end of the storage capacitor, the second end of the second transistor is connected to the second end of the storage capacitor, and the control end of the first transistor and the control end of the second transistor are connected together to form the control end of the first switching circuit.

[0014] Optionally, the switching output circuit includes:

[0015] a switch circuit, wherein an input end of the switch circuit is connected to an output end of the flip circuit, and the switch circuit is configured to be triggered to be turned on upon receiving a third level signal of the pulse control signal, or to be triggered to be turned off upon receiving a fourth level signal of the pulse control signal;

[0016] a bias circuit connected to the output end of the switch circuit, the bias circuit being configured to bias the voltage at the output end of the switch circuit to a preset potential when the switch circuit is in an off state;

[0017] a second switching circuit, connected to the common electrode terminal, the switch circuit, the bias circuit, and the storage capacitor, respectively, the second switching circuit being configured to transmit the common electrode voltage to the first terminal of the storage capacitor upon receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor upon receiving the preset potential;

[0018] an output circuit connected between the first end of the storage capacitor and the pixel electrode, the output circuit further connected to the output end of the switching circuit, the output circuit configured to trigger a shutdown upon receiving the first level signal, or trigger a conduction upon receiving the preset potential and transmit the voltage at the first end of the storage capacitor to the pixel electrode;

[0019] The cycle time of the pulse control signal is two frames long. The pulse control signal in each cycle time is composed of a third level signal and a fourth level signal. The phase of the third level signal is the same as the phase of the row start signal of the previous frame in the two frame length.

[0020] Optionally, the switching circuit includes a third transistor;

[0021] The first end of the third transistor constitutes the input end of the switch circuit, the control end of the third transistor is used to receive the pulse control signal, and the second end of the third transistor constitutes the output end of the switch circuit.

[0022] Optionally, the bias circuit includes a bias resistor;

[0023] The first end of the bias resistor is connected to the output end of the switch circuit, the control end of the output circuit and the control end of the second switching circuit respectively, and the second end of the bias resistor is used to input a preset potential.

[0024] Optionally, the second switching circuit includes a fourth transistor and a fifth transistor;

[0025] The first end of the fourth transistor, the first end of the fifth transistor and the common electrode end are connected, the second end of the fourth transistor is connected to the second end of the storage capacitor, the second end of the fifth transistor is connected to the first end of the storage capacitor, and the control end of the fourth transistor and the control end of the fifth transistor are connected to form the control end of the second switching circuit.

[0026] Optionally, the output circuit includes a sixth transistor;

[0027] The first end of the sixth transistor is connected to the first end of the storage capacitor, the second end of the sixth transistor is connected to the pixel electrode, and the control end of the sixth transistor constitutes the control end of the output circuit.

[0028] Optionally, the flip circuit includes a seventh transistor, an eighth transistor and a ninth transistor;

[0029] The first end of the seventh transistor and the first end of the eighth transistor are connected to the scan line, the second end of the seventh transistor and the second end of the ninth transistor are commonly connected to form the output end of the flip circuit, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control end of the seventh transistor and the control end of the eighth transistor are used to input a pulse control signal, and the first end of the ninth transistor is used to input the first level signal.

[0030] A second aspect of an embodiment of the present invention provides a display panel, comprising a plurality of scan lines, a plurality of data lines, and a plurality of pixel units as described above, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.

[0031] A third aspect of the embodiments of the present invention provides a display device, including a display panel driving circuit and the display panel as described above, wherein the display panel driving circuit is connected to the display panel.

[0032] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: the above-mentioned pixel unit includes a pixel electrode, a storage capacitor, a first switching circuit, a switching output circuit and a flip circuit. During the line-by-line scanning of the previous frame, the pixel unit of the current row can receive a line start signal and a data signal, and the flip circuit can switch to output a first level signal. At this time, the first switching circuit and the switching output circuit are switched accordingly, and a first drive signal is output to the pixel electrode. During the line-by-line scanning of the next frame, the flip circuit switches to output a second level signal. At this time, the first switching circuit and the switching output circuit are switched accordingly, and a second drive signal with a polarity opposite to the first drive signal is output to the pixel electrode. The pixel electrode can form a drive voltage with a polarity opposite to that of the common electrode layer on the color film substrate to drive the liquid crystal layer in the two previous and next frames. The polarity switching is achieved by switching the switch, thereby reducing the charging and discharging power consumption of the storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic structural diagram of a display panel provided in Embodiment 1 and Embodiment 4 of the present invention;

[0034] Figure 2 A schematic structural diagram of a pixel unit provided in the first embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the signal timing of a pixel unit provided in the first embodiment of the present invention;

[0036] Figure 4 A schematic structural diagram of a pixel unit provided in the second embodiment of the present invention;

[0037] Figure 5 A schematic diagram of the signal timing of the pixel unit provided in the second and third embodiments of the present invention;

[0038] Figure 6 A circuit diagram of a pixel unit provided in a third embodiment of the present invention;

[0039] Figure 7 This is a structural diagram of a display device provided in Example 5 of the present invention.

[0040] Among them, the reference numerals in the figures are:

[0041] 100, display panel; 200, display panel driving circuit; 210, source driving circuit; 220, gate driving circuit; 230, timing controller; 10, pixel unit; 11, pixel electrode; 12, first switching circuit; 13, switching output circuit; 14, flip circuit; 131, switch circuit; 132, bias circuit; 133, second switching circuit; 134, output circuit;

[0042] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; Cst, storage capacitor; S, data line; G, scan line;

[0043] t11, the first time period of the first frame; t12, the second time period of the first frame; t21, the first time period of the second frame; t22, the second time period of the second frame;

[0044] Vgate, row scan signal; Vdata, data signal; Vcom, common electrode voltage; VG, row turn-on signal; VL, row turn-off signal; V1, first level signal; V2, second level signal; V3, third level signal; V4, fourth level signal; Vref, preset potential; Ctr1, output signal of the flip circuit; Ctr2, pulse control signal; Vout, output signal of the output circuit. DETAILED DESCRIPTION

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] The terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0047] Example 1

[0048] A first aspect of an embodiment of the present invention provides a pixel unit 10, such as Figure 1As shown, the pixel units 10 are arranged in an array on an array substrate of a display panel 100. The array substrate also includes a plurality of scan lines G, a plurality of data lines S, and a common electrode terminal. The common electrode terminal has a common electrode voltage Vcom1. Each pixel unit 10 is connected to a data line S and a scan line G respectively. The display panel 100 also includes a color filter substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the color filter substrate. Figure 2 As shown, the pixel unit 10 includes a pixel electrode 11, a color filter layer and a common electrode layer are provided on the color filter substrate, the common electrode layer has a second common electrode voltage, and a plurality of scanning lines G are used to input a row start signal VG to the pixel units 10 of each row row by row, and when the pixel units 10 of each row receive the row start signal VG, the data line S outputs a data signal Vdata of corresponding size to the pixel units 10 of the corresponding row, and the pixel unit 10 generates a corresponding driving signal to the pixel electrode 11 based on the received row start signal VG and the data signal Vdata. The driving signal input to the pixel electrode 11 and the second common electrode voltage form a driving voltage, and drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display the corresponding image information.

[0049] In an optional embodiment, the common electrode voltage Vcom is equal to the second common electrode voltage, such as 5V, 8V, etc.

[0050] Among them, the row-on signal VG is opposite to the row-off signal VL. During row-by-row scanning, multiple scan lines G receive the row-on signal VG in sequence according to the corresponding timing, and other rows that are not selected for scanning input the row-off signal VL. The row-on signal VG and the row-off signal VL constitute the row scanning signal Vgate.

[0051] In order to reduce the power consumption of the pixel unit 10, in this embodiment, as shown in FIG. Figure 2 As shown, the pixel unit 10 includes:

[0052] pixel electrode 11;

[0053] Storage capacitor Cst;

[0054] a first switching circuit 12 connected to the data line S and the storage capacitor Cst, respectively, and configured to transmit the data signal Vdata on the data line S to the second end of the storage capacitor Cst upon receiving a first level signal V1, or transmit the data signal Vdata to the first end of the storage capacitor Cst upon receiving a second level signal V2, or trigger shutdown upon receiving a line-off signal VL;

[0055] a switching output circuit 13, connected to the common electrode terminal, the storage capacitor Cst, and the pixel electrode 11, respectively. The switching output circuit 13 is configured to transmit a common electrode voltage Vcom at the common electrode terminal to the first terminal of the storage capacitor Cst when receiving a first level signal V1, or transmit the common electrode voltage Vcom to the second terminal of the storage capacitor Cst and output the voltage of the first terminal of the storage capacitor Cst to the pixel electrode 11 when receiving a second level signal V2 or a line-off signal VL;

[0056] The flipping circuit 14 is respectively connected to the scan line G, the first switching circuit 12 and the switching output circuit 13. The flipping circuit 14 is used to output the first level signal V1 or the second level signal V2 when receiving the row start signal VG transmitted by the scan line G, and switch the polarity of the output level when receiving the row start signal VG again, or output the row close signal VL when receiving the row close signal VL transmitted by the scan line G.

[0057] In this embodiment, Figure 3 As shown, the first level signal V1 and the second level signal V2 are high and low level signals with opposite polarities.

[0058] For each pixel unit 10, each frame includes a first period and a second period. In the first period, a row start signal VG is input to realize row-by-row start, and in the second period, a row stop signal VL is input. In each frame, the first period of a single pixel unit 10 is shorter than the second period.

[0059] The first switching circuit 12 has an input end, a first output end, and a second output end. The input end of the first switching circuit 12 is connected to the data line S and is used to input the data signal Vdata. The first output end of the first switching circuit 12 is connected to the first end of the storage capacitor Cst. The second output end of the first switching circuit 12 is connected to the second end of the storage capacitor Cst.

[0060] The switching output circuit 13 has an input end, a first output end, a second output end and a third output end. The input end of the switching output circuit 13 is connected to the common electrode end and is used to input the common electrode voltage Vcom. The first output end of the switching output circuit 13 is connected to the first end of the storage capacitor Cst. The second output end of the switching output circuit 13 is connected to the second end of the storage capacitor Cst. The third output end of the switching output circuit 13 is connected to the pixel electrode 11.

[0061] Assume that in the first period t11 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row start signal VG, and the output signal Ctr1 of the flip circuit 14 is the first level signal V1. At this time, after receiving the first level signal V1, the first switching circuit 12 triggers the connection between its own input terminal and the second output terminal, and transmits the data signal Vdata to the second terminal of the storage capacitor Cst. After receiving the first level signal V1, the switching output circuit 13 triggers the connection between its own input terminal and the first output terminal, and transmits the common electrode voltage Vcom to the first terminal of the storage capacitor Cst. At this time, the voltage difference between the first terminal and the second terminal of the storage capacitor Cst is:

[0062] ΔV=Vcom-Vdata;

[0063] In the second time period t12 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row shutdown signal VL. At this time, the flip circuit 14 switches to output the row shutdown signal VL. The first switching circuit 12 remains in the off state after receiving the row shutdown signal VL. After receiving the row shutdown signal VL, the switching output circuit 13 triggers the connection between its own input end and the second output end, and connects the first end of the storage capacitor Cst and the pixel electrode 11, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst, and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom-Vdata, the voltage of the second end of the storage capacitor Cst is Vcom. Therefore, the voltage of the first end of the storage capacitor Cst is 2*Vcom-Vdata, that is, the output signal Vout of the switching output circuit 13 is 2*Vcom-Vdata.

[0064] The pixel electrode 11 and the common electrode layer of the color filter layer form a first driving voltage, and the first driving voltage is:

[0065] VData1=2*Vcom-Vdata-Vcom;

[0066] That is, the first driving voltage VData1 is -(Vdata-Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V and the data signal Vdata is 10V, the first driving voltage is -2V.

[0067] When the current frame scan ends and switches to the second frame, in the first period t21 of the second frame, the flip circuit 14 receives another row start signal VG, and the output signal Ctr1 of the flip circuit 14 switches to the second level signal V2 and outputs it to the first switching circuit 12 and the switching output circuit 13. At this time, the first switching circuit 12 switches to connect its own input terminal and the first output terminal and transmits the data signal Vdata of the current frame to the first terminal of the storage capacitor Cst. The switching output circuit 13 switches to connect its own input terminal and the second output terminal and transmits the common electrode voltage Vcom to the second terminal of the storage capacitor Cst, and outputs the voltage of the first terminal of the storage capacitor Cst to the pixel electrode 11. At this time, the voltage difference between the first terminal and the second terminal of the storage capacitor Cst is:

[0068] ΔV=Vdata-Vcom;

[0069] In the second period t22 of the second frame, the flip circuit 14 receives the row-off signal VL and converts and outputs the row-off signal VL. The first switching circuit 12 is triggered to shut down. After receiving the row-off signal VL, the switching output circuit 13 maintains its own input end and second output end. The voltage at the first end of the storage capacitor Cst is maintained at Vdata. After receiving the row-off signal VL, the first end of the storage capacitor Cst is connected to the pixel electrode 11, and the voltage at the first end of the storage capacitor Cst is output to the pixel electrode 11. The output signal Vout of the switching output circuit 13 is Vdata. The pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is:

[0070] VData1=Vdata-Vcom;

[0071] For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, the data signal Vdata is 10V, and the second driving voltage is 2V, the first driving voltage and the second driving voltage have the same absolute value but opposite polarity.

[0072] By analogy, in subsequent odd frames, the pixel unit 10 operates according to the working timing and signal flow of the first frame, and switches to output the first driving voltage, and in subsequent even frames, the pixel unit 10 operates according to the working timing and signal flow of the second frame, and switches to output the second driving voltage with opposite polarity.

[0073] By setting the flip circuit 14, the first switching circuit 12 and the switching output circuit 13, two adjacent frames can be used as a frame cycle. During the frame scanning process, the polarity of the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0074] Among them, the flip circuit 14, the first switching circuit 12, and the switching output circuit 13 can adopt corresponding switching circuits 131, switching devices, etc. The flip circuit 14 can adopt structures such as latches, triggers, and logic gates, and the specific structure is not limited.

[0075] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned pixel unit 10 includes a pixel electrode 11, a storage capacitor Cst, a first switching circuit 12, a switching output circuit 13 and a flip circuit 14. During the previous frame of progressive scanning, the pixel unit 10 of the current row can receive a row start signal VG and a data signal Vdata, and the flip circuit 14 can switch to output a first level signal V1. At this time, the first switching circuit 12 and the switching output circuit 13 are switched accordingly and output a first drive signal to the pixel electrode 11. During the next frame of progressive scanning, the flip circuit 14 switches to output a second level signal V2. At this time, the first switching circuit 12 and the switching output circuit 13 are switched accordingly and output a second drive signal with a polarity opposite to the first drive signal to the pixel electrode 11. The pixel electrode 11 can form a drive voltage with a polarity opposite to that of the common electrode layer on the color filter substrate to drive the liquid crystal layer in the previous and next frames. Polarity switching is achieved through switching, thereby reducing the charging and discharging power consumption of the storage capacitor Cst.

[0076] Example 2

[0077] In an optional embodiment, the switching output circuit 13 includes:

[0078] a switch circuit 131, wherein the input end of the switch circuit 131 is connected to the output end of the flip circuit 14, and the switch circuit 131 is configured to be triggered to be turned on upon receiving the third level signal V3 of the pulse control signal Ctr2, or to be triggered to be turned off upon receiving the fourth level signal V4 of the pulse control signal Ctr2;

[0079] a bias circuit 132 connected to the output end of the switch circuit 131 , and configured to bias the voltage at the output end of the switch circuit 131 to a preset potential Vref when the switch circuit 131 is in an off state;

[0080] a second switching circuit 133 connected to the common electrode terminal, the switch circuit 131, the bias circuit 132, and the storage capacitor Cst, respectively. The second switching circuit 133 is configured to transmit the common electrode voltage Vcom to the first terminal of the storage capacitor Cst upon receiving the first level signal V1, or to transmit the common electrode voltage Vcom to the second terminal of the storage capacitor Cst upon receiving the preset potential Vref;

[0081] an output circuit 134 connected between the first end of the storage capacitor Cst and the pixel electrode 11, and further connected to the output end of the switch circuit 131. The output circuit 134 is configured to be turned off upon receiving a first level signal V1, or turned on upon receiving a preset potential Vref and transmit the voltage at the first end of the storage capacitor Cst to the pixel electrode 11;

[0082] The cycle time of the pulse control signal Ctr2 is two frames. The pulse control signal Ctr2 in each cycle time is composed of a third level signal V3 and a fourth level signal V4. The phase of the third level signal V3 is the same as the phase of the row start signal VG of the previous frame in the two frame length.

[0083] In this embodiment, the second switching circuit 133 has an input end, a first output end and a second output end. The input end of the first switching circuit 12 is connected to the common electrode end and is used to input the common electrode voltage Vcom. The first output end of the second switching circuit 133 is connected to the first end of the storage capacitor Cst. The second output end of the second switching circuit 133 is connected to the second end of the storage capacitor Cst.

[0084] Assume that in the first period t11 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row start signal VG, and the output signal Ctr1 of the flip circuit 14 is the first level signal V1. At this time, after receiving the first level signal V1, the first switching circuit 12 triggers to connect its own input terminal and the second output terminal, and transmits the data signal Vdata to the second terminal of the storage capacitor Cst. When the switch circuit 131 receives the first level signal V1, the pulse control signal Ctr2 is the third level signal V3. The switch circuit 131 is triggered to turn on and transmits the first level signal V1 to the second switching circuit 133 and the output circuit 134. The output circuit 134 is triggered to turn off. The second switching circuit 133 is triggered to connect its own input terminal and the first output terminal, and transmits the common electrode voltage Vcom to the first terminal of the storage capacitor Cst. At this time, the voltage difference between the first terminal and the second terminal of the storage capacitor Cst is:

[0085] ΔV=Vcom-Vdata;

[0086] In the second period t12 of the first frame, the flip circuit 14 of the pixel unit 10 in the current row receives the row-off signal VL. At this time, the flip circuit 14 switches to output the row-off signal VL. The first switching circuit 12 remains in the off state after receiving the row-off signal VL. At this time, the switch circuit 131 receives the fourth level signal V4, the switch circuit 131 is triggered to turn off, the bias circuit 132 biases the control end of the second switching circuit 133 and the control end of the output circuit 134 to the preset potential Vref, the second switching circuit 133 is triggered to connect its own input end and the second output end, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 connects the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom-Vdata, the voltage at the second end of the storage capacitor Cst is Vcom. Therefore, the voltage at the first end of the storage capacitor Cst is 2*Vcom-Vdata.

[0087] The pixel electrode 11 and the common electrode layer of the color filter layer form a first driving voltage, and the first driving voltage is:

[0088] VData1=2*Vcom-Vdata-Vcom;

[0089] That is, the first driving voltage VData1 is -(Vdata-Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V and the data signal Vdata is 10V, the first driving voltage is -2V.

[0090] When the current frame scan ends and switches to the second frame, in the first period t21 of the second frame, the flip circuit 14 receives another row start signal VG, and the flip circuit 14 switches to output the second level signal V2 to the first switching circuit 12 and the switching output circuit 13. At this time, the first switching circuit 12 switches to connect its own input end and the first output end and transmits the data signal Vdata of the current frame to the first end of the storage capacitor Cst. The switch circuit 131 continues to receive the fourth level signal V4 and remains in the off state. At this time, the bias circuit 132 biases the control end of the second switching circuit 133 and the control end of the output circuit 134 to the preset potential Vref. The second switching circuit 133 triggers to connect its own input end and the second output end, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 connects the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. The voltage difference between the first end and the second end of the storage capacitor Cst is:

[0091] ΔV=Vdata-Vcom;

[0092] During the second period t22 of the second frame, the flip circuit 14 receives the line-off signal VL and converts and outputs the line-off signal VL. The first switching circuit 12 is triggered to turn off, and the switch circuit 131 continues to receive the fourth level signal V4 and remains in the off state. At this time, the bias circuit 132 biases the control end of the second switching circuit 133 and the control end of the output circuit 134 to the preset potential Vref. The second switching circuit 133 continues to transmit the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 continues to connect the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. The voltage of the first end of the storage capacitor Cst is maintained at Vdata. The pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is:

[0093] VData1=Vdata-Vcom;

[0094] For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, the data signal Vdata is 10V, and the second driving voltage is 2V, the first driving voltage and the second driving voltage have the same absolute value but opposite polarity.

[0095] By analogy, in subsequent odd frames, the pixel unit 10 operates according to the working timing and signal flow of the first frame, and switches to output the first driving voltage, and in subsequent even frames, the pixel unit 10 operates according to the working timing and signal flow of the second frame, and switches to output the second driving voltage with opposite polarity.

[0096] By setting the flip circuit 14, the first switching circuit 12, the second switching circuit 133, the switch circuit 131, the output circuit 134 and the bias circuit 132, two adjacent frames can be used as a frame cycle, and during the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0097] Example 3

[0098] In an alternative embodiment, if Figure 6 As shown, the first switching circuit 12 includes a first transistor T1 and a second transistor T2;

[0099] A first end of the first transistor T1 and a first end of the second transistor T2 are connected to the data line S, a second end of the first transistor T1 is connected to the first end of the storage capacitor Cst, a second end of the second transistor T2 is connected to the second end of the storage capacitor Cst, and a control end of the first transistor T1 and a control end of the second transistor T2 are connected together to form a control end of the first switching circuit 12.

[0100] The switch circuit 131 includes a third transistor T3;

[0101] A first end of the third transistor T3 constitutes an input end of the switch circuit 131 , a control end of the third transistor T3 is used to receive the pulse control signal Ctr2 , and a second end of the third transistor T3 constitutes an output end of the switch circuit 131 .

[0102] The bias circuit 132 includes a bias resistor R1;

[0103] A first end of the bias resistor R1 is connected to the output end of the switch circuit 131 , the control end of the output circuit 134 , and the control end of the second switch circuit 133 , respectively. A second end of the bias resistor R1 is used to input a preset potential Vref.

[0104] The second switching circuit 133 includes a fourth transistor T4 and a fifth transistor T5;

[0105] The first end of the fourth transistor T4, the first end of the fifth transistor T5 and the common electrode end are connected, the second end of the fourth transistor T4 is connected to the second end of the storage capacitor Cst, the second end of the fifth transistor T5 is connected to the first end of the storage capacitor Cst, and the control end of the fourth transistor T4 and the control end of the fifth transistor T5 are connected to form the control end of the second switching circuit 133.

[0106] The output circuit 134 includes a sixth transistor T6;

[0107] A first end of the sixth transistor T6 is connected to the first end of the storage capacitor Cst, a second end of the sixth transistor T6 is connected to the pixel electrode 11 , and a control end of the sixth transistor T6 constitutes a control end of the output circuit 134 .

[0108] The flip circuit 14 includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9;

[0109] A first end of the seventh transistor T7 and a first end of the eighth transistor T8 are connected to the scan line G, a second end of the seventh transistor T7 and a second end of the ninth transistor T9 are commonly connected to form an output end of the flip circuit 14, a second end of the eighth transistor T8 is connected to a control end of the ninth transistor T9, the control end of the seventh transistor T7 and the control end of the eighth transistor T8 are used to input the pulse control signal Ctr2, and a first end of the ninth transistor T9 is used to input the first level signal V1.

[0110] In this embodiment, Figure 5As shown, in order to ensure that the first transistor T1 and the second transistor T2 are triggered to turn off when receiving the row shutdown signal VL, the voltage of the row shutdown signal VL is zero, and the first transistor T1 and the second transistor T2 both remain in the off state when receiving zero voltage, and switch on accordingly when receiving a high level or a low level.

[0111] Among them, the first level signal V1 and the second level signal V2 are opposite level signals, for example, the first level signal V1 is a low level signal, and the second level signal V2 is a high level signal. In an optional embodiment, the row start signal VG is the second level signal V2, and the second level signal V2 is a high level.

[0112] Assume that in the first time period t11 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row start signal VG, the seventh transistor T7 and the eighth transistor T8 receive the third level signal V3 of the pulse control signal Ctr2, the eighth transistor T8 is triggered to turn on, the seventh transistor T7 is triggered to turn off, the row start signal VG is transmitted to the ninth transistor T9 through the eighth transistor T8, the ninth transistor T9 is triggered to turn on, and the first level signal V1 is transmitted to the first switching circuit 12 and the switch circuit 131.

[0113] When the first transistor T1 and the second transistor T2 receive the first level signal V1, the first transistor T1 is triggered to turn off and the second transistor T2 is triggered to turn on. The first switching circuit 12 transmits the data signal Vdata to the second end of the storage capacitor Cst. At the same time, the third transistor T3 of the switch circuit 131 receives the third level signal V3 and is triggered to turn on, and transmits the first level signal V1 to the second switching circuit 133 and the output circuit 134. At this time, the fifth transistor T5 of the second switching circuit 133 is triggered to turn on and the fourth transistor T4 is triggered to turn off, transmitting the common electrode voltage Vcom to the first end of the storage capacitor Cst. At this time, the voltage difference between the first end and the second end of the storage capacitor Cst is:

[0114] ΔV=Vcom-Vdata;

[0115] In the second period t12 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row shutdown signal VL. At this time, the seventh transistor T7 and the eighth transistor T8 receive the fourth level signal V4, the seventh transistor T7 is triggered to turn on, and the eighth transistor T8 is triggered to turn off. The seventh transistor T7 transmits the row shutdown signal VL to the first switching circuit 12 and the switch circuit 131. The first transistor T1 and the second transistor T2 of the first switching circuit 12 receive the row shutdown signal VL and switch to the off state. At this time, the third transistor T3 receives the fourth level signal V4, the third transistor T3 is triggered to turn off, and the bias resistor R 1 is biased to a preset potential Vref, the fourth transistor T4 is triggered to be turned on, the fifth transistor T5 is triggered to be turned off, and the common electrode voltage Vcom is transmitted to the second end of the storage capacitor Cst. The sixth transistor T6 is triggered to be turned on, connecting the first end of the storage capacitor Cst and the pixel electrode 11, and outputting the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom-Vdata, the voltage of the second end of the storage capacitor Cst is Vcom. Therefore, the voltage of the first end of the storage capacitor Cst is 2*Vcom-Vdata.

[0116] The pixel electrode 11 and the common electrode layer of the color filter layer form a first driving voltage, and the first driving voltage is:

[0117] VData1=2*Vcom-Vdata-Vcom;

[0118] That is, the first driving voltage VData1 is -(Vdata-Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V and the data signal Vdata is 10V, the first driving voltage is -2V.

[0119] When the current frame scan ends and switches to the second frame, in the first time period t21 of the second frame, the seventh transistor T7 and the eighth transistor T8 continue to receive the fourth level signal V4, the seventh transistor T7 remains in the on state, and the eighth transistor T8 remains in the off state. The flip circuit 14 switches the output row start signal VG to the first switching circuit 12 and the switch circuit 131. At this time, the first transistor T1 is triggered to turn on, and the second transistor T2 is triggered to turn off, transmitting the data signal Vdata of the current frame to the first end of the storage capacitor Cst. The third transistor T3 continues to receive the fourth level signal V4 and remains in the off state. At this time, the bias resistor R1 maintains the bias function, the fourth transistor T4 remains in the on state, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The sixth transistor T6 remains in the on state and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. The voltage difference between the first end and the second end of the storage capacitor Cst is:

[0120] ΔV=Vdata-Vcom;

[0121] During the second period t22 of the second frame, the seventh transistor T7 and the eighth transistor T8 continue to receive the fourth level signal V4, the seventh transistor T7 remains in the on state, the eighth transistor T8 remains in the off state, the flip circuit 14 outputs the row-off signal VL, the first transistor T1 and the second transistor T2 are triggered to turn off, and the third transistor T3 continues to receive the fourth level signal V4 and remains in the off state. At this time, the bias resistor R1 is biased to the preset potential Vref, the fourth transistor T4 continues to transmit the common electrode voltage Vcom to the second end of the storage capacitor Cst, and the sixth transistor T6 outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. The voltage of the first end of the storage capacitor Cst is maintained at Vdata. The pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is:

[0122] VData1=Vdata-Vcom;

[0123] For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, the data signal Vdata is 10V, and the second driving voltage is 2V, the first driving voltage and the second driving voltage have the same absolute value but opposite polarity.

[0124] By analogy, in subsequent odd frames, the pixel unit 10 operates according to the operating timing and signal flow of the first frame, and switches to output the first driving voltage, and in subsequent even frames, the pixel unit 10 operates according to the operating timing and signal flow of the second frame, and switches to output the second driving voltage with opposite polarity. This allows two adjacent frames to be treated as a frame cycle, and during the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the operating reliability of the liquid crystal layer.

[0125] The first transistor T1 and the ninth transistor T9 may be NMOS transistors, and the second transistor T2 may be a PMOS transistor.

[0126] The fourth transistor T4 and the sixth transistor T6 can be transistors of the same type, and the fourth transistor T4 and the fifth transistor T5 are transistors of opposite types. The specific types are specifically set according to the input first level signal V1 and the preset potential Vref. In an optional embodiment, the preset potential Vref is a high potential, the first level signal V1 is a low level signal, the fourth transistor T4 and the sixth transistor T6 are NMOS transistors, and the fifth transistor T5 is a PMOS transistor.

[0127] The third transistor T3 and the eighth transistor T8 are transistors of the same type, and the eighth transistor T8 and the seventh transistor T7 are transistors of opposite types. The specific types are determined according to the specific potentials of the third level signal V3 and the fourth level signal V4 of the input pulse control signal Ctr2. In an optional embodiment, the third level signal V3 is a low level signal, the fourth level signal V4 is a high level signal, the third transistor T3 and the eighth transistor T8 are PMOS transistors, and the seventh transistor T7 is an NMOS transistor.

[0128] Example 4

[0129] like Figure 1 As shown, a second aspect of the present invention provides a display panel 100. The display panel 100 includes a plurality of scan lines G, a plurality of data lines S, and a plurality of pixel units 10. The specific structure of the pixel units 10 is similar to that of the above embodiments. Since the present display panel 100 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and a detailed description thereof will not be repeated here. The pixel units 10 are respectively connected to a scan line G and a data line S.

[0130] The pixel units 10 are arranged in an array on an array substrate of a display panel 100. The array substrate further includes a plurality of scan lines G, a plurality of data lines S, and a common electrode terminal. The common electrode terminal has a first common electrode voltage Vcom1. Each pixel unit 10 is connected to a data line S and a scan line G respectively. The display panel 100 further includes a color filter substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. Figure 2 As shown, the pixel unit 10 includes a pixel electrode 11, a color filter layer and a common electrode layer are provided on the color filter substrate, the common electrode layer has a second common electrode voltage, and a plurality of scanning lines G are used to input a row scanning signal Vgate to the pixel units 10 of each row row by row, and when the pixel units 10 of each row receive the row scanning signal Vgate, the data line S outputs a corresponding data signal Vdata to the pixel units 10 of the corresponding row, and the pixel unit 10 generates a corresponding voltage signal to the pixel electrode 11 based on the received row scanning signal Vgate and the data signal Vdata. The voltage signal input to the pixel electrode 11 and the second common electrode voltage form a driving voltage, and drive the liquid crystal deflection of the liquid crystal layer, and cooperate with the color filter layer to control the pixel unit 10 to display corresponding image information.

[0131] In an optional embodiment, the common electrode voltage Vcom is equal to the second common electrode voltage, such as 5V, 8V, etc.

[0132] Example 5

[0133] like Figure 7As shown, a third aspect of the embodiments of the present invention provides a display device, which includes a display panel drive circuit 200 and a display panel 100. The specific structure of the display panel 100 is referred to the above embodiments. Since the present display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The display panel drive circuit 200 is connected to the display panel 100.

[0134] In this embodiment, the driving circuit 200 of the display panel may include a timing controller 230, a source driving circuit 210 and a gate driving circuit 220. The timing controller 230 is used to control the gate driving circuit 220 to output a row scanning signal Vgate to each row scanning line G row by row, and to control the source driving circuit 210 to output a data signal Vdata to each column data line S. This can realize that two adjacent frames are regarded as a frame cycle, and during the frame scanning process, the polarity on the data line S can remain unchanged, and the pixel unit 10 switches the polarity of the driving voltage of the liquid crystal layer in the frame cycle, thereby reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0135] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A pixel unit, characterized in that: include: pixel electrode; Storage capacitor; a first switching circuit, connected to the data line and the storage capacitor, respectively, the first switching circuit being configured to transmit the data signal on the data line to the second end of the storage capacitor upon receiving a first level signal, or to transmit the data signal to the first end of the storage capacitor upon receiving a second level signal, or to trigger shutdown upon receiving a row-off signal; a switching output circuit, connected to the common electrode terminal, the storage capacitor, and the pixel electrode, respectively, the switching output circuit being configured to transmit the common electrode voltage at the common electrode terminal to the first terminal of the storage capacitor when receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor and output the voltage of the first terminal of the storage capacitor to the pixel electrode when receiving the second level signal or the row off signal; A flip circuit is respectively connected to the scan line, the first switching circuit and the switching output circuit. The flip circuit is used to output the first level signal or the second level signal when receiving the row start signal transmitted by the scan line, and switch the polarity of the output level when receiving the row start signal again, or output the row close signal when receiving the row close signal transmitted by the scan line.

2. The pixel unit according to claim 1, wherein: The first switching circuit includes a first transistor and a second transistor; The first end of the first transistor, the first end of the second transistor and the data line are connected, the second end of the first transistor is connected to the first end of the storage capacitor, the second end of the second transistor is connected to the second end of the storage capacitor, and the control end of the first transistor and the control end of the second transistor are connected together to form the control end of the first switching circuit.

3. The pixel unit according to claim 1 or 2, wherein: The switching output circuit includes: a switch circuit, wherein an input end of the switch circuit is connected to an output end of the flip circuit, and the switch circuit is configured to be triggered to be turned on upon receiving a third level signal of the pulse control signal, or to be triggered to be turned off upon receiving a fourth level signal of the pulse control signal; a bias circuit connected to the output end of the switch circuit, the bias circuit being configured to bias the voltage at the output end of the switch circuit to a preset potential when the switch circuit is in an off state; a second switching circuit, connected to the common electrode terminal, the switch circuit, the bias circuit, and the storage capacitor, respectively, the second switching circuit being configured to transmit the common electrode voltage to the first terminal of the storage capacitor upon receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor upon receiving the preset potential; an output circuit connected between the first end of the storage capacitor and the pixel electrode, the output circuit further connected to the output end of the switching circuit, the output circuit configured to trigger a shutdown upon receiving the first level signal, or trigger a conduction upon receiving the preset potential and transmit the voltage at the first end of the storage capacitor to the pixel electrode; The cycle time of the pulse control signal is two frames long. The pulse control signal in each cycle time is composed of a third level signal and a fourth level signal. The phase of the third level signal is the same as the phase of the row start signal of the previous frame in the two frame length.

4. The pixel unit according to claim 3, wherein: The switch circuit includes a third transistor; The first end of the third transistor constitutes the input end of the switch circuit, the control end of the third transistor is used to receive the pulse control signal, and the second end of the third transistor constitutes the output end of the switch circuit.

5. The pixel unit according to claim 3, wherein: The bias circuit includes a bias resistor; The first end of the bias resistor is connected to the output end of the switch circuit, the control end of the output circuit and the control end of the second switching circuit respectively, and the second end of the bias resistor is used to input a preset potential.

6. The pixel unit according to claim 3, wherein: The second switching circuit includes a fourth transistor and a fifth transistor; The first end of the fourth transistor, the first end of the fifth transistor and the common electrode end are connected, the second end of the fourth transistor is connected to the second end of the storage capacitor, the second end of the fifth transistor is connected to the first end of the storage capacitor, and the control end of the fourth transistor and the control end of the fifth transistor are connected to form the control end of the second switching circuit.

7. The pixel unit according to claim 3, wherein: The output circuit includes a sixth transistor; The first end of the sixth transistor is connected to the first end of the storage capacitor, the second end of the sixth transistor is connected to the pixel electrode, and the control end of the sixth transistor constitutes the control end of the output circuit.

8. The pixel unit according to claim 3, wherein: The flip circuit includes a seventh transistor, an eighth transistor and a ninth transistor; The first end of the seventh transistor and the first end of the eighth transistor are connected to the scan line, the second end of the seventh transistor and the second end of the ninth transistor are commonly connected to form the output end of the flip circuit, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control end of the seventh transistor and the control end of the eighth transistor are used to input the pulse control signal, and the first end of the ninth transistor is used to input the first level signal.

9. A display panel, characterized in that: The device comprises a plurality of scan lines, a plurality of data lines and a plurality of pixel units according to any one of claims 1 to 8, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.

10. A display device, characterized in that: The device comprises a display panel driving circuit and the display panel as claimed in claim 9, wherein the display panel driving circuit is connected to the display panel.

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