Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof and an electronic device, the semiconductor device comprising: a first reading transistor comprising a first electrode connected with a capacitor, a second electrode connected with an input signal terminal, and a first gate electrode connected with a first writing transistor; a second reading transistor comprising a third electrode connected with the capacitor, a fourth electrode connected with a ground signal terminal, and a second gate electrode connected with a second writing transistor; the first writing transistor comprising a fifth electrode connected with a first bit line, a sixth electrode connected with the first gate electrode, and a third gate electrode connected with a word line; the second writing transistor comprising a seventh electrode connected with the second gate electrode, an eighth electrode connected with a second bit line, and a fourth gate electrode connected with the word line; and the capacitor is further connected with a read signal terminal. The circuit structure of the semiconductor device of the embodiment of the application is relatively simple, which is conducive to realizing a device physical structure with simpler structure and a simplified process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to, but are not limited to, the technical field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] The progress of artificial intelligence needs strong computing power support. In recent years, with the continuous development of artificial neural network technology, the computing power bottleneck has become increasingly apparent. In the Von Neumann architecture, the logic control device and the memory are separate units. The logic control device reads data from the memory and stores it back to the memory after corresponding processing. Data is transmitted back and forth between the logic control device and the memory, and the memory and the logic control device are respectively in different chips. The back-and-forth transmission of data between different chips leads to high power consumption and low performance.

[0003] As a new computing architecture, the core of storage and computing integration is to integrate storage and computing. According to the distance between storage and computing, the technology of generalized storage and computing integration is divided into three categories, namely, processing near memory (PNM), processing in memory (PIM) and computing in memory (CIM). Processing in memory is the narrow sense of storage and computing integration. Processing in memory can realize in-memory processing of data, reduce the number of data flow, and realize computing acceleration. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of protection of the present application.

[0005] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device. The circuit junction of the semiconductor device is relatively simple.

[0006] Embodiments of the present application provide a semiconductor device, comprising: a first reading transistor, a second reading transistor, a first writing transistor, a second writing transistor and a capacitor;

[0007] The first reading transistor comprises a first electrode connected with the capacitor, a second electrode connected with an input signal end, and a first gate electrode connected with the first writing transistor;

[0008] The second reading transistor comprises a third electrode connected with the capacitor, a fourth electrode connected with a ground signal end, and a second gate electrode connected with the second writing transistor;

[0009] The first writing transistor comprises a fifth electrode connected with a first bit line, a sixth electrode connected with the first gate electrode, and a third gate electrode connected with a word line.

[0010] The second write transistor includes a seventh electrode connected to the second gate electrode, an eighth electrode connected to a second bit line, and a fourth gate electrode connected to the word line;

[0011] One end of the capacitor is connected to the first electrode and the third electrode, and the other end is connected to a read signal terminal.

[0012] In some embodiments, the first read transistor and the second read transistor are arranged in parallel on a substrate;

[0013] The first write transistor is stacked above the first read transistor and the second read transistor;

[0014] The second write transistor is stacked above the first read transistor and the second read transistor;

[0015] The first write transistor and the second write transistor are stacked on the substrate.

[0016] In some embodiments, the first write transistor is located above the second write transistor.

[0017] In some embodiments, the first electrode, the third electrode, and the one end of the capacitor are the same electrode, and the other end of the capacitor is located above the first electrode and insulated from the first electrode.

[0018] In some embodiments, the first read transistor, the second read transistor, the first write transistor, and the second write transistor are all planar transistors.

[0019] In some embodiments, the first read transistor includes a first semiconductor layer connecting the first electrode and the second electrode, the second read transistor includes a second semiconductor layer connecting the third electrode and the fourth electrode, and the first semiconductor layer and the second semiconductor layer both extend in a first direction parallel to the substrate;

[0020] The first write transistor includes a third semiconductor layer connecting the fifth electrode and the sixth electrode, and the second write transistor includes a fourth semiconductor layer connecting the seventh electrode and the eighth electrode, and the third semiconductor layer and the fourth semiconductor layer both extend in the first direction;

[0021] The fourth electrode, the first electrode, and the second electrode are arranged in parallel in the first direction.

[0022] In some embodiments, the third semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

[0023] The fourth semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

[0024] In some embodiments, the materials of the first semiconductor layer and the second semiconductor layer comprise silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer comprise metal oxide semiconductor materials.

[0025] In some embodiments, the materials of the first semiconductor layer and the second semiconductor layer are both silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer are metal oxides containing at least one of indium, gallium, zinc, and tin.

[0026] In some embodiments, the method for manufacturing the semiconductor device comprises:

[0027] forming the first read transistor and the second read transistor on the same main surface of the substrate, and making the first electrode and the third electrode the same electrode;

[0028] depositing an insulating layer and an electrode corresponding to the other end of the capacitor on the side of the first electrode away from the substrate;

[0029] forming the second write transistor and the first write transistor in sequence on the side of the first read transistor and the second read transistor away from the substrate.

[0030] Embodiments of the present application also provide an electronic device, which comprises the semiconductor device provided by the embodiments of the present application.

[0031] The semiconductor device and the manufacturing method thereof and the electronic device provided by the embodiments of the present application have the following beneficial effects.

[0032] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The purposes and advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and are used to explain the technical solutions of the application, and do not constitute a limitation on the technical solutions of the application.

[0034] Figure 1 A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0035] Figure 2A A perspective structural schematic diagram of a semiconductor device provided for an exemplary embodiment of the present application;

[0036] Figure 2B A perspective structural schematic diagram of another angle of the semiconductor device shown in Figure 2A

[0037] Figure 2C A longitudinal sectional structural schematic diagram of the device shown in Figure 2A

[0038] A logic circuit diagram of another semiconductor device provided for an exemplary embodiment of the present application; Figure 3

[0039] A partial structural equivalent circuit diagram provided for an embodiment of the present application; Figure 4

[0040] A computing process schematic diagram of the semiconductor device shown in Figure 5 Figure 3 A perspective structural schematic diagram of a semiconductor device provided for an exemplary embodiment of the present application after forming a capacitor;

[0041] Figure 6A A longitudinal sectional structural schematic diagram of the device shown in

[0042] Figure 6B Figure 6A A perspective structural schematic diagram of a semiconductor device provided for an exemplary embodiment of the present application after forming a storage node;

[0043] Figure 7A A longitudinal sectional structural schematic diagram of the device shown in

[0044] Figure 7B A longitudinal sectional structural schematic diagram of the device shown in Figure 7A ​​​​

[0045] Figure 8A A schematic diagram of the three-dimensional structure of a semiconductor device after the formation of a second write transistor, provided as an exemplary embodiment of this application;

[0046] Figure 8B for Figure 8A A schematic diagram of the longitudinal cross-section of the device shown;

[0047] Figure 9A A three-dimensional structural diagram of a semiconductor device manufacturing method provided for an exemplary embodiment of this application after forming a conductive layer between a first write transistor and a second write transistor;

[0048] Figure 9B for Figure 9A The diagram shows a longitudinal cross-sectional view of the device. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0050] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0052] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0053] In this application, unless otherwise specified and limited, the terms "mount", "connected", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0054] In this application, the transistor refers to an element including at least three terminals of gate electrode, drain electrode and source electrode.

[0055] In this application, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this application, if not specifically stated, "source electrode" and "drain electrode" can be exchanged with each other.

[0056] In this application, "electrically connected" or "connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect, such as electrical signal connection (coupled to), or physical direct connection. The "element having a certain electrical effect" is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0057] In this application, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and therefore, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore, a state in which the angle is 85° or more and 95° or less is also included.

[0058] In the embodiments of this application, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be replaced by "conductive film". Similarly, "insulating film" can be replaced by "insulating layer".

[0059] The "integrated structure of A and B" in the embodiments of the present application can refer to no obvious fault or gap, or other obvious boundary interface in the microstructure. Generally, the connected film layers are integrated on a film layer. For example, A and B are formed by using the same material to form a film layer and are simultaneously formed by the same patterning process to have a connection relationship, or B is directly grown on A by epitaxy, and the materials of A and B can not be completely the same.

[0060] In the present application, the spaced distribution can be understood as a separated distribution, which can be physically disconnected to achieve spacing, and can also be electrically disconnected. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0061] The transistor with metal oxide such as indium gallium zinc oxide (InGaZnO, IGZO) as the channel material has low leakage performance and can be used to realize some transistors in the in-memory computing circuit. However, the miniaturization of the metal oxide semiconductor transistor such as IGZO is difficult, and as the size of IGZO decreases, its performance becomes difficult to control.

[0062] The matrix vector multiplication (MVM) or multiply accumulate (MAC) operation accounts for about 70% to 90% of the computation in neural network computation. The embodiments of the present application provide a logic circuit and a semiconductor device that can be used at least for MAC simulation calculation, which can accelerate neural network training and calculation at low power consumption. Each semiconductor device is an in-memory computing unit.

[0063] Figure 1 A logic circuit diagram of a semiconductor device is provided for the exemplary embodiments of the present application. As shown in Figure 1 The logic circuit of the semiconductor device is a 4T1C structure, which includes a first read transistor T2, a second read transistor T3, a first write transistor T1, a second write transistor T4, and a capacitor C.

[0064] The first read transistor T2 includes a first electrode P1 connected to the capacitor C, a second electrode P2 connected to an input signal terminal 1L, and a first gate electrode G1 connected to the first write transistor T1.

[0065] The second read transistor T3 includes a third electrode P3 connected to the capacitor C, a fourth electrode P4 connected to a ground signal terminal, and a second gate electrode G2 connected to the second write transistor T4.

[0066] The first write transistor T1 includes a fifth electrode P5 connected to the first bit line BL1, a sixth electrode P6 connected to the first gate electrode G1, and a third gate electrode G3 connected to the word line WL.

[0067] The second write transistor T4 includes a seventh electrode P7 connected to the second gate electrode G2, an eighth electrode P8 connected to the second bit line BL2, and a fourth gate electrode G4 connected to the word line WL.

[0068] The two ends of capacitor C are connected to the first electrode P1 and the readout signal terminal, respectively.

[0069] In some embodiments, capacitor C includes a ninth electrode P9 connected to the first electrode P1 and the third electrode P3, and a tenth electrode P10 connected to the readout signal terminal or readout line RL, wherein the ninth electrode P9 and the tenth electrode P10 are insulated from each other.

[0070] The logic circuit structure of the semiconductor device in this application embodiment is simple, so a high-performance semiconductor device can be manufactured through a simple process.

[0071] Figure 2A and Figure 2B A three-dimensional structural schematic diagram of a semiconductor device provided for an exemplary embodiment of this application; Figure 2C for Figure 2A The diagram shows a schematic longitudinal cross-sectional structure of the semiconductor device. (As shown...) Figures 2A-2C As shown, the semiconductor device is located on the substrate 10, and the first read transistor T2 and the second read transistor T3 are located on the same main surface of the substrate 10 and are arranged at intervals on the substrate 10; the same main surface can be a plane parallel to the substrate 10.

[0072] The first write transistor T1 is stacked on top of the first read transistor T2 and the second read transistor T3; the second write transistor T4 is stacked on top of the first read transistor T2 and the second read transistor T3; the first write transistor T1 and the second write transistor T4 are stacked on the substrate 10.

[0073] In some embodiments, the first write transistor is located above the second write transistor.

[0074] The first write transistor T1 and the second write transistor T4 of the semiconductor device in this application embodiment are stacked on top of each other, and simultaneously stacked with the first read transistor T2 and the second read transistor T3. This results in a device with a simpler physical structure, which is easier to manufacture, and also reduces the area occupied by the semiconductor device, thereby allowing more in-memory computing units to be integrated on a limited chip.

[0075] For example, such as Figures 2A-2CAs shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0076] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1. Figures 2A-2C As shown, the first electrode P1 and the third electrode P3 are a common electrode or an integrated structure.

[0077] As shown, the first electrode P1 and the third electrode P3 are a common electrode or an integrated structure.

[0078] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1. Figures 2A-2C As shown, the capacitor C is located between the substrate 10 and the second write transistor T4, and the ninth electrode P9 and the tenth electrode P10 are stacked on the substrate 10; the first electrode P1, the third electrode P3, and the ninth electrode P9 are a common electrode, and the tenth electrode P10 is located on the side of the common electrode away from the substrate 10 and is insulated from the second write transistor T4. The tenth electrode P10 is connected with the read line RL, and the two are an integrated structure, and the tenth electrode P10 is part of the read line RL.

[0079] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0080] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0081] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0082] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0083] As shown, the first read transistor T2 and the second read transistor T3 are located on the surface of one side of the substrate 10, and the second write transistor T4 is located between the first read transistor T2 or the second read transistor T3 and the first write transistor T1.

[0084] The fourth semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

[0085] Exemplarily, as shown in Figure 2C The first semiconductor layer includes a first channel region 21 between the first electrode P1 and the second electrode P2, which can extend along a first direction parallel to the substrate 10;

[0086] The second semiconductor layer includes a second channel region 22 between the third electrode P3 and the fourth electrode P4, which can extend along the first direction;

[0087] The third semiconductor layer includes a third channel region 23 between the fifth electrode P5 and the sixth electrode P6, which can extend along the first direction;

[0088] The fourth semiconductor layer includes a fourth channel region 24 between the seventh electrode P7 and the eighth electrode P8, which can extend along the first direction.

[0089] Figures 2A-2C It can be seen that the third semiconductor layer (the third channel region 23) extends from the region corresponding to the first semiconductor layer (the first channel region 21) to the region corresponding to the second semiconductor layer (the second channel region 22) in the first direction;

[0090] The fourth semiconductor layer (the fourth channel region 24) extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

[0091] The third semiconductor layer (the third channel region 23) and the fourth semiconductor layer (the fourth channel region 24) are stacked, and the projections on the substrate overlap as much as possible to reduce the circuit occupation area.

[0092] The first direction can be an X direction as shown in Figure 2C , that is, the arrangement direction between the first read transistor and the second read transistor. In Figures 2A-2C , the first channel region 21, the second channel region 22, the third channel region 23 and the fourth channel region 24 all extend along the first direction.

[0093] The channel regions of the first write transistor and the second write transistor of the embodiment of the present application are large, for example, can cover at least the channel regions of two read transistors, such as the area of any one write transistor is about twice the area of a read transistor, which reduces the processing difficulty of the transistor with metal oxide material as the channel.

[0094] As shown in Figure 2C The first gate electrode G1 is connected to the sixth electrode P6 through the conductive layer 12.

[0095] As shown in Figure 2C The first gate electrode G1 and the first channel region 21, the second gate electrode G2 and the second channel region 22, the third gate electrode G3 and the third channel region 23, the fourth gate electrode G4 and the fourth channel region 24, and the capacitor C and the first electrode P1 (or the common third electrode P3) are insulated by the insulating layer 11 (also serving as a gate insulating layer).

[0096] Exemplarily, the materials of the first semiconductor layer and the second semiconductor layer comprise silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer comprise metal oxide semiconductor materials. Exemplarily, the materials of the first semiconductor layer and the second semiconductor layer are both silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer are metal oxides containing at least one of indium, gallium, zinc and tin.

[0097] Exemplarily, the first read transistor T2 and the second read transistor T3 are both N-type transistors, for example, the first read transistor T2 and the second read transistor T3 are both silicon channel N-type transistors. The first write transistor T1 and the second write transistor T4 are both N-type transistors, for example, metal oxide semiconductor as the channel.

[0098] Exemplarily, the main body materials of the channel regions of the first read transistor T2 and the second read transistor T3 are silicon, and the main body materials of the channel regions of the first write transistor T1 and the second write transistor T4 are metal oxides containing at least one of indium, gallium, zinc and tin.

[0099] Exemplarily, the first read transistor T2 and the second read transistor T3 are formed on a silicon substrate, and the channel and the electrode are both formed by modifying the silicon substrate.

[0100] The embodiments of the present application adopt silicon-based transistors as read transistors, which are easier to miniaturize and have better stability. The electron mobility of silicon is relatively high, so the read performance of the transistors is better. The read transistors using metal oxide semiconductor materials have smaller leakage current, and the length of the channel region formed by the metal oxide semiconductor material is longer, which not only can further reduce the leakage current and the refresh frequency, but also can reduce or even avoid the process challenges encountered by the metal oxide semiconductor material in the miniaturization process, thereby reducing the process difficulty.

[0101] Exemplarily, the first read transistor T2 and the second read transistor T3 are not limited to be planar transistors, and can each independently be a fin field effect transistor, a super fin field effect transistor or a fully wrapped gate field effect transistor.

[0102] Exemplarily, the first read transistor T2 and the second read transistor T3 are both planar transistors, and the first write transistor T1 and the second write transistor T4 are both planar transistors.

[0103] Exemplarily, the capacitor is configured to output the voltage of the first gate electrode and the second gate electrode to the read signal end through charge coupling in a data reading stage. The voltage of the capacitor is an average voltage of the capacitors of a plurality of in-memory computing units connected to the same read signal end.

[0104] The substrate in the embodiments of the present application can be a support structure, such as a silicon substrate, or a support structure on which other film layers or functions or circuits have been distributed, and the device involved in the inventive construction of the embodiments of the present application is arranged on the main surface of the support structure.

[0105] Exemplarily, the main body material of the channel region of the first write transistor and the second write transistor can be silicon, for example, can be a material such as silicon or polysilicon with a band gap less than 1.65 eV.

[0106] Exemplarily, the metal oxide semiconductor material can be a wide band gap material, such as a metal oxide semiconductor material with a band gap greater than 1.65 eV.

[0107] For example, the metal oxide semiconductor material can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as elements N, Si, and the like; and can also include other small amounts of doped elements.

[0108] In some embodiments, the metal oxide semiconductor material can include any one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to actual conditions.

[0109] The band gap of these materials is wide, and the leakage current is low, for example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A to 10 -18 A, so that the working performance of the dynamic memory can be improved.

[0110] The above metal oxide semiconductor material only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0111] Exemplarily, the material of the first bit line and the second bit line can each independently be selected from any one or more of tungsten, molybdenum, cobalt, and other metal materials having similar properties. The first bit line and the second bit line can each independently be a single-layer or a multi-layer structure, for example, can be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0112] Exemplarily, the material of the first gate electrode, the second gate electrode, the third gate electrode, the fourth gate electrode, and the word line can each independently be selected from any one or more of the following materials:

[0113] For example, it can contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals; it can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, it can also be polycrystalline silicon conductive materials or silicon conductive materials, which can achieve conductivity by doping with metals.

[0114] For example, the semiconductor device in the embodiments of this application can be a semiconductor device for in-memory computing.

[0115] Figure 3 A logic circuit diagram of another semiconductor device as an exemplary embodiment of this application.

[0116] Will Figure 3 The first read transistor T2 and the second read transistor T3 in the figure are considered as voltage-controlled resistors, such as Figure 4 As shown ( Figure 4 To illustrate the circuit connection diagram of the first and second read transistors when they are considered as voltage-controlled resistors, V in The voltage input to the input signal terminal, V out To read the voltage output from the signal terminal, R T2 R T3 The resistors for the first read transistor and the second read transistor are respectively, indicating that the first read transistor and the second read transistor are considered as voltage-controlled resistors.

[0117]

[0118] Figure 3 The output voltage V of the in-memory computing unit array shown RL for:

[0119]

[0120] Figure 5 for Figure 3 The diagram shows a schematic of the computation process of a semiconductor device used for in-memory analog computation.

[0121] The following is based on Figure 3 The working principle of the in-memory computing unit of this application will be illustrated using an example. The in-memory computing unit of this application embodiment can be used for vector operations. Figure 3 The structure shown is an array of in-memory computing units repeated vertically, capable of calculating vector products. Below is an example of its operation:

[0122] Write operation: Write weights [W1 W2 ... W] sequentially. n ]( Figure 3 Only one in-memory calculation unit is shown, here referred to as W1, W2, ..., W... n This indicates the weight of the computational unit within this column, in Figure 5 If the memory contains multiple rows and columns of internal calculation units, then W is used. 1,1 W 1,2 W 1,n ... W M,N This represents the weight of a multi-row, multi-column in-memory computation unit. Taking Wi as an example, WL... i Set the voltage to 1, set the other WL values ​​to 0, then set the voltage of the first line BL1 to Wi, and the voltage of BL2 to... Then WL i Set BL1 and BL2 to 0 to complete the write operation;

[0123] Read operation: Float the electrode corresponding to the read line RL (i.e., do not connect it to any potential), and connect the voltages [V1, V2, ..., Vn] to be calculated to the corresponding signal input terminals 1L1, 1L2, ..., 1Ln.

[0124] Finally, by reading the voltage value at the readout signal terminal, the multiplication operation of vectors V and W can be completed.

[0125] Therefore, the semiconductor device in this application embodiment can realize analog computing in memory, which can accelerate neural network training and computation.

[0126] This application also provides a method for manufacturing a semiconductor device as described in the above embodiments, the manufacturing process including:

[0127] The first read transistor and the second read transistor are formed on the same main surface on the substrate, and the first electrode and the third electrode are shared electrodes;

[0128] An insulating layer is deposited on the side of the common electrode away from the substrate to form the tenth electrode of the capacitor, and the common electrode is used as the ninth electrode. The ninth electrode, the tenth electrode, and the insulating layer constitute the capacitor.

[0129] The second write transistor and the first write transistor are sequentially formed on the side of the first read transistor and the second read transistor away from the substrate.

[0130] Figures 6A-9B and Figures 2A-2CThis is a schematic diagram of the intermediate process and the structure of the final semiconductor device obtained, provided as an exemplary embodiment of this application.

[0131] like Figures 6A-9B and Figures 2A-2C As shown, the manufacturing method may include the following steps.

[0132] S10: Forming a first read transistor T2 and a second read transistor T3 on the same main surface of the substrate 10, including:

[0133] A substrate 10, such as a silicon substrate, is provided. A first electrode P1, a first channel region 21, and a second electrode P2 of a first read transistor T2 are formed on the substrate 10. A third electrode P3, a second channel region 22, and a fourth electrode P4 of a second read transistor T3 are also formed on the substrate 10. A ninth electrode P9 of a capacitor C is also formed on the substrate 10. The first electrode P1, the third electrode P3, and the ninth electrode P9 are a single electrode. The first electrode P1, the first channel region 21, the second electrode P2, the third electrode P3, the second channel region 22, and the fourth electrode P4 are located on the same main surface and are arranged sequentially in the same direction in the order of second electrode P2, first channel region 21, first electrode P1 / third electrode P3, second channel region 22, and fourth electrode P4.

[0134] An insulating layer 11 is deposited on the side of the first channel region 21, the first electrode P1 / the third electrode P3, and the second channel region 22 away from the substrate 10. On the side of the insulating layer 11 away from the substrate 10, the first gate electrode G1, the tenth electrode P10 of the capacitor C, and the second gate electrode G2 are formed sequentially. For example, a gate electrode layer can be deposited and the first gate electrode G1 and the second gate electrode G2 can be formed simultaneously through a patterning process.

[0135] A conductive layer 12 is deposited on the side of the second electrode P2 and the fourth electrode P4 away from the substrate 10, and an input signal terminal 1L connected to the second electrode P2 and a ground signal terminal connected to the fourth electrode P4 are formed by a patterning process. Figure 6A and Figure 6B As shown.

[0136] S20: An insulating layer 11 is deposited on the substrate 10, covering the first read transistor T2, the second read transistor T3, the capacitor C, and the patterned conductive layer 12. Through-holes are etched in the insulating layer 11, exposing the first gate electrode G1 and the second gate electrode G2. A conductive layer 12 is deposited within the through-holes to form connection electrodes M0, which are respectively connected to the first gate electrode G1 and the second gate electrode G2. The first gate electrode G1 and the second gate electrode G2 are then led out for subsequent use as memory nodes (SNs). Figure 7A and Figure 7B As shown.

[0137] S30: A second write transistor T4 is formed on the surface of the insulating layer 11 away from the substrate 10, including depositing a conductive layer and patterning to form a seventh electrode P7 and an eighth electrode P8 of the second write transistor T4, the eighth electrode P8 is an integral structure with the second bit line BL2, and the eighth electrode P8 is part of the second bit line BL2; a semiconductor layer is deposited on the surface of the seventh electrode P7 and the eighth electrode P8 away from the substrate 10 to form a fourth channel region 24 of the second write transistor T4, and a gate electrode layer is deposited on the surface of the fourth channel region 24 away from the substrate 10 to form a fourth gate electrode G4, as shown in Figure 8A and Figure 8B .

[0138] S40: A conductive layer 12 is deposited on the connecting electrode M0 of the first gate electrode G1, which is used as a connecting electrode between the first gate electrode G1 and the first write transistor T1 later, as shown in Figure 9A and Figure 9B .

[0139] S50: A first write transistor T1 is formed on the second write transistor T4 away from the substrate 10, including: depositing a conductive layer and patterning to form a fifth electrode P5 and a sixth electrode P6 of the first write transistor T1, the fifth electrode P5 and the first bit line BL1 are an integral structure, and the fifth electrode P5 is part of the first bit line BL1; a semiconductor layer is deposited on the surface of the fifth electrode P5 and the sixth electrode P6 away from the substrate 10 to form a third channel region 23 of the first write transistor T1, and a gate electrode layer is deposited on the surface of the third channel region 23 away from the substrate 10 to form a third gate electrode G3, as shown in Figures 2A-2C .

[0140] The embodiments of the present application also provide an electronic device, which comprises the semiconductor device provided by the embodiments of the present application.

[0141] Exemplarily, the electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0142] Although the embodiments disclosed in the present application are as above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art without departing from the spirit and scope of the present application can make any modification and change in the form and details, but the protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized by, The application relates to a read / write memory cell. The read / write memory cell comprises a first read transistor, a second read transistor, a first write transistor, a second write transistor and a capacitor. The first read transistor comprises a first electrode connected to the capacitor, a second electrode connected to an input signal terminal and a first gate electrode connected to the first write transistor. The second read transistor comprises a third electrode connected to the capacitor, a fourth electrode connected to a ground signal terminal and a second gate electrode connected to the second write transistor. The first write transistor comprises a fifth electrode connected to a first bit line, a sixth electrode connected to the first gate electrode and a third gate electrode connected to a word line. The second write transistor comprises a seventh electrode connected to the second gate electrode, an eighth electrode connected to a second bit line and a fourth gate electrode connected to the word line. One end of the capacitor is connected to the first electrode and the third electrode, and the other end is connected to a read signal terminal. The first read transistor and the second read transistor are arranged at intervals on a substrate. The first write transistor is stacked above the first read transistor and the second read transistor. The second write transistor is stacked above the first read transistor and the second read transistor. The first write transistor and the second write transistor are stacked on the substrate.

2. The semiconductor device according to claim 1, wherein The first write transistor is located above the second write transistor.

3. The semiconductor device of claim 2, wherein The first electrode, the third electrode and the one end of the capacitor are the same electrode, and the other end of the capacitor is located above the first electrode and insulated from the first electrode.

4. The semiconductor device of claim 1, wherein The first read transistor, the second read transistor, the first write transistor and the second write transistor are all planar transistors.

5. The semiconductor device of claim 4, wherein, The first read transistor comprises a first semiconductor layer connecting the first electrode and the second electrode, the second read transistor comprises a second semiconductor layer connecting the third electrode and the fourth electrode, and the first semiconductor layer and the second semiconductor layer both extend along a first direction parallel to the substrate. The first write transistor comprises a third semiconductor layer connecting the fifth electrode and the sixth electrode, and the second write transistor comprises a fourth semiconductor layer connecting the seventh electrode and the eighth electrode, and the third semiconductor layer and the fourth semiconductor layer both extend along the first direction. The fourth electrode, the first electrode and the second electrode are arranged at intervals in the first direction.

6. The semiconductor device according to claim 5, wherein The third semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction. The fourth semiconductor layer extends from the region corresponding to the first semiconductor layer to the region corresponding to the second semiconductor layer in the first direction.

7. The semiconductor device of claim 5, wherein The materials of the first semiconductor layer and the second semiconductor layer comprise silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer comprise metal oxide semiconductor materials.

8. The semiconductor device of claim 7, wherein, The materials of the first semiconductor layer and the second semiconductor layer are both silicon, and the materials of the third semiconductor layer and the fourth semiconductor layer are metal oxides containing at least one of indium, gallium, zinc and tin.

9. A method of manufacturing a semiconductor device according to any one of claims 1 to 8, characterized by, Comprising: forming the first read transistor and the second read transistor on the same main surface of the substrate, and making the first electrode and the third electrode the same electrode; depositing an insulating layer and an electrode corresponding to the other end of the capacitor on the side of the first electrode away from the substrate; forming the second write transistor and the first write transistor in sequence on the side of the first read transistor and the second read transistor away from the substrate.

10. An electronic device, comprising: The semiconductor device according to any one of claims 1 to 8.

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