Logical block address state identification

Abstract

Embodiments described herein relate to logical block address state identification. In some implementations, a processing device may send a command including at least a first parameter and a second parameter, and a memory device may receive the command. The first parameter may indicate a logical block address start value and the second parameter may indicate a logical block address range value. The memory device may send a packet that includes a logical block address list and indicates, for each logical block address in the logical block address list, whether the logical block address is valid or invalid, and the processing device may receive the packet. The processing device may identify a mismatch between a valid logical block address and a corresponding file system entry, and may send an erase command to the memory device indicating an erase of the valid logical block address.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 604,573, filed on Nov. 30, 2023, titled "LOGICAL BLOCK ADDRESS STATUS IDENTIFICATION" and assigned to its assignee. The disclosure of the prior application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices, memory device operations, and, for example, to logical block address status identification. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. A memory device includes memory cells. A memory cell is an electronic circuit capable of being programmed to a data state among two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value, typically represented by binary "1" or binary "0". As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a group of memory cells. To access the stored information, the electronic device can read from or sense the stored state of the group of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and others. A memory device can be volatile or non-volatile. A non-volatile memory (e.g., flash memory) can store data for an extended period even in the absence of an external power source. A volatile memory (e.g., DRAM) may lose the stored data over time unless the volatile memory is refreshed by a power source. Summary of the Invention

[0006] One aspect of the present disclosure discloses a memory device, comprising: one or more components configured to: receive a command containing at least a first parameter and a second parameter from a processing device, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and send a packet containing a logical block address list and indicating whether each logical block address in the logical block address list is valid or invalid to the processing device, wherein the first logical block address in the logical block address list corresponds to the logical block address start value, and wherein the number of logical block addresses in the logical block address list corresponds to the logical block address range value.

[0007] Another aspect of the present disclosure discloses a system, comprising: a processing device configured to: send a command containing at least a first parameter and a second parameter to a memory device, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and receive a packet containing a logical block address list and indicating whether each logical block address in the logical block address list is valid or invalid from the memory device, wherein the first logical block address in the logical block address list corresponds to the logical block address start value, and wherein the number of logical block addresses in the logical block address list corresponds to the logical block address range value.

[0008] Another aspect of the present disclosure discloses a device, comprising: means for receiving a command containing at least a first parameter and a second parameter from a processing device, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and means for sending a packet containing a logical block address list and indicating whether each logical block address in the logical block address list is valid or invalid to the processing device, wherein the first logical block address in the logical block address list corresponds to the logical block address start value, and wherein the number of logical block addresses in the logical block address list corresponds to the logical block address range value. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system capable of performing logical block address status recognition.

[0010] Figure 2 is a diagram of an example component included in a memory device.

[0011] Figure 3 is a diagram of an example component included in a host device.

[0012] Figure 4 is a diagram illustrating an example process for logical block address status recognition.

[0013] Figure 5 A diagram of an example component included in a NAND memory.

[0014] Figure 6 A flowchart of an example method for logical block address status identification performed by a memory device.

[0015] Figure 7 A flowchart of an example method for logical block address status identification performed by a host device. Detailed Description

[0016] A memory device is an electronic component capable of storing and retrieving data within various electronic systems. A memory device may include volatile memory (e.g., RAM) that loses data when power is removed and / or non-volatile memory that may retain data after power is removed. A NAND memory is a type of non-volatile memory structured as an array of memory cells and organized into pages and blocks. A NAND memory device may perform read operations to retrieve data from NAND memory cells, write operations to program new data into the memory cells or move data within the memory cells (e.g., to maintain uniform wear on the memory cells and extend the life of the NAND device), and erase operations to erase data from the memory cells (e.g., memory cell blocks).

[0017] The amount of used and unused space within the memory cells of a NAND device may be referred to as the fill level. When data is written to and erased from the memory cells of a NAND device, the fill level of the memory cells fluctuates, which may affect the efficiency and performance of the NAND device. In some cases, the performance of a NAND device may vary significantly based on the fill level of the memory cells. For example, writing data to a memory block with a low fill level may be faster because little or no data movement or erasure may be required. In contrast, writing data to a memory block with a high fill level may be slower due to the need to erase and / or move data. In some cases, a processing device (e.g., a host device) may send an erase command to the NAND device to reduce the fill level of the NAND device, which may improve the write performance of the NAND device. Additionally or alternatively, the processing device may use a wear leveling algorithm to evenly distribute write and erase operations across the memory cells and extend the life of the NAND device.

[0018] Managed NAND (mNAND) is a memory device that integrates a NAND memory chip with a memory controller and firmware into a single package. This integration provides a complete, self - contained storage solution that can be used in embedded systems such as smartphones, tablet computers, smart TVs, and Internet of Things (IoT) devices. Managed NAND devices simplify the integration process for device manufacturers by providing a standardized interface, error correction, wear leveling, and block management within a single package, thereby reducing the complexity of managing NAND memory at the software and firmware levels. Managed NAND can be an attractive option for applications where data storage is compact, reliable, and easy to integrate (for example, to save time and reduce development complexity).

[0019] A logical block address (LBA) can be used to identify a specific data block within a memory device and serves as a consistent way to reference and locate data. Each LBA can correspond to a fixed - size data block within the memory device. In some instances, the fixed - size data block can range from 512 bytes to 4 kilobytes (KB). In some instances, LBAs can be assigned sequentially. For example, the first LBA can have a value of 0, and when data is stored in a memory cell, the LBA can be incremented (for example, incremented by 1). The LBA provides a level of abstraction that enables the operating system and file system to interact with the memory device without having to concern themselves with the physical organization of the data. This abstraction simplifies data management and enables features such as random access, error correction, and wear leveling to be handled at the hardware level. When data is read from or written to a memory cell, the storage controller can map the LBA to a physical location on the memory device, thereby allowing for efficient data retrieval and management while shielding the user and higher - level software from the potential complexity of the memory device's physical structure. If the data stored at an LBA is invalid, then the LBA is "invalid". For example, if the processing device has not written data to the LBA or if the processing device has erased data from the LBA, then the LBA may be invalid. In contrast, if the data stored at an LBA is valid, then the LBA is "valid". For example, if the processing device has written data to the LBA and the processing device has not erased data from the LBA, then the LBA can be valid.

[0020] In some cases, problems in NAND memory management may be caused by mismatches between software levels. For example, in some applications, there may be several software layers, and there may be information mismatches between different software layers. In one instance, a processing device (e.g., a host file system) may erase data at the file system level. However, the processing device (e.g., the software of the processing device) may not have sent an erase command to the NAND device to erase the data at the NAND device. As a result, the mapping of the data may be different at the host file system layer and at the NAND device. The processing device may not be able to efficiently check for mismatches between the layers. In one instance, the processing device and the NAND device may be associated with an automobile. A vendor command may be issued by the processing device, e.g., to perform a debug operation or to verify a discard policy at the NAND device. However, a command may need to be issued separately for each LBA to be verified by the processing device. This may be time-consuming and may be a significant waste of processing resources. Additionally or alternatively, this may expose the physical mapping of the NAND device to the processing device, which may reduce the security of the automobile. Therefore, the processing device may not be able to compare the file system data with the NAND data and, thus, may not be able to determine whether there is an opportunity to reduce the fill level of the NAND device. This may result in the NAND device having a high fill level, which may lead to reduced write performance, slower read and write operations, increased power consumption, and a shorter lifespan of the NAND device, among other instances.

[0021] This document describes various embodiments for LBA status recognition. In some embodiments, a processing device (e.g., a host device) may send a command to a memory device that includes a first parameter and a second parameter, where the first parameter indicates an LBA start value and the second parameter indicates an LBA range value. The memory device may receive the command from the processing device and may identify whether each LBA starting from the LBA start indicated by the LBA start value and included in the LBA range indicated by the LBA range value is valid or invalid. The memory device may send a packet to the processing device that includes an LBA list and indicates whether each LBA included in the LBA list is valid or invalid. In one example, the memory device may generate a table that includes a plurality of entries, where each entry includes an LBA and a bit indicating whether the corresponding LBA is valid (e.g., using a value of 0) or invalid (e.g., using a value of 1). The processing device may receive the packet from the memory device and may compare the data included in the packet with the data stored at the host file system. For example, the processing device may compare each LBA indicated as a valid LBA in the table with the data stored at the processing device. In some embodiments, the processing device may detect a mismatch between the valid LBA and the data stored at the processing device, and may send an erase command for the LBA associated with the mismatch. For example, the processing device may determine that the data stored at the valid LBA is no longer needed to be stored by the NAND, and may send an erase command to the NAND indicating that the NAND erase the data stored at the LBA. This may enable the processing device to determine whether an LBA is valid or invalid for a plurality of LBAs (e.g., a series of LBAs) and using a single command, and to identify whether there is a mismatch between the data stored at the LBA and the data at the corresponding location stored in the host file system. The processing device may issue an erase command for the LBA associated with the mismatch, which may result in the NAND having a lower fill level, thereby improving the write performance of the NAND, enabling faster read and write operations at the NAND, reducing the power consumption at the NAND, and increasing the lifespan of the NAND. Additional details regarding these features are described below.

[0022] Figure 1 FIG. is a diagram illustrating an example system 100 capable of performing logical block address status recognition. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host device 110 and a memory device 120. The memory device 120 may include a controller 130 and a memory 140. The host device 110 may communicate with the memory device 120 (e.g., the controller 130 of the memory device 120) via a host interface 150. The controller 130 and the memory 140 may communicate via a memory interface 160.

[0023] System 100 can be any electronic device configured to store data in a memory. For example, System 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or an airplane), and / or an Internet of Things (IoT) device. The host device 110 can include one or more processors configured to execute instructions and store data in the memory 140. For example, the host device 110 can include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or another type of processing component.

[0024] The memory device 120 can be any electronic device or apparatus configured to store data in a memory. In some embodiments, the memory device 120 can be an electronic device configured to persistently store data in a non-volatile memory. For example, the memory device 120 can be a hard disk drive, a solid state drive (SSD), a flash memory device (e.g., a NAND flash memory device or a NOR flash memory device), a universal serial bus (USB) thumb drive, a memory card (e.g., a secure digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, and / or a universal flash storage (UFS) device. In this case, the memory 140 can include a non-volatile memory configured to maintain the stored data after the memory device 120 is powered off. For example, the memory 140 can include NAND memory or NOR memory. In some embodiments, the memory 140 can include a volatile memory that requires power to maintain the stored data and loses the stored data after the memory device 120 is powered off, such as one or more latches and / or random access memory (RAM), such as dynamic RAM (DRAM) and / or static RAM (SRAM). For example, the volatile memory can cache data read from the non-volatile memory or to be written to the non-volatile memory, and / or can cache instructions to be executed by the controller 130.

[0025] The controller 130 can be any device configured to communicate with a host device (e.g., via the host interface 150) and communicate with the memory 140 (e.g., via the memory interface 160). Additionally or alternatively, the controller 130 can be configured to control the operation of the memory device 120 and / or the memory 140. For example, the controller 130 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the controller 130 can be a high-level controller that can communicate directly with the host device 110 and can instruct one or more low-level controllers regarding memory operations to be performed in conjunction with the memory 140. In some embodiments, the controller 130 can be a low-level controller that can receive instructions regarding memory operations from a high-level controller that interfaces directly with the host device 110. As an example, the high-level controller can be an SSD controller, and the low-level controller can be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some embodiments, a set of operations described herein as being performed by the controller 130 can be performed by a single controller (e.g., the entire set of operations can be performed by a single high-level controller or a single low-level controller). Alternatively, a set of operations described herein as being performed by the controller 130 can be performed by more than one controller (e.g., a first subset of the operations can be performed by a high-level controller and a second subset of the operations can be performed by a low-level controller).

[0026] The host interface 150 enables communication between the host device 110 and the memory device 120. The host interface 150 can include, for example, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, an NVMe interface, a USB interface, a Universal Flash Storage (UFS) interface, and / or an Embedded Multimedia Card (eMMC) interface.

[0027] The memory interface 160 enables communication between the controller 130 and the memory 140. The memory interface 160 can include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 160 can include a volatile memory interface (e.g., for communicating with volatile memory), such as a Double Data Rate (DDR) interface.

[0028] In some embodiments, Figure 1One or more systems, devices, apparatuses, components, and / or controllers may be configured to: receive, from a host device, a command that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and send, to the host device, a packet that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0029] In some embodiments, Figure 1 One or more systems, devices, apparatuses, components, and / or controllers may be configured to: send, to a memory device, a command that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and receive, from the memory device, a packet that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0030] As indicated above, provide Figure 1 as an example. Other examples may be different from what is described with respect to Figure 1 described.

[0031] Figure 2 is a diagram of an example component 200 included in a memory device 120. As described above in connection with Figure 1 described, the memory device 120 may include a controller 130 and a memory 140. As Figure 2 shown in Figure 2 , the memory 140 may include one or more non-volatile memory arrays 205, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Additionally or alternatively, the memory 140 may include one or more volatile memory arrays 210, such as one or more SRAM arrays and / or one or more DRAM arrays. The controller 130 may use a non-volatile memory interface 215 to transmit signals to and receive signals from the non-volatile memory arrays 205. The controller 130 may use a volatile memory interface 220 to transmit signals to and receive signals from the volatile memory arrays 210.

[0032] The controller 130 can control the operation of the memory 140, for example, by executing one or more instructions. For example, the memory device 120 can store one or more instructions as firmware in the memory 140, and the controller 130 can execute the one or more instructions. Additionally or alternatively, the controller 130 can receive one or more instructions from the host device 110 via the host interface 150 and can execute the one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by the controller 130. The controller 130 can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, the execution of the set of instructions by the controller 130 causes the controller 130 and / or the memory device 120 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, one or more components of the controller 130 and / or the memory device 120 can be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands".

[0033] For example, the controller 130 can transmit signals to and / or receive signals from the memory 140 based on one or more instructions, such as transferring (e.g., writing or programming) data to the memory 140 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of the memory 140), transferring (e.g., reading) data from the memory 140, and / or erasing all or a portion of the memory 140. Additionally or alternatively, the controller 130 can be configured to control access to the memory 140 and / or provide a translation layer between the host device 110 and the memory 140 (e.g., for mapping logical addresses to physical addresses of the memory array). In some embodiments, the controller 130 can convert host interface commands (e.g., commands received from the host device 110) into memory interface commands (e.g., commands for performing operations on the memory array).

[0034] As Figure 2 shown, the controller 130 can include a memory management component 225, an LBA validity component 230, and / or a packet generation component 235. In some embodiments, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by the controller 130. Alternatively, one or more of these components can be implemented as an application specific integrated circuit distinct from the controller 130.

[0035] The memory management component 225 may be configured to manage the performance of the memory device 120. For example, the memory management component 225 may perform wear leveling, bad block management, block retirement, read disturbance management, and / or other memory management operations. In some embodiments, the memory device 120 may store one or more memory management tables (e.g., in the memory 140). The memory management tables may store information that may be used or updated by the memory management component 225, such as information regarding memory block age, memory block erase count, and / or error information associated with a memory partition (e.g., a memory cell, a memory row, a memory block, or the like).

[0036] The LBA validity component 230 may be configured to identify whether an LBA is valid or invalid. In some embodiments, the LBA validity component 230 may obtain an LBA start value (LBA start) and an LBA range value (LBA range). For example, the LBA validity component 230 may receive a first parameter indicating the LBA start value and a second parameter indicating the LBA range value from the host device 110 via the host interface 150. The LBA validity component 230 may identify whether an LBA is valid or invalid for each LBA within the LBA range corresponding to the LBA range value and starting from the LBA start corresponding to the LBA start value. If data has not been written to the LBA by the host device 110 or if the data has been erased from the LBA by the host device 110, then the LBA validity component 230 may identify the LBA as invalid. Alternatively, if data has been written to the LBA by the host device 110 and if the data written to the LBA has not been erased from the LBA by the host device 110, then the LBA validity component 230 may identify the LBA as valid.

[0037] The packet generation component 235 may be configured to generate a packet that includes information indicating whether an LBA is valid or invalid. For example, the packet generation component 235 may generate a packet that includes an LBA list and indicates whether each LBA in the LBA list is valid or invalid. The LBA list may include the LBA range corresponding to the LBA range value and may start from the LBA start corresponding to the LBA range value. For example, the first LBA in the LBA list may correspond to the LBA having the LBA start value, and the number of LBAs included in the LBA list may be equal to the LBA start value plus the LBA range value minus 1 (LBA start + LBA range - 1). In some embodiments, the packet generation component may generate a table that includes a plurality of entries, where each entry includes an LBA and a bit indicating whether the LBA is valid or invalid. For example, a bit having a first value (“0”) may indicate that the corresponding LBA is valid, while a bit having a second value (“1”) may indicate that the corresponding bit is invalid. The memory device 120 and / or the packet generation component 235 may send the packet that includes the list (and / or table) of valid and invalid LBAs to the host device 110.

[0038] Figure 2 One or more of the devices or components shown herein may be configured to perform the operations described herein, such as Figure 4 one or more operations of Figure 6 and / or one or more process blocks of the method of

[0039] Provide Figure 2 the number and arrangement of the components shown in Figure 2 as an example. In fact, compared to Figure 2 the components shown in Figure 2 there may be additional components, fewer components, different components, or components arranged in a different manner. Additionally, Figure 2 two or more of the components shown in Figure 2 may be implemented within a single component, or

[0040] Figure 3 is a diagram of an example component 300 included in the host device 110. The host device 110 may include a controller 310 and a memory 320. The controller 310 associated with the host device 110 may include some or all of the features of the controller 130 associated with the memory device 120. Additionally or alternatively, the memory 320 associated with the host device 110 may include some or all of the features of the memory 140 associated with the memory device 120.

[0041] The controller 310 can control the operation of the memory 320, for example, by executing one or more instructions. For example, the host device 110 can store one or more instructions in the memory 320, and the controller 310 can execute the one or more instructions. Additionally or alternatively, the controller 310 can receive one or more instructions from the memory device 120 via the host interface 150 and can execute the one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by the controller 310. The controller 310 can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller 310 causes the controller 310 and / or the host device 110 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, one or more components of the controller 310 and / or the host device 110 can be configured to perform one or more operations or methods described herein.

[0042] As Figure 3 shown, the controller 310 can include a parameter generation component 330, a data comparison component 340, and / or an LBA management component 350. In some embodiments, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by the controller 310. Alternatively, one or more of these components can be implemented as an application specific integrated circuit distinct from the controller 310.

[0043] The parameter generation component 330 can be configured to generate one or more parameters. For example, the parameter generation component 330 can be configured to generate one or more parameters associated with determining the validity of one or more LBAs of the memory device 120. In some embodiments, the parameter generation component 330 can generate a first parameter and a second parameter. The first parameter can indicate an LBA start value (LBA start). The LBA start value can be the first LBA of the memory device 120 for which the validity is to be determined. The second parameter can indicate an LBA range value (LBA range). The LBA range value can indicate the number of LBAs (starting from the first LBA start) of the memory device 120 for which the validity is to be determined. The host device 110 and / or the parameter generation component 330 can send the first parameter and the second parameter to the memory device 120 via the host interface 150.

[0044] The data comparison component 340 can be configured to compare the data received from the memory device 120 with the data stored at the host device 110. For example, the data comparison component 340 can be configured to compare the LBA validity data received from the packet generation component 235 of the memory device 120 with the data stored at the file system of the host device 110. In some embodiments, the data comparison component 340 can compare each LBA indicated as a valid LBA (for example, in a list or table received from the packet generation component 235) with the corresponding valid entry in the file system of the host device 110. For example, if the host device 110 determines that the data stored at the valid LBA is no longer needed, the data stored at the valid LBA should have been erased at a previous time, or the data should not have been written to the valid LBA, then the data comparison component 340 can detect a mismatch between the LBA and the corresponding entry in the file system of the host device 110.

[0045] The LBA management component 350 can be configured to issue commands for managing the data stored in the LBAs of the memory device 120. In some embodiments, the LBA management component can obtain an indication associated with a mismatch of the data stored at an LBA of the memory device 120. For example, the LBA management component 350 can receive (from the memory device 120 and / or the data comparison component 340) an indication that the data stored at the LBA is different from the data stored at the corresponding location in the file system of the host device 110. In this instance, the LBA management component 350 and / or the host device 110 can send an erase command to the memory device 120 instructing to erase the data from the LBA.

[0046] Figure 3 One or more of the devices or components shown in can be used to perform the operations described elsewhere herein, such as Figure 4 one or more of the operations of and / or Figure 7 one or more of the process blocks of the method of. For example, the parameter generation component 330, the data comparison component 340, and / or the LBA management component 350 can perform one or more operations and / or methods of the host device 110.

[0047] Provide Figure 3 The number and arrangement of the components shown in are provided as an example. In fact, compared to Figure 3 the components shown in, there may be additional components, fewer components, different components, or components arranged in a different manner. Additionally, Figure 3 two or more of the components shown in can be implemented within a single component, or Figure 3 a single component shown in can be implemented as multiple distributed components. Additionally or alternatively, Figure 3 a set of components shown in (e.g., one or more components) can perform what is described as being performed byFigure 3 One or more operations performed by another set of components shown in

[0048] Figure 4 FIG. 400 is a diagram illustrating an example 400 of logical block address status recognition. A host device (e.g., host device 110) may communicate with a memory device 120 to identify the status of a plurality of logical block addresses. The status may indicate, for example, whether each logical block address in the plurality of logical block addresses is valid or invalid. In some embodiments, the memory device 120 may be a NAND device, such as a managed NAND device. Although Figure 4 the host device in

[0049] is described as host device 110, the host device may be any type of device, processor, and / or processing device. For example, the memory device 120 may communicate with a processing device that performs one or more functions of the host device 110.

[0050] As shown by reference numeral 405, the host device 110 may send a command to the memory device 120. The command may be a vendor command. The command may include at least a first parameter and a second parameter. The first parameter may indicate a logical block address start value (LBA start) and the second command may indicate a logical block address range value (LBA range). In some embodiments, the command may instruct the memory device 120 to determine the validity of the number of LBAs corresponding to the LBA range value and starting from the LBA start corresponding to the LBA start value.

[0051] As shown by reference numeral 410, the memory device 120 may identify whether an LBA is valid or invalid. In some embodiments, the memory device 120 and / or the LBA validity component 230 may identify whether an LBA is valid or invalid (e.g., whether the data stored at the LBA is valid or invalid) for each LBA indicated in a command. As described herein, the number of LBAs may correspond to an LBA range indicated by an LBA range value and starting from an LBA start value. For example, the number of LBAs may be equal to the LBA start plus the LBA range minus 1 (LBA start + LBA range – 1). In some embodiments, the memory device 120 may sequentially analyze the LBAs. For example, the memory device 120 may identify whether the data stored at a first LBA (indicated by the LBA start) is valid or invalid. Next, the memory device 120 may identify whether the data stored at a second LBA (LBA start + 1) is valid or invalid. The memory device 120 may repeat this process for each of the number of LBAs, and ultimately, may identify whether the data stored at the last LBA (LBA start + LBA range – 1) indicated in the command is valid or invalid. In some other embodiments, the memory device may analyze the LBAs in parallel. As described herein, if the host device 110 has not written data to an LBA or if the host device 110 has erased data from an LBA, then the memory device 120 may determine that the data stored at the LBA among the number of LBAs is invalid. Alternatively, if the host device 110 has written data to an LBA and the host device 110 has not erased data from the LBA, then the memory device 120 may determine that the data stored at the LBA among the number of LBAs is valid.

[0052] As shown in instance 400, the memory device 120 may analyze each LBA indicated in a command. For example, the memory device 120 may analyze each LBA starting from LBA 00011 and within an LBA range corresponding to the LBA range value 10101. Thus, the memory device 120 may analyze each LBA from LBA 00011 to LBA 10111 to determine whether the LBA is valid or invalid. In an instance where the memory device 120 will sequentially analyze the LBAs, the memory device may first determine whether LBA 00011 is valid or invalid. Next, the memory device 120 may determine whether LBA 00100 is valid or invalid. The memory device 120 may repeat this process for each LBA up to and including 10111.

[0053] As shown by reference numeral 415, the memory device 120 may generate a list of valid and invalid LBAs and may send the list to the host device 110. For example, the memory device 120 and / or the packet generation component 235 may generate a packet that includes a list of LBAs and an indication of whether each LBA in the list of LBAs is valid or invalid. In some embodiments, the memory device 120 and / or the packet generation component 235 may generate a table that includes a plurality of entries, where each entry in the table includes an LBA and a bit indicating whether the LBA is valid or invalid. For example, a bit having a first value (“0”) may indicate that the corresponding LBA is valid, while a bit having a second value (“1”) may indicate that the corresponding LBA is invalid. An example table showing valid and invalid LBAs is shown in Table 1:

[0054] Table 1

[0055] LBA bit 00011 0 00100 1 00101 0 00110 1 00111 1 01000 0 01001 0 01010 1 01011 1 01100 1 01101 1 01110 1 01111 0 10000 0 10001 0 10010 1 10011 0 10100 1 10101 0 11100 1 11101 1

[0056] As shown by reference numeral 420, the host device 110 may compare the LBA data with the data stored at the file system of the host device 110. In some embodiments, the host device 110 and / or the data comparison component 340 may compare one or more valid LBAs (e.g., LBAs indicated as containing valid data in the list of LBAs) with the data stored at the file system of the host device 110. For example, the host device 110 may compare each valid LBA with the corresponding valid file system entry stored at the host device 110. For example, if the host device 110 determines that the data stored at the valid LBA is no longer needed, the data stored at the valid LBA should have been erased at a previous time, and / or the data should not have been written to the valid LBA, then the host device 110 may detect a mismatch between the LBA and the corresponding entry in the file system of the host device 110.

[0057] In Example 400, the host device 110 may compare each valid LBA with the data stored at the file system of the host device 110. For example, the host device 110 may compare LBA 00011, LBA 00101, LBA 01000, LBA01001, LBA 01111, LBA10000, LBA 10001, LBA 10011, and LBA 10101 with the corresponding valid entries in the file system of the host device 110. In one example, the host device 110 may identify a mismatch between LBA 01001 and the valid file system entry corresponding to LBA01001 and may identify a mismatch between LBA 10011 and the valid file system entry corresponding to LBA 10011.

[0058] As shown by reference numeral 425, host device 110 may send an erase command to memory device 120. The erase command may instruct memory device 120 to erase data from one or more valid LBAs associated with the mismatch. For example, if there is a mismatch between an LBA and a corresponding valid entry in the file system of host device 110, host device 110 and / or LBA management component 350 may send an erase command to memory device 120 instructing memory device 120 to erase data from the LBA.

[0059] As shown in instance 400, host device 110 may detect a mismatch associated with LBA 01001 and LBA 10011. For example, host device 110 may detect a mismatch between LBA 01001 and a valid file system entry corresponding to LBA 01001 and may detect a mismatch between LBA 10011 and a valid file system entry corresponding to LBA 10011. Accordingly, host device 110 may send an erase command to memory device 120 instructing memory device 120 to erase data contained in LBA01001 and LBA10011.

[0060] The embodiments described herein enable host device 110 to send a vendor command that requests validity data for multiple LBAs from memory device 120. Additionally, the embodiments described herein may enable memory device 120 to send validity data for multiple LBAs to host device 110. For example, memory device 120 may send a list of LBAs to host device 110 that indicates whether each LBA in the list of LBAs is valid or invalid. Host device 110 may compare each valid LBA in the list of LBAs to a corresponding valid entry in the file system of host device 110. In the case of a mismatch between a valid LBA and a corresponding valid entry in the file system, host device 110 may send an erase command instructing memory device 120 to erase data stored at the valid LBA. This may reduce the fill level of memory device 120, which may enable an improvement in the write performance of memory device 120, faster read and write operations at memory device 120, a reduction in power consumption at memory device 120, and / or an increase in the lifespan of memory device 120. Additionally, the embodiments described herein may enable LBA validity data to be shared with host device 110 without exposing the physical mapping of host device 110 to memory device 120. This may reduce the likelihood of damage to memory device 120. In some embodiments, the vendor command may be used within a Linux environment. Specifically, the vendor command may be used to debug one or more client settings in a Linux environment and / or may be used to determine whether a block discard policy at a Linux device is enabled and operating properly.

[0061] As indicated above, provided Figure 4 as an example. Other examples may differ with respect to Figure 4 the content described.

[0062] Figure 5 is a diagram of an example component 500 included in the memory device 120. As described above in connection with Figure 1 the memory device 120 may include a controller 130 and a memory 140. As Figure 5 shown in, the memory 140 may include a memory array 502. In some embodiments, the memory array 502 is a NAND memory array. However, in some other embodiments, the memory array 502 may be another type of memory array, such as a NOR memory array, a resistive RAM (RRAM) memory array, a magnetoresistive RAM (MRAM) memory array, a ferroelectric RAM (FeRAM) memory array, a spin transfer torque RAM (STT-RAM) memory array, or the like. In some embodiments, the memory array 502 may be part of a three-dimensional stack of memory arrays, such as 3D NAND flash memory, 3D NOR flash memory, or the like.

[0063] The memory array 502 includes a plurality of memory cells 504. The memory cells 504 may store an analog value (e.g., a voltage or a charge) representing a data state (e.g., a digital value). The analog value and the corresponding data state depend on the number of electrons trapped or present in a region of the memory cell 504 (e.g., in a charge trap such as a floating gate), as described below.

[0064] A NAND string 506 (sometimes referred to as a string) may include a plurality of memory cells 504 connected in series. The NAND string 506 is coupled to a bit line 508 (sometimes referred to as a digit line or a column line and shown as BL0 to BLn). Data may be read from or written to the memory cells 504 of the NAND string 506 via the corresponding bit line 508 using one or more input / output (I / O) components 510 (e.g., I / O circuits, I / O buses, page buffers, and / or sensing components such as sense amplifiers). Memory cells 504 of different NAND strings 506 (e.g., one memory cell 504 per NAND string 506) may be coupled to each other via access lines 512 (sometimes referred to as word lines or row lines and shown as AL0 to ALm), and the access lines 512 select which row (which rows) of the memory cells 504 is (are) affected by a memory operation (e.g., a read operation or a write operation).

[0065] The NAND string 506 can be connected to the bit line 508 at one end and to a common source line (CSL) 514 at the other end. A string select line (SSL) 516 can be used to control the corresponding string select transistor 518. The string select transistor 518 selectively couples the NAND string 506 to the corresponding bit line 508. A ground select line (GSL) 520 can be used to control the corresponding ground select transistor 522. The ground select transistor 522 selectively couples the NAND string 506 to the common source line 514.

[0066] A "page" (or "memory page") of the memory can refer to a group of memory cells 504 connected to the same access line 512, as shown by reference numeral 524. In some embodiments (e.g., for single-level cells), the memory cells 504 connected to the access line 512 can be associated with a single page of the memory. In some embodiments (e.g., for multi-level cells), the memory cells 504 connected to the access line 512 can be associated with multiple pages of the memory, where each page represents one bit stored in each of the memory cells 504 (e.g., a lower page representing the first bit stored in each memory cell 504 and an upper page representing the second bit stored in each memory cell 504). In a NAND memory, a page is the smallest physically addressable data unit for a write operation (sometimes referred to as a programming operation).

[0067] In some embodiments, the memory cell 504 is a floating-gate transistor memory cell. In this case, the memory cell 504 can include a channel 526, a source region 528, a drain region 530, a floating gate 532, and a control gate 534. The source region 528, the drain region 530, and the channel 526 can be located on a substrate 536 (e.g., a semiconductor substrate). The memory device 120 can store a data state in the memory cell 504 by charging the floating gate 532 to a specific voltage associated with the data state and / or a voltage within a voltage range associated with the data state. When a specified read voltage is applied to the control gate 534 (e.g., via the corresponding access line 512 connected to the control gate 534), this causes a predefined amount of current to flow through the channel 526 (e.g., from the source region 528 to the drain region 530). Although not shown, a tunneling oxide layer (or tunneling dielectric layer) can be interposed between the floating gate 532 and the channel 526, and a gate oxide layer (e.g., a gate dielectric layer) can be interposed between the floating gate 532 and the control gate 534. As shown, the drain voltage Vd can be supplied from the bit line 508, the control gate voltage Vcg can be supplied from the access line 512, and the source voltage Vs can be supplied via the common source line 514 (in some embodiments, Vs is a ground voltage).

[0068] To write to or program the memory cell 504, when current flows through the channel 526 (e.g., from the common source line 514 to the bit line 508, or vice versa), a strong positive voltage potential can be generated between the control gate 534 and the channel 526 (e.g., by applying a large positive voltage to the control gate 534 via the corresponding access line 512). The strong positive voltage at the control gate 534 causes electrons in the channel 526 to tunnel through the tunnel oxide layer and be trapped in the floating gate 532. These negatively charged electrons then act as an electron barrier between the control gate 534 and the channel 526, which increases the threshold voltage of the memory cell 504. The threshold voltage is the voltage required at the control gate 534 to cause current (e.g., a threshold amount of current) to flow through the channel 526. Fowler-Nordheim tunneling is an example technique for storing charge in the floating gate, and other techniques such as channel hot electron injection can be used.

[0069] To read the memory cell 504, a read voltage can be applied to the control gate 534 (e.g., via the corresponding access line 512), and the I / O component 510 (e.g., a sense amplifier) can determine the data state of the memory cell 504 based on whether current flows through the memory cell 504 (e.g., the channel 526) due to the applied voltage. A pass voltage can be applied to all memory cells 504 (except the memory cell 504 being read) in the same NAND string 506 as the memory cell 504 being read. For example, the pass voltage can be applied to each access line 512 except the access line 512 of the memory cell 504 being read (e.g., where the read voltage is applied here). The pass voltage is higher than the highest read voltage associated with any memory cell data state, such that all other memory cells 504 in the NAND string 506 are turned on, and the I / O component 510 can detect the data state of the memory cell 504 being read by sensing the current (or lack of current) on the corresponding bit line 508. For example, in a single-level memory cell storing one of two data states, if current is detected, the data state is "1", and if no current is detected, the data state is "0". In a multi-level memory cell storing one of three or more data states, multiple read voltages are applied to the control gate 534 over time to distinguish between the three or more data states and determine the data state of the memory cell 504.

[0070] To erase memory cell 504, a strong negative voltage potential may be generated between control gate 534 and channel 526 (e.g., by applying a large negative voltage to control gate 534 via corresponding access line 512). The strong negative voltage at control gate 534 causes trapped electrons in floating gate 532 to tunnel back from floating gate 532 across the oxide layer to channel 526 and flow between common source line 514 and bit line 508. This removes the electron barrier between control gate 534 and channel 526 and reduces the threshold voltage of memory cell 504 (e.g., reduces it to an empty or erased state, which may represent a “1”). In a NAND memory, a block is the smallest memory unit that can be erased. A block of a NAND memory contains multiple pages. Thus, an individual page of a block cannot be erased without erasing every other page of the block. In some embodiments, a block may be divided into multiple sub-blocks. A sub-block is a part of a block and may contain a subset of the pages of the block and / or a subset of the memory cells of the block.

[0071] As indicated above, provided Figure 5 as an example. Other examples may be different from what is described with respect to Figure 5 the description.

[0072] Figure 6 is a flow chart of an example method 600 for logical block address state identification performed by a memory device. In some embodiments, a memory device (e.g., memory device 120) may execute or may be configured to execute method 600. In some embodiments, another device or group of devices (e.g., system 100) separate from or including the memory device may execute or may be configured to execute method 600. Additionally or alternatively, one or more components of the memory device (e.g., controller 130, memory management component 225, LBA validity component 230, and / or packet generation component 235) may execute or may be configured to execute method 600. Thus, the means for performing method 600 may include the memory device and / or one or more components of the memory device. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by a memory device (e.g., controller 130 of memory device 120), cause the memory device to execute method 600.

[0073] As Figure 6 shown, method 600 may include receiving, from a processing device, a command that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value (block 610). As Figure 6Further shown in [the figure], method 600 may include sending a packet to a processing device, the packet including a list of logical block addresses and indicating, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, wherein a first logical block address in the list of logical block addresses corresponds to a logical block address start value, and wherein the number of logical block addresses in the list of logical block addresses corresponds to a logical block address range value (block 620).

[0074] Method 600 may include additional aspects, such as any individual aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0075] In a first aspect, if data has not been written by the processing device to a logical block address in the list of logical block addresses or if data has been erased by the processing device from the logical block address, then the logical block address is invalid, and if data has been written by the processing device to a logical block address in the list of logical block addresses and if the data written to the logical block address has not been erased by the processing device from the logical block address, then the logical block address is valid.

[0076] In a second aspect (either alone or in combination with the first aspect), method 600 includes determining that a logical block address is invalid based on no data being written to the logical block address in the list of logical block addresses or based on data being erased from the logical block address, or determining that a logical block address is valid based on data being written to the logical block address in the list of logical block addresses and based on the data not being erased from the logical block address.

[0077] In a third aspect (either alone or in combination with one or more of the first and second aspects), the number of logical block addresses begins at a logical block address corresponding to the logical block address start value and ends at a logical block address corresponding to the logical block address start value plus the logical block address range value minus 1.

[0078] In a fourth aspect (either alone or in combination with one or more of the first to third aspects), the list of logical block addresses is a table including multiple entries, wherein each entry in the multiple entries includes a logical block address among the number of logical block addresses and a bit, wherein the bit has a first value indicating that the corresponding logical block address is valid, and the bit has a second value indicating that the corresponding logical block address is invalid.

[0079] In a fifth aspect (either alone or in combination with one or more of the first to fourth aspects), method 600 includes, after sending the packet to the processing device, receiving from the processing device an erase command indicating erasure of data from one or more valid logical block addresses.

[0080] In a sixth aspect, either alone or in combination with one or more of the first through fifth aspects, each logical block address among one or more valid logical block addresses is associated with a mismatch between data stored at the logical block address and data stored at the processing device.

[0081] Although Figure 6 illustrative boxes of method 600 are shown, in some embodiments, method 600 may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner compared to the boxes depicted in Figure 6 . Additionally or alternatively, two or more boxes of method 600 may be executed in parallel. Method 600 is an example of a method executable by one or more of the devices described herein. These one or more devices may execute or may be configured to execute one or more other methods based on the operations described herein.

[0082] Figure 7 is a flow diagram of an example method 700 for logical block address status identification to be executed by a host device. In some embodiments, a processing device (e.g., host device 110) may execute or may be configured to execute method 700. In some embodiments, another device or group of devices (e.g., system 100) separate from or including the processing device may execute or may be configured to execute method 700. Additionally or alternatively, one or more components of the host device (e.g., parameter generation component 330, data comparison component 340, and / or LBA management component 350) may execute or may be configured to execute method 700. Thus, the means for executing method 700 may include the host device and / or one or more components of the host device. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the processing device, cause the processing device to execute method 700.

[0083] As Figure 7 shown, method 700 may include sending a command to a memory device that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value (block 710). As Figure 7 further shown, method 700 may include receiving from the memory device a packet that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address start value, and where the number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value (block 720).

[0084] Method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0085] In a first aspect, if data has not been written by a device to a logical block address in a logical block address list or if data has been erased by the device from the logical block address, then the logical block address is invalid, and if data has been written by the device to a logical block address in the logical block address list and if the data written to the logical block address has not been erased by the device from the logical block address, then the logical block address is valid.

[0086] In a second aspect (alone or in combination with the first aspect), the number of logical block addresses begins at a logical block address corresponding to a logical block address start value and ends at a logical block address corresponding to the logical block address start value plus the logical block address range value minus one.

[0087] In a third aspect (alone or in combination with one or more of the first and second aspects), the logical block address list is a table that includes a plurality of entries, where each entry in the plurality of entries includes a logical block address and a bit in the number of logical block addresses, where the bit has a first value indicating that the corresponding logical block address is valid, and the bit has a second value indicating that the corresponding logical block address is invalid.

[0088] In a fourth aspect (alone or in combination with one or more of the first through third aspects), method 700 may detect a mismatch between data stored at a valid logical block address in the logical block address list and data stored at the device for one or more valid logical block addresses.

[0089] In a fifth aspect (alone or in combination with one or more of the first through fourth aspects), method 700 includes, after receiving a packet from a memory device, sending an erase command to the memory device indicating to erase data from one or more valid logical block addresses.

[0090] Although Figure 7 example blocks of method 700 are shown, in some embodiments, compared to the blocks depicted in Figure 7 method 700 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner. Additionally or alternatively, two or more blocks of method 700 may be executed in parallel. Method 700 is an example of a method executable by one or more of the devices described herein. These one or more devices may execute or may be configured to execute one or more other methods based on the operations described herein.

[0091] In some embodiments, a memory device includes one or more components configured to: receive a command from a processing device that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and send a packet to the processing device that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0092] In some embodiments, a system includes a processing device configured to: send a command to a memory device that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and receive a packet from the memory device that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0093] In some embodiments, a device includes: means for receiving a command from a processing device that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and means for sending a packet to the processing device that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0094] In some embodiments, a device includes: means for sending a command to a memory device that includes at least a first parameter and a second parameter, where the first parameter indicates a logical block address starting value and the second parameter indicates a logical block address range value; and means for receiving a packet from the memory device that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, where a first logical block address in the list of logical block addresses corresponds to the logical block address starting value, and where a number of logical block addresses in the list of logical block addresses corresponds to the logical block address range value.

[0095] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or obtained from practice of the embodiments described herein.

[0096] Even if a particular combination of features is recited in the appended claims and / or disclosed in the present specification, such combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features may be combined in ways not explicitly recited in the appended claims and / or not explicitly disclosed in the present specification. For example, the present disclosure encompasses each dependent claim in a claim set in combination with each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase “at least one of” with respect to a list of items refers to any combination of those items, including a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination with multiples of the same element (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c or any other ordering of a, b, and c).

[0097] When a “component” or “one or more components” (or another element, such as a “controller” or “one or more controllers”) is described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise explicitly claimed (e.g., by using “a first component” and “a second component” or other language that differentiates components in the claims), such language is intended to cover a single component that performs or is configured to perform all operations, a group of components that jointly perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform the operations. For example, when a claim has the form “one or more components, configured to: perform X; perform Y; and perform Z,” the claim should be interpreted to mean “one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (also possibly different) components configured to perform Z.”

[0098] Elements, acts, or instructions used herein should not be construed as critical or essential unless expressly described as such. Also, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Additionally, as used herein, the article "the" is intended to include one or more items referenced in conjunction with the article "the" and may be used interchangeably with "the one or more." Where only one item is intended, the phrase "only one," "single," or similar language is used. Also, as used herein, the term "has / have / having" or the like is intended to be an open-ended term that does not limit the element it modifies (e.g., an element that "has" A may also have B). Additionally, unless expressly stated otherwise, the phrase "based on" is intended to mean "at least partially based on." As used herein, the term "multiple" may be replaced with "a plurality of," and vice versa. Also, as used herein, unless expressly stated otherwise (e.g., if used in combination with "any" or "only one of..."), the term "or" when used in a series is intended to be inclusive and may be used interchangeably with "and / or."

Claims

1. A memory device, comprising: One or more components configured to: receiving a command including at least a first parameter and a second parameter from a processing device, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and sending a packet to the processing device that includes a list of logical block addresses and indicates, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, The first logical block address in the logical block address list corresponds to the logical block address start value, and the number of logical block addresses in the logical block address list corresponds to the logical block address range value.

2. A memory device according to claim 1, wherein if data has not been written by the processing device to a logical block address in the logical block address list or if data has been erased from the logical block address by the processing device, then the logical block address is invalid, and wherein if data has been written by the processing device to the logical block address in the logical block address list and if the data that has been written to the logical block address has not been erased from the logical block address by the processing device, then the logical block address is valid.

3. The memory device of claim 1 , wherein the one or more components are configured to: determining that the logical block address is invalid based on no data being written to the logical block address in the logical block address list or based on the data being erased from the logical block address; or The logical block address is determined to be valid based on data being written to the logical block address in the logical block address list and based on the data not being erased from the logical block address.

4. The memory device of claim 1, wherein the number of logical block addresses begins at a logical block address corresponding to the logical block address start value and ends at a logical block address corresponding to the logical block address start value plus the logical block address range value minus 1.

5. The memory device of claim 1 , wherein the logical block address list is a table comprising a plurality of entries, wherein each entry of the plurality of entries comprises a logical block address and a bit among the number of logical block addresses, wherein the bit has a first value indicating that the corresponding logical block address is valid, and the bit has a second value indicating that the corresponding logical block address is invalid.

6. The memory device of claim 1, wherein the one or more components are configured to receive an erase command from the processing device indicating to erase data from one or more valid logical block addresses after sending the packet to the processing device.

7. The memory device of claim 6, wherein each logical block address of the one or more valid logical block addresses is associated with a mismatch between data stored at the logical block address and data stored at the processing device.

8. A system comprising: A processing device configured to: sending a command including at least a first parameter and a second parameter to a memory device, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and receiving from the memory device a packet including a list of logical block addresses and indicating, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, The first logical block address in the logical block address list corresponds to the logical block address start value, and the number of logical block addresses in the logical block address list corresponds to the logical block address range value.

9. A system according to claim 8, wherein if data has not been written by the processing device to the logical block address in the logical block address list or if data has been erased from the logical block address by the processing device, then the logical block address is invalid, and wherein if data has been written by the processing device to the logical block address in the logical block address list and if the data that has been written to the logical block address has not been erased from the logical block address by the processing device, then the logical block address is valid.

10. The system of claim 8, wherein the number of logical block addresses begins at a logical block address corresponding to the logical block address start value and ends at a logical block address corresponding to the logical block address start value plus the logical block address range value minus 1.

11. The system of claim 8, wherein the logical block address list is a table comprising a plurality of entries, wherein each entry of the plurality of entries comprises a logical block address and a bit among the number of logical block addresses, wherein the bit has a first value indicating that the corresponding logical block address is valid, and the bit has a second value indicating that the corresponding logical block address is invalid.

12. The system of claim 8, wherein the processing device is further configured to detect, for one or more valid logical block addresses in the logical block address list, a mismatch between data stored at the valid logical block address and data stored at the processing device.

13. The system of claim 12, wherein the processing device is further configured to send an erase command to the memory device instructing to erase data from the one or more valid logical block addresses after receiving the packet from the memory device.

14. An apparatus comprising: means for receiving from a processing device a command comprising at least a first parameter and a second parameter, wherein the first parameter indicates a logical block address start value and the second parameter indicates a logical block address range value; and means for sending to the processing device a packet including a list of logical block addresses and indicating, for each logical block address in the list of logical block addresses, whether the logical block address is valid or invalid, The first logical block address in the logical block address list corresponds to the logical block address start value, and the number of logical block addresses in the logical block address list corresponds to the logical block address range value.

15. An apparatus according to claim 14, wherein if data has not been written by the processing device to the logical block address in the logical block address list or if data has been erased from the logical block address by the processing device, then the logical block address is invalid, and wherein if data has been written by the processing device to the logical block address in the logical block address list and if the data that has been written to the logical block address has not been erased from the logical block address by the processing device, then the logical block address is valid.

16. The apparatus of claim 14, further comprising: means for determining that the logical block address is invalid based on no data being written to the logical block address in the logical block address list or based on the data being erased from the logical block address; or Means for determining that the logical block address is valid based on data being written to the logical block address in the logical block address list and based on the data not being erased from the logical block address.

17. The apparatus of claim 14, wherein the number of logical block addresses begins at a logical block address corresponding to the logical block address start value and ends at a logical block address corresponding to the logical block address start value plus the logical block address range value minus 1.

18. The apparatus of claim 14, wherein the logical block address list is a table comprising a plurality of entries, wherein each entry of the plurality of entries comprises a logical block address and a bit among the number of logical block addresses, wherein the bit has a first value indicating that the corresponding logical block address is valid, and the bit has a second value indicating that the corresponding logical block address is invalid.

19. The apparatus of claim 14, further comprising means for receiving an erase command from the processing device indicating to erase data from one or more valid logical block addresses after sending the packet to the processing device.

20. The apparatus of claim 19, wherein each logical block address of the one or more valid logical block addresses is associated with a mismatch between data stored at the logical block address and data stored at the processing device.

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