Semiconductor device and operating method using the same

Abstract

The present disclosure relates to a semiconductor device and an operating method using the same, the semiconductor device may include: a first source line driving circuit driving a first source line; a second source line driving circuit driving the second source line; a first memory block including a plurality of first memory strings respectively coupled between the first source line and the plurality of bit lines; and a second memory block including a plurality of second memory strings respectively coupled between the second source line and the plurality of bit lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0170321, filed on November 30, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor integrated circuit, and more particularly, to a semiconductor device and an operating method using the semiconductor device. Background Art

[0004] Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a need for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices. Semiconductor devices can be roughly classified into volatile memory devices and non - volatile memory devices. Volatile memory devices have a high data processing speed, but the disadvantage is that continuous power supply is required to retain the stored data, while non - volatile memory devices do not require continuous power supply to retain the stored data, but their disadvantage is low data processing speed.

[0005] Non - volatile memory devices perform a programming operation to store data therein and perform an erase operation to erase the stored data. Non - volatile memory devices perform an operation to verify whether the data has been properly programmed or erased during the programming operation or the erase operation.

[0006] Therefore, in order to improve the data processing speed of non - volatile memory devices, research is being conducted to reduce the time required for programming or erase operations and the time required for verifying each operation. Summary of the Invention

[0007] A semiconductor device according to an embodiment of the present disclosure may include: a first source - line driving circuit that drives a first source line; a second source - line driving circuit that drives a second source line; a first memory block including a plurality of first memory strings respectively connected between the first source line and a plurality of bit lines; and a second memory block including a plurality of second memory strings respectively connected between the second source line and a plurality of bit lines.

[0008] An operating method of a semiconductor device according to an embodiment of the present disclosure may include: driving the first source line to a level of an erase voltage; driving the second source line to a level of a ground voltage or a power supply voltage; performing an erase operation on the first memory block connected to the first source line; and performing a read operation or a programming operation on the second memory block connected to the second source line. Brief Description of the Drawings

[0009] Figure 1Is a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 Is a diagram for describing a semiconductor device according to another embodiment of the present disclosure.

[0011] Figure 3 And Figure 4 Is a diagram for describing a memory block of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5 Is a diagram for describing a page buffer of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 And Figure 7 Is a diagram for describing the operation of a semiconductor device according to an embodiment of the present disclosure. Detailed Description

[0014] Various embodiments of the present disclosure aim to provide a semiconductor device in which, when some of the memory blocks sharing a page buffer are performing a specific operation, at least one other memory block can perform an operation different from the specific operation.

[0015] Embodiments of the present disclosure can improve the operation speed of a memory device because each memory block can perform mutually different operations.

[0016] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0017] Figure 1 Is a diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0018] Referring to Figure 1 , a semiconductor device according to an embodiment of the present disclosure may include a control circuit 100, a line driving circuit 200, a page buffer group 300, a cell array 400, a first source line driving circuit (SD1) 510, and a second source line driving circuit (SD2) 520.

[0019] The control circuit 100 can control the line driver circuit 200 and the page buffer bank 300. For example, the control circuit 100 can control the line driver circuit 200 and the page buffer bank 300 based on the command signal CMD and the address signal ADD. The control circuit 100 can generate a driving address signal ADD_d based on the command signal CMD and the address signal ADD. The control circuit 100 can control the line driver circuit 200 by providing the driving address signal ADD_d to the line driver circuit 200. The control circuit 100 can also generate a page buffer control signal PB_ctrl based on the command signal CMD and the address signal ADD. The control circuit 100 can control the page buffer bank 300 by providing the page buffer control signal PB_ctrl to the page buffer bank 300.

[0020] The line driver circuit 200 can receive the driving address signal ADD_d from the control circuit 100. The line driver circuit 200 can drive each of the drain select lines DSL, word lines WL, and source select lines SSL to at least one voltage level among multiple voltage levels based on the driving address signal ADD_d. For example, the multiple voltages can be voltages provided from inside or outside the semiconductor device, and the multiple voltages can have different voltage levels. The multiple voltages can include a pass voltage, a read voltage, and a program voltage having mutually different voltage levels.

[0021] The page buffer bank 300 can include multiple page buffers PB1 to PBn. The multiple page buffers PB1 to PBn can be respectively connected to multiple bit lines BL1 to BLn. During a read operation, each of the multiple page buffers PB1 to PBn can sense the value of data stored in the memory cells of the cell array 400 through the bit lines under the control of the page buffer control signal PB_ctrl, and output the sensed value as data DATA. During a verify operation, each of the multiple page buffers PB1 to PBn can output the threshold voltage of the memory cells sensed through the bit lines as a verify result under the control of the page buffer control signal PB_ctrl. During a program operation, each of the multiple page buffers PB1 to PBn can adjust the voltage level of the bit lines under the control of the page buffer control signal PB_ctrl.

[0022] The unit array 400 may include a plurality of memory blocks. For example, the plurality of memory blocks may include a first memory block BK1 and a second memory block BK2. Each of the first memory block BK1 and the second memory block BK2 may be selected via a word line WL. The memory strings of a selected one of the first memory block BK1 and the second memory block BK2 may be connected to a plurality of page buffers PB1 to PBn via a plurality of bit lines BL1 to BLn. Each of the first memory block BK1 and the second memory block BK2 may include a plurality of memory strings in which a plurality of memory cells are connected in series. In addition to the plurality of memory cells connected in series, each of the plurality of memory strings may further include a first select transistor and a second select transistor (e.g., a drain select transistor and a source select transistor). The first select transistor may be configured to be turned on or off via a drain select line DSL, and the second select transistor may be configured to be turned on or off via a source select line SSL. The plurality of memory strings included in the first memory block BK1 may be connected between a first source line SL1 and the plurality of bit lines BL1 to BLn. The plurality of memory strings included in the second memory block BK2 may be connected between a second source line SL2 and the plurality of bit lines BL1 to BLn.

[0023] The first source line driving circuit 510 may drive the first source line SL1. For example, during a read operation or a program operation, the first source line driving circuit 510 may drive the first source line SL1 to a first voltage level. During an erase operation, the first source line driving circuit 510 may drive the first source line SL1 to a second voltage level.

[0024] The second source line driving circuit 520 may drive the second source line SL2. For example, during a read operation or a program operation, the second source line driving circuit 520 may drive the second source line SL2 to a first voltage level. During an erase operation, the second source line driving circuit 520 may drive the second source line SL2 to a second voltage level. In this case, the first voltage level may be a ground voltage level, and the second voltage level may be an erase voltage greater than the ground voltage level.

[0025] In a semiconductor device according to an embodiment of the present disclosure configured as described above, when one of a first memory block BK1 and a second memory block BK2 performs a read operation or a program operation by using an electrically disconnected first source line SL1 or second source line SL2, the other of the first memory block BK1 and the second memory block BK2 may perform an erase operation. For example, when a first voltage is provided to the first source line SL1 and a second voltage is provided to the second source line SL2, a read operation or a program operation may be performed on a selected memory string of the first memory block BK1 according to a word line WL, a drain select line DSL, and a source select line SSL. When performing a read operation or a program operation on the first memory block BK1, an erase operation may be performed on all memory strings of the second memory block BK2.

[0026] A semiconductor device according to an embodiment of the present disclosure may include source lines that are electrically disconnected from each other for each memory block sharing a plurality of bit lines, and a source line driving circuit that drives each source line such that when performing a read operation or a write operation on one of the memory blocks, an erase operation may be performed on at least one other memory block. In a semiconductor device according to an embodiment of the present disclosure, the memory blocks share a plurality of bit lines such that after performing a read operation or a write operation, an erase verification operation may be performed on at least one memory block that has undergone an erase operation.

[0027] Figure 2 is a diagram for describing a semiconductor device according to another embodiment of the present disclosure. In Figure 2 Since other configurations except for the cell array 400 in Figure 2 are the same as the configuration of Figure 1 only the configuration of the cell array 400 will be described below.

[0028] Referring to Figure 2, the unit array 400 may include a plurality of memory blocks. For example, the plurality of memory blocks may include a first memory block BK1-1 to BK1-i and a second memory block BK2-1 to BK2-j. Each of the first memory block BK1-1 to BK1-i and the second memory block BK2-1 to BK2-j may be selected by a word line WL. The memory strings of one memory block selected from the first memory block BK1-1 to BK1-i and the second memory block BK2-1 to BK2-j may be connected to a plurality of page buffers PB1 to PBn through a plurality of bit lines BL1 to BLn. Each of the first memory block BK1-1 to BK1-i and the second memory block BK2-1 to BK2-j may further include a plurality of memory strings in which a plurality of memory cells are connected in series. In addition to the plurality of memory cells connected in series, each of the plurality of memory strings may further include a first selection transistor and a second selection transistor (e.g., a drain selection transistor and a source selection transistor). The first selection transistor may be configured to be turned on or off through a drain selection line DSL, and the second selection transistor may be configured to be turned on or off through a source selection line SSL. The plurality of memory strings included in the first memory block BK1-1 to BK1-i may be connected between a first source line SL1 and a plurality of bit lines BL1 to BLn. The plurality of memory strings included in the second memory block BK2-1 to BK2-j may be connected between a second source line SL2 and a plurality of bit lines BL1 to BLn.

[0029] The first memory block BK1-1 to BK1-i may be connected to a first source line SL1 driven by a first source line driver circuit (SD1) 510. The second memory block BK2-1 to BK2-j may be connected to a second source line SL2 driven by a second source line driver circuit (SD2) 520. Hereinafter, the configuration and operation of the semiconductor device according to an embodiment of the present disclosure will be described in detail.

[0030] Figure 3 and Figure 4 are diagrams for describing the memory blocks of the semiconductor device according to an embodiment of the present disclosure. The drain selection line DSL may include at least one first drain selection line DSLA ( Figure 3 ) and at least one second drain selection line DSLB ( Figure 4 ). The word line WL may include a plurality of first word lines WL1A to WLnA ( Figure 3 ) and a plurality of second word lines WL1B to WLnB ( Figure 4 ). The source selection line SSL may include at least one first source selection line SSLA ( Figure 3 ) and at least one second source selection line SSLB ( Figure 4 ).

[0031] First, refer to Figure 3The first memory block BK1 is described as follows.

[0032] The first memory block BK1 may include a plurality of first memory strings St_1A to St_nA connected between a plurality of bit lines BL1 to BLn and a first source line SL1. The plurality of bit lines BL1 to BLn may include a first bit line BL1 to an nth bit line BLn. For example, the first memory string St_1A may be connected between the first bit line BL1 and the first source line SL1. The first memory string St_2A may be connected between the second bit line BL2 and the first source line SL1. The first memory string St_nA may be connected between the nth bit line BLn and the first source line SL1.

[0033] Each of the plurality of first memory strings St_1A to St_nA may include a first drain select transistor DSTA, a plurality of first memory cells MC1A to MCnA, and a first source select transistor SSTA connected in series. The first drain select transistor DSTA may be configured to be controlled by a first drain select line DSLA, and the first source select transistor SSTA may be configured to be controlled by a first source select line SSLA. The plurality of first memory cells MC1A to MCnA may be configured to be controlled by a plurality of first word lines WL1A to WLnA, respectively.

[0034] The operation of the first memory block BK1 of the semiconductor device according to an embodiment of the present disclosure configured as described above is described as follows.

[0035] During a programming operation, the first source line SL1 may be driven to an external power supply voltage level by a first source line driver circuit (SD1) 510. A ground voltage may be provided to at least one bit line selected from the first bit line BL1 to the nth bit line BLn, and an external power supply voltage may be provided to the unselected bit lines. A programming voltage may be provided to a word line selected from the plurality of first word lines WL1A to WLnA, and a pass voltage may be provided to the remaining unselected word lines. The first drain select transistor DSTA may be turned on, and the first source select transistor SSTA may be turned off.

[0036] In this case, among the memory cells of the memory string connected to the selected bit line - that is, the bit line whose received voltage level is greater than the ground voltage - the memory cells receiving the programming voltage through the selected word line may be programmed.

[0037] The semiconductor device is described in more detail using examples.

[0038] During a programming operation, the first bit line BL1 is selected from the first bit line BL1 to the nth bit line BLn, and the first first word line WL1A is selected from the plurality of first word lines WL1A to WLnA.

[0039] In this case, the first memory cell MC1A among the first memory cells MC1A to MCnA of the first first memory string St_1A connected to the selected bit line, that is, the first bit line BL1 receiving the ground voltage, which is connected to the first first word line WL1A, can be programmed.

[0040] During a read operation, the first source line SL1 can be driven to the ground voltage level by the first source line driving circuit 510. A voltage greater than the ground voltage can be provided to at least one bit line selected from the first bit line BL1 to the nth bit line BLn. A read voltage can be provided to the word line selected from the plurality of first word lines WL1A to WLnA, and a pass voltage can be provided to the remaining unselected word lines. The first drain select transistor DSTA and the first source select transistor SSTA can be turned on so that current can flow through the memory string connected to the selected bit line.

[0041] At least one memory string selected from the plurality of first memory strings St_1A to St_nA and connected to at least one bit line can allow current to flow from the bit line to the first source line SL1. In this case, the amount of current flowing from the bit line to the first source line SL1 can be adjusted according to the data stored in the memory cells included in the at least one memory string that receive the read voltage through the selected word line. In this case, the page buffer connected to the selected bit line can sense and store the data stored in the memory cells receiving the read voltage by detecting the voltage level of the selected bit line or the amount of current flowing through the bit line. The read operation can be completed by outputting the data stored in the page buffer.

[0042] During an erase operation, the first source line SL1 can be driven to an erase voltage level greater than the ground voltage level by the first source line driving circuit 510. The first drain select transistor DSTA can be turned off, and the first source select transistor SSTA can be turned on. A ground voltage can be provided to the plurality of first word lines WL1A to WLnA. In this case, an erase operation can be performed on the memory cells included in the plurality of first memory strings St_1A to St_nA connected to the first source line SL1.

[0043] After performing a programming operation or an erase operation, a verification operation can be performed using the plurality of page buffers PB connected to the first bit line BL1 to the nth bit line BLn through the first drain select transistor DSTA.

[0044] As described above, the first memory block BK1 performs read, program, and verify operations while the first drain select transistor DSTA is turned on, such that the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 can be electrically connected to the plurality of bit lines BL1 to BLn, respectively, during the read, program, and verify operations.

[0045] The first memory block BK1 further performs an erase operation while the first drain select transistor DSTA is turned off, such that the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 can be electrically disconnected from the plurality of bit lines BL1 to BLn, respectively, during the erase operation.

[0046] The following will refer to Figure 4 describe the second memory block BK2 as follows.

[0047] The second memory block BK2 may include a plurality of second memory strings St_1B to St_nB connected between the plurality of bit lines BL1 to BLn and the second source line SL2. The plurality of bit lines BL1 to BLn may include a first bit line BL1 to an nth bit line BLn. For example, the second memory string St_1B may be connected between the first bit line BL1 and the second source line SL2. The second memory string St_2B may be connected between the second bit line BL2 and the second source line SL2. The second memory string St_nB may be connected between the nth bit line BLn and the second source line SL2.

[0048] Each of the plurality of second memory strings St_1B to St_nB may include a second drain select transistor DSTB, a plurality of second memory cells MC1B to MCnB, and a second source select transistor SSTB connected in series. The second drain select transistor DSTB may be configured to be controlled by a second drain select line DSLB, and the second source select transistor SSTB may be configured to be controlled by a second source select line SSLB. The plurality of second memory cells MC1B to MCnB may be configured to be controlled by a plurality of second word lines WL1B to WLnB, respectively.

[0049] The operation of the second memory block BK2 of the semiconductor device according to an embodiment of the present disclosure will be described as follows.

[0050] During a programming operation, the second source line SL2 can be driven to an external power supply voltage level by a second source line driver circuit (SD2) 520. A ground voltage can be provided to at least one bit line selected from the first bit line BL1 to the nth bit line BLn, and an external power supply voltage can be provided to the unselected bit lines. A programming voltage can be provided to a word line selected from a plurality of second word lines WL1B to WLnB, and a pass voltage can be provided to the remaining unselected word lines. The second drain select transistor DSTB can be turned on, and the second source select transistor SSTB can be turned off.

[0051] In this case, among the memory cells of the memory string connected to the selected bit line, i.e., the bit line receiving the ground voltage, the memory cells receiving the programming voltage through the selected word line can be programmed.

[0052] During a read operation, the second source line SL2 can be driven to a ground voltage level by the second source line driver circuit 520. A voltage greater than the ground voltage can be provided to at least one bit line selected from the first bit line BL1 to the nth bit line BLn. A read voltage can be provided to a word line selected from a plurality of second word lines WL1B to WLnB, and a pass voltage can be provided to the remaining unselected word lines. The second drain select transistor DSTB and the second source select transistor SSTB can be turned on so that current can flow through the memory string connected to the selected bit line.

[0053] At least one memory string selected from a plurality of second memory strings St_1B to St_nB and connected to at least one bit line can allow current to flow from the bit line to the second source line SL2. In this case, the amount of current flowing from the bit line to the second source line SL2 can be adjusted according to the data stored in the memory cells included in the at least one memory string that receive the read voltage through the selected word line. In this case, the page buffer connected to the selected bit line can sense and store the data stored in the memory cells receiving the read voltage by detecting the voltage level of the selected bit line or the amount of current flowing through the bit line. The read operation can be completed by outputting the data stored in the page buffer.

[0054] During an erase operation, the second source line SL2 can be driven to an erase voltage level greater than the ground voltage level by the second source line driver circuit 520. The second drain select transistor DSTB can be turned off, and the second source select transistor SSTB can be turned on. A ground voltage can be provided to a plurality of second word lines WL1B to WLnB. In this case, an erase operation can be performed on the memory cells included in the plurality of second memory strings St_1B to St_nB connected to the second source line SL2.

[0055] After performing a programming operation or an erasing operation, a verification operation may be performed using a plurality of page buffers PB connected to first bit lines BL1 to n-th bit lines BLn through second drain select transistors DSTB.

[0056] As described above, the second memory block BK2 performs a read operation, a programming operation, and a verification operation in a state where the second drain select transistor DSTB is turned on, so that a plurality of second memory strings St_1B to St_nB included in the second memory block BK2 can be electrically connected to a plurality of bit lines BL1 to BLn, respectively, during the read operation, the programming operation, and the verification operation.

[0057] The second memory block BK2 performs an erasing operation in a state where the second drain select transistor DSTB is turned off, so that a plurality of second memory strings St_1B to St_nB included in the second memory block BK2 can be electrically disconnected from a plurality of bit lines BL1 to BLn, respectively, during the erasing operation.

[0058] In this way, a semiconductor device according to an embodiment of the present disclosure may include source lines for each of a plurality of memory blocks that share a plurality of bit lines. In addition, the semiconductor device may supply a ground voltage to the source lines of the memory block that performs a programming operation, a read operation, and a verification operation in a state where the memory block that performs a programming operation, a read operation, and a verification operation is connected to a plurality of bit lines and the memory block that performs an erasing operation is electrically disconnected from the plurality of bit lines, and may supply an erasing voltage having a voltage level greater than the ground voltage to the source lines of the memory block that performs an erasing operation. Therefore, a semiconductor device according to an embodiment of the present disclosure may allow some of a plurality of memory blocks to perform a programming operation, a read operation, and a verification operation, while allowing other memory blocks to perform an erasing operation.

[0059] Figure 5 is a diagram for describing a page buffer of a semiconductor device according to an embodiment of the present disclosure.

[0060] Figure 5 The page buffer PB of the semiconductor device according to an embodiment of the present disclosure shown may have Figure 1 the configuration of each of the plurality of page buffers PB1 to PBn shown.

[0061] Referring to Figure 5 , the page buffer PB may include a plurality of latches Latch1 to Latch5 and a first switch SW1. In this case, the page buffer PB including the first latch Latch1 to the fifth latch Latch5 and the first switch SW1 is described as an example, and the number of latches is not limited.

[0062] The first switch SW1 can electrically connect or disconnect the bit line BL and the common node Node_SO from each other based on the first page buffer selection signal PBSelA. The first switch SW1 can include a transistor TR. The transistor TR can receive the first page buffer selection signal PBSelA through its gate, and the bit line BL and the common node Node_SO can be respectively connected to both ends (drain and source) of the transistor TR.

[0063] Each of the first latch Latch1 to the fifth latch Latch5 can be connected to the common node Node_SO. In this case, the first latch Latch1 can be set to be closest to the bit line BL, and the fifth latch Latch5 can be set to be farthest from the bit line BL. The second latch Latch2 to the fourth latch Latch4 can be set between the first latch Latch1 and the fifth latch Latch5.

[0064] The first latch Latch1 can be a sense latch. The first latch Latch1 can sense the voltage level of the bit line BL or the amount of current in the bit line BL, and store data according to the sensed value. Therefore, the first latch Latch1 can be controlled to be activated during a read operation or a verify operation.

[0065] The fifth latch Latch5 can be a cache latch. The fifth latch Latch5 can receive data DATA from outside the page buffer PB and store the received data DATA during a programming operation, or output the data DATA to outside the page buffer PB during a read operation. Therefore, the fifth latch Latch5 can be controlled to be activated during a programming operation or a read operation.

[0066] The second latch Latch2 to the fourth latch Latch4 can be data storage latches. Figure 5 The reason for showing and describing the data storage latches as three latches Latch2 to Latch4 is that the memory cell can store 3-bit (LSB, CSB, MSB) data. Therefore, during a programming operation, the second latch Latch2 to the fourth latch Latch4 can store the 3-bit (LSB, CSB, MSB) data transmitted from the fifth latch Latch5. During a read operation, the second latch Latch2 to the fourth latch Latch4 can store the 3-bit (LSB, CSB, MSB) data sent from the first latch Latch1. Therefore, the second latch Latch2 to the fourth latch Latch4 can be controlled to be activated during a read operation or a programming operation. The number of data storage latches can vary according to the number of data bits that can be stored in the memory cell.

[0067] Figure 6 and Figure 7 are diagrams for describing the operation of a semiconductor device according to an embodiment of the present disclosure.

[0068] As Figure 6 shown, a semiconductor device according to an embodiment of the present disclosure may perform an erase operation by using an Incremental Step Pulse Erase (ISPE) method of gradually increasing the level of an erase voltage provided to a first source line SL1 or a second source line SL2 or both the first source line SL1 and the second source line SL2.

[0069] That is, each of the memory blocks BK1 and BK2 included in a semiconductor device according to an embodiment of the present disclosure may perform an erase operation by using the ISPE method. Referring to Figure 6 , an erase operation of each of the memory blocks BK1 and BK2 according to the ISPE method is described. In this case, in Figure 6 , for ease of description, the source lines SL1 and SL2 and the word lines WL1A to WLnA and WL1B to WLnB of each of the memory blocks BK1 and BK2 are respectively shown as SL and WL.

[0070] Referring to Figure 6 , in a state where the word line WL is at a ground voltage level, a first erase pulse 1 st Pulse having an erase voltage level may be provided to the source line SL so that a first erase operation may be performed.

[0071] After the first erase operation ends, a first erase verification operation may be performed by driving the source line SL to a ground voltage level and providing a read voltage Vread to the word line WL. In this case, when it is determined that the first erase operation has failed in the first erase verification operation, a second erase operation may be performed.

[0072] The second erase operation may be performed by driving the word line WL to a ground voltage level again and providing a second erase pulse 2 nd Pulse to the source line SL. In this case, the voltage level of the second erase pulse 2 nd Pulse may be a voltage level greater than the voltage level of the first erase pulse 1 st Pulse. That is, the erase voltage provided to the source line SL during the second erase operation may be an erase voltage having a voltage level greater than the voltage level during the first erase operation by a preset voltage level V STEP .

[0073] After the second erasing operation is completed, a second erasing verification operation can be performed by driving the source line SL to a ground voltage level and applying a read voltage Vread to the word line WL. In this case, when the second erasing operation is determined to be successful (Pass) in the second erasing verification operation, the erasing operation of the memory block can be terminated.

[0074] When the second erasing operation is determined to be a failure (Fail), a third erasing operation can be performed, and the level of the erasing voltage applied to the source line SL in the third erasing operation can be greater than the erasing voltage level in the second erasing operation.

[0075] In this way, a semiconductor device according to an embodiment of the present disclosure can perform an ISPE erasing operation and apply a source voltage to a source line that is electrically disconnected, where the voltage level of the source voltage gradually increases. For example, Figure 1 each of the illustrated first source line driving circuit 510 and second source line driving circuit 520 can be configured to apply an erasing voltage according to the ISPE method during an erasing operation.

[0076] Figure 7 It is shown that in memory blocks BK1 and BK2 included in a semiconductor device according to an embodiment of the present disclosure, some of the memory blocks BK1 are performing an erasing operation (Erase), while the remaining memory blocks BK2 are performing a read operation (Read) or a programming operation (Program). In this case, for convenience of description, the first memory block BK1 performs an erasing operation, and the second memory block BK2 performs a read operation.

[0077] Refer to Figure 3 and Figure 4 to describe the first memory block BK1 performing an erasing operation and the second memory block BK2 performing a read operation or a programming operation.

[0078] The erasing operation can be performed while the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 are electrically disconnected from the respective bit lines BL1 to BLn. In this case, the first source line SL1 can be driven by the first source line driving circuit 510 to the level of the erasing voltage.

[0079] The read operation or the programming operation can be performed while the plurality of second memory strings St_1B to St_nB included in the second memory block BK2 are electrically connected to the respective bit lines BL1 to BLn. In this case, the second source line driving circuit 520 can drive the second source line SL2 to a ground voltage level during the read operation, and drive the second source line SL2 to an external power supply voltage level during the programming operation.

[0080] As described above, when the first memory block BK1 performs a read operation or a program operation and the second memory block BK2 performs an erase operation, the first memory block BK1 may be electrically connected to a plurality of bit lines BL1 to BLn, and the second memory block BK2 may be electrically disconnected from the plurality of bit lines BL1 to BLn. The first source line SL1 may be driven by the first source line driver circuit 510 to a ground voltage level or a level of an external power supply voltage, while the second source line SL2 may be driven by the second source line driver circuit 520 to an erase voltage level.

[0081] Subsequently, when another memory block completes a read operation or a program operation, the memory block that has performed the erase operation may be electrically connected to the plurality of bit lines BL1 to BLn and perform a verification operation of the erase operation through the plurality of page buffers PB1 to PBn.

[0082] In this way, the semiconductor device according to an embodiment of the present disclosure may be configured to include a source line for each of a plurality of memory blocks, and may control some of the plurality of memory blocks to perform an erase operation while other memory blocks perform a read operation or a program operation. Therefore, the semiconductor device according to an embodiment of the present disclosure may perform an erase operation and other operations simultaneously, thereby performing more operations required by a host than a conventional semiconductor device that separately performs an erase operation and other operations.

[0083] Although embodiments according to the technical idea of the present disclosure have been described above with reference to the drawings, this is only for describing embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical idea of the present disclosure defined by the claims, those skilled in the art to which the present disclosure pertains may make various types of substitutions, modifications, and changes to the embodiments, and it should be understood that these substitutions, modifications, and changes all fall within the scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: A first source line driving circuit drives a first source line; A second source line driving circuit drives a second source line; A first memory block including a plurality of first memory strings respectively connected between the first source line and a plurality of bit lines; as well as The second memory block includes a plurality of second memory strings respectively coupled between the second source lines and the plurality of bit lines.

2. The semiconductor device according to claim 1, wherein The first source line driving circuit and the second source line driving circuit respectively drive the first source line and the second source line to mutually different voltage levels.

3. The semiconductor device according to claim 2, wherein: When a read operation or a program operation is performed on the first memory block, the first source line driving circuit drives the first source line to a ground voltage level or a power supply voltage level, and When an erase operation is performed on the first memory block, the first source line driving circuit drives the first source line to an erase voltage level greater than the ground voltage level.

4. The semiconductor device according to claim 3, wherein: When a read operation or a program operation is performed on the second memory block, the second source line driving circuit drives the second source line to the ground voltage level or the power supply voltage level, and When an erase operation is performed on the second memory block, the second source line driving circuit drives the second source line to the erase voltage level. 5 . The semiconductor device according to claim 4 , further comprising a plurality of page buffers respectively coupled to the plurality of bit lines.

6. The semiconductor device according to claim 5, wherein: The plurality of page buffers are electrically coupled to a selected memory block of the first memory block and the second memory block through the plurality of bit lines and perform a read operation or a verification operation for a program operation, and The selected memory block performs a read operation or a program operation.

7. The semiconductor device according to claim 6, wherein: The plurality of page buffers are electrically disconnected from a specific memory block of the first memory block and the second memory block, and Wherein, the specific storage block performs the erase operation.

8. The semiconductor device according to claim 7, wherein: When the erase operation is completed, the plurality of page buffers are electrically coupled to the specific memory block on which the erase operation has been performed, and a verification operation for the erase operation is performed.

9. The semiconductor device according to claim 1, wherein: Each of the plurality of first memory strings and the plurality of second memory strings comprises: a plurality of drain selection transistors respectively connected to the plurality of bit lines; a plurality of source selection transistors coupled to the first source line or the second source line; and A plurality of memory cells are coupled in series between each of the plurality of drain select transistors and each of the plurality of source select transistors.

10. The semiconductor device according to claim 9, wherein: The plurality of first memory strings and the plurality of second memory strings are electrically coupled to the plurality of bit lines or are electrically disconnected from the plurality of bit lines according to turning on and off of the plurality of drain selection transistors.

11. The semiconductor device according to claim 10, wherein The plurality of first memory strings and the plurality of second memory strings are electrically coupled to the first source line and the second source line, respectively, or are electrically disconnected from the first source line and the second source line, respectively, according to the turning on and off of the plurality of source selection transistors.

12. A method for operating a semiconductor device, comprising: driving the first source line to a level of an erase voltage; driving the second source line to a level of one of a ground voltage or a power supply voltage; performing an erase operation on a first storage block connected to the first source line; as well as A read operation or a program operation is performed on a second memory block coupled to the second source line.

13. The operating method according to claim 12, wherein: Executing the erasing operation includes: electrically disconnecting a plurality of first memory strings included in the first memory block from a plurality of bit lines; and The first source line is electrically coupled to the plurality of first memory strings.

14. The operating method according to claim 13, wherein: Executing the erase operation further includes: A plurality of first word lines coupled to the plurality of first memory strings are driven to a level of the ground voltage.

15. The operating method according to claim 13, wherein: Executing the read operation or the program operation includes: electrically coupling a plurality of second memory strings included in the second memory block to the plurality of bit lines; and The second source line is electrically coupled to the plurality of second memory strings during the read operation, and the second source line is electrically disconnected from the plurality of second memory strings during the program operation.

16. A semiconductor device comprising: a first source line; a second source line; multiple bit lines; A first memory block including a plurality of first memory strings respectively connected between the first source line and the plurality of bit lines; A second memory block including a plurality of second memory strings respectively connected between the second source line and the plurality of bit lines; A control circuit that simultaneously performs an erase operation on the first storage block and a read operation or a program operation on the second storage block; a first source line driving circuit, driving the first source line to an erase voltage; as well as The second source line driving circuit drives the second source line to a ground voltage lower than the erase voltage.

17. The semiconductor device according to claim 16, further comprising: A plurality of page buffers are respectively coupled to the plurality of bit lines.

18. The semiconductor device according to claim 16, wherein: Each of the plurality of first memory strings and the plurality of second memory strings comprises: a plurality of drain selection transistors respectively connected to the plurality of bit lines; a plurality of source selection transistors coupled to the first source line or the second source line; and A plurality of memory cells are coupled in series between each of the plurality of drain select transistors and each of the plurality of source select transistors.

19. The semiconductor device according to claim 18, wherein: The plurality of first memory strings and the plurality of second memory strings are respectively electrically coupled to the plurality of bit lines or respectively electrically disconnected from the plurality of bit lines according to turning on and off of the plurality of drain selection transistors.

20. The semiconductor device according to claim 19, wherein The plurality of first memory strings and the plurality of second memory strings are electrically coupled to the first source line and the second source line, respectively, or are electrically disconnected from the first source line and the second source line, respectively, according to the turning on and off of the plurality of source selection transistors.

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