Memory and test method

Abstract

The invention provides a memory and a test method, and the method comprises the steps: respectively applying different voltages to a first bit line and a second bit line for a memory array sheet at a non-head-and-tail position, so as to achieve the bit line pressure test of the memory array sheet at the non-head-and-tail position; and in the other step, aiming at the storage array sheets at the head and tail positions, different voltages are respectively applied to the first bit lines with the odd numbers and the first bit lines with the even numbers, so that the bit line pressure test of the storage array sheets at the head and tail positions is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a memory and a test method. Background Art

[0002] With the development of semiconductor technology, the integration requirements and performance standards of memories have been gradually increasing. Therefore, the internal circuit structure is also gradually optimized, and a matching test method for the optimized internal circuit structure is also a problem that needs to be solved. Summary of the Invention

[0003] Embodiments of the present disclosure provide a memory and a test method.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a memory, which includes N memory array slices arranged in sequence along a first direction, where N is a natural number; each memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array slices at head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side, and the first bit line is electrically isolated from the second bit line adjacent to the second side; the memory is configured to, in one step, apply different voltages to the first bit lines and the second bit lines respectively for the memory array slices at non-head and non-tail positions to implement bit line stress testing for the memory array slices at non-head and non-tail positions; and, in another step, apply different voltages to the first bit lines with odd numbers and the first bit lines with even numbers respectively for the memory array slices at head and tail positions to implement bit line stress testing for the memory array slices at head and tail positions; where the memory array slices are numbered along the first direction, for the memory array slices with odd numbers, its first bit line is the second bit line; for the memory array slices with even numbers, its first bit line is the first bit line; for each memory array slice, the first bit lines therein are numbered in sequence along the second direction, and the second bit lines therein are numbered in sequence along the second direction.

[0006] In some embodiments, a sense amplifier module is distributed between every two memory array slices, and the sense amplifier module includes a plurality of sense amplifiers arranged in sequence along the second direction; the second end of the sense amplifier is connected to a first bit line on the third side through a first depolarization switch, and the first end of the sense amplifier is connected to a first bit line on the third side through a first isolation switch; the first end of the sense amplifier is further connected to a second bit line on the fourth side through a second depolarization switch, and the second end of the sense amplifier is further connected to a second bit line on the fourth side through a second isolation switch.

[0007] In some embodiments, the sense amplifier modules are numbered along a first direction; for the sense amplifier modules with odd numbers, one of the first end or the second end of the sense amplifier therein is further connected to a first power supply terminal through a precharge switch; for the sense amplifier modules with even numbers, one of the first end or the second end of the sense amplifier therein is further connected to a second power supply terminal through a precharge switch.

[0008] In some embodiments, the memory is specifically configured to, in one step, turn off all the sense amplifiers, control the first power supply terminal to be a first voltage value and the second power supply terminal to be a second voltage value, and perform a conventional precharge operation; and, after a preset time duration, control the first power supply terminal to be the second voltage value and the second power supply terminal to be the first voltage value, and perform a conventional precharge operation; wherein, the first voltage value and the second voltage value are different; in the conventional precharge operation, all the precharge switches, isolation switches, and debiasing switches are in an on state.

[0009] In some embodiments, the memory array slices at the head and tail positions each include a plurality of twin sub-units, the twin sub-units include 2 memory cells storing the same data, the 2 memory cells are both electrically connected to the same word line, and there is an electrical connection between the bit lines respectively corresponding to the 2 memory cells, and the twin sub-units perform data reading and writing simultaneously; for each memory array slice at the head and tail positions, the twin sub-units are numbered along a second direction; the memory is further configured to, in another step, only turn on the sense amplifiers adjacent to the memory array slices at the head and tail positions, write a first data to the twin sub-units with odd numbers, and write a second data to the twin sub-units with even numbers; and, after a preset time duration, write the second data to the twin sub-units with odd numbers, and write the first data to the twin sub-units with even numbers; wherein, the first data and the second data are different.

[0010] In some embodiments, the sense amplifier modules are numbered along a first direction, and the first sense amplifier module has an odd number; for each sense amplifier module, the sense amplifiers therein are numbered along a second direction; for the sense amplifier modules with odd numbers, the second end of the sense amplifiers with odd numbers therein is connected to a third power supply terminal through a precharge switch, and the first end of the sense amplifiers with even numbers therein is connected to a fourth power supply terminal through a precharge switch; for the sense amplifier modules with even numbers, the second end of the sense amplifiers with odd numbers therein is connected to a fifth power supply terminal through a precharge switch, and the first end of the sense amplifiers with even numbers therein is connected to a sixth power supply terminal through a precharge switch.

[0011] In some embodiments, the memory is specifically configured to, in one step, turn off all sense amplifiers, control both the third power supply terminal and the fourth power supply terminal to be a first voltage value, and both the fifth power supply terminal and the sixth power supply terminal to be a second voltage value; and perform a conventional precharge operation; and, after a preset duration, control both the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform a conventional precharge operation.

[0012] In some embodiments, the memory is specifically configured to, in another step, turn off all sense amplifiers, control both the third power supply terminal and the fifth power supply terminal to be the first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the second voltage value; and perform a conventional precharge operation; and, after a preset duration, control both the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform a conventional precharge operation.

[0013] In some embodiments, the memory is specifically configured to, in one step, turn off all sense amplifiers, control both the third power supply terminal and the fourth power supply terminal to be the first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the second voltage value; and perform a first test precharge operation; and, after a preset duration, control both the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform a first test precharge operation; wherein, in the first test precharge operation, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the off state, and all the remaining precharge switches, isolation switches, and depolarization switches are in the on state.

[0014] In some embodiments, the memory is specifically configured to, in another step, turn off all sense amplifiers, control both the third power supply terminal and the fifth power supply terminal to be the first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the second voltage value; and perform a second test precharge operation; and, after a preset duration, control both the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform a second test precharge operation; wherein, in the second test precharge operation, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the on state, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at non-head and non-tail positions are all in the off state; the precharge switches of the readout amplifier modules at the head and tail positions are all in the on state, and the precharge switches in the remaining readout amplifier modules are all in the off state.

[0015] In some embodiments, the first test precharge operation, the second test precharge operation, and the normal precharge operation all belong to the precharge operation. The memory further includes: a control circuit configured to generate a valid initial isolation signal and a valid initial debiasing signal when the memory is instructed to perform the precharge operation; and generate an invalid initial isolation signal and an invalid initial debiasing signal when the memory is not instructed to perform the precharge operation; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter set and the initial isolation signal; and generate a first edge debiasing signal and a second edge debiasing signal based on the edge test parameter set and the initial debiasing signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter set and the initial isolation signal; and generate a first internal debiasing signal and a second internal debiasing signal based on the internal test parameter set and the initial debiasing signal; wherein the first isolation switch, the second isolation switch, the first debiasing switch, and the second debiasing switch between the sense amplifier modules at the head and tail positions and the adjacent memory array slices are controlled by the first edge isolation signal, the second edge isolation signal, the first edge debiasing signal, and the second edge debiasing signal respectively; the first isolation switch, the second isolation switch, the first debiasing switch, and the second debiasing switch between the sense amplifier modules at non-head and non-tail positions and the adjacent memory array slices are controlled by the first internal isolation signal, the second internal isolation signal, the first internal debiasing signal, and the second internal debiasing signal respectively.

[0016] In some embodiments, the edge test parameter group at least includes a first test parameter and a second test parameter, and the internal test parameter group at least includes a third test parameter and a fourth test parameter; if the current pre-charge operation is a normal pre-charge operation, the first test parameter, the second test parameter, the third test parameter, and the fourth test parameter are all in a first state; if the test parameter group indicates that the current pre-charge operation is a first test pre-charge operation, the second test parameter is in a second state, and the first test parameter, the third test parameter, and the fourth test parameter are all in a first state; if the current pre-charge operation is a second test pre-charge operation, the first test parameter is in a second state, and the second test parameter, the third test parameter, and the fourth test parameter are all in a first state; if the second test parameter is in a first state, the first edge isolation signal and the first edge depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the second test parameter is in a second state, the first edge isolation signal and the first edge depolarization signal are both invalid; if the first test parameter is in a first state, the second edge isolation signal and the second edge depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the first test parameter is in a second state, the second edge isolation signal and the second edge depolarization signal are both invalid; if the fourth test parameter is in a first state, the first internal isolation signal and the first internal depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the fourth test parameter is in a second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the third test parameter is in a first state, the second internal isolation signal and the second internal depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the third test parameter is in a second state, the second internal isolation signal and the second internal depolarization signal are both invalid.

[0017] In some embodiments, the first state is a high level and the second state is a low level; the first preprocessing circuit includes: a first AND gate, whose two input terminals respectively receive a first test parameter and an initial isolation signal, and whose output terminal outputs a second edge isolation signal; a second AND gate, whose two input terminals respectively receive a second test parameter and the initial isolation signal, and whose output terminal outputs a first edge isolation signal; a third AND gate, whose two input terminals respectively receive the first test parameter and an initial depolarization signal, and whose output terminal outputs a second edge depolarization signal; a fourth AND gate, whose two input terminals respectively receive the second test parameter and the initial depolarization signal, and whose output terminal outputs a first edge depolarization signal; the second preprocessing circuit includes: a fifth AND gate, whose two input terminals respectively receive a third test parameter and the initial isolation signal, and whose output terminal outputs a second internal isolation signal; a sixth AND gate, whose two input terminals respectively receive a fourth test parameter and the initial isolation signal, and whose output terminal outputs a first internal isolation signal; a seventh AND gate, whose two input terminals respectively receive the third test parameter and the initial depolarization signal, and whose output terminal outputs a second internal depolarization signal; an eighth AND gate, whose two input terminals respectively receive the fourth test parameter and the initial depolarization signal, and whose output terminal outputs a first internal depolarization signal.

[0018] In a second aspect, the present disclosure provides a test method, which is applied to a memory. The memory includes N memory array slices arranged in sequence along a first direction. The memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array slices at head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side; the method includes: in one step, for the memory array slices at non-head and non-tail positions, different voltages are respectively applied to the first bit lines and the second bit lines therein to implement bit line stress testing of the memory array slices at non-head and non-tail positions; in another step, for the memory array slices at head and tail positions, different voltages are respectively applied to the first bit lines with odd numbers and the first bit lines with even numbers therein to implement bit line stress testing of the memory array slices at head and tail positions; wherein, the memory array slices are numbered along the first direction. For the memory array slices with odd numbers, the first bit line thereof is the second bit line; for the memory array slices with even numbers, the first bit line thereof is the first bit line; for each memory array slice, the first bit lines therein are sequentially numbered along the second direction, and the second bit lines therein are sequentially numbered along the second direction.

[0019] In some embodiments, for the first memory array slice, the second bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the first bit lines therein are precharged via the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last memory array slice, the first bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the second bit lines therein are precharged via the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the memory array slices at non-head and non-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the second bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches; the precharge power supplies for the second bit lines in the odd-numbered memory arrays and the first bit lines in the even-numbered memory array slices are both the first power supply terminal, and the precharge power supplies for the first bit lines in the odd-numbered memory arrays and the second bit lines in the even-numbered memory array slices are both the second power supply terminal; for the memory array slices at non-head and non-tail positions, different voltages are applied to the first bit lines and the second bit lines therein, including: controlling the first power supply terminal to be a first voltage value and the second power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; performing a conventional precharge operation; wherein, in the conventional precharge operation, each bit line is in an on state with its respective precharge power supply; after a preset duration, the conventional precharge operation is stopped, the first power supply terminal is controlled to be the second voltage value and the second power supply terminal is controlled to be the first voltage value; performing the conventional precharge operation and maintaining the preset duration.

[0020] In some embodiments, the memory array slices at the head and tail positions each include a plurality of twin cells, and a twin cell includes 2 memory cells storing the same data. The 2 memory cells are both electrically connected to the same word line, and the bit lines corresponding to the 2 memory cells are electrically connected. The twin cells perform data reading and writing simultaneously; for the memory array slices at the head and tail positions, different voltages are applied to the odd-numbered first bit lines and the even-numbered first bit lines therein, including: for the memory array slices at the head and tail positions, writing a first data to the odd-numbered twin cells and writing a second data to the even-numbered twin cells; the first data and the second data are different; after a preset duration, the data writing operation is stopped, writing the second data to the odd-numbered twin cells and writing the first data to the even-numbered twin cells, and maintaining the preset duration.

[0021] In some embodiments, for the first memory array slice, the second bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the first bit lines therein are precharged via the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last memory array slice, the first bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the second bit lines therein are precharged via the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the memory array slices at non-head and non-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches, and the second bit lines therein are connected to their respective corresponding precharge power supplies via precharge switches; the precharge power supply for the second bit lines in the memory arrays with odd numbers is the third power supply terminal, the precharge power supply for the first bit lines in the memory array slices with even numbers is the fourth power supply terminal, the precharge power supply for the first bit lines in the memory arrays with odd numbers is the fifth power supply terminal, and the precharge power supply for the second bit lines in the memory array slices with even numbers is the sixth power supply terminal; for the memory array slices at non-head and non-tail positions, different voltages are applied to the first bit lines and the second bit lines therein respectively, including: controlling the third power supply terminal and the fourth power supply terminal to be a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; a conventional precharge operation is performed; after a preset time duration, the conventional precharge operation is stopped, and the third power supply terminal and the fourth power supply terminal are controlled to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal are controlled to be the first voltage value; a conventional precharge operation is performed and maintained for the preset time duration.

[0022] In some embodiments, for the memory array slices at head and tail positions, different voltages are applied to the first bit lines with odd numbers and the first bit lines with even numbers therein respectively, including: controlling the third power supply terminal and the fifth power supply terminal to be a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be a second voltage value; a conventional precharge operation is performed; after a preset time duration, the conventional precharge operation is stopped, and the third power supply terminal and the fifth power supply terminal are controlled to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal are controlled to be the first voltage value; a conventional precharge operation is performed and maintained for the preset time duration.

[0023] In some embodiments, the precharge power supply for the second bit lines in the odd-numbered memory arrays is the third power supply terminal, the precharge power supply for the first bit lines in the even-numbered memory array slices is the fourth power supply terminal, the precharge power supply for the first bit lines in the odd-numbered memory arrays is the fifth power supply terminal, and the precharge power supply for the second bit lines in the even-numbered memory array slices is the sixth power supply terminal; for the memory array slices at the head and tail positions, one of the first bit lines and the second bit lines corresponds to the precharge power supply; for the memory array slices at non-head-and-tail positions, different voltages are applied to the first bit lines and the second bit lines therein, including: controlling the third power supply terminal and the fourth power supply terminal to be a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; perform a first test precharge operation; wherein, in the first test precharge operation, all the bit lines in the memory array slices at the head and tail positions are in a disconnected state from their respective precharge power supplies, and all the bit lines in the memory array slices at non-head-and-tail positions are in a connected state to their respective precharge power supplies; after a preset time duration, stop the precharge operation, control the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; perform the first test precharge operation and maintain it for a preset time duration.

[0024] In some embodiments, for the memory array slices at the head and tail positions, different voltages are applied to the odd-numbered first bit lines and the even-numbered first bit lines therein, including: controlling the third power supply terminal and the fifth power supply terminal to be a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; perform a second test precharge operation; wherein, in the second test precharge operation, all the bit lines in the memory array slices at the head and tail positions are in a connected state to their respective precharge power supplies, and all the bit lines in the memory array slices at non-head-and-tail positions are in a disconnected state from their respective precharge power supplies; after a preset time duration, stop the precharge operation, control the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; perform the second test precharge operation and maintain it for a preset time duration.

[0025] The embodiments of the present disclosure provide a memory and a test method, which reduce the area of the memory array slices at the edge to half of the area of other memory array slices, thereby being able to reduce the area of the chip and improve the integration degree; at the same time, a corresponding test method is also provided for this structure to improve the test process of the memory with this structure and ensure the factory performance. Description of the Drawings

[0026] Figure 1 It is a schematic diagram of a partial structure of a DRAM Figure 1 ;

[0027] Figure 2 It is a schematic diagram of a partial structure of a DRAM Figure 2 ;

[0028] Figure 3A Schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0029] Figure 3B Schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0030] Figure 4 Schematic diagram III of a partial structure of a memory provided by an embodiment of the present disclosure;

[0031] Figure 5 Schematic diagram of the structure of a sense amplifier provided by an embodiment of the present disclosure Figure 1 ;

[0032] Figure 6 Schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure Figure 4 ;

[0033] Figure 7 Schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure Figure 5 ;

[0034] Figure 8 Schematic diagram of the structure of a sense amplifier provided by an embodiment of the present disclosure Figure 2 ;

[0035] Figure 9 Schematic diagram of the structures of a first preprocessing circuit and a second preprocessing circuit provided by an embodiment of the present disclosure;

[0036] Figure 10 Another schematic diagram of the structure of a first preprocessing circuit provided by an embodiment of the present disclosure;

[0037] Figure 11 Schematic diagram of the flow of a test method provided by an embodiment of the present disclosure. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0039] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0040] If similar descriptions such as "first / second" appear in the application documents, the following description shall be added. In the following description, the terms "first / second / third" involved are only used to distinguish similar objects and do not represent a specific sorting of the objects. It can be understood that "first / second / third" can be interchanged in a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are for the purpose of describing embodiments of the present disclosure only and are not intended to limit the present disclosure.

[0042] Taking a dynamic random access memory (DRAM) as an example, see Figure 1 , which shows a partial structural schematic diagram of a DRAM provided by an embodiment of the present disclosure. As Figure 1 shown, for a DRAM, its core is a memory array slice (or called Section), a sense amplifier module, a row decoder and control (XDEC) circuit, a column decoder and control (YDEC) circuit, a secondary sense amplifier (SSa) circuit, and a write driver (Write Driver) circuit. The secondary sense amplifier circuit and the write driver circuit are collectively called the SSa&Write Driver circuit.

[0043] The memory array slice is composed of a large number of memory cells (or called Cells). Data reading, data writing, or data refreshing operations can be performed on the selected memory cells through word lines (Word Line, WL) and bit lines (Bit Line, BL).

[0044] Generally, 65 memory array slices along the first direction can be used as repeatable structures in the memory (for example: memory half bank Half Bank). Figure 1 Zooming in further, see Figure 2 , the bit lines in each memory array slice (such as 11_1, 11_2... 11_65) are alternately called the first bit line BLa and the second bit line BLb ( Figure 2Only the first bit line BLa and the second bit line BLb of the marked part are shown by way of example. In particular, for the odd-numbered memory array chips (such as 11_1, 11_3... 11_65), the first bit line is the second bit line BLb; for the even-numbered memory array chips (such as 11_2, 11_4... 11_64), the first bit line is the first bit line BLa. In particular, the first bit line BLa and the second bit line BLb are only a division based on position. In fact, the first bit line BLa and the second bit line BLb have exactly the same physical structure.

[0045] A sense amplifier module (such as 12_1, 12_2... 12_64) is arranged between every two memory array chips. Each sense amplifier module includes a plurality of sense amplifiers (Sense amplifier, Sa). One end of each Sa is connected to the bit line in the memory array chip on one side (such as the upper side), and the other end of the Sa is connected to the bit line in the memory array chip on the other side (such as the lower side).

[0046] Please refer to Figure 1 and Figure 2 , the word line signal is given by XDEC to turn on the target word line in the memory array chip, and then the column selection signal is given by YDEC to control the corresponding Sa to work. Furthermore, the Sa exchanges electrical signals with the target bit line, and finally writes, reads, or refreshes data to the target memory cell.

[0047] As Figure 2 shown, for the memory array chips at the head and tail positions (Edge), only half of the bit lines can be connected to the adjacent sense amplifier modules, which results in that the other half of the bit lines and their corresponding memory cells are actually unusable. For example, the first bit line BLa in the memory array chips 11_1 and 11_65 is not connected to the sense amplifier module, causing waste of memory cells and being not conducive to improving the chip integration.

[0048] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0049] In an embodiment of the present disclosure, referring to Figure 3A or Figure 3B , it shows a partial structural schematic diagram of a memory 10 provided by an embodiment of the present disclosure. As Figure 3A or Figure 3B shown, the memory 10 includes N memory array chips arranged in sequence along a first direction (such as 11_1, 11_2... 11_N, that is, the memory array chips are numbered along the first direction). Here, N can be any natural number, Figure 3A taking N as an odd number as an example for illustration, Figure 3B taking N as an even number as an example for illustration.

[0050] Please refer to Figure 3A and Figure 3B , each memory array slice includes a plurality of first bit lines BLa and a plurality of second bit lines BLb, and the first bit lines BLa and the second bit lines BLb are alternately arranged along the second direction; for the memory array slices at non-head and tail positions (such as 11_2... 11_N-1), the first bit lines BLa and the adjacent second bit lines BLb are electrically isolated; for the memory array slices at head and tail positions (such as 11_1 and 11_N), the first bit lines BLa are electrically connected to the second bit lines BLb adjacent to the first side (for example: the right side), and the first bit lines BLa are electrically isolated from the second bit lines BLb adjacent to the second side (for example: the left side).

[0051] Here, the sense amplifier circuit 10 in the embodiments of the present disclosure is applied to various signal amplification scenarios, such as DRAM, Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate DRAM, Low Power DRAM, etc., and those skilled in the art can apply it flexibly.

[0052] It should be noted that for the memory array slices at head and tail positions (11_1, 11_N), since actually two bit lines are connected to form an integral bit line, the length of each bit line can be shortened by nearly half. Specifically, for the memory array slices at non-head and tail positions, the distance between one end of each bit line connected to Sa and the other end of the bit line is denoted as L1, and for the memory array slices at head and tail positions, the distance between one end of the integral bit line (the first bit line + the second bit line) connected to Sa and the other end of the integral bit line is denoted as L2, and L1 = L2.

[0053] Therefore, the area of the memory array slices at head and tail positions (11_1, 11_N) is shortened by nearly half compared with the area of the memory array slices at non-head and tail positions (11_2... 11_N-1), the integration degree of the memory 10 is improved, and the overall area occupied by the storage cells is reduced.

[0054] In particular, the bit line stress test (BL stress) is an important performance test item of the memory 10, and the test method is to apply different voltages to adjacent bit lines and then observe whether the storage cells can work normally. For Figure 3A or Figure 3B the memory 10 shown, the bit line structures of the memory array slices at head and tail positions (11_1, 11_N) are different from those of the memory array slices at non-head and tail positions (11_2... 11_N-1), resulting in that the conventional method cannot achieve BL stress.

[0055] Therefore, the embodiments of the present disclosure also provide for Figure 3A or Figure 3BTesting method for BL stress of the memory 10 shown

[0056] For the sake of convenience in explanation, for Figure 3A or Figure 3B , for the odd-numbered memory array slices (11_1, 11_3, 11_5...), its first bit line is the second bit line BLb; for the even-numbered memory array slices (11_2, 11_6, 11_6...), its first bit line is the first bit line BLa. For each memory array slice, the first bit line BLa therein is numbered sequentially along the second direction, and the second bit line BLb therein is numbered sequentially along the second direction.

[0057] Taking the numbering starting point as an odd number as an example, please refer to Figure 4 (which is shown with N = 65 as an example, and other values of N should be understood adaptively), the bit lines in the memory array slice 11_1 are sequentially: BLbo, BLao, BLbe, BLae along the second direction, and the bit lines in the memory array slice 11_2 are sequentially: BLao, BLbo, BLae, BLbe...

[0058] Specifically, the memory 10 is configured to, in one step, for the memory array slices (11_2...11_64) at non-head and non-tail positions, apply different voltages to the first bit line BLa (for Figure 4 , both BLao and BLae are the first bit line BLa) and the second bit line BLb (for Figure 4 , both BLbo and BLbe are the second bit line BLb) respectively, so as to implement the bit line stress test BL stress of the memory array slices (11_2...11_64) at non-head and non-tail positions; and, in another step, for the memory array slices (11_1 and 11_65) at head and tail positions, apply different voltages to the odd-numbered first bit line BLao and the even-numbered first bit line BLae respectively, so as to implement the bit line stress test BL stress of the memory array slices (11_1 and 11_N) at head and tail positions.

[0059] In this way, the BL stress is split into two steps (Step) for execution. The BL stress of the memory array slices at non-head and non-tail positions is realized in one step, and the BL stress of the memory array slices at head and tail positions is realized in another step, thereby realizing Figure 3A or Figure 3B the BL stress of the memory shown, and ensuring the product performance of the memory. Here, the execution order of the two steps is not specified and can be flexibly determined according to the application scenario.

[0060] Please note that as Figure 3A or Figure 3BEach memory array slice shows 8 bit lines, but this is only an abbreviated representation. In fact, the number of bit lines in each memory array slice is very large.

[0061] Subsequent illustrations and descriptions will be based on N = 65. For the cases where N is an even number or other values, appropriate understanding should be made.

[0062] Please refer to Figure 4 , there is a sense amplifier module distributed between every two memory array slices, and the sense amplifier modules are numbered along the first direction. That is, the sense amplifier modules are numbered 12_1, 12_2... 12_64 in sequence along the first direction.

[0063] The sense amplifier module includes a plurality of sense amplifiers Sa arranged in sequence along the second direction. As Figure 5 shown, each sense amplifier Sa includes a first transistor 21, a second transistor 22, a third transistor 23, and a fourth transistor 24 that are cross-coupled. The source of the first transistor 21 and the drain of the third transistor 23 are both connected to the second complementary bit line SaBlb. The source of the second transistor 22 and the drain of the fourth transistor 24 are both connected to the first complementary bit line saBLa. The gate of the third transistor 23 is connected to the first bit line BLa, and the gate of the fourth transistor 24 is connected to the second bit line BLb. Additionally, NCS refers to the pull-down module, and PCS refers to the pull-up module. This part does not affect the understanding of the present disclosure solution and will not be further elaborated.

[0064] Please refer to Figure 5 , one end of the sense amplifier Sa is connected to a second bit line BLb on the third side (e.g., the upper side) through a first depolarization switch 31, and the other end of the sense amplifier Sa is connected to a second bit line BLb on the third side through a first isolation switch 32.

[0065] The other end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side (e.g., the lower side) through a second depolarization switch 33, and one end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side through a second isolation switch 34.

[0066] Here, the first depolarization switch 31, the second depolarization switch 33, the first isolation switch 32, and the second isolation switch 34 are all transistors. The gates of the first depolarization switch 31 and the second depolarization switch 33 each receive a depolarization signal OcEn, and the gates of the first isolation switch 32 and the second isolation switch 34 each receive an isolation signal Iso.

[0067] It should be noted that, as Figure 5 shown, one end or the other end of the sense amplifier Sa is also connected to a precharge power supply VAD through a precharge switch 35. In particular, in Figure 5In [the figure], the precharge switch 35 is disposed on one side of the second bit line BLb, and is specifically connected to the first end of the sense amplifier Sa, but this does not constitute a specific limitation. In some other embodiments, the precharge switch 35 may also be disposed on one side of the first bit line BLa and is specifically connected to the second end of the sense amplifier Sa.

[0068] Please refer to Figure 6 , in a first specific embodiment, for the odd-numbered read amplification modules (12_1, 12_3... 12_63), the first end or the second end of the sense amplifier Sa therein is also connected to the first power supply terminal VAD2O through the precharge switch 35; for the even-numbered read amplification modules (12_2, 12_4... 12_64), the first end or the second end of the sense amplifier Sa therein is also connected to the second power supply terminal VAD2E through the precharge switch 35.

[0069] It should be noted that in Figure 6 , for each read amplification module, the second end of the odd-numbered sense amplifier 40o is connected to the corresponding power supply terminal through the precharge switch 35, and the first end of the even-numbered sense amplifier 40e is connected to the corresponding power supply terminal through the precharge switch 35, but this does not constitute a corresponding limitation, as long as it is ensured that the precharge power supply corresponding to the sense amplifier Sa in the odd-numbered read amplification module is the first power supply terminal VAD2O, and the precharge power supply corresponding to the sense amplifier Sa in the even-numbered read amplification module is the first power supply terminal VAD2E.

[0070] Based on Figure 6 the structure, the process by which the memory 10 performs BL stress on the non-edge memory array chips is as follows:

[0071] The memory 10 is specifically configured to, in one step, turn off all the sense amplifiers Sa, control the first power supply terminal VAD2O to be a first voltage value and the second power supply terminal VAD2E to be a second voltage value, and perform a conventional precharge operation; in the conventional precharge operation, all the precharge switches 35, isolation switches, and depolarization switches are in the on state; and, after a preset duration (the specific value can be based on the actual application scenario), control the first power supply terminal VAD2O to be the second voltage value and the second power supply terminal VAD2E to be the first voltage value, and perform a conventional precharge operation.

[0072] Here, the first voltage value and the second voltage value are different. For example: the first voltage value is a high level and the second voltage value is a low level, or, the first voltage value is a low level and the second voltage value is a high level.

[0073] Based on Figure 6 the structure shown, the above steps will be described in detail below with the first voltage value being a high level and the second voltage value being a low level as an example.

[0074] First, control the first power supply terminal VAD2O to a high level (e.g., 1.55V) and the second power supply terminal VAD2E to a low level (e.g., 0V). At this time, the results of the conventional pre-charge operation are as follows:

[0075] (1) For the memory array chip 11_1, all the first bit lines and the second bit lines connected thereto are at a high level (pre-charged by VAD2O);

[0076] (2) For the memory array chip 11_65, all the first bit lines and the second bit lines connected thereto are at a low level (pre-charged by VAD2E);

[0077] (3) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5... 11_63), the first bit line BLa is at a low level (pre-charged by VAD2E), and the second bit line BLb is at a high level (pre-charged by VAD2O);

[0078] (4) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4... 11_64), the first bit line BLa is at a high level (pre-charged by VAD2O), and the second bit line BLb is at a low level (pre-charged by VAD2E).

[0079] That is, in this step, only the adjacent bit lines in the memory array chips at non-head and non-tail positions can be at different voltage values respectively.

[0080] Secondly, control the first power supply terminal VAD2O to a low level and the second power supply terminal VAD2E to a high level. At this time, the results of the conventional pre-charge operation are as follows:

[0081] (5) For the memory array chip 11_1, all the first bit lines and the second bit lines connected thereto are at a low level (pre-charged by VAD2O);

[0082] (6) For the memory array chip 11_65, all the first bit lines and the second bit lines connected thereto are at a high level (pre-charged by VAD2E);

[0083] (7) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5... 11_63), the first bit line BLa is at a high level (pre-charged by VAD2E), and the second bit line BLb is at a low level (pre-charged by VAD2O);

[0084] (8) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4... 11_64), the first bit line BLa is at a low level (pre-charged by VAD2O), and the second bit line BLb is at a high level (pre-charged by VAD2E).

[0085] Similarly, in this step, only the adjacent bit lines in the memory array slices other than the head and tail positions can be set to different voltage values respectively.

[0086] In this way, through the above steps, the BL Stress of the memory array slices other than the head and tail positions can be completed.

[0087] It should also be noted that for the memory array slices at the head and tail positions, since their two bit lines are combined into one overall bit line, the operation object each time must be a pair of memory cells rather than a single memory cell. Specifically, each of the memory array slices at the head and tail positions includes multiple twin cells. A twin cell includes two memory cells storing the same data. The two memory cells are both electrically connected to the same word line, and there is an electrical connection between the bit lines corresponding to the two memory cells respectively. The twin cells perform data reading and writing simultaneously. For the convenience of description, each memory array slice at the head and tail positions is numbered for the twin cells along the second direction.

[0088] In another step, the process by which the memory 10 performs BL stress on the memory array slices at the edges is as follows:

[0089] The memory 10 is further configured to, in another step, only turn on the sense amplifiers Sa adjacent to the memory array slices at the head and tail positions, write the first data to the twin cells with odd numbers, and write the second data to the twin cells with even numbers, so that the voltage values of the first bit line and the second bit line connected thereto of the twin cells with odd numbers are the first voltage value, and the voltage values of the first bit line and the second bit line connected thereto of the twin cells with even numbers are the second voltage value; and, after a preset time duration, write the second data to the twin cells with odd numbers, and write the first data to the twin cells with even numbers, so that the voltage values of the first bit line and the second bit line connected thereto of the twin cells with odd numbers are the second voltage value, and the voltage values of the first bit line and the second bit line connected thereto of the twin cells with even numbers are the first voltage value. Herein, the first data and the second data are different.

[0090] It should be understood that during the write operation, all the isolation switches, precharge switches, and depolarization switches are turned off, and the data to be written is transmitted from the local data line (LIO) to the corresponding bit line.

[0091] Taking the first data as 1 and the second data as 0 as an example, it can be known that for the memory array chips at the head and tail positions, during the process of writing 1 to the odd-numbered twin cells and writing 0 to the even-numbered twin cells, the first bit line BLao of the odd numbers and the second bit line BLbo connected thereto are at a high level, and the first bit line BLae of the even numbers and the second bit line BLbe connected thereto are at a low level; conversely, when writing 0 to the odd-numbered twin cells and writing 1 to the even-numbered twin cells, the first bit line BLao of the odd numbers and the second bit line BLbo connected thereto are at a low level, and the first bit line BLae of the even numbers and the second bit line BLbe connected thereto are at a high level; thus, the BL stress of the memory array chips at the head and tail positions is completed.

[0092] In this way, the BL stress is performed on the memory array chips at non-head-and-tail positions and head-and-tail positions respectively through two steps to achieve the corresponding test effects.

[0093] In the second specific embodiment, another specific structure of the memory 10 is provided. Please refer to Figure 7 , for the odd-numbered sense amplifier modules (12_1, 12_3... 12_63), the second ends of the odd-numbered sense amplifiers 40o therein are connected to the third power supply terminal VAD2Oa through the precharge switches 35, and the first ends of the even-numbered sense amplifiers 40e are connected to the fourth power supply terminal VAD2Ob through the precharge switches 35;

[0094] For the even-numbered sense amplifier modules (12_2, 12_4... 12_64), the second ends of the odd-numbered sense amplifiers 40o therein are connected to the fifth power supply terminal VAD2Ea through the precharge switches 35, and the first ends of the even-numbered sense amplifiers 40e are connected to the sixth power supply terminal VAD2Eb through the precharge switches 35.

[0095] Based on Figure 7 the above structure, the process of the memory 10 performing BL stress on the non-edge memory array chips is as follows:

[0096] The memory 10 is specifically configured to, in one step, turn off all the sense amplifiers Sa, control both the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to be the first voltage value, and both the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to be the second voltage value; and perform a conventional precharge operation; and, after a preset time duration, control both the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to be the second voltage value, and the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to be the first voltage value; and perform a conventional precharge operation.

[0097] Briefly speaking, the precharge power supply for the sense amplifier Sa in the memory is divided into 4 groups, so as to perform the precharge operation more flexibly.

[0098] The above steps will be described in detail below by taking the first voltage value as high level and the second voltage value as low level as an example.

[0099] First, control the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob = high level (for example: 1.55V), and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb = low level (for example: 0V). At this time,

[0100] (1) For the memory array chip 11_1, all the first bit lines and the second bit lines connected thereto are at high level (precharged by VAD2Oa or VAD2Ob);

[0101] (2) For the memory array chip 11_65, all the first bit lines and the second bit lines connected thereto are at low level (precharged by VAD2Ea or VAD2Eb);

[0102] (3) For the non-edge and odd-numbered memory array chips (such as memory array chips 11_3, 11_5... 11_63), the first bit line BLa is at low level (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is at high level (precharged by VAD2Oa or VAD2Ob);

[0103] (4) For the non-edge and even-numbered memory array chips (such as memory array chips 11_2, 11_4... 11_64), the first bit line BLa is at high level (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is at low level (precharged by VAD2Ea or VAD2Eb).

[0104] That is, in this step, only the adjacent bit lines in the memory array chips at non-head and non-tail positions can be at different voltage values.

[0105] Secondly, control the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob = low level, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb = high level. The conventional precharge operation will cause:

[0106] (1) For the memory array chip 11_1, all the first bit lines and the second bit lines connected thereto are at low level (precharged by VAD2Oa or VAD2Ob);

[0107] (2) For the memory array chip 11_65, all the first bit lines and the second bit lines connected thereto are at high level (precharged by VAD2Ea or VAD2Eb);

[0108] (3) For non-edge and odd-numbered memory array slices (such as memory array slices 11_3, 11_5... 11_63), the first bit line BLa is at a high level (pre-charged by VAD2Ea or VAD2Eb), and the second bit line BLb is at a low level (pre-charged by VAD2Oa or VAD2Ob);

[0109] (4) For non-edge and even-numbered memory array slices (such as memory array slices 11_2, 11_4... 11_64), the first bit line BLa is at a low level (pre-charged by VAD2Oa or VAD2Ob), and the second bit line BLb is at a high level (pre-charged by VAD2Ea or VAD2Eb). Similarly, in this step, only the adjacent bit lines in the non-head and non-tail memory array slices can be at different voltage values.

[0110] In this way, through the above steps, the BL Stress of the non-head and non-tail memory array slices can be completed.

[0111] Based on Figure 7 the structure, the process of the memory 10 performing BL stress on the head and tail memory array slices is as follows:

[0112] The memory 10 is specifically configured to, in another step, turn off all sense amplifiers Sa, control the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea to be at the first voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb to be at the second voltage value; and perform a conventional pre-charge operation; and, after a preset duration, control the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea to be at the second voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb to be at the first voltage value; and perform a conventional pre-charge operation.

[0113] The following takes the first voltage value as a high level and the second voltage value as a low level as an example to illustrate the above steps in detail.

[0114] First, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea = high level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb = low level. At this time, the result of the conventional pre-charge operation is:

[0115] (1) For the memory array slice 11_1, the odd-numbered first bit line BLao and the second bit line BLbo connected thereto are both at a high level (pre-charged by VAD2Oa), and the even-numbered first bit line BLae and the second bit line BLbe connected thereto are both at a low level (pre-charged by VAD2Ob);

[0116] (2) For the memory array slice 11_65, the first bit line BLao with odd number and its connected second bit line BLbo are both at high level (pre-charged by VAD2Ea), and the first bit line BLae with even number and its connected second bit line BLbe are both at low level (pre-charged by VAD2Eb);

[0117] (3) For the non-edge and odd-numbered memory array slices (such as memory array slices 11_3, 11_5... 11_63), the first bit line BLao with odd number is at high level (pre-charged by VAD2Ea), the second bit line BLbo with odd number is at high level (pre-charged by VAD2Oa), the first bit line BLae with even number is at low level (pre-charged by VAD2Eb), and the second bit line BLbe with even number is at low level (pre-charged by VAD2Ob).

[0118] (4) For the non-edge and even-numbered memory array slices (such as memory array slices 11_2, 11_4... 11_64), the first bit line BLao with odd number is at high level (pre-charged by VAD2Oa), the second bit line BLbo with odd number is at high level (pre-charged by VAD2Ea), the first bit line BLae with even number is at low level (pre-charged by VAD2Ob), and the second bit line BLbe with even number is at low level (pre-charged by VAD2Eb).

[0119] That is, in this step, only the adjacent bit lines in the memory array slices at the head and tail positions can be at different voltage values respectively.

[0120] Secondly, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea = low level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb = high level. At this time, the result of the conventional pre-charging operation is:

[0121] (5) For the memory array slice 11_1, the first bit line BLao with odd number and its connected second bit line BLbo are both at low level (pre-charged by VAD2Oa), and the first bit line BLae with even number and its connected second bit line BLbe are both at high level (pre-charged by VAD2Ob);

[0122] (6) For the memory array slice 11_65, the first bit line BLao with odd number and its connected second bit line BLbo are both at low level (pre-charged by VAD2Ea), and the first bit line BLae with even number and its connected second bit line BLbe are both at high level (pre-charged by VAD2Eb);

[0123] (7) For non-edge and odd-numbered memory array slices (such as memory array slices 11_3, 11_5... 11_63), the first bit line BLao of odd numbers is at a low level (pre-charged by VAD2Ea), the second bit line BLbo of odd numbers is at a low level (pre-charged by VAD2Oa), the first bit line BLae of even numbers is at a high level (pre-charged by VAD2Eb), and the second bit line BLbe of even numbers is at a high level (pre-charged by VAD2Ob).

[0124] (8) For non-edge and even-numbered memory array slices (such as memory array slices 11_2, 11_4... 11_64), the first bit line BLao of odd numbers is at a low level (pre-charged by VAD2Oa), the second bit line BLbo of odd numbers is at a low level (pre-charged by VAD2Ea), the first bit line BLae of even numbers is at a high level (pre-charged by VAD2Ob), and the second bit line BLbe of even numbers is at a high level (pre-charged by VAD2Eb).

[0125] Similarly, in this step, only the adjacent bit lines in the memory array slices at the head and tail positions can be set to different voltage values.

[0126] In short, by dividing the pre-charge power supply of the sense amplifier Sa into 4 groups, the BL stress test of all memory array slices can be completed only through the pre-charge operation, and the test steps are simpler.

[0127] However, in the above test steps, in the step of performing the BL stress test on the non-head and non-tail memory array slices, the bit lines in the head and tail memory array slices are also pre-charged; in the step of performing the BL stress test on the head and tail memory array slices, the bit lines in the non-head and non-tail memory array slices are also pre-charged, resulting in waste of energy consumption and over-charge problems. To further solve this problem, the embodiments of the present disclosure provide the following test method for Figure 7 the memory 10 structure shown:

[0128] Based on Figure 7 the structure, the process of the memory 10 performing BL stress on non-edge memory array slices is as follows:

[0129] Memory 10 is specifically configured to, in one step, turn off all sense amplifiers Sa, control the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to both be at a first voltage value, and the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to be at a second voltage value; and perform a first test precharge operation; and, after a preset duration, control the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to both be at the second voltage value, and the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to be at the first voltage value; and perform a first test precharge operation; wherein, in the first test precharge operation, the isolation switches and depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the off state, and all the remaining precharge switches, isolation switches, and depolarization switches are in the on state.

[0130] The above steps will be described in detail below with the first voltage value being a high level and the second voltage value being a low level as an example.

[0131] First, control the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob = high level, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb = low level, and, the isolation switches and depolarization switches between the sense amplifier Sa in the readout amplifier module 12_1 and the memory array chip 11_1 are all in the off state, and the isolation switches and depolarization switches between the sense amplifier Sa in the readout amplifier module 12_64 and the memory array chip 11_65 are all in the off state, and all the remaining precharge switches, isolation switches, and depolarization switches are in the on state.

[0132] At this time, the result of the first test precharge operation is:

[0133] (1) For the memory array chips 11_1 and 11_65, since the bit lines therein are electrically isolated from the sense amplifier Sa, the bit lines therein will not be precharged.

[0134] (2) For the non-edge and odd-numbered memory array chips (such as memory array chips 11_3, 11_5... 11_63), the first bit line BLa is all at a low level (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is all at a high level (precharged by VAD2Oa or VAD2Ob).

[0135] (3) For the non-edge and even-numbered memory array chips (such as memory array chips 11_2, 11_4... 11_64), the first bit line BLa is all at a high level (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is all at a low level (precharged by VAD2Ea or VAD2Eb).

[0136] That is, in this step, only the adjacent bit lines in the memory array slices other than the head and tail positions can be set to different voltage values respectively.

[0137] Secondly, control the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob = low level, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb = high level. Similarly, the isolation switch and the depolarization switch between the sense amplifier Sa in the sense amplifier module 12_1 and the memory array slice 11_1 are both in the off state, and the isolation switch and the depolarization switch between the sense amplifier Sa in the sense amplifier module 12_64 and the memory array slice 11_65 are both in the off state. All the other precharge switches, isolation switches, and depolarization switches are in the on state;

[0138] At this time, the result of the first test precharge operation is:

[0139] (4) For the memory array slices 11_1 and 11_65, since the bit lines therein are electrically isolated from the sense amplifier Sa, the bit lines therein will not be precharged;

[0140] (5) In the non-edge and odd-numbered memory array slices (such as the memory array slices 11_3, 11_5... 11_63), the first bit line BLa is all at high level (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is all at low level (precharged by VAD2Oa or VAD2Ob);

[0141] (6) In the non-edge and even-numbered memory array slices (such as the memory array slices 11_2, 11_4... 11_64), the first bit line BLa is all at low level (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is all at high level (precharged by VAD2Ea or VAD2Eb).

[0142] That is, in this step, only the adjacent bit lines in the memory array slices other than the head and tail positions can be set to different voltage values respectively.

[0143] In this way, through the above steps, the BL Stress of the memory array slices other than the head and tail positions can be completed.

[0144] In another step, the process of the memory 10 performing BL stress on the edge memory array slices is as follows:

[0145] Memory 10 is specifically configured such that in another step, all sense amplifiers Sa are turned off, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are both set to a first voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are set to a second voltage value; and a second test precharge operation is performed; and, after a preset duration, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are both set to the second voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are set to the first voltage value; and a second test precharge operation is performed; wherein, in the second test precharge operation, the isolation switches and depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the on state, and the isolation switches and depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at non-head and non-tail positions are all in the off state; the precharge switches 35 of the readout amplifier modules at the head and tail positions are all in the on state, and the precharge switches 35 in the remaining readout amplifier modules are all in the off state.

[0146] It should be noted that the precharge switches 35 in the readout amplifier modules at non-head and non-tail positions are turned off, that is, these sense amplifiers Sa will not be precharged, so the isolation switches / depolarization switches between the readout amplifier modules at non-head and non-tail positions and the adjacent memory array chips can be in either the on state or the off state.

[0147] The above steps will be described in detail below with the first voltage value being a high level (for example: 1.55V) and the second voltage value being a low level (for example: 0V) as an example.

[0148] First, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea = high level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb = low level. At the same time, the isolation switches and depolarization switches between the readout amplifier module 12_1 and the memory array chip 11_1 are both in the on state, and the isolation switches and depolarization switches between the readout amplifier module 12_64 and the memory array chip 11_65 are both in the on state. However, the isolation switches and depolarization switches between the readout amplifier module 12_1 and the memory array chip 11_2 are both in the off state, and the isolation switches and depolarization switches between the readout amplifier module 12_64 and the memory array chip 11_64 are both in the off state; at the same time, the precharge switches 35 corresponding to the readout amplifier module 12_1 and the readout amplifier module 12_64 are both on, but the precharge switches 35 corresponding to the readout amplifier modules 12_2 to 12_63 are all off.

[0149] The result of the second test precharge operation at this time is:

[0150] (1) For the storage array slice 11_1, the first bit line BLao with odd numbers and the second bit line BLbo connected thereto are both at high level (pre-charged by VAD2Oa), and the first bit line BLae with even numbers and the second bit line BLbe connected thereto are both at low level (pre-charged by VAD2Ob);

[0151] (2) For the storage array slice 11_65, the first bit line BLao with odd numbers and the second bit line BLbo connected thereto are both at high level (pre-charged by VAD2Ea), and the first bit line BLae with even numbers and the second bit line BLbe connected thereto are both at low level (pre-charged by VAD2Eb);

[0152] (3) For the storage array slices at non-head and non-tail positions, first, for the storage array slices 11_3 to 11_63, their adjacent Sa will not be pre-charged (the pre-charging switch is off), so the bit lines therein will not be pre-charged either; second, for the storage array slice 11_2, although the sense amplifier module 12_1 on one side thereof will be pre-charged, the bit lines therein are electrically isolated from the Sa in the sense amplifier module 12_1 (the isolation switch and the depolarization switch are off), so they will not be pre-charged either; for the storage array slice 11_64, although the sense amplifier module 12_64 on one side thereof will be pre-charged, the bit lines therein are electrically isolated from the Sa in the sense amplifier module 12_64 (the isolation switch and the depolarization switch are off), so they will not be pre-charged either.

[0153] Second, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea = low level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb = high level. At the same time, the isolation switches and the depolarization switches between the sense amplifier module 12_1 and the storage array slice 11_1 are both in the on state, and the isolation switches and the depolarization switches between the sense amplifier module 12_64 and the storage array slice 11_65 are both in the on state, but the isolation switches and the depolarization switches between the sense amplifier module 12_1 and the storage array slice 11_2 are both in the off state, and the isolation switches and the depolarization switches between the sense amplifier module 12_64 and the storage array slice 11_64 are both in the off state; at the same time, the pre-charging switches 35 corresponding to the sense amplifier module 12_1 and the sense amplifier module 12_64 are both on, but the pre-charging switches 35 corresponding to the sense amplifier modules 12_2 to 12_63 are all off.

[0154] At this time, the result of the second test pre-charging operation is:

[0155] (1) For the storage array slice 11_1, the first bit line BLao with odd numbers and the second bit line BLbo connected thereto are both at low level (pre-charged by VAD2Oa), and the first bit line BLae with even numbers and the second bit line BLbe connected thereto are both at high level (pre-charged by VAD2Ob);

[0156] (2) For the memory array slice 11_65, the first bit line BLao with odd number and the second bit line BLbo connected thereto are both at low level (pre-charged by VAD2Ea), and the first bit line BLae with even number and the second bit line BLbe connected thereto are both at high level (pre-charged by VAD2Eb).

[0157] (3) For the memory array slices at non-head and non-tail positions, first, for the memory array slices 11_3 to 11_63, their adjacent Sa will not be pre-charged (the pre-charge switch is off), so the bit lines therein will not be pre-charged either. Second, for the memory array slice 11_2, although the sense amplifier module 12_1 on one side thereof will be pre-charged, the bit lines therein are electrically isolated from Sa in the sense amplifier module 12_1 (the isolation switch and the depolarization switch are off), so they will not be pre-charged either. For the memory array slice 11_64, although the sense amplifier module 12_64 on one side thereof will be pre-charged, the bit lines therein are electrically isolated from Sa in the sense amplifier module 12_64 (the isolation switch and the depolarization switch are off), so they will not be pre-charged either.

[0158] Similarly, in this step, only the adjacent bit lines in the memory array slices at the head and tail positions can be made to have different voltage values.

[0159] In short, by pre-charging only the memory array slices at the head and tail positions or only the memory array slices at the internal positions, over-precharging problems can be avoided, all memory array slices can be better tested for BLstress, power consumption can be saved, and over-stress can be avoided.

[0160] To implement the above test method, please refer to Figure 8 , the gates of the first depolarization switch 31 and the second depolarization switch 33 respectively receive the control signals OcEnb and OcEna, and the gates of the first isolation switch 32 and the second isolation switch 34 respectively receive the control signals Isob and Isoa.

[0161] Regarding Figure 7, the read amplification module 12-1 is connected to the memory array chip 11-1 through the first depolarization switch 31 and the first isolation switch 32, but the read amplification module 12-64 is connected to the memory array chip 11-65 through the second depolarization switch 33 and the second isolation switch 34. For the convenience of the above test method, in a specific embodiment, by changing some definitions (such as changing the definitions of the first bit line and the second bit line in the last and the penultimate memory array chips, or changing the definitions of the depolarization switch and the isolation switch in the read amplification module 12-64, etc.), the read amplification module 12-64 is also connected to the memory array chip 11-65 through the first depolarization switch 31 and the first isolation switch 32. Thus, only by turning off the first depolarization switch 31 and the first isolation switch 32 corresponding to the read amplification module 12-1 and the read amplification module 12-64, the memory array chips at the head and tail positions can be electrically isolated from the adjacent sense amplifiers Sa.

[0162] At this time, the memory 10 further includes:

[0163] A control circuit configured to generate a valid initial isolation signal IsoPre and a valid initial depolarization signal OcPre when the memory 10 is instructed to perform a precharge operation; and generate an invalid initial isolation signal IsoPre and an invalid initial depolarization signal OcPre when the memory 10 is not instructed to perform a precharge operation; wherein, the first test precharge operation, the second test precharge operation, and the normal precharge operation all belong to the precharge operation;

[0164] A first preprocessing circuit 50 configured to generate a first edge isolation signal IsobEdge and a second edge isolation signal IsoaEdge based on the edge test parameter set and the initial isolation signal IsoPre; and generate a first edge depolarization signal OcEnbEdge and a second edge depolarization signal OcEnaEdge based on the edge test parameter set and the initial depolarization signal OcPre;

[0165] A second preprocessing circuit 60 configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter set and the initial isolation signal IsoPre; and generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter set and the initial depolarization signal OcPre;

[0166] Among them, (1) The first edge isolation signal IsobEdge is used to control the first isolation switch 32 between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions. That is, IsobEdge can be regarded as the Isob between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions; (2) The second edge isolation signal IsoaEdge is used to control the second isolation switch 34 between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions. That is, IsoaEdge can be regarded as the Isoa between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions; (3) The first edge depolarization signal OcEnbEdge is used to control the first depolarization switch 31 between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions. That is, OcEnbEdge can be regarded as the OcEnb between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions; (4) The second edge depolarization signal OcEnaEdge is used to control the second depolarization switch 33 between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions. That is, OcEnaEdge can be regarded as the OcEna between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions; (5) The first internal isolation signal IsobInter is used to control the first isolation switch 32 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips. That is, IsobInter can be regarded as the Isob between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (6) The second internal isolation signal IsoaInter is used to control the second isolation switch 34 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips. That is, IsoaInter can be regarded as the Isoa between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (7) The first internal depolarization signal OcEnbInter is used to control the first depolarization switch 31 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips. That is, OcEnbInter can be regarded as the OcEnb between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (8) The second internal depolarization signal OcEnaInter is used to control the second depolarization switch 33 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips. That is, OcEnaInter can be regarded as the OcEna between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips.

[0167] In this way, by introducing an additional preprocessing circuit to distinguish between the conventional precharge operation, the first test precharge operation, and the second test precharge operation, in the first test precharge operation, only the bit lines in the memory array chips at non-head-and-tail positions are precharged, and in the second test precharge operation, only the bit lines in the memory array chips at the head and tail positions are precharged. That is, it saves energy consumption and can also avoid the problems of bit line overcharge and overpressure.

[0168] In some embodiments, the edge test parameter group at least includes a first test parameter TmEdge<0> and a second test parameter TmEdge<1>, and the internal test parameter group at least includes a third test parameter TmInter<0> and a fourth test parameter TmInter<1>.

[0169] If the test parameter group indicates that this pre-charge operation is a normal pre-charge operation, the first test parameter TmEdge<0>, the second test parameter TmEdge<1>, the third test parameter TmInter<0>, and the fourth test parameter TmInter<1> are all in the first state; if the test parameter group indicates that this pre-charge operation is a first test pre-charge operation, the second test parameter TmEdge<1> is in the second state, and the first test parameter TmEdge<0>, the third test parameter TmInter<0>, and the fourth test parameter TmInter<1> are all in the first state; if the test parameter group indicates that this pre-charge operation is a second test pre-charge operation, the first test parameter TmEdge<0> is in the second state, and the second test parameter TmEdge<1>, the third test parameter TmInter<0>, and the fourth test parameter TmInter<1> are all in the first state;

[0170] If the second test parameter TmEdge<1> is in the first state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are respectively at the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the second test parameter TmEdge<1> is in the second state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are both invalid.

[0171] If the first test parameter TmEdge<0> is in the first state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge are respectively at the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the first test parameter TmEdge<0> is in the second state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge are both invalid.

[0172] If the fourth test parameter TmInter<1> is in the first state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are respectively at the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the fourth test parameter TmInter<1> is in the second state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are both invalid.

[0173] If the third test parameter TmInter<0> is in the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are respectively at the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the third test parameter TmInter<0> is in the second state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are both invalid.

[0174] It should be noted that for the above isolation signal, depolarization signal, and pre-charge signal, when they are invalid, the corresponding switches are in the off state; when they are valid, the corresponding switches are in the on state.

[0175] In some embodiments, please refer to Figure 9 , the first state is a high level, the second state is a low level, valid means the signal is at a high level, and invalid means the signal is at a low level. The first preprocessing circuit 50 includes:

[0176] A first AND gate 501, whose two input terminals respectively receive the first test parameter TmEdge<0> and the initial isolation signal IsoPre, and whose output terminal outputs a second edge isolation signal IsoaEdge; a second AND gate 502, whose two input terminals respectively receive the second test parameter TmEdge<1> and the initial isolation signal IsoPre, and whose output terminal outputs a first edge isolation signal IsobEdge; a third AND gate 503, whose two input terminals respectively receive the first test parameter TmEdge<0> and the initial depolarization signal OcPre, and whose output terminal outputs a second edge depolarization signal OcEnaEdge; a fourth AND gate 504, whose two input terminals respectively receive the second test parameter TmEdge<1> and the initial depolarization signal OcPre, and whose output terminal outputs a first edge depolarization signal OcEnbEdge;

[0177] The second preprocessing circuit 60 includes:

[0178] A fifth AND gate 601, whose two input terminals respectively receive the third test parameter TmInter<0> and the initial isolation signal IsoPre, and whose output terminal outputs a second internal isolation signal IsoaInter; a sixth AND gate 602, whose two input terminals respectively receive the fourth test parameter TmInter<1> and the initial isolation signal IsoPre, and whose output terminal outputs a first internal isolation signal IsobInter; a seventh AND gate 603, whose two input terminals respectively receive the third test parameter TmInter<0> and the initial depolarization signal OcPre, and whose output terminal outputs a second internal depolarization signal OcEnaInter; an eighth AND gate 604, whose two input terminals respectively receive the fourth test parameter TmInter<1> and the initial depolarization signal OcPre, and whose output terminal outputs a first internal depolarization signal OcEnbInter.

[0179] In a specific embodiment, the first isolation switch 32, the second isolation switch 34, the first depolarization switch 31, and the second depolarization switch 33 are all N-type field effect transistors; the following specifically describes the conventional pre-charge operation, the first test pre-charge operation, and the second test pre-charge operation.

[0180] Specifically, (1) during the execution of the conventional pre-charge operation, TmEdge<1:0> = 11, TmInter<1:0> = 11. Therefore, the first edge isolation signal IsobEdge = the second edge isolation signal IsoaEdge = the first edge depolarization signal OcEnbEdge = the second edge depolarization signal OcEnaEdge = the first internal isolation signal IsobInter = the second internal isolation signal IsoaInter = the first internal depolarization signal OcEnbInter = the second internal depolarization signal OcEnaInter = 1, so that all the first isolation switches 32, the second isolation switches 34, the first depolarization switches 31, and the second depolarization switches 33 are turned on; thus, all bit lines can be pre-charged.

[0181] (2) During the execution of the first test pre-charge operation, TmEdge<1:0> = 01, TmInter<1:0> = 11. Therefore, the first edge isolation signal IsobEdge = the first edge depolarization signal OcEnbEdge = 0, the second edge isolation signal IsoaEdge = the second edge depolarization signal OcEnaEdge = the first internal isolation signal IsobInter = the second internal isolation signal IsoaInter = the first internal depolarization signal OcEnbInter = the second internal depolarization signal OcEnaInter = 1, so that the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_65. However, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_64. The sense amplifier modules 12_2 to 12_63 in the middle part are each electrically connected to the memory array chips on both sides; thus, only the bit lines in the memory array chips in the middle part are pre-charged.

[0182] (3) During the execution of the second test pre-charge operation, TmEdge<1:0> = 10, TmInter<1:0> = 11. Therefore, the first edge isolation signal IsobEdge = the first edge depolarization signal OcEnbEdge = the first internal isolation signal IsobInter = the second internal isolation signal IsoaInter = the first internal depolarization signal OcEnbInter = the second internal depolarization signal OcEnaInter = 1, and the second edge isolation signal IsoaEdge = the second edge depolarization signal = 0. As a result, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_1, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_65. However, the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_2, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_64. On the other hand, although each of the sense amplifier modules 12_2 to 12_63 is electrically connected to the adjacent memory array chips on both sides, since the pre-charge switches in the sense amplifier modules 12_1 to 12_64 are not turned on, the bit lines in the adjacent memory array chips of the sense amplifier modules 12_1 to 12_64 are not pre-charged. Thus, only the bit lines in the memory array chips at the head and tail are pre-charged.

[0183] Of course, in another embodiment, a first depolarization switch 31 and a first isolation switch 32 are provided between the sense amplifier module 12_1 and the memory array chip 11_1, and the connection between the sense amplifier module 12_65 and the memory array chip 11_64 is a second depolarization switch 33 and a second isolation switch 34. Based on this, another structure of the first pre-processing circuit 50 is provided.

[0184] As Figure 10 shown, the first pre-processing circuit 50 includes a first processing sub-circuit 51 and a second processing sub-circuit 52, and the edge test parameter group includes a head-end parameter group TmEdge0<1:0> and a tail-end parameter group TmEdge1<1:0>;

[0185] The first processing sub-circuit 51 is configured to generate a first head-end isolation signal IsobEdge0 and a second head-end isolation signal IsoaEdge0 based on the head-end parameter group TmEdge0<1:0> and the initial isolation signal IsoPre; and generate a first head-end depolarization signal OcEnbEdge0 and a second head-end depolarization signal OcEnaEdge0 based on the head-end parameter group and the initial depolarization signal OcPre;

[0186] The second sub-processing circuit 52 is configured to generate a first tail-end isolation signal IsobEdge1 and a second tail-end isolation signal IsoaEdge1 based on the tail-end parameter group TmEdge1<1:0> and the initial isolation signal IsoPre; and generate a first tail-end depolarization signal OcEnbEdge1 and a second tail-end depolarization signal OcEnaEdge1 based on the head-end parameter group and the initial depolarization signal OcPre.

[0187] Among them, the first isolation switch 32, the second isolation switch 34, the first depolarization switch 31, and the second depolarization switch 33 between the first read amplification module and the adjacent memory array chip are controlled by the first head-end isolation signal IsobEdge0, the second head-end isolation signal IsoaEdge0, the first head-end depolarization signal OcEnbEdge0, and the second head-end depolarization signal OcEnaEdge0; the first isolation switch 32, the second isolation switch 34, the first depolarization switch 31, and the second depolarization switch 33 between the last read amplification module and the adjacent memory array chip are controlled by the first tail-end isolation signal IsobEdge1, the second tail-end isolation signal IsoaEdge1, the first tail-end depolarization signal OcEnbEdge1, and the second tail-end depolarization signal OcEnaEdge1.

[0188] Specifically, the head-end test parameter group includes a fifth test parameter TmEdge0<0> and a sixth test parameter TmEdge0<1>, and the tail-end test parameter group includes a seventh test parameter TmEdge1<0> and an eighth test parameter TmEdge1<1>.

[0189] Correspondingly, as Figure 10 shown, the first processing sub-circuit 51 includes:

[0190] A ninth AND gate 511, whose two input terminals respectively receive the fifth test parameter TmEdge0<0> and the initial isolation signal IsoPre, and whose output terminal outputs the second head-end isolation signal IsoaEdge0;

[0191] A tenth AND gate 512, whose two input terminals respectively receive the sixth test parameter TmEdge0<1> and the initial isolation signal IsoPre, and whose output terminal outputs the first head-end isolation signal IsobEdge0;

[0192] An eleventh AND gate 513, whose two input terminals respectively receive the fifth test parameter TmEdge0<0> and the initial depolarization signal OcPre, and whose output terminal outputs the second head-end depolarization signal OcEnaEdge0;

[0193] The twelfth AND gate 514 has two input terminals respectively receiving the sixth test parameter TmEdge0<1> and the initial depolarization signal OcPre, and its output terminal outputs the first head-end depolarization signal OcEnbEdge0.

[0194] The second processing sub-circuit 52 includes:

[0195] The thirteenth AND gate 521 has two input terminals respectively receiving the seventh test parameter TmEdge1<0> and the initial isolation signal IsoPre, and its output terminal outputs the second tail-end isolation signal IsoaEdge1;

[0196] The fourteenth AND gate 522 has two input terminals respectively receiving the eighth test parameter TmEdge1<1> and the initial isolation signal IsoPre, and its output terminal outputs the first tail-end isolation signal IsobEdge1;

[0197] The fifteenth AND gate 523 has two input terminals respectively receiving the seventh test parameter TmEdge1<0> and the initial depolarization signal OcPre, and its output terminal outputs the second tail-end depolarization signal OcEnaEdge1;

[0198] The sixteenth AND gate 524 has two input terminals respectively receiving the eighth test parameter TmEdge1<1> and the initial depolarization signal OcPre, and its output terminal outputs the first tail-end depolarization signal OcEnbEdge1.

[0199] Specifically, during the execution of the conventional precharge operation, TmEdge0<1:0> = 11, TmInter<1:0> = 11, TmEdge0<1:0> = 11. Therefore, all the first isolation switches 32, the second isolation switches 34, the first depolarization switches 31, and the second depolarization switches 33 are turned on; thus, all the bit lines can be precharged.

[0200] During the execution of the first test precharge operation, TmEdge0<1:0> = 01, TmInter<1:0> = 11, TmEdge1<1:0> = 10. Therefore, the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_65. However, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_64; the sense amplifier modules 12_2 to 12_63 are each electrically connected to the memory array chips on both sides; thus, the bit lines in the memory array chips at non-head and non-tail positions can be precharged.

[0201] During the execution of the second test precharge operation, TmEdge0<1:0> = 10, TmInter<1:0> = 11, TmEdge1<1:0> = 01, so it is read that the sense amplifier module 12_1 is electrically connected to the memory array chip 11_1, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_65. However, the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_2, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_64. Each of the sense amplifier modules 12_1 to 12_64 is electrically connected to the adjacent memory array chips on both sides. However, since the precharge switches in the sense amplifier modules 12_2 to 12_63 are not turned on, the bit lines in the adjacent memory array chips of each of the sense amplifier modules 12_2 to 12_63 are not precharged. Thus, the bit lines in the memory array chips at non-head and non-tail positions can be precharged.

[0202] In summary, the embodiments of the present disclosure provide a memory, which reduces the area of the memory array chips at the edge to half of the area of other memory array chips, thereby being able to reduce the area of the chip and improve the integration degree. At the same time, a corresponding test method is also provided for this structure to improve the test process of the memory with this structure and ensure the factory performance.

[0203] In another embodiment of the present disclosure, refer to Figure 11 , which shows a schematic flow chart of a test method provided by the embodiments of the present disclosure. As Figure 11 shown, this test method is applied to the memory shown in Figure 3A or Figure 3B . The memory 10 includes N memory array chips arranged in sequence along the first direction. The memory array chip includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along the second direction. For the memory array chips at non-head and non-tail positions, the first bit line is electrically isolated from the adjacent second bit line. For the memory array chips at the head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side.

[0204] For convenience of description, the memory array chips are numbered along the first direction. For the memory array chips with odd numbers, the first bit line thereof is the second bit line. For the memory array chips with even numbers, the first bit line thereof is the first bit line. For each memory array chip, the first bit lines therein are sequentially numbered along the second direction, and the second bit lines therein are sequentially numbered along the second direction.

[0205] This method includes:

[0206] S701: For the memory array chips at non-head and non-tail positions, apply different voltages to the first bit line and the second bit line respectively to implement the bit line stress test for the memory array chips at non-head and non-tail positions.

[0207] S702: For the memory array chips at head and tail positions, apply different voltages to the first bit lines with odd numbers and the first bit lines with even numbers respectively to implement the bit line stress test for the memory array chips at head and tail positions.

[0208] Here, there is no limitation on the execution order of step S701 and step S702.

[0209] In some embodiments, for Figure 6 the memory 10 shown, that is: for the first memory array chip, the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the first bit lines therein are precharged through the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last memory array chip, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are precharged through the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the memory array chips at non-head and non-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches; the precharge power supplies for the second bit lines in the memory arrays with odd numbers and the first bit lines in the memory array chips with even numbers are both the first power supply terminal, and the precharge power supplies for the first bit lines in the memory arrays with odd numbers and the second bit lines in the memory array chips with even numbers are both the second power supply terminal; for the memory array chips at head and tail positions, only one type of the first bit lines and the second bit lines corresponds to the precharge power supply;

[0210] The aforementioned step S701 includes:

[0211] Control the first power supply terminal to be a first voltage value and the second power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; perform a conventional precharge operation; wherein, in the conventional precharge operation, each bit line is in an on state with its respective precharge power supply; stop the conventional precharge operation after a preset duration, control the first power supply terminal to be the second voltage value and the second power supply terminal to be the first voltage value; perform the conventional precharge operation and maintain it for a preset duration.

[0212] It should be noted that each of the memory array chips at head and tail positions includes a plurality of twin cells. The twin cell includes 2 memory cells storing the same data. The 2 memory cells are both electrically connected to the same word line, and the bit lines corresponding to the 2 memory cells are electrically connected. The twin cells read and write data simultaneously.

[0213] Based on this, the aforementioned step S702 includes:

[0214] For the memory array slices at the head and tail positions, write the first data to the twin cells with odd numbers and write the second data to the twin cells with even numbers; the first data and the second data are different; after a preset time duration, stop the data writing operation, write the second data to the twin cells with odd numbers, and write the first data to the twin cells with even numbers, and maintain for a preset time duration.

[0215] In some embodiments, for Figure 7 the memory 10 shown, for the first memory array slice, the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the first bit lines therein are precharged through the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last memory array slice, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are precharged through the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the memory array slices at non-head-and-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches; that is: the precharge power supply for the second bit lines in the memory arrays with odd numbers is the third power supply terminal, the precharge power supply for the first bit lines in the memory array slices with even numbers is the fourth power supply terminal, the precharge power supply for the first bit lines in the memory arrays with odd numbers is the fifth power supply terminal, and the precharge power supply for the second bit lines in the memory array slices with even numbers is the sixth power supply terminal;

[0216] The foregoing step 701 includes:

[0217] Control the third power supply terminal and the fourth power supply terminal to be the first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the second voltage value; the first voltage value and the second voltage value are different; perform a conventional precharge operation; after a preset time duration, stop the conventional precharge operation, control the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; perform a conventional precharge operation and maintain for a preset time duration.

[0218] The foregoing step 702 includes:

[0219] Control the third power supply terminal and the fifth power supply terminal to be the first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the second voltage value; perform a conventional precharge operation; after a preset time duration, stop the conventional precharge operation, control the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; perform a conventional precharge operation and maintain for a preset time duration.

[0220] In some other embodiments, also for Figure 7 the memory 10 shown, the foregoing step 701 includes:

[0221] Control the third power supply terminal and the fourth power supply terminal to a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; perform a first test pre-charge operation; wherein, in the first test pre-charge operation, all bit lines in the memory array chips at the head and tail positions are in a disconnected state from their respective pre-charge power supplies, and all bit lines in the memory array chips at non-head and non-tail positions are in a connected state to their respective pre-charge power supplies; after a preset duration, stop the pre-charge operation, control the third power supply terminal and the fourth power supply terminal to the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to the first voltage value; perform the first test pre-charge operation and maintain the preset duration.

[0222] In some embodiments, the foregoing step 702 includes:

[0223] Control the third power supply terminal and the fifth power supply terminal to a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; perform a second test pre-charge operation; wherein, in the second test pre-charge operation, all bit lines in the memory array chips at the head and tail positions are in a connected state to their respective pre-charge power supplies, and all bit lines in the memory array chips at non-head and non-tail positions are in a disconnected state from their respective pre-charge power supplies; after a preset duration, stop the pre-charge operation, control the third power supply terminal and the fifth power supply terminal to the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to the first voltage value; perform the second test pre-charge operation and maintain the preset duration.

[0224] In summary, the embodiments of the present disclosure provide a test method, which reduces the area of the memory array chips located at the edge to half of the area of other memory array chips, thereby being able to reduce the area of the chip and improve the integration degree; at the same time, a corresponding test method is also provided for this structure to improve the test process of the memory of this structure and ensure the performance at the time of factory.

[0225] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0226] The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0227] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory device, characterized in that, the memory device includes N memory array slices arranged in sequence along a first direction, where N is a natural number; each memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are arranged alternately along a second direction; for the memory array slices at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array slices at head and tail positions, the first bit lines are electrically connected to the second bit lines adjacent to the first side, and the first bit lines are electrically isolated from the second bit lines adjacent to the second side; the memory device is configured to, in one step, apply different voltages to the first bit lines and the second bit lines respectively for the memory array slices at non-head and non-tail positions to implement bit line stress testing for the memory array slices at non-head and non-tail positions; and, in another step, apply different voltages to the first bit lines with odd numbers and the first bit lines with even numbers respectively for the memory array slices at head and tail positions to implement bit line stress testing for the memory array slices at head and tail positions; wherein, the memory array slices are numbered along the first direction. For the memory array slices with odd numbers, their first bit line is the second bit line; for the memory array slices with even numbers, their first bit line is the first bit line; for each memory array slice, the first bit lines therein are numbered in sequence along the second direction, and the second bit lines therein are numbered in sequence along the second direction.

2. The memory device according to claim 1, characterized in that, a sense amplifier module is distributed between every two memory array slices, and the sense amplifier module includes a plurality of sense amplifiers arranged in sequence along the second direction; a first end of the sense amplifier is connected to a second bit line on a third side through a first depolarization switch, and a second end of the sense amplifier is connected to a second bit line on the third side through a first isolation switch; the second end of the sense amplifier is further connected to a first bit line on a fourth side through a second depolarization switch, and the first end of the sense amplifier is further connected to a first bit line on the fourth side through a second isolation switch.

3. The memory device according to claim 2, characterized in that, the sense amplifier modules are numbered along the first direction; for the sense amplifier modules with odd numbers, a first end or a second end of the sense amplifiers therein is further connected to a first power supply terminal through a precharge switch; for the sense amplifier modules with even numbers, a first end or a second end of the sense amplifiers therein is further connected to a second power supply terminal through the precharge switch.

4. The memory device according to claim 3, characterized in that, the memory device is specifically configured to, in one step, turn off all sense amplifiers, control the first power supply terminal to be a first voltage value and the second power supply terminal to be a second voltage value, and perform a conventional precharge operation; and, after a preset time duration, control the first power supply terminal to be the second voltage value and the second power supply terminal to be the first voltage value, and perform the conventional precharge operation; Wherein, the first voltage value and the second voltage value are different; in the conventional pre-charging operation, all pre-charging switches, isolation switches, and bias cancellation switches are in the on state.

5. The memory according to claim 4, wherein, the memory array chips at the head and tail positions each include a plurality of twin cells, the twin cells include 2 memory cells storing the same data, the 2 memory cells are both electrically connected to the same word line, and there is an electrical connection between the bit lines corresponding to the 2 memory cells respectively, and the twin cells read and write data simultaneously; for each of the memory array chips at the head and tail positions, the twin cells are numbered along the second direction; the memory is further configured to, in another step, only turn on the sense amplifiers adjacent to the memory array chips at the head and tail positions, write the first data to the oddly numbered twin cells, and write the second data to the evenly numbered twin cells; and, after a preset time duration, write the second data to the oddly numbered twin cells, and write the first data to the evenly numbered twin cells; wherein, the first data and the second data are different.

6. The memory according to claim 2, wherein, the sense amplifier modules are numbered along the first direction, and the first sense amplifier module is oddly numbered; for each sense amplifier module, the sense amplifiers therein are numbered along the second direction; for the oddly numbered sense amplifier modules, the second ends of the oddly numbered sense amplifiers therein are connected to the third power supply terminal through pre-charging switches, and the first ends of the evenly numbered sense amplifiers are connected to the fourth power supply terminal through pre-charging switches; for the evenly numbered sense amplifier modules, the second ends of the oddly numbered sense amplifiers therein are connected to the fifth power supply terminal through pre-charging switches, and the first ends of the evenly numbered sense amplifiers are connected to the sixth power supply terminal through pre-charging switches.

7. The memory according to claim 6, wherein, the memory is specifically configured to, in one step, turn off all sense amplifiers, control both the third power supply terminal and the fourth power supply terminal to be the first voltage value, and both the fifth power supply terminal and the sixth power supply terminal to be the second voltage value; and perform a conventional pre-charging operation; and, after a preset time duration, control both the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform the conventional pre-charging operation.

8. The memory according to claim 7, wherein, the memory is specifically configured to, in another step, turn off all sense amplifiers, control both the third power supply terminal and the fifth power supply terminal to be the first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the second voltage value; and perform the conventional pre-charging operation; and, after the preset time duration, control both the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; and perform the conventional pre-charging operation.

9. The memory according to claim 6, It is characterized in that the memory is specifically configured to, in a step, turn off all sense amplifiers, control the third power supply terminal and the fourth power supply terminal to be both a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be a second voltage value; and perform a first test precharge operation; and after a preset time duration, control the third power supply terminal and the fourth power supply terminal to be both a second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be a first voltage value; and perform the first test precharge operation; wherein, in the first test precharge operation, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the off state, and all the remaining precharge switches, isolation switches and depolarization switches are in the on state.

10. The memory according to claim 9, It is characterized in that the memory is specifically configured to, in another step, turn off all sense amplifiers, control the third power supply terminal and the fifth power supply terminal to be both a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be a second voltage value; and perform a second test precharge operation; and after the preset time duration, control the third power supply terminal and the fifth power supply terminal to be both a second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be a first voltage value; and perform the second test precharge operation; wherein, in the second test precharge operation, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at the head and tail positions are all in the on state, the isolation switches and the depolarization switches between the readout amplifier modules at the head and tail positions and the memory array chips at non-head and non-tail positions are all in the off state; the precharge switches of the readout amplifier modules at the head and tail positions are all in the on state, and the precharge switches in the remaining readout amplifier modules are all in the off state.

11. The memory according to claim 10, It is characterized in that the first test precharge operation, the second test precharge operation, and the conventional precharge operation all belong to precharge operations, and the memory further includes: a control circuit configured to generate a valid initial isolation signal and a valid initial depolarization signal when the memory is instructed to perform the precharge operation; and generate an invalid initial isolation signal and an invalid initial depolarization signal when the memory is not instructed to perform the precharge operation; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter set and the initial isolation signal; and generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter set and the initial depolarization signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter set and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter set and the initial depolarization signal; Among them, the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read amplification modules at the head and tail positions and the adjacent memory array chips are controlled by the first edge isolation signal, the second edge isolation signal, the first edge depolarization signal, and the second edge depolarization signal respectively; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read amplification modules at non-head and tail positions and the adjacent memory array chips are controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal respectively.

12. The memory according to claim 11, wherein, the edge test parameter group at least includes a first test parameter and a second test parameter, and the internal test parameter group at least includes a third test parameter and a fourth test parameter; if the current precharge operation is a conventional precharge operation, the first test parameter, the second test parameter, the third test parameter, and the fourth test parameter are all in the first state; if the test parameter group indicates that the current precharge operation is a first test precharge operation, the second test parameter is in the second state, and the first test parameter, the third test parameter, and the fourth test parameter are all in the first state; if the current precharge operation is a second test precharge operation, the first test parameter is in the second state, and the second test parameter, the third test parameter, and the fourth test parameter are all in the first state; if the second test parameter is in the first state, the first edge isolation signal and the first edge depolarization signal are respectively the same as the initial isolation signal and the initial depolarization signal in level; if the second test parameter is in the second state, the first edge isolation signal and the first edge depolarization signal are both invalid; if the first test parameter is in the first state, the second edge isolation signal and the second edge depolarization signal are respectively the same as the initial isolation signal and the initial depolarization signal in level; if the first test parameter is in the second state, the second edge isolation signal and the second edge depolarization signal are both invalid; if the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal are respectively the same as the initial isolation signal and the initial depolarization signal in level; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal are respectively the same as the initial isolation signal and the initial depolarization signal in level; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid.

13. The memory according to claim 12, wherein, the first state is a high level, and the second state is a low level; the first preprocessing circuit includes: A first AND gate, with two input terminals respectively receiving the first test parameter and the initial isolation signal, and an output terminal outputting the second edge isolation signal; A second AND gate, with two input terminals respectively receiving the second test parameter and the initial isolation signal, and an output terminal outputting the first edge isolation signal; A third AND gate, with two input terminals respectively receiving the first test parameter and the initial depolarization signal, and an output terminal outputting the second edge depolarization signal; A fourth AND gate, with two input terminals respectively receiving the second test parameter and the initial depolarization signal, and an output terminal outputting the first edge depolarization signal; The second preprocessing circuit includes: A fifth AND gate, with two input terminals respectively receiving the third test parameter and the initial isolation signal, and an output terminal outputting the second internal isolation signal; A sixth AND gate, with two input terminals respectively receiving the fourth test parameter and the initial isolation signal, and an output terminal outputting the first internal isolation signal; A seventh AND gate, with two input terminals respectively receiving the third test parameter and the initial depolarization signal, and an output terminal outputting the second internal depolarization signal; An eighth AND gate, with two input terminals respectively receiving the fourth test parameter and the initial depolarization signal, and an output terminal outputting the first internal depolarization signal.

14. A test method, characterized in that, applied to a memory, the memory includes N memory array slices arranged in sequence along a first direction, the memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the first bit line and the second bit line are alternately arranged along a second direction; for the memory array slices at non-head and non-tail positions, the first bit line and the adjacent second bit line are electrically isolated; for the memory array slices at head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side; the method includes: In one step, for the memory array slices at non-head and non-tail positions, different voltages are respectively applied to the first bit line and the second bit line therein to implement bit line stress testing of the memory array slices at non-head and non-tail positions; In another step, for the memory array slices at head and tail positions, different voltages are respectively applied to the first bit lines with odd numbers and the first bit lines with even numbers therein to implement bit line stress testing of the memory array slices at head and tail positions; wherein, the memory array slices are numbered along the first direction, for the memory array slices with odd numbers, its first bit line is the second bit line; for the memory array slices with even numbers, its first bit line is the first bit line; for each memory array slice, the first bit lines therein are sequentially numbered along the second direction, and the second bit lines therein are sequentially numbered along the second direction.

15. The method according to claim 14, characterized in that, For the first storage array slice, the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the first bit lines therein are precharged through the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last storage array slice, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are precharged through the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the storage array slices at non-head and non-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches; the precharge power supplies for the second bit lines in the storage arrays with odd numbers and the first bit lines in the storage array slices with even numbers are both the first power supply terminal, and the precharge power supplies for the first bit lines in the storage arrays with odd numbers and the second bit lines in the storage array slices with even numbers are both the second power supply terminal; For the storage array slices at non-head and non-tail positions, applying different voltages to the first bit line and the second bit line therein respectively includes: Controlling the first power supply terminal to be a first voltage value and the second power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; Performing a conventional precharge operation; wherein, in the conventional precharge operation, each bit line is in an on state with its respective precharge power supply; After a preset duration, stopping the conventional precharge operation, and controlling the first power supply terminal to be the second voltage value and the second power supply terminal to be the first voltage value; Performing the conventional precharge operation and maintaining the preset duration.

16. The method according to claim 15, wherein, The storage array slices at head and tail positions each include a plurality of twin cells, the twin cells include 2 storage cells storing the same data, the 2 storage cells are both electrically connected to the same word line, and the bit lines corresponding to the 2 storage cells are electrically connected, and the twin cells perform data reading and writing simultaneously; For the storage array slices at head and tail positions, applying different voltages to the odd-numbered first bit lines and the even-numbered first bit lines therein respectively includes: For the storage array slices at head and tail positions, writing first data to the odd-numbered twin cells and writing second data to the even-numbered twin cells; the first data and the second data are different; After a preset duration, stopping the data writing operation, writing second data to the odd-numbered twin cells and writing first data to the even-numbered twin cells, and maintaining the preset duration.

17. The method according to claim 14, wherein, For the first storage array chip, the second bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the first bit lines are precharged through the precharge power supplies corresponding to the second bit lines electrically connected thereto; for the last storage array chip, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines are precharged through the precharge power supplies corresponding to the first bit lines electrically connected thereto; for the storage array chips at non-head and non-tail positions, the first bit lines therein are connected to their respective corresponding precharge power supplies through precharge switches, and the second bit lines are connected to their respective corresponding precharge power supplies through precharge switches; the precharge power supply for the second bit lines in the storage arrays with odd numbers is the third power supply terminal, the precharge power supply for the first bit lines in the storage array chips with even numbers is the fourth power supply terminal, the precharge power supply for the first bit lines in the storage arrays with odd numbers is the fifth power supply terminal, and the precharge power supply for the second bit lines in the storage array chips with even numbers is the sixth power supply terminal; For the storage array chips at non-head and non-tail positions, applying different voltages to the first bit lines and the second bit lines therein respectively includes: Controlling the third power supply terminal and the fourth power supply terminal to be a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to be a second voltage value; the first voltage value and the second voltage value are different; Performing a conventional precharge operation; After a preset time duration, stopping the conventional precharge operation, controlling the third power supply terminal and the fourth power supply terminal to be the second voltage value, and the fifth power supply terminal and the sixth power supply terminal to be the first voltage value; Performing a conventional precharge operation and maintaining the preset time duration.

18. The method according to claim 17, wherein, For the storage array chips at head and tail positions, applying different voltages to the first bit lines with odd numbers and the first bit lines with even numbers therein respectively includes: Controlling the third power supply terminal and the fifth power supply terminal to be a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to be a second voltage value; Performing a conventional precharge operation; After a preset time duration, stopping the conventional precharge operation, controlling the third power supply terminal and the fifth power supply terminal to be the second voltage value, and the fourth power supply terminal and the sixth power supply terminal to be the first voltage value; Performing a conventional precharge operation and maintaining the preset time duration.

19. The method according to claim 14, wherein, The precharge power supply for the second bit lines in the storage arrays with odd numbers is the third power supply terminal, the precharge power supply for the first bit lines in the storage array chips with even numbers is the fourth power supply terminal, the precharge power supply for the first bit lines in the storage arrays with odd numbers is the fifth power supply terminal, and the precharge power supply for the second bit lines in the storage array chips with even numbers is the sixth power supply terminal; for the storage array chips at head and tail positions, one type of the first bit lines and the second bit lines corresponds to the precharge power supply; For the storage array chips at non-head and non-tail positions, applying different voltages to the first bit lines and the second bit lines therein respectively includes: Control the third power supply terminal and the fourth power supply terminal to a first voltage value, and the fifth power supply terminal and the sixth power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; Perform a first test precharge operation; wherein, in the first test precharge operation, all bit lines in the memory array slices at the head and tail positions are in a disconnected state from their respective precharge power supplies, and all bit lines in the memory array slices at non-head and non-tail positions are in a connected state to their respective precharge power supplies; After a preset time duration, stop the precharge operation and control the third power supply terminal and the fourth power supply terminal to a second voltage value, and the fifth power supply terminal and the sixth power supply terminal to a first voltage value; Perform the first test precharge operation and maintain the preset time duration.

20. The method according to claim 19, wherein, For the memory array slices at the head and tail positions, applying different voltages to the odd-numbered first bit lines and the even-numbered first bit lines therein respectively, includes: Control the third power supply terminal and the fifth power supply terminal to a first voltage value, and the fourth power supply terminal and the sixth power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; Perform a second test precharge operation; wherein, in the second test precharge operation, all bit lines in the memory array slices at the head and tail positions are in a connected state to their respective precharge power supplies, and all bit lines in the memory array slices at non-head and non-tail positions are in a disconnected state from their respective precharge power supplies; After a preset time duration, stop the precharge operation, control the third power supply terminal and the fifth power supply terminal to a second voltage value, and the fourth power supply terminal and the sixth power supply terminal to a first voltage value; Perform the second test precharge operation and maintain the preset time duration.

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