A memory

Abstract

The present disclosure provides a memory, in which, for a non-first-and-last-position memory array slice, each bit line is coupled to a corresponding stress test power supply, and a first bit line is coupled to a different stress test power supply than a second adjacent bit line; for a first-and-last-position memory array slice, each first bit line is coupled to a corresponding stress test power supply, and an odd-numbered first bit line is coupled to a different stress test power supply than an even-numbered first bit line.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a memory. BACKGROUND

[0002] With the development of semiconductor technology, the integration requirement and performance standard of memory are gradually increasing, and therefore the internal circuit structure is gradually optimized, and it is also a problem to be solved to provide a matching test method for the optimized internal circuit structure. SUMMARY

[0003] The present disclosure provides a memory.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a memory, comprising N memory array slices arranged in sequence along a first direction, N being a natural number; each of the memory array slices comprises a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices at non-first and non-last positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array slices at first and last positions, the first bit lines are electrically connected with the second bit lines adjacent to a first side, and the first bit lines are electrically isolated from the second bit lines adjacent to a second side; the first side and the second side are two sides opposite along the second direction; the memory array slices are numbered along the first direction; and in each of the memory array slices, the first bit lines are numbered along the second direction, and the second bit lines are numbered along the second direction; for the memory array slices at non-first and non-last positions, each of the bit lines is coupled to a corresponding stress test power supply, and the stress test power supply corresponding to the first bit line is different from the stress test power supply corresponding to the adjacent second bit line; for the memory array slices at first and last positions, the first bit lines are coupled to corresponding stress test power supplies, and the stress test power supply corresponding to the first bit line with an odd number is different from the stress test power supply corresponding to the first bit line with an even number.

[0006] In some embodiments, the first bit line of the storage array slice numbered with odd number is the second bit line, and the first bit line of the storage array slice numbered with even number is the first bit line; a sense amplifier is arranged between every two storage array slices, and the sense amplifier comprises a plurality of sense amplifiers arranged in sequence along a second direction; a first end of the sense amplifier is connected with one of the second bit lines on a third side through a first un-bias switch, and a second end of the sense amplifier is connected with one of the second bit lines on the third side through a first isolation switch; the second end of the sense amplifier is also connected with one of the first bit lines on a fourth side through a second un-bias switch, and the first end of the sense amplifier is also connected with one of the first bit lines on the fourth side through a second isolation switch; the third side and the fourth side are two sides opposite to each other along the first direction; the first end or the second end of each sense amplifier is also connected with a pre-charge power source through a corresponding pre-charge switch, so that each bit line is coupled with one pre-charge power source.

[0007] In some embodiments, for the storage array slice at a non-first or non-last position, the pre-charge power source coupled with the bit line serves as the stress test power source; for the storage array slice at the first or last position, the first bit line is also coupled with a respective edge test power source through a first test switch, and the edge test power source coupled with the first bit line serves as the stress test power source.

[0008] In some embodiments, for the storage array slice at a non-first or non-last position, the bit line is also coupled with a respective pre-charge power source through a column gate switch and a second test switch; for the storage array slice at the first or last position, the first bit line is also coupled with a respective pre-charge power source through a column gate switch and a second test switch; for each storage array slice, the pre-charge power source coupled with each bit line serves as the stress test power source.

[0009] In some embodiments, for the storage array slice at a non-first or non-last position, the bit line is also coupled with a respective pre-charge power source through a column gate switch and a second test switch; for the storage array slice at the first or last position, the first bit line is also coupled with a respective pre-charge power source through a column gate switch and a second test switch; for each storage array slice, the pre-charge power source coupled with each bit line serves as the stress test power source.

[0010] In some embodiments, the sense amplifiers in the readout amplification modules are numbered along the first direction; for the odd-numbered readout amplification modules, the first end or the second end of the sense amplifier is connected to the first pre-charge power source through the corresponding pre-charge switch; for the even-numbered readout amplification modules, the first end or the second end of the sense amplifier is connected to the second pre-charge power source through the corresponding pre-charge switch, so that the pressure test power source corresponding to the first bit line is different from the pressure test power source corresponding to the adjacent second bit line.

[0011] In some embodiments, for the storage array chips at the first and last positions, the odd-numbered first bit lines are connected to the first edge test power source through the respective first test switches, and the even-numbered first bit lines are connected to the second edge test power source through the respective first test switches; or, for the first storage array chip, the odd-numbered first bit lines are connected to the first edge test power source through the respective first test switches, and the even-numbered first bit lines are connected to the second edge test power source through the respective first test switches; for the last storage array chip, the odd-numbered first bit lines are connected to the second edge test power source through the respective first test switches, and the even-numbered first bit lines are connected to the first edge test power source through the respective first test switches.

[0012] In some embodiments, the memory is configured to control the first edge test power source to be a first voltage value, the second edge test power source to be a second voltage value, the first pre-charge power source to be a third voltage value, and the second pre-charge power source to be a fourth voltage value, and perform a bit line pressure test operation; and control the first edge test power source to be a second voltage value, the second edge test power source to be a first voltage value, the first pre-charge power source to be a fourth voltage value, and the second pre-charge power source to be a third voltage value, and perform the bit line pressure test operation; wherein the first voltage value and the second voltage value are different, and the third voltage value and the fourth voltage value are different; in the bit line pressure test operation, all first test switches are in a closed state, isolation switches and anti-skew switches between the storage array chips at the first and last positions and the adjacent readout amplification modules are in an off state, and the remaining isolation switches, the remaining anti-skew switches, and all pre-charge switches are in a closed state.

[0013] In some embodiments, the bit lines in the storage array slices at the head and tail positions are electrically connected with the adjacent sense amplification modules through the first un-bias switch or the first isolation switch; the memory further comprises: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial un-bias signal; wherein, when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal and the initial un-bias signal are all in an active state; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter group and the initial isolation signal, and generate a first edge un-bias signal and a second edge un-bias signal based on the edge test parameter group and the initial un-bias signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal, and generate a first internal un-bias signal and a second internal un-bias signal based on the internal test parameter group and the initial un-bias signal; wherein, all the first test switches are controlled by the test enable signal, the first isolation switch, the second isolation switch, the first un-bias switch and the second un-bias switch between the readout amplification modules at the head and tail positions and the adjacent storage array slices are correspondingly controlled by the first edge isolation signal, the second edge isolation signal, the first edge un-bias signal and the second edge un-bias signal; and the first isolation switch, the second isolation switch, the first un-bias switch and the second un-bias switch between the readout amplification modules at the non-head and non-tail positions and the adjacent storage array slices are correspondingly controlled by the first internal isolation signal, the second internal isolation signal, the first internal un-bias signal and the second internal un-bias signal.

[0014] In some embodiments, the edge test parameter group includes a first test parameter and a second test parameter, the internal test parameter group includes a third test parameter and a fourth test parameter; if the first test parameter is in a first state, the second edge isolation signal and the second edge deskew signal are respectively identical to the level of the initial isolation signal and the initial deskew signal; if the first test parameter is in a second state, the second edge isolation signal and the second edge deskew signal are both invalid; if the second test parameter is in a first state, the first edge isolation signal and the first edge deskew signal are respectively identical to the level of the initial isolation signal and the initial deskew signal; if the second test parameter is in a second state, the first edge isolation signal and the first edge deskew signal are both invalid; if the fourth test parameter is in a first state, the first internal isolation signal and the first internal deskew signal are respectively identical to the level of the initial isolation signal and the initial deskew signal; if the fourth test parameter is in a second state, the first internal isolation signal and the first internal deskew signal are both invalid; if the third test parameter is in a first state, the second internal isolation signal and the second internal deskew signal are respectively identical to the level of the initial isolation signal and the initial deskew signal; if the third test parameter is in a second state, the second internal isolation signal and the second internal deskew signal are both invalid; wherein during the process that the memory is instructed to perform a bit line stress test operation, the second test parameter is in a second state, and the first test parameter, the third test parameter and the fourth test parameter are all in a first state.

[0015] In some embodiments, the first state is a high level and the second state is a low level; the first preprocessing circuit includes: a first AND gate having two input ends respectively receiving the first test parameter and the initial isolation signal and an output end outputting the second edge isolation signal; a second AND gate having two input ends respectively receiving the second test parameter and the initial isolation signal and an output end outputting the first edge isolation signal; a third AND gate having two input ends respectively receiving the first test parameter and the initial deskew signal and an output end outputting the second edge deskew signal; and a fourth AND gate having two input ends respectively receiving the second test parameter and the initial deskew signal and an output end outputting the first edge deskew signal.

[0016] In some embodiments, the bit lines in the first storage array slice are electrically connected with the adjacent sense amplification modules through the first isolation switch or the first offset cancellation switch, the bit lines in the last storage array slice are electrically connected with the first and last sense amplification modules through the second isolation switch or the second offset cancellation switch, the memory further comprises: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial offset cancellation signal; wherein, when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal and the initial offset cancellation signal are all in an active state; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal, and generate a first internal offset cancellation signal and a second internal offset cancellation signal based on the internal test parameter group and the initial offset cancellation signal; a third preprocessing circuit configured to generate a first first-end isolation signal and a second first-end isolation signal based on a first-end test parameter group and the initial isolation signal, and generate a first first-end offset cancellation signal and a second first-end offset cancellation signal based on the first-end test parameter group and the initial offset cancellation signal; a fourth preprocessing circuit configured to generate a first tail-end isolation signal and a second tail-end isolation signal based on a tail-end test parameter group and the initial isolation signal, and generate a first tail-end offset cancellation signal and a second tail-end offset cancellation signal based on the tail-end test parameter group and the initial offset cancellation signal; wherein, all the first test switches are controlled by the test enable signal, the first isolation switch, the second isolation switch, the first offset cancellation switch and the second offset cancellation switch between the first readout amplification module and the adjacent storage array slice are controlled by the first first-end isolation signal, the second first-end isolation signal, the first first-end offset cancellation signal and the second first-end offset cancellation signal respectively; the first isolation switch, the second isolation switch, the first offset cancellation switch and the second offset cancellation switch between the last readout amplification module and the adjacent storage array slice are controlled by the first tail-end isolation signal, the second tail-end isolation signal, the first tail-end offset cancellation signal and the second tail-end offset cancellation signal respectively; the first isolation switch, the second isolation switch, the first offset cancellation switch and the second offset cancellation switch between the readout amplification module at a non-first-end and non-tail-end position and the adjacent storage array slice are controlled by the first internal isolation signal, the second internal isolation signal, the first internal offset cancellation signal and the second internal offset cancellation signal respectively.

[0017] In some embodiments, the internal test parameter group includes at least a third test parameter and a fourth test parameter; the head-end test parameter group includes a fifth test parameter and a sixth test parameter, and the tail-end test parameter group includes a seventh test parameter and an eighth test parameter; if the third test parameter is in a first state, the second internal isolation signal and the second internal skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the third test parameter is in a second state, the second internal isolation signal and the second internal skew signal are both invalid; if the fourth test parameter is in the first state, the first internal isolation signal and the first internal skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal skew signal are both invalid; if the fifth test parameter is in the first state, the second head-end isolation signal and the second head-end skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the fifth test parameter is in the second state, the second head-end isolation signal and the second head-end skew signal are both invalid; if the sixth test parameter is in the first state, the first head-end isolation signal and the first head-end skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the sixth test parameter is in the second state, the first head-end isolation signal and the first head-end skew signal are both invalid; if the seventh test parameter is in the first state, the second tail-end isolation signal and the second tail-end skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the seventh test parameter is in the second state, the second tail-end isolation signal and the second tail-end skew signal are both invalid; if the eighth test parameter is in the first state, the first tail-end isolation signal and the first tail-end skew signal are respectively identical to the level of the initial isolation signal and the initial skew signal; if the eighth test parameter is in the second state, the first tail-end isolation signal and the first tail-end skew signal are both invalid; wherein during the process in which the memory is instructed to perform a bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

[0018] In some embodiments, the first state is high level and the second state is low level; the second preprocessing circuit comprises: a fifth AND gate, whose two input terminals receive the third test parameter and the initial isolation signal respectively, and whose output terminal outputs the second internal isolation signal; a sixth AND gate, whose two input terminals receive the fourth test parameter and the initial isolation signal respectively, and whose output terminal outputs the first internal isolation signal; a seventh AND gate, whose two input terminals receive the third test parameter and the initial cancellation signal respectively, and whose output terminal outputs the second internal cancellation signal; an eighth AND gate, whose two input terminals receive the fourth test parameter and the initial cancellation signal respectively, and whose output terminal outputs the first internal cancellation signal.

[0019] In some embodiments, the first state is high level and the second state is low level; the third preprocessing circuit comprises: a ninth AND gate, whose two input terminals receive the fifth test parameter and the initial isolation signal respectively, and whose output terminal outputs the second head-end isolation signal; a tenth AND gate, whose two input terminals receive the sixth test parameter and the initial isolation signal respectively, and whose output terminal outputs the first head-end isolation signal; an eleventh AND gate, whose two input terminals receive the fifth test parameter and the initial cancellation signal respectively, and whose output terminal outputs the second head-end cancellation signal; a twelfth AND gate, whose two input terminals receive the sixth test parameter and the initial cancellation signal respectively, and whose output terminal outputs the first head-end cancellation signal; the fourth preprocessing circuit comprises: a thirteenth AND gate, whose two input terminals receive the seventh test parameter and the initial isolation signal respectively, and whose output terminal outputs the second tail-end isolation signal; a fourteenth AND gate, whose two input terminals receive the eighth test parameter and the initial isolation signal respectively, and whose output terminal outputs the first tail-end isolation signal; a fifteenth AND gate, whose two input terminals receive the seventh test parameter and the initial cancellation signal respectively, and whose output terminal outputs the second tail-end cancellation signal; a sixteenth AND gate, whose two input terminals receive the eighth test parameter and the initial cancellation signal respectively, and whose output terminal outputs the first tail-end cancellation signal.

[0020] In some embodiments, the storage array tiles in non-head-tail positions, wherein the bit lines in each of the storage array tiles in non-head-tail positions are coupled to a respective local data line via a respective column gate switch; wherein: for a second bit line in the storage array tile in non-head-tail position and odd number and a first bit line in the storage array tile in non-head-tail position and even number, the local data line coupled thereto is further connected to a first pre-charge source through a respective second test switch; for a first bit line in the storage array tile in non-head-tail position and odd number and a second bit line in the storage array tile in non-head-tail position and even number, the local data line coupled thereto is further connected to a second pre-charge source through a respective second test switch.

[0021] In some embodiments, for the storage array tiles at the head and tail positions, the first bit lines therein are coupled to respective local data lines via respective column gating switches; wherein: for the storage array tiles at the head and tail positions, the local data lines coupled to the odd numbered first bit lines are coupled to a second pre-charge source via the second test switch, and the local data lines coupled to the even numbered first bit lines are coupled to a first pre-charge source via the second test switch; or, for the first storage array tile, the local data lines coupled to the odd numbered first bit lines are coupled to a second pre-charge source via the second test switch, and the local data lines coupled to the even numbered first bit lines are coupled to a first pre-charge source via the second test switch; and, for the last storage array tile, the local data lines coupled to the odd numbered first bit lines are coupled to a first pre-charge source via the second test switch, and the local data lines coupled to the even numbered second bit lines are coupled to a first pre-charge source via the second test switch.

[0022] In some embodiments, the memory is configured to control all of the isolation switches, the cancellation switches, and the pre-charge switches to be in an off state, control all of the column gating switches and the second test switch to be in a closed state, and control the first pre-charge source to be at a first voltage value and the second pre-charge source to be at a second voltage value, to perform a first bit line stress test; or, control all of the isolation switches, the cancellation switches, and the pre-charge switches to be in an off state, control all of the column gating switches and the second test switch to be in a closed state, and control the first pre-charge source to be at a second voltage value and the second pre-charge source to be at a first voltage value, to perform a second bit line stress test.

[0023] In some embodiments, for the storage array tiles at the head and tail positions, the first bit lines therein are coupled to respective local data lines via respective column gating switches; wherein: for the storage array tiles at the head and tail positions, the local data lines coupled to the odd numbered first bit lines are coupled to a second pre-charge source via the second test switch, and the local data lines coupled to the even numbered first bit lines are coupled to a first pre-charge source via the second test switch; or, for the first storage array tile, the local data lines coupled to the odd numbered first bit lines are coupled to a second pre-charge source via the second test switch, and the local data lines coupled to the even numbered first bit lines are coupled to a first pre-charge source via the second test switch; and, for the last storage array tile, the local data lines coupled to the odd numbered first bit lines are coupled to a first pre-charge source via the second test switch, and the local data lines coupled to the even numbered second bit lines are coupled to a first pre-charge source via the second test switch.

[0024] In some embodiments, for the storage array pieces at the head and tail positions, the first bit lines therein are coupled to the respective local data lines via the respective column gate switches; wherein: for the storage array pieces at the head and tail positions, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power source via the second test switches; or, for the first storage array piece, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power source via the second test switches; for the last storage array piece, the local data lines corresponding to the odd-numbered first bit lines are coupled to the first preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to the second preset test power source via the second test switches.

[0025] In some embodiments, the memory is configured to control all the isolation switches and the offset cancellation switches to be in the off state, control all the pre-charge switches to be in the closed state, and control the pre-charge power source to be at a fifth voltage value; control all the column gate switches and the second test switches to be in the closed state, and control the first preset test power source to be at a first voltage value and the second preset test power source to be at a second voltage value, to perform a first bit line stress test; control all the isolation switches and the offset cancellation switches to be in the off state, control all the pre-charge switches to be in the closed state, and control the pre-charge power source to be at the fifth voltage value; control all the column gate switches and the second test switches to be in the closed state, and control the first preset test power source to be at the second voltage value and the second preset test power source to be at the first voltage value, to perform a second bit line stress test; wherein the fifth voltage value is between the first voltage value and the second voltage value.

[0026] The embodiments of the present disclosure provide a memory, which reduces the area of the storage array pieces at the edges to half of the area of the other storage array pieces, thereby reducing the area of the chip and improving the integration; meanwhile, for the memory, each bit line in the storage array pieces at the non-head and non-tail positions is coupled to a stress test power source, and the first bit lines in the storage array pieces at the head and tail positions are coupled to the stress test power source, which can simultaneously cause the adjacent two bit lines in the storage array pieces at the non-head and non-tail positions to be at different voltages and the odd-numbered first bit lines and the even-numbered first bit lines in the storage array pieces at the head and tail positions to be at different voltages, thereby efficiently implementing the bit line stress test, perfecting the test flow of the memory of the structure, and ensuring the performance after leaving the factory. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1A partial structure of a DRAM Figure 1 ;

[0028] Figure 2 A partial structure of a DRAM Figure 2 ;

[0029] Figure 3A A partial structure of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0030] Figure 3B A partial structure of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0031] Figure 4 A partial structure of a memory provided by an embodiment of the present disclosure

[0032] Figure 5 A partial structure of a memory provided by an embodiment of the present disclosure Figure 4 ;

[0033] Figure 6 A structure of a sensitive amplifier provided by an embodiment of the present disclosure

[0034] Figure 7 A partial structure of a memory provided by an embodiment of the present disclosure Figure 5 ;

[0035] Figure 8 A control part of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0036] Figure 9 A control part of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0037] Figure 10 A partial structure of a memory provided by an embodiment of the present disclosure Figure 6 ;

[0038] Figure 11 A partial structure of a memory provided by an embodiment of the present disclosure Figure 7 . DETAILED DESCRIPTION

[0039] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limitations of the present disclosure. All other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0040] In the following description, reference is made to the "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other as long as there is no conflict.

[0041] If there are similar descriptions of "first / second" in the application file, the following description is added: In the following description, the terms "first / second / third" referred to only distinguish similar objects, and do not represent a specific order of the objects. It is understood that "first / second / third" can be interchanged in a specific order or sequence as long as it is allowed, so that the embodiments of the disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0043] Taking Dynamic Random Access Memory (DRAM) as an example, referring to Figure 1 , which shows a partial structure schematic diagram of a DRAM provided by an embodiment of the present disclosure. As Figure 1 shown, for a DRAM, its core is a storage array slice (or called Section), a sense amplifier module, a row decoding and control (XDEC) circuit, a column decoding and control (YDEC) circuit, a secondary sense amplifier (SSa) circuit and a write driver circuit. The secondary sense amplifier circuit and the write driver circuit are collectively referred to as SSa&Write Driver circuit.

[0044] The storage array slice is composed of a large number of storage units (or called Cell), and through the word line (Word Line, WL) and the bit line (Bit Line, BL), the selected storage unit can be read, written or refreshed.

[0045] Generally, 65 storage array slices in the first direction can be used as a repeatable structure (for example: storage half Half Bank) in the memory. The Figure 1 Further enlargement, please refer to Figure 2 , the bit lines in each storage array slice (such as 11_1, 11_2, …, 11_65) are alternately called first bit line BLa and second bit line BLb Figure 2For example, the first bit line BLa and the second bit line BLb are only a kind of position-based division, in fact, the first bit line BLa and the second bit line BLb have the same physical structure.

[0046] A readout amplification module (for example, 12_1, 12_2, …, 12_64) is arranged between every two storage array pieces, and each readout amplification module includes a plurality of sense amplifiers (Sa), one end of each Sa is connected with a bit line in the storage array piece on one side (for example, the upper side), and the other end of the Sa is connected with a bit line in the storage array piece on the other side (for example, the lower side).

[0047] Please refer to Figure 1 and Figure 2 , the target word line in the storage array piece is opened by the XDEC to give the word line signal, and then the corresponding Sa is controlled to work by the YDEC to give the column selection signal, and then the target bit line is exchanged with the electrical signal, and finally the data is written, read or refreshed to the target storage unit.

[0048] As shown in Figure 2 , for the storage array pieces at the edges, only half of the bit lines can be connected to the adjacent readout amplification module, which causes the other half of the bit lines and the corresponding storage units to be actually unusable, for example, the first bit line BLa in the storage array piece 11_1 and the storage array piece 11_65 is not connected to the readout amplification module, which causes the waste of the storage unit and is not conducive to the improvement of the chip integration.

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] In an embodiment of the present disclosure, refer to Figure 3A or Figure 3B , which shows a partial structure schematic diagram of a memory 10 provided by an embodiment of the present disclosure. As shown in Figure 3A or Figure 3B , the memory 10 includes N storage array pieces (for example, 11_1, 11_2, …, 11_N, that is, the storage array pieces are numbered along the first direction) arranged in sequence along the first direction. Here, N can be any natural number, Figure 3A Taking N as an odd number as an example, Figure 3B Taking N as an even number as an example.

[0051] Please refer toFigure 3A and Figure 3B Each memory array slice includes a plurality of first bit lines BLa and a plurality of second bit lines BLb, and the first bit lines BLa and the second bit lines BLb are arranged alternately along the second direction; for the memory array slices other than the first and last positions (for example, 11_2…11_N-1), the first bit line BLa and the adjacent second bit line BLb are electrically isolated; for the memory array slices at the first and last positions (for example, 11_1 and 11_N), the first bit line BLa is electrically connected with the second bit line BLb adjacent to the first side (for example, the left side along the second direction), and the first bit line BLa is electrically isolated from the second bit line BLb adjacent to the second side (for example, the right side along the second direction), that is, the first side and the second side are two opposite sides along the second direction.

[0052] Here, the sensitive amplification circuit 10 in the embodiments of the present disclosure is applied to various signal amplification scenarios, such as DRAM, SDRAM (Synchronous Dynamic Random Access Memory), double-speed DRAM, low-power DRAM, etc., which can be flexibly applied by those skilled in the art.

[0053] It should be noted that for the memory array slices at the first and last positions (11_1, 11_N), since two bit lines are connected to form a whole bit line, the length of each bit line can be shortened by nearly half. Specifically, for the memory array slices other than the first and last positions, the distance between one end of Sa connected to each bit line and the other end of the bit line is denoted as L1, and for the memory array slices at the first and last positions, the distance between one end of Sa connected to the whole bit line (first bit line + second bit line) and the other end of the whole bit line is denoted as L2, L1=L2.

[0054] Therefore, the area of the memory array slices at the first and last positions (11_1, 11_N) is shortened by nearly half compared to the area of the memory array slices other than the first and last positions (11_2…11_N-1), the integration of the memory 10 is improved, and the overall area occupied by the memory cells is reduced.

[0055] Please note that Figure 3A or Figure 3B Each memory array slice in the above-mentioned embodiments shows 8 bit lines, but this is only an omission of representation, and in fact the number of bit lines in each memory array slice is much larger.

[0056] Subsequent illustrations and descriptions are based on N=65, and the case where N is an even number or other values should be understood adaptively.

[0057] In particular, bit line stress (BL stress) is an important performance test item of the memory 10, and the test method is to apply different voltages to adjacent bit lines, and then observe whether the memory cells can work normally. For the memory 10 shown in Figure 3A or Figure 3B The bit line structures of the storage array pieces (11_1, 11_N) at the head and tail positions are different from those of the storage array pieces (11_2, …, 11_N-1) at the non-head and non-tail positions, which causes the conventional method to fail to implement the BL stress.

[0058] Therefore, the embodiments of the present disclosure further provide a test method for the BL stress of the memory 10 shown in Figure 3A or Figure 3B

[0059] For convenience of description, for the memory 10 shown in Figure 3A or Figure 3B For the odd-numbered storage array pieces (11_1, 11_3, 11_5, …), the first bit line is the second bit line BLb; for the even-numbered storage array pieces (11_2, 11_4, 11_6, …), the first bit line is the first bit line BLa, and for each storage array piece, the first bit lines BLa therein are sequentially numbered along the second direction, and the second bit lines BLb therein are sequentially numbered along the second direction.

[0060] Taking the odd-numbered starting point as an example, please refer to Figure 4 which takes N=65 as an example, and other values of N are adaptively understood, the bit lines in the storage array piece 11_1 along the second direction are BLbo, BLao, BLbe, and BLae in sequence, and the bit lines in the storage array piece 11_2 along the second direction are BLao, BLbo, BLae, and BLbe in sequence.

[0061] The embodiments of the present disclosure provide a memory 10, for the storage array pieces (11_2, 11_3, …, 11_64) at the non-head and non-tail positions, each bit line therein is coupled to a corresponding stress test power supply TXo / TXe, and the stress test power supply corresponding to the first bit line Bla is different from the stress test power supply corresponding to the adjacent second bit line BLb; for example, please refer to Figure 5 for the storage array piece 11_2, the stress test power supply corresponding to Bla is TXo, and the stress test power supply corresponding to Blb is TXe; for the storage array piece 11_3, the stress test power supply corresponding to Bla is TXe, and the stress test power supply corresponding to Blb is TXo.

[0062] ​For the first and last storage array pieces (11_1, 11_65), the first bit lines therein are all coupled to corresponding pressure test power supplies, and the pressure test power supply corresponding to the odd-numbered first bit line BLao is different from the pressure test power supply corresponding to the even-numbered first bit line BLae. It should be understood that, in the embodiment, the first bit line Bla in the storage array piece is coupled to the corresponding pressure test power supply through the Blb to which it is electrically connected; only as an example, the pressure test power supply corresponding to the Blao is TXe, and the pressure test power supply corresponding to the Blae is TXo. Figure 5 Figure 5

[0063] In particular, Figure 5 Only as an example, the pressure test power supply has more design methods in the actual scene, for example, for the storage array piece that is not at the first or last position, all the first bit lines are connected to TXo, and all the second bit lines are connected to Txe.

[0064] Please refer to Figure 5 , readout amplification modules are distributed between every 2 storage array pieces, and the readout amplification modules are numbered along the first direction, that is, the readout amplification modules are sequentially numbered as 12_1, 12_2, …, 12_64 along the first direction.

[0065] The readout amplification module includes a plurality of sensitive amplifiers Sa arranged along the second direction, for each readout amplification module, the sensitive amplifiers are numbered along the second direction, the odd-numbered sensitive amplifiers Sa are represented as 40o, and the even-numbered sensitive amplifiers Sa are represented as 40e, the structure of each sensitive amplifier Sa can be seen from Figure 6 . As shown in Figure 6 , the sensitive amplifier Sa includes first to fourth transistors 21, 22, 23, and 24 connected in cross coupling, the drain of the first transistor 21 and the drain of the third transistor 23 are both connected on the second complementary bit line SaBlb, the drain of the second transistor 22 and the drain of the fourth transistor 24 are both connected on the first complementary bit line SaBLa, the gate of the third transistor 23 is connected with the first bit line BLa, and the gate of the fourth transistor 24 is connected with the second bit line BLb; in addition, NCS refers to a pull-down module, and PCS refers to a pull-up module, which does not affect the understanding of the present disclosure scheme, and will not be described additionally.

[0066] Please refer to Figure 6 ​​The first end of the sense amplifier Sa is connected to a second bit line BLb on the third side (e.g. upper side in the first direction) through a first un-bias switch 31, and the second end of the sense amplifier Sa is connected to a second bit line BLb on the third side through a first isolation switch 32. The second end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side (e.g. lower side in the first direction) through a second un-bias switch 33, and the first end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side through a second isolation switch 34. The third side and the fourth side are opposite sides in the third direction.

[0067] For example, the first un-bias switch 31, the second un-bias switch 33, the first isolation switch 32 and the second isolation switch 34 are transistors.

[0068] The first end or the second end of each sense amplifier Sa is also connected to a pre-charge power source VAD through a corresponding pre-charge switch 35. It should be understood that, in the embodiment, the second bit line BLb is coupled to the pre-charge power source VAD through the first un-bias switch 31 and the pre-charge switch 35, and the first bit line BLa is coupled to the pre-charge power source VAD through the second isolation switch 34 and the pre-charge switch 35, i.e. each bit line is coupled to a pre-charge power source VAD, and the two bit lines connected to the same sense amplifier share the same pre-charge power source VAD. Figure 6

[0069] In this way, the embodiment of the disclosure provides a memory, which reduces the area of the storage array chip located at the edge to half of the area of other storage array chips, and each bit line of the storage array chip has a respective pressure test power source, so that the bit line pressure test can be efficiently implemented.

[0070] In a first specific embodiment, for the storage array chips (11_2, 11_3, …, 11_64) other than the first and last positions, the pre-charge power sources coupled to the bit lines are used as the pressure test power sources; however, for the storage array chips (11_1, 11_65) at the first and last positions, the first bit lines are also coupled to respective edge test power sources through first test switches, and the edge test power sources coupled to the first bit lines are used as the pressure test power sources.

[0071] The following is a specific description.

[0072] Please refer to Figure 7 In the memory 10, two groups of pre-charge power sources VAD are included, one group is referred to as the first pre-charge power source VAD2O, and the other group is referred to as the second pre-charge power source VAD2E; only for the storage array chips (11_2, 11_3, …, 11_64) other than the first and last positions, the first pre-charge power source VAD2O is used as the pressure test power source Txo, and the second pre-charge power source VAD2E is used as the pressure test power source Txe.

[0073] On the one hand, as​Figure 7 As shown, for odd-numbered readout amplification modules (12_1, 12_3, …, 12_63), the first end or the second end of the sense amplifier Sa therein is further connected to the first pre-charge power source VAD20 through the pre-charge switch 35; for even-numbered readout amplification modules (12_2, 12_4, …, 12_64), the first end or the second end of the sense amplifier Sa therein is further connected to the second pre-charge power source VAD2E through the pre-charge switch 35, so as to realize that the pressure test power source corresponding to the first bit line BLa is different from the pressure test power source corresponding to the adjacent second bit line BLb.

[0074] It should be understood that, in the above description, Figure 7 the second end of the odd-numbered sense amplifier 40o is connected to the corresponding pre-charge power source through the pre-charge switch 35, and the first end of the even-numbered sense amplifier 40e is connected to the corresponding pre-charge power source through the pre-charge switch 35, but this does not constitute a corresponding limitation, as long as the pre-charge power source corresponding to the sense amplifier Sa in the odd-numbered readout amplification module is the first pre-charge power source VAD20, and the pre-charge power source corresponding to the sense amplifier Sa in the even-numbered readout amplification module is the second pre-charge power source VAD2E.

[0075] On the other hand, the memory 10 further comprises 2 groups of edge test power sources, one group being referred to as the first edge test power source VAD2Eedge, and the other group being referred to as the second edge test power source VAD20edge; for the first and last storage array slices (11_1 and 11_65), the first edge test power source VAD2Eedge is used as the pressure test power source TXe, and the second edge test power source VAD20edge is used as the pressure test power source TXo.

[0076] In one case, please refer to Figure 7 for the first and last storage array slices (11_1, 11_65), the odd-numbered first bit lines BLao are connected to the first edge test power source VAD2Eedge via the respective first test switches 13, and the even-numbered first bit lines BLae are connected to the second edge test power source VAD20edge via the respective first test switches 13, so as to realize that the pressure test power source corresponding to the odd-numbered first bit line BLao is different from the pressure test power source corresponding to the even-numbered first bit line BLae.

[0077] In another case, for the first memory array slice 11_1, the odd-numbered first bit lines BLao are connected to the first edge test power supply VAD2Eedge via respective test switches, and the even-numbered first bit lines BLae are connected to the second edge test power supply VAD2Oedge via respective test switches; for the last memory array slice 11_65, the odd-numbered first bit lines BLao are connected to the second edge test power supply VAD2Oedge via respective test switches, and the even-numbered first bit lines BLae are connected to the first edge test power supply VAD2Eedge via respective test switches, so that the odd-numbered first bit lines BLao correspond to different test power supplies from the even-numbered first bit lines BLae.

[0078] In this way, the adjacent bit lines in the memory array slices at non-first and non-last positions are connected to different pre-charge power supplies, and the odd-numbered first bit lines BLao and the even-numbered first bit lines BLae in the memory array slices at the first and last positions are connected to different edge test power supplies, so that the bit line stress test BL stress can be conveniently implemented, and the product performance of the memory is ensured.

[0079] Based on the structure of Figure 7 , the memory 10 performs the process of BL stress on the memory array slices at non-first and non-last positions as follows:

[0080] First, the memory 10 is specifically configured to control the first edge test power supply VAD2Eedge to be a first voltage value, the second edge test power supply VAD2Oedge to be a second voltage value, the first pre-charge power supply VAD2O to be a third voltage value, and the second pre-charge power supply VAD2E to be a fourth voltage value, and to perform a bit line stress test operation; wherein the first voltage value and the second voltage value are different, and the third voltage value and the fourth voltage value are different. For example: the first voltage value is high and the second voltage value is low, or vice versa; the third voltage value is high and the fourth voltage value is low, or vice versa.

[0081] At the same time, in the bit line stress test operation, all the first test switches 13 are in a closed state, the isolation switches and the skew cancellation switches between the memory array slices at the first and last positions and the adjacent sense amplification modules are in an off state, and the remaining isolation switches, the remaining skew cancellation switches, and all the pre-charge switches are in a closed state.

[0082] It is assumed that the first voltage value = the third voltage value = high, the second voltage value = the fourth voltage value = low, and the memory structure shown in Figure 7 is taken as an example for specific description:

[0083] In this way, on the one hand, the isolation switches and the cancellation switches between the storage array slices at non-first and non-last positions and the adjacent read amplification modules are in the closed state, so the bit lines therein are in electrical communication with the respective pre-charge sources via the corresponding sense amplifiers; specifically:

[0084] (1) In the storage array slices at non-first and non-last positions and odd numbers (for example, the storage array slices 11_3, 11_5, …, 11_63), the first bit lines BLa are all at low levels (pre-charged by VAD2E), and the second bit lines BLb are all at high levels (pre-charged by VAD2O);

[0085] (2) In the storage array slices at non-first and non-last positions and even numbers (for example, the storage array slices 11_2, 11_4, …, 11_64), the first bit lines BLa are all at high levels (pre-charged by VAD2O), and the second bit lines BLb are all at low levels (pre-charged by VAD2E);

[0086] On the other hand, since the isolation switches and the cancellation switches between the storage array slices at the first and last positions and the adjacent read amplification modules are in the closed state, the first bit lines BLa of the storage array slices at the first and last positions are not in electrical communication with the corresponding pre-charge sources; however, since all the first test switches 13 are open, the first bit lines BLa of the storage array slices at the first and last positions are in electrical communication with the corresponding test sources; specifically:

[0087] (3) For the storage array slices 11_1 and 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are all at high levels (pre-charged by VAD2Eedge), and the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are all at low levels (pre-charged by VAD2OEdge).

[0088] In this way, by controlling the voltage values of the respective power sources and the working states of the corresponding switches, the adjacent bit lines in all the storage array slices can be made to be at different levels, thereby facilitating the execution of the bit line stress test.

[0089] In some embodiments, the memory 10 is further configured to control the first edge test source VAD2Eedge to be at a second voltage value, the second edge test source VAD2Oedge to be at a first voltage value, the first pre-charge source VAD2O to be at a fourth voltage value, and the second pre-charge source VAD2E to be at a third voltage value, and to perform the bit line stress test operation.

[0090] Suppose that the first voltage value = the third voltage value = high level, the second voltage value = the fourth voltage value = low level, and the memory structure shown in FIG. 1 is taken as an example for specific description: Figure 7

[0091] ​(4) In the non-first and non-last and odd-numbered memory array slices (e.g. memory array slices 11_3, 11_5, …, 11_63), the first bit lines BLa are all high (pre-charged by VAD2E), and the second bit lines BLb are all low (pre-charged by VAD2O);

[0092] (5) In the non-first and non-last and even-numbered memory array slices (e.g. memory array slices 11_2, 11_4, …, 11_64), the first bit lines BLa are all low (pre-charged by VAD2O), and the second bit lines BLb are all high (pre-charged by VAD2E).

[0093] (6) In the memory array slices 11_1, 11_65, the odd-numbered first bit lines BLa and their electrically connected second bit lines BLb are all low (pre-charged by VAD2Eedge), and the even-numbered first bit lines BLa and their electrically connected second bit lines BLb are all high (pre-charged by VAD2OEdge).

[0094] In this way, by managing the pre-charge power in two groups and additionally providing a separate test power for the bit lines in the first and last memory array slices, the bit line stress test can be efficiently implemented.

[0095] To implement the above-mentioned test method, please refer to Figure 6 The gate of the first de-bias switch 31 and the gate of the second de-bias switch 33 are connected to different control signals OcEnb and OcEna respectively, and the gate of the first isolation switch 32 and the gate of the second isolation switch 34 are connected to different control signals Isob and Isoa respectively.

[0096] In combination with Figure 6 and Figure 7 It can be seen that the readout amplification module 12_1 is connected to the memory array slice 11_1 through the first de-bias switch 31 and the first isolation switch 32, but the readout amplification module 12_64 is connected to the memory array slice 11_65 through the second de-bias switch 33 and the second isolation switch 34. In order to more conveniently implement the above-mentioned test method, in a specific embodiment, by changing some definitions (e.g. changing the definitions of the first bit lines BLa and the second bit lines BLb in the last memory array slice and the second-to-last memory array slice, or changing the definitions of the de-bias switch and the isolation switch in the readout amplification module 12_64, etc.), so that the readout amplification module 12_64 is also connected to the memory array slice 11_65 through the first de-bias switch 31 and the first isolation switch 32.

[0097] In other words, the bit lines in the first and last memory array chips are connected to the adjacent sensitive amplifier modules via the first debias switch 31 or the first isolation switch 32. Therefore, by simply turning off the first debias switch 31 and the first isolation switch 32 corresponding to the readout amplifier module 12_1 and the readout amplifier module 12_64, the first and last memory array chips can be electrically isolated from the adjacent sensitive amplifier Sa. At this point, please refer to... Figure 7 The memory 10 also includes a command control circuit. Figure 8 (Not shown), first preprocessing circuit 50 and second preprocessing circuit 60. Specifically,

[0098] The command control circuit is configured to generate a test enable signal, an initial isolation signal IsoPre, and an initial debiasing signal OcPre; wherein, when the memory 10 is instructed to perform a bit line pressure test operation, the test enable signal, the initial isolation signal IsoPre, and the initial debiasing signal OcPre are all in an active state.

[0099] The first preprocessing circuit 50 is configured to generate a first edge isolation signal IsobEdge and a second edge isolation signal IsoaEdge based on the edge test parameter group TmEdge<1:0> and the initial isolation signal IsoPre; and to generate a first edge depolarization signal OcEnbEdge and a second edge depolarization signal OcEnaEdge based on the edge test parameter group TmEdge<1:0> and the initial depolarization signal OcPre.

[0100] The second preprocessing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre; and to generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter group TmInter<1:0> and the initial depolarization signal OcPre.

[0101] Among them, the test enable signal is used to control all the first test switches 13; at the same time, (1) the first edge isolation signal IsobEdge is used to control the first isolation switch 32 between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions; (2) the second edge isolation signal IsoaEdge is used to control the second isolation switch 34 between the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions; (3) the first edge debiasing signal OcEnbEdge is used to control the first debiasing switch 31 between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions; (4) the second edge debiasing signal OcEnaEdge is used to control the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions. (5) The first internal isolation signal IsobInter is used to control the first isolation switch 32 between the read amplification module at the non-first and last position and the adjacent memory array chip; (6) The second internal isolation signal IsoaInter is used to control the second isolation switch 34 between the read amplification module at the non-first and last position and the adjacent memory array chip; (7) The first internal debiasing signal OcEnbInter is used to control the first debiasing switch 31 between the read amplification module at the non-first and last position and the adjacent memory array chip; (8) The second internal debiasing signal OcEnaInter is used to control the second debiasing switch 33 between the read amplification module at the non-first and last position and the adjacent memory array chip.

[0102] In this way, the bit lines in the memory array are divided into two categories. During the bit line stress test, the first pre-charge power supply VAD2O and the second pre-charge power supply VAD2E are used to charge the two consecutive numbered first bit lines BLa and the second bit line BLb in the memory array slices that are not at the beginning or end. The first edge test power supply VAD2Eedge and the second edge test power supply VAD2Oedge are used to charge the two adjacent numbered first bit lines BLa (and their respective electrically connected second bit lines BLb) in the memory array slices at the beginning and end. This allows the adjacent bit lines of the entire memory array slice to be in different voltage states, which can efficiently complete the bit line stress test, save energy, and avoid the problems of bit line overcharging and excessive pressure.

[0103] In one specific embodiment, such as Figure 8 As shown, the edge test parameter set includes at least the first test parameter TmEdge. <0> The second test parameter, TmEdge <1> The internal test parameter set includes at least the third test parameter TmInter. <0> and the fourth test parameter TmInter <1> .

[0104] If the second test parameter TmEdge<1> is in the first state, the first edge isolation signal IsobEdge and the first edge cancellation signal OcEnbEdge are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the second test parameter TmEdge<1> is in the second state, the first edge isolation signal IsobEdge and the first edge cancellation signal OcEnbEdge are both invalid.

[0105] If the first test parameter TmEdge<0> is in the first state, the second edge isolation signal IsoaEdge and the second edge cancellation signal OcEnaEdge are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the first test parameter TmEdge<0> is in the second state, the second edge isolation signal IsoaEdge and the second edge cancellation signal OcEnaEdge are both invalid.

[0106] If the fourth test parameter TmInter<1> is in the first state, the first internal isolation signal IsobInter and the first internal cancellation signal OcEnbInter are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the fourth test parameter TmInter<1> is in the second state, the first internal isolation signal IsobInter and the first internal cancellation signal OcEnbInter are both invalid.

[0107] If the third test parameter TmInter<0> is in the first state, the second internal isolation signal IsoaInter and the second internal cancellation signal OcEnaInter are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the third test parameter TmInter<0> is in the second state, the second internal isolation signal IsoaInter and the second internal cancellation signal OcEnaInter are both invalid.

[0108] During the process in which the memory is instructed to perform the bit line stress test operation, the second test parameter TmEdge<1> is in the second state, and the first test parameter TmEdge<0>, the third test parameter TmInter<0> and the fourth test parameter TmInter<1> are all in the first state.

[0109] It should be noted that, for the above isolation signals, cancellation signals and pre-charge signals, when they are invalid, the corresponding switches are in the off state; when they are valid, the corresponding switches are in the on state.

[0110] A specific working scenario is provided: the first isolation switch 32, the second isolation switch 34, the first cancellation switch 31 and the second cancellation switch 33 are all N-type field effect tubes, and the effective state is high level state, and the invalid state is low level state.

[0111] Then, during the bit line stress test operation, TmEdge<1:0>=01, TmInter<1:0>=11, thus, the first edge isolation signal IsobEdge=0, the first edge cancellation signal OcEnbEdge=0, the second edge isolation signal IsoaEdge=1, and the second edge cancellation signal OcEnaEdge=1, so that the readout amplification module 12_1 is electrically isolated from the storage array chip 11_1, the readout amplification module 12_64 is electrically isolated from the storage array chip 11_65, i.e., the bit lines in the storage array chips at the head and tail positions are electrically isolated from the corresponding pre-charge power supply; however, the readout amplification module 12_1 is in electrical communication with the storage array chip 11_2, the readout amplification module 12_64 is in electrical communication with the storage array chip 11_64, and the readout amplification modules 12_2-12_63 are each in electrical communication with the storage array chips on both sides, so that the bit lines in the storage array chips at the non-head and non-tail positions are in electrical communication with the corresponding pre-charge power supply.

[0112] In the above scenario, please refer to Figure 8 , the first pre-processing circuit 50 comprises:

[0113] a first AND gate 501, which receives the first test parameter TmEdge<0> and the initial isolation signal IsoPre at two input ends respectively, and outputs the second edge isolation signal IsoaEdge at an output end;

[0114] a second AND gate 502, which receives the second test parameter TmEdge<1> and the initial isolation signal IsoPre at two input ends respectively, and outputs the first edge isolation signal IsobEdge at an output end;

[0115] a third AND gate 503, which receives the first test parameter TmEdge<0> and the initial cancellation signal OcPre at two input ends respectively, and outputs the second edge cancellation signal OcEnaEdge at an output end;

[0116] a fourth AND gate 504, which receives the second test parameter TmEdge<1> and the initial cancellation signal OcPre at two input ends respectively, and outputs the first edge cancellation signal OcEnbEdge at an output end;

[0117] the second pre-processing circuit 60 comprises:

[0118] The fifth AND gate 601 receives the third test parameter TmInter at its two inputs. <0> And the initial isolation signal IsoPre, its output terminal outputs the second internal isolation signal IsoaInter;

[0119] The sixth AND gate 602 receives the fourth test parameter TmInter at its two inputs. <1> And the initial isolation signal IsoPre, its output terminal outputs the first internal isolation signal IsobInter;

[0120] The seventh AND gate 603 receives the third test parameter TmInter at its two inputs. <0> And the initial debiasing signal OcPre, its output terminal outputs the second internal debiasing signal OcEnaInter;

[0121] The eighth AND gate 604 receives the fourth test parameter TmInter at its two inputs. <1> The initial debiasing signal OcPre is used, and its output terminal outputs the first internal debiasing signal OcEnbInter.

[0122] In another specific embodiment, please refer to Figure 6 and Figure 7 The readout amplification module 12_1 is connected to the storage array chip 11_1 through the first debias switch 31 and the first isolation switch 32, but the readout amplification module 12_64 is connected to the storage array chip 11_65 through the second debias switch 33 and the second isolation switch 34.

[0123] In other words, the bit lines in the first memory array chip 11_1 are electrically connected to the adjacent sensitive amplification module through a first debias switch or a first isolation switch, and the bit lines in the last memory array chip 11_65 are electrically connected to the sensitive amplification modules at the beginning and end through a second debias switch or a second isolation switch. Please refer to [link to relevant documentation]. Figure 9 The memory 10 also includes a command control circuit, a second preprocessing circuit 50, a third preprocessing circuit 70, and a fourth preprocessing circuit 80.

[0124] Command control circuit ( Figure 9 (Not shown), configured to generate a test enable signal, an initial isolation signal IsoPre, and an initial debiasing signal OcPre; wherein, when the memory is instructed to perform a stress test operation, the test enable signal, the initial isolation signal IsoPre, and the initial debiasing signal OcPre are all in an active state;

[0125] The second preprocessing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre, and generate a first internal cancellation signal OcEnbInter and a second internal cancellation signal OcEnaInter based on the internal test parameter group and the initial cancellation signal OcPre;

[0126] The third preprocessing circuit 70 is configured to generate a first edge isolation signal IsobEdge0 and a second edge isolation signal IsoaEdge0 based on the edge test parameter group TmEdge0<1:0> and the initial isolation signal IsoPre, and generate a first edge cancellation signal OcEnbEdge0 and a second edge cancellation signal OcEnaEdge0 based on the edge test parameter group and the initial cancellation signal OcPre;

[0127] The fourth preprocessing circuit 80 is configured to generate a first tail isolation signal IsobEdge1 and a second tail isolation signal IsoaEdge1 based on the tail test parameter group TmEdge1<1:0> and the initial isolation signal IsoPre, and generate a first tail cancellation signal OcEnbEdge1 and a second tail cancellation signal OcEnaEdge1 based on the tail test parameter group and the initial cancellation signal OcPre.

[0128] All the test switches 13 are controlled by a test enable signal, and the first isolation switch, the second isolation switch, the first cancellation switch and the second cancellation switch between the first readout amplification module 11_1 and the adjacent memory array chip are controlled by the first edge isolation signal IsobEdge0, the second edge isolation signal IsoaEdge0, the first edge cancellation signal OcEnbEdge0 and the second edge cancellation signal OcEnaEdge0 respectively; the first isolation switch 31, the second isolation switch 33, the first cancellation switch 32 and the second cancellation switch 34 between the last readout amplification module 11_65 and the adjacent memory array chip are controlled by the first tail isolation signal IsobEdge1, the second tail isolation signal IsoaEdge1, the first tail cancellation signal OcEnbEdge1 and the second tail cancellation signal respectively; the first isolation switch 31, the second isolation switch 33, the first cancellation switch 32 and the second cancellation switch 34 between the readout amplification module (11_2, 11_3……11_64) and the adjacent memory array chip are controlled by the first internal isolation signal IsobInter, the second internal isolation signal IsoaInter, the first internal cancellation signal OcEnbInter and the second internal cancellation signal OcEnaInter respectively.

[0129] In some embodiments, the internal test parameter group at least includes a third test parameter TmInter<0> and a fourth test parameter TmInter<1>; the head-end test parameter group includes a fifth test parameter TmEdge0<0> and a sixth test parameter TmEdge0<1>, and the tail-end test parameter group includes a seventh test parameter TmEdge1<0> and an eighth test parameter TmEdge1<1>;

[0130] If the third test parameter TmInter<0> is in the first state, the second internal isolation signal IsoaInter and the second internal cancellation signal OcEnaInter are one-to-one corresponding to the same level as the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the third test parameter TmInter<0> is in the second state, the second internal isolation signal IsoaInter and the second internal cancellation signal OcEnaInter are both invalid.

[0131] If the fourth test parameter TmInter<1> is in the first state, the first internal isolation signal IsobInter and the first internal cancellation signal OcEnbInter are one-to-one corresponding to the same level as the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the fourth test parameter TmInter<1> is in the second state, the first internal isolation signal IsobInter and the first internal cancellation signal OcEnbInter are both invalid.

[0132] If the fifth test parameter TmEdge0<0> is in the first state, the second head-end isolation signal IsoaEdge0 and the second head-end cancellation signal OcEnaEdge0 are one-to-one corresponding to the same level as the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the fifth test parameter TmEdge0<0> is in the second state, the second head-end isolation signal IsoaEdge0 and the second head-end cancellation signal OcEnaEdge0 are both invalid.

[0133] If the sixth test parameter TmEdge0<1> is in the first state, the first head-end isolation signal IsobEdge0 and the first head-end cancellation signal OcEnbEdge0 are one-to-one corresponding to the same level as the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the sixth test parameter TmEdge0<1> is in the second state, the first head-end isolation signal IsobEdge0 and the first head-end cancellation signal OcEnbEdge0 are both invalid.

[0134] If the seventh test parameter TmEdge1<0> is in the first state, the second tail-end isolation signal IsoaEdge1 and the second tail-end cancellation signal OcEnaEdge1 are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the seventh test parameter TmEdge1<0> is in the second state, the second tail-end isolation signal IsoaEdge1 and the second tail-end cancellation signal OcEnaEdge1 are both invalid.

[0135] If the eighth test parameter TmEdge1<1> is in the first state, the first tail-end isolation signal IsobEdge1 and the first tail-end cancellation signal OcEnbEdge1 are respectively the same as the level of the initial isolation signal IsoPre and the initial cancellation signal OcPre; if the eighth test parameter TmEdge1<1> is in the second state, the first tail-end isolation signal IsobEdge1 and the first tail-end cancellation signal OcEnbEdge1 are both invalid.

[0136] Wherein, in the process that the memory is instructed to perform the bit line stress test operation, the sixth test parameter TmEdge0<1> and the seventh test parameter TmEdge1<0> are in the second state, and the third test parameter TmInter<0>, the fourth test parameter TmInter<1>, the fifth test parameter TmEdge0<0> and the eighth test parameter TmEdge1<1> are all in the first state.

[0137] Specifically, in the execution process of the bit line stress test operation, TmEdge0<1:0>=01, TmInter<1:0>=11, TmEdge1<1:0>=10, therefore, the readout amplification module 12_1 is electrically isolated from the storage array chip 11_1, and the readout amplification module 12_64 is electrically isolated from the storage array chip 11_65, but the readout amplification module 12_1 is electrically connected with the storage array chip 11_2, and the readout amplification module 12_64 is electrically connected with the storage array chip 11_64; the readout amplification module 12_2 to the readout amplification module 12_63 are respectively electrically connected with the storage array chips on both sides; thus, the bit lines in the storage array chips at non-first and non-last positions can be pre-charged by the pre-charging source, but the bit lines in the storage array chips at the first and last positions cannot be pre-charged by the pre-charging source, but are charged by the edge test power supply.

[0138] In the above scenario, the structure of the second preprocessing circuit 60 is also as shown in Figure 8 , and will not be described again

[0139] Please refer to Figure 9 , the third preprocessing circuit 70 comprises:

[0140] a ninth AND gate 701, whose two input terminals respectively receive the fifth test parameter TmEdge0<0> and the initial isolation signal IsoPre, and whose output terminal outputs a second head-end isolation signal IsoaEdge0;

[0141] a tenth AND gate 702, whose two input terminals respectively receive the sixth test parameter TmEdge0<1> and the initial isolation signal IsoPre, and whose output terminal outputs a first head-end isolation signal IsobEdge0;

[0142] an eleventh AND gate 703, whose two input terminals respectively receive the fifth test parameter TmEdge0<0> and the initial cancellation signal OcPre, and whose output terminal outputs a second head-end cancellation signal OcEnaEdge0;

[0143] a twelfth AND gate 704, whose two input terminals respectively receive the sixth test parameter TmEdge0<1> and the initial cancellation signal OcPre, and whose output terminal outputs a first head-end cancellation signal OcEnbEdge0;

[0144] In this scenario, please refer to Figure 8 , the fourth pre-processing circuit 80 comprises:

[0145] a thirteenth AND gate 801, whose two input terminals respectively receive the seventh test parameter TmEdge1<0> and the initial isolation signal IsoPre, and whose output terminal outputs a second tail-end isolation signal IsoaEdge1;

[0146] a fourteenth AND gate 802, whose two input terminals respectively receive the eighth test parameter TmEdge1<1> and the initial isolation signal IsoPre, and whose output terminal outputs a first tail-end isolation signal IsobEdge1;

[0147] a fifteenth AND gate 803, whose two input terminals respectively receive the seventh test parameter TmEdge1<0> and the initial cancellation signal OcPre, and whose output terminal outputs a second tail-end cancellation signal OcEnaEdge1;

[0148] a sixteenth AND gate 804, whose two input terminals respectively receive the eighth test parameter TmEdge1<1> and the initial cancellation signal OcPre, and whose output terminal outputs a first tail-end cancellation signal OcEnbEdge1.

[0149] In summary, the embodiments of the present disclosure provide a memory, which reduces the area of the storage array chip located at the edge to half of the area of other storage array chips; meanwhile, the pre-charge power supply is divided into two groups for management, and a separate edge test power supply is additionally provided for the bit lines in the storage array chips at the head and tail positions, which can efficiently implement bit line pressure testing, perfect the testing process of the memory of this structure, and ensure the performance after leaving the factory.

[0150] In a second specific embodiment, for the non-first-and-last-position memory array tiles (11_2, 11_3,..., 11_64), the bit lines therein are coupled to the respective pre-charge sources through the column-gating switches and the second test switches; for the first-and-last-position memory array tiles (11_1, 11_65), the first bit lines therein are coupled to the respective pre-charge sources through the column-gating switches and the second test switches. That is, only when both the column-gating switch and the second test switch are on, the first bit line is electrically connected to its pre-charge source. For each memory array tile, the pre-charge source coupled to each bit line serves as the stress test source.

[0151] The following is a detailed description.

[0152] Please refer to Figure 10 , the memory 10 includes two groups of pre-charge sources, i.e., the first pre-charge source VAD20 and the second pre-charge source VAD2E.

[0153] Meanwhile, in one possibility, for all the memory array tiles, each bit line is coupled to the first pre-charge source VAD20 through the respective pre-charge switch 35, but one type of bit lines is connected to the first pre-charge source VAD20 through the column-gating switch + the second test switch, and another type of bit lines is connected to the second pre-charge source VAD2E through the column-gating switch + the second test switch, so that, in the process of stress test, the pre-charge switch 35 is open, and the column-gating switch + the second test switch are both closed, so that (in the internal array tiles) two adjacent bit lines (or two first bit lines with consecutive numbers in the first-and-last-position array tiles) are pre-charged by the first pre-charge source VAD20 and the second pre-charge source VAD2E respectively; in the process of normal operation, the pre-charge switch 35 is closed, and the second test switch is open, so that all the bit lines are pre-charged by the first pre-charge source VAD20, thereby realizing the normal pre-charge function.

[0154] Similarly, in another possibility, for all the memory array tiles, each bit line is coupled to the second pre-charge source VAD2E through the respective pre-charge switch 35; or, in yet another possibility, part of the bit lines are coupled to the first pre-charge source VAD20 through the respective pre-charge switch 35, and the rest of the bit lines are coupled to the second pre-charge source VAD2E through the respective pre-charge switch 35, such as the case described in the above embodiment.

[0155] Please refer to Figure 6 and Figure 10, each bit line is coupled to the corresponding pre-charge source through the pre-charge switch 35, and is coupled to the pre-charge source through the column gate switch 38+the second test switch 14; meanwhile, during the stress test, the pre-charge switch 35 is turned off, and the column gate switch 38+the second test switch 14 are both closed, at this time, the first pre-charge source VAD20 and the second pre-charge source VAD2E can be used as the stress test power TXo and TXe respectively.

[0156] Specifically, for the storage array slices (11_2, 11_3…11_64) other than the first and last positions, the bit lines therein are coupled to the corresponding local data lines (IO / ION) through the corresponding column gate switches 38; wherein: (1) for the second bit lines BLb in the odd-numbered storage array slices (11_3, 11_5…11_63) other than the first and last positions and the first bit lines BLa in the even-numbered storage array slices (11_2, 11_4…11_64), the coupled local data lines are further connected to the first pre-charge source VAD20 through the corresponding second test switches 14; (2) for the first bit lines BLa in the odd-numbered storage array slices (11_3, 11_5…11_63) other than the first and last positions and the second bit lines BLb in the even-numbered storage array slices (11_2, 11_4…11_65), the coupled local data lines are further connected to the second pre-charge source VAD2E through the corresponding second test switches 14.

[0157] Meanwhile, for the first and last storage array slices (11_1, 11_65), the first bit lines therein are coupled to the corresponding local data lines through the corresponding column gate switches.

[0158] In one case, referring to Figure 10 (1) for the first and last storage array slices (11_1, 11_65), the coupled local data lines of the odd-numbered first bit lines BLao are coupled to the second pre-charge source VAD2E through the second test switches 14, and the coupled local data lines of the even-numbered second bit lines BLae are coupled to the first pre-charge source VAD20 through the second test switches 14.

[0159] In another case, for the first storage array slice 11_1, the coupled local data lines of the odd-numbered first bit lines BLao are coupled to the second pre-charge source VAD2E through the second test switches 14, and the coupled local data lines of the even-numbered first bit lines BLae are coupled to the first pre-charge source VAD20 through the second test switches 14; and for the last storage array slice 11_65, the coupled local data lines of the odd-numbered first bit lines BLao are coupled to the first pre-charge source VAD20 through the second test switches 14, and the coupled local data lines of the even-numbered first bit lines BLae are coupled to the second pre-charge source VAD2E through the second test switches 14.

[0160] In brief, for the storage array tiles at the head and tail positions, the pre-charge source to which the first bit line is connected via the pre-charge switch 35 and the pre-charge source to which the first bit line is connected via the column gating switch 38+the second test switch 14 can not be the same. Assume that in one case, all the first bit lines BLa in the storage array tile 11_1 are connected to the first pre-charge source VAD20 via the pre-charge switch 35, but the Blas in the storage array tile 11_1 are coupled to the second pre-charge source VAD2E via the column gating switch 38+the second test switch 14, and the Blae are coupled to the first pre-charge source VAD20 via the column gating switch 38+the second test switch 14, which is only one possible case. Meanwhile, during the bit line stress test, all the bit lines are connected to the corresponding pre-charge source via the column gating switch 38+the second test switch 14, but the pre-charge switch is closed; during the normal pre-charge operation, all the bit lines are connected to the corresponding pre-charge source via the pre-charge switch, but the column gating switch 38+the second test switch 14 is closed.

[0161] Based on the structure of Figure 10 , the memory 10 performs the BL stress test on the storage array tiles at the non-head and non-tail positions as follows:

[0162] The memory 10 is configured to control all the isolation switches, the de-skewing switches and the pre-charge switches to be in the off state, control all the column gating switches and the second test switches to be in the closed state, and control the first pre-charge source to be the first voltage value and the second pre-charge source to be the second voltage value, so as to perform a bit line stress test.

[0163] In this way, during the bit line stress test, all the bit lines are connected to the corresponding pre-charge source via the column gating switch 38+the second test switch 14. Assume that the first voltage value = the third voltage value = high level (for example, 1.55V), and the second voltage value = the fourth voltage value = low level (for example, 0V), please refer to Figure 10 , in particular:

[0164] (1) In the storage array tiles at the non-head and non-tail positions and with odd numbers (for example, the storage array tiles 11_3, 11_5, …, 11_63), the first bit lines BLa are all low level (pre-charged by VAD2E), and the second bit lines BLb are all high level (pre-charged by VAD20);

[0165] (2) In the storage array tiles at the non-head and non-tail positions and with even numbers (for example, the storage array tiles 11_2, 11_4, …, 11_64), the first bit lines BLa are all high level (pre-charged by VAD20), and the second bit lines BLb are all low level (pre-charged by VAD2E);

[0166] (3) For the storage array chips 11_1, 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are all at low level (pre-charged by VAD2E); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are all at high level (pre-charged by VAD2O).

[0167] In addition, the memory 10 is further configured to control all the isolation switches, the bias cancellation switches and the pre-charge switches to be in the off state, control all the column gating switches and the second test switches to be in the closed state, and control the first pre-charge power supply to be at the second voltage value and the second pre-charge power supply to be at the first voltage value, so as to perform another bit line stress test.

[0168] It is assumed that the first voltage value = the third voltage value = high level, and the second voltage value = the fourth voltage value = low level. Please refer to Figure 10 , in particular:

[0169] (4) In the odd-numbered storage array chips (for example, the storage array chips 11_3, 11_5, …, 11_63) at non-first and non-last positions, the first bit lines BLa are all at high level (pre-charged by VAD2E), and the second bit lines BLb are all at low level (pre-charged by VAD2O);

[0170] (5) In the even-numbered storage array chips (for example, the storage array chips 11_2, 11_4, …, 11_64) at non-first and non-last positions, the first bit lines BLa are all at low level (pre-charged by VAD2O), and the second bit lines BLb are all at high level (pre-charged by VAD2E);

[0171] (6) For the storage array chips 11_1, 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are all at high level (pre-charged by VAD2E); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are all at low level (pre-charged by VAD2O).

[0172] The embodiments of the present disclosure provide a memory, and each bit line is further connected to a pre-charge power supply through a column gating switch and a second test switch to serve as a stress test power supply. On the one hand, the bit line stress test can be efficiently implemented, the test process of the memory with the structure is perfected, and the performance after leaving the factory is ensured. On the other hand, 2 groups of separate edge test power supplies do not need to be arranged for the storage array chips at the first and last positions, and the circuit area is reduced.

[0173] In a third specific embodiment, for the non-edge memory array tiles (11_2, 11_3,..., 11_64), the bit lines therein are coupled to respective local data lines (IO / ION) via respective column gate switches 38; (1) for the second bit lines BLb in the odd-numbered non-edge memory array tiles (11_3, 11_5,..., 11_63) and the first bit lines BLa in the even-numbered non-edge memory array tiles (11_2, 11_4,..., 11_64), the local data lines coupled thereto are coupled to the first preset test power source Vintlp20 via the second test switch 14; (2) for the first bit lines BLa in the odd-numbered non-edge memory array tiles (11_3, 11_5,..., 11_63) and the second bit lines BLb in the even-numbered non-edge memory array tiles (11_2, 11_4,..., 11_65), the local data lines coupled thereto are coupled to the second preset test power source Vintlp2e via the second test switch 14.

[0174] That is, the memory 10 is provided with two sets of preset test power sources, i.e., the first preset test power source Vintlp20 and the second preset test power source Vintlp2e, which are used as the stress test power sources TXo and TXe respectively, in addition to the pre-charge power source.

[0175] The following is a specific description.

[0176] Please refer to Figure 6 and Figure 11 , for the non-edge memory array tiles (11_2, 11_3,..., 11_64), the bit lines therein are coupled to respective local data lines (IO / ION) via respective column gate switches 38; (1) for the second bit lines BLb in the odd-numbered non-edge memory array tiles (11_3, 11_5,..., 11_63) and the first bit lines BLa in the even-numbered non-edge memory array tiles (11_2, 11_4,..., 11_64), the local data lines coupled thereto are coupled to the first preset test power source Vintlp20 via the second test switch 14; (2) for the first bit lines BLa in the odd-numbered non-edge memory array tiles (11_3, 11_5,..., 11_63) and the second bit lines BLb in the even-numbered non-edge memory array tiles (11_2, 11_4,..., 11_65), the local data lines coupled thereto are coupled to the second preset test power source Vintlp2e via the second test switch 14.

[0177] Meanwhile, for the edge memory array tiles (11_1, 11_65), the first bit lines therein are coupled to respective local data lines via respective column gate switches; wherein:

[0178] In one case, please refer to Figure 11 , (1) for the edge memory array tiles (11_1, 11_65), the odd-numbered first bit lines BLao are coupled to the local data lines coupled to the second preset test power source Vintlp2e via the second test switch 14, and the even-numbered second bit lines BLae are coupled to the local data lines coupled to the first preset test power source Vintlp20 via the second test switch 14.

[0179] In another case, for the first memory array tile 11_1, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the second preset test power source Vintlp2e via the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the first preset test power source Vintlp2o via the second test switch 14; and for the last memory array tile 11_65, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the first preset test power source Vintlp2o via the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the second preset test power source Vintlp2e via the second test switch 14.

[0180] For example, the first preset test power source can be the pre-charge power source of the local data line IO, and the second preset test power source can be the pre-charge power source of the local data line ION, without adding an additional independent power source, thereby saving circuit area.

[0181] Based on the structure of Figure 11 , the memory 10 performs the BL stress process on the memory array tiles at non-first and non-last positions as follows:

[0182] The memory 10 is configured to control all the isolation switches and the offset cancellation switches to be in the off state, control all the pre-charge switches to be in the closed state, and control the pre-charge power source VAD to be a fifth voltage value; control all the column selection switches and the second test switches to be in the closed state, and control the first preset test power source to be a first voltage value and the second preset test power source to be a second voltage value, so as to perform a bit line stress test.

[0183] It should be noted that the fifth voltage value is between the first voltage value and the second voltage value. In this way, the first voltage value can be a high level (for example, 1.55V), the second voltage value can be a low level (for example, 0V), and the fifth voltage value can be 0.5V, so that in the process of the bit line stress test, the pull-up unit NCS and the pull-down unit PCS are pre-charged to 0.5V by the pre-charge power source VAD via the pre-charge switch 38, so that the sense amplifier SA is not excessively stressed.

[0184] Under the above voltage conditions, as shown in Figure 11 ,

[0185] (1) In the memory array tiles at non-first and non-last positions and odd-numbered (for example, the memory array tiles 11_3, 11_5, …, 11_63), the first bit lines BLa are all low (pre-charged by Vintlp2e), and the second bit lines BLb are all high (pre-charged by Vintlp2o);

[0186] (2) For the non-first and non-last position and even-numbered storage array pieces (for example, storage array pieces 11_2, 11_4, …, 11_64), the first bit line BLa is all high (pre-charged by Vintlp20), and the second bit line BLb is all low (pre-charged by Vintlp2e);

[0187] (3) For the storage array pieces 11_1 and 11_65, the odd-numbered first bit line BLao and the second bit line BLbo electrically connected thereto are all low (pre-charged by Vintlp2e); and the even-numbered first bit line BLa and the second bit line BLb electrically connected thereto are all high (pre-charged by Vintlp20).

[0188] In addition, the memory 10 is further configured to control all the isolation switches and the bias cancellation switches to be in an off state, control all the pre-charging switches to be in a closed state, and control the pre-charging power supply to be a fifth voltage value; control all the column selection switches and the second test switches to be in a closed state, and control the first preset test power supply to be a second voltage value and the second preset test power supply to be a first voltage value, so as to perform another bit line stress test.

[0189] It is assumed that the first voltage value = the third voltage value = high, the second voltage value = the fourth voltage value = low, and the fifth voltage value = 0.5V. Please refer to Figure 11 , in particular:

[0190] (4) For the non-first and non-last position and odd-numbered storage array pieces (for example, storage array pieces 11_3, 11_5, …, 11_63), the first bit line BLa is all high (pre-charged by Vintlp2e), and the second bit line BLb is all low (pre-charged by Vintlp20).

[0191] (5) For the non-first and non-last position and even-numbered storage array pieces (for example, storage array pieces 11_2, 11_4, …, 11_64), the first bit line BLa is all low (pre-charged by Vintlp20), and the second bit line BLb is all high (pre-charged by Vintlp2e).

[0192] (6) For the storage array pieces 11_1 and 11_65, the odd-numbered first bit line BLao and the second bit line BLbo electrically connected thereto are all high (pre-charged by Vintlp2e); and the even-numbered first bit line BLa and the second bit line BLb electrically connected thereto are all low (pre-charged by Vintlp20).

[0193] Briefly speaking, in the process of the bit line stress test, all the bit lines are connected with the corresponding preset test power supply through the column gate switch 38 + the second test switch 14, and the pre-charge switch is open, so that the pull-up module PCS and the pull-down module NCS are about 0.5V, avoiding the sensitive amplifier SA from being over-stressed; in the conventional pre-charge operation, all the bit lines are connected with the corresponding pre-charge power supply through the pre-charge switch, but the column gate switch 38 + the second test switch 14 is closed.

[0194] The embodiment of the present disclosure provides a memory, which reduces the area of the storage array chip at the edge to half of the area of other storage array chips, provides two groups of preset test power supplies in addition to the pre-charge power supply, can efficiently realize the bit line stress test, perfect the test process of the memory of the structure, and guarantee the performance after leaving the factory.

[0195] In another embodiment of the present disclosure, a test method is provided, which is applied to the aforementioned memory 10, the memory 10 includes N storage array chips arranged in sequence along a first direction, the storage array chip includes a plurality of first bit lines and a plurality of second bit lines, and the first bit line and the second bit line are alternately arranged along a second direction; for the storage array chip at a non-first or non-last position, the first bit line and the adjacent second bit line are electrically isolated; for the storage array chip at a first or last position, the first bit line is electrically connected with the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side.

[0196] For convenience of description, the storage array chips are numbered along the first direction, for the odd-numbered storage array chip, the first bit line is the second bit line; for the even-numbered storage array chip, the first bit line is the first bit line; for each storage array chip, the first bit lines therein are sequentially numbered along the second direction, and the second bit lines therein are sequentially numbered along the second direction.

[0197] The method includes:

[0198] S901: in the process of performing the bit line stress test operation, for the storage array chip at a first or last position, each first bit line is charged by using the pressure test power supply corresponding to each first bit line; and for the storage array chip at a non-first or non-last position, each bit line is charged by using the pressure test power supply corresponding to each bit line; the above is performed simultaneously.

[0199] For the storage array chip at a first or last position, the pressure test power supply corresponding to the odd-numbered first bit line is different from the pressure test power supply corresponding to the even-numbered first bit line in voltage; for the storage array chip at a non-first or non-last position, the pressure test power supply corresponding to the first bit line is different from the pressure test power supply corresponding to the adjacent second bit line in voltage.

[0200] In summary, for the memory 10 described above, the embodiment of the present disclosure further provides a test method, through one step, all adjacent bit lines of the memory array chip are at different voltages, the bit line stress test can be efficiently realized, the test process of the memory with the structure is improved, and the performance when leaving the factory is ensured.

[0201] It should be noted that, in this document, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0202] The above-mentioned serial numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0203] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, comprising: The memory comprises N memory array slices arranged in sequence along a first direction, N being a natural number; each of the memory array slices comprises a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices other than the first and last ones, the first bit line and the adjacent second bit line are electrically isolated; for the first and last memory array slices, the first bit line is electrically connected with the second bit line adjacent to the first side, and the first bit line is electrically isolated from the second bit line adjacent to the second side; the first side and the second side are two opposite sides along the second direction; The memory array slices are numbered along the first direction; and in each of the memory array slices, the first bit lines are numbered along the second direction, and the second bit lines are numbered along the second direction; For the memory array slices other than the first and last ones, each of the bit lines is coupled to a corresponding stress test power supply, and the stress test power supply corresponding to the first bit line is different from the stress test power supply corresponding to the adjacent second bit line; For the first and last memory array slices, the first bit lines are coupled to corresponding stress test power supplies, and the stress test power supply corresponding to the odd-numbered first bit line is different from the stress test power supply corresponding to the even-numbered first bit line.

2. The memory of claim 1, wherein, The first bit line of the odd-numbered memory array slice is a second bit line, and the first bit line of the even-numbered memory array slice is a first bit line; A readout amplification module is distributed between every 2 memory array slices, and the readout amplification module comprises a plurality of sensitive amplifiers arranged in sequence along the second direction; a first end of the sensitive amplifier is connected with one of the second bit lines on the third side through a first un-biasing switch, and a second end of the sensitive amplifier is connected with one of the second bit lines on the third side through a first isolation switch; The second end of the sensitive amplifier is also connected with one of the first bit lines on the fourth side through a second un-biasing switch, and the first end of the sensitive amplifier is also connected with one of the first bit lines on the fourth side through a second isolation switch; the third side and the fourth side are two opposite sides along the first direction; The first end or the second end of each of the sensitive amplifiers is also connected to a pre-charging power supply through a corresponding pre-charging switch, so that each bit line is coupled to a pre-charging power supply.

3. The memory according to claim 2, wherein For the memory array slices other than the first and last ones, the pre-charging power supply coupled to the bit lines serves as the stress test power supply; For the first and last memory array slices, the first bit lines are also coupled to respective edge test power supplies through first test switches, and the edge test power supply coupled to the first bit line serves as the stress test power supply.

4. The memory according to claim 2, wherein For the memory array slices other than the first and last ones, the bit lines are also coupled to respective pre-charging power supplies through column gating switches and second test switches; For the first and last storage array slices, the first bit line is coupled to the respective pre-charge source through a column gate switch and a second test switch. For each of the storage array slices, the pre-charge source coupled to each bit line is used as the stress test source.

5. The memory of claim 2, wherein, For the non-first and non-last storage array slices, the bit line is coupled to the respective pre-charge source through a column gate switch and a second test switch. For the first and last storage array slices, the first bit line is coupled to the respective pre-charge source through a column gate switch and a second test switch. For each of the storage array slices, the pre-charge source coupled to each bit line is used as the stress test source.

6. The memory of claim 3, wherein, The sense amplifiers are numbered in a first direction; For the odd numbered sense amplifiers, the first end or the second end of the sense amplifier is connected to a first pre-charge source through a corresponding pre-charge switch; for the even numbered sense amplifiers, the first end or the second end of the sense amplifier is connected to a second pre-charge source through a corresponding pre-charge switch, so that the stress test source of the first bit line and the stress test source of the adjacent second bit line are different.

7. The memory of claim 6, wherein, For the first and last storage array slices, the odd numbered first bit line is connected to a first edge test source through a respective first test switch, and the even numbered first bit line is connected to a second edge test source through a respective first test switch. Alternatively, For the first storage array slice, the odd numbered first bit line is connected to a first edge test source through a respective first test switch, and the even numbered first bit line is connected to a second edge test source through a respective first test switch; for the last storage array slice, the odd numbered first bit line is connected to the second edge test source through a respective first test switch, and the even numbered first bit line is connected to the first edge test source through a respective first test switch.

8. The memory of claim 7, wherein, The memory is configured to control the first edge test source to be a first voltage value, the second edge test source to be a second voltage value, the first pre-charge source to be a third voltage value, the second pre-charge source to be a fourth voltage value, and perform a bit line stress test operation; and, control the first edge test source to be a second voltage value, the second edge test source to be a first voltage value, the first pre-charge source to be a fourth voltage value, the second pre-charge source to be a third voltage value, and perform the bit line stress test operation; wherein the first voltage value and the second voltage value are different, and the third voltage value and the fourth voltage value are different. In the bit line stress test operation, all first test switches are in a closed state, isolation switches between the storage array slices at the head and tail positions and adjacent readout amplification modules, and offset cancellation switches are in an off state, and the rest of the isolation switches, the rest of the offset cancellation switches, and all pre-charge switches are in a closed state.

9. The memory of claim 8, wherein, The bit lines in the storage array slices at the head and tail positions are electrically connected to adjacent sense amplification modules through the first offset cancellation switch or the first isolation switch; the memory further comprises: a command control circuit configured to generate a test enable signal, an initial isolation signal, and an initial offset cancellation signal; wherein when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal, and the initial offset cancellation signal are all in an active state; a first pre-processing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter group and the initial isolation signal, and generate a first edge offset cancellation signal and a second edge offset cancellation signal based on the edge test parameter group and the initial offset cancellation signal; a second pre-processing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal, and generate a first internal offset cancellation signal and a second internal offset cancellation signal based on the internal test parameter group and the initial offset cancellation signal; wherein all first test switches are controlled by the test enable signal, the first isolation switches, the second isolation switches, the first offset cancellation switches, and the second offset cancellation switches between the readout amplification modules at the head and tail positions and adjacent storage array slices are respectively controlled by the first edge isolation signal, the second edge isolation signal, the first edge offset cancellation signal, and the second edge offset cancellation signal; the first isolation switches, the second isolation switches, the first offset cancellation switches, and the second offset cancellation switches between the readout amplification modules at non-head and non-tail positions and adjacent storage array slices are respectively controlled by the first internal isolation signal, the second internal isolation signal, the first internal offset cancellation signal, and the second internal offset cancellation signal.

10. The memory of claim 9, wherein, The edge test parameter group includes a first test parameter and a second test parameter, and the internal test parameter group includes a third test parameter and a fourth test parameter; If the first test parameter is in a first state, the second edge isolation signal and the second edge offset cancellation signal are respectively the same as the level of the initial isolation signal and the initial offset cancellation signal; if the first test parameter is in a second state, the second edge isolation signal and the second edge offset cancellation signal are both invalid; If the second test parameter is in a first state, the first edge isolation signal and the first edge offset cancellation signal are respectively the same as the level of the initial isolation signal and the initial offset cancellation signal; if the second test parameter is in a second state, the first edge isolation signal and the first edge offset cancellation signal are both invalid; and If the second test parameter is in a first state, the first edge isolation signal and the first edge offset cancellation signal are respectively the same as the level of the initial isolation signal and the initial offset cancellation signal; if the second test parameter is in a second state, the first edge isolation signal and the first edge offset cancellation signal are both invalid. If the fourth test parameter is in a first state, the first internal isolation signal and the first internal cancellation signal are respectively identical to the level of the initial isolation signal and the initial cancellation signal; if the fourth test parameter is in a second state, the first internal isolation signal and the first internal cancellation signal are both invalid; If the third test parameter is in a first state, the second internal isolation signal and the second internal cancellation signal are respectively identical to the level of the initial isolation signal and the initial cancellation signal; if the third test parameter is in a second state, the second internal isolation signal and the second internal cancellation signal are both invalid. In the process that the memory is instructed to perform the bit line stress test operation, the second test parameter is in the second state, and the first test parameter, the third test parameter and the fourth test parameter are all in the first state.

11. The memory of claim 10, wherein, The first state is a high level, and the second state is a low level. The first preprocessing circuit comprises: a first AND gate, whose two input ends receive the first test parameter and the initial isolation signal respectively, and whose output end outputs the second edge isolation signal; a second AND gate, whose two input ends receive the second test parameter and the initial isolation signal respectively, and whose output end outputs the first edge isolation signal; a third AND gate, whose two input ends receive the first test parameter and the initial cancellation signal respectively, and whose output end outputs the second edge cancellation signal; a fourth AND gate, whose two input ends receive the second test parameter and the initial cancellation signal respectively, and whose output end outputs the first edge cancellation signal.

12. The memory of claim 8, wherein, The bit line in the first storage array slice and the adjacent sense amplification module are electrically connected through the first cancellation switch or the first isolation switch, and the bit line in the last storage array slice and the sense amplification module at the head and tail positions are electrically connected through the second cancellation switch or the second isolation switch, and the memory further comprises: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial cancellation signal; wherein when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal and the initial cancellation signal are all in an effective state; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal, and generate a first internal cancellation signal and a second internal cancellation signal based on the internal test parameter group and the initial cancellation signal; a third preprocessing circuit configured to generate a first head-end isolation signal and a second head-end isolation signal based on a head-end test parameter group and the initial isolation signal, and generate a first head-end cancellation signal and a second head-end cancellation signal based on the head-end test parameter group and the initial cancellation signal; a fourth preprocessing circuit configured to generate a first tail-end isolation signal and a second tail-end isolation signal based on a tail-end test parameter group and the initial isolation signal, and generate a first tail-end cancellation signal and a second tail-end cancellation signal based on the tail-end test parameter group and the initial cancellation signal; The first test switches are all controlled by a test enable signal, the first isolation switches, the second isolation switches, the first un-bias switches and the second un-bias switches between the first readout amplifier module and the adjacent memory array slice are controlled by the first head isolation signal, the second head isolation signal, the first head un-bias signal and the second head un-bias signal respectively, the first isolation switches, the second isolation switches, the first un-bias switches and the second un-bias switches between the last readout amplifier module and the adjacent memory array slice are controlled by the first tail isolation signal, the second tail isolation signal, the first tail un-bias signal and the second tail un-bias signal respectively, and the first isolation switches, the second isolation switches, the first un-bias switches and the second un-bias switches between the readout amplifier module at the non-head and non-tail position and the adjacent memory array slice are controlled by the first internal isolation signal, the second internal isolation signal, the first internal un-bias signal and the second internal un-bias signal respectively.

13. The memory of claim 12, wherein, The internal test parameter group at least includes a third test parameter and a fourth test parameter, the head test parameter group includes a fifth test parameter and a sixth test parameter, and the tail test parameter group includes a seventh test parameter and an eighth test parameter. If the third test parameter is in a first state, the second internal isolation signal and the second internal un-bias signal are identical to the level of the initial isolation signal and the initial un-bias signal respectively, and if the third test parameter is in a second state, the second internal isolation signal and the second internal un-bias signal are invalid. If the fourth test parameter is in a first state, the first internal isolation signal and the first internal un-bias signal are identical to the level of the initial isolation signal and the initial un-bias signal respectively, and if the fourth test parameter is in a second state, the first internal isolation signal and the first internal un-bias signal are invalid. If the fifth test parameter is in a first state, the second head isolation signal and the second head un-bias signal are identical to the level of the initial isolation signal and the initial un-bias signal respectively, and if the fifth test parameter is in a second state, the second head isolation signal and the second head un-bias signal are invalid. If the sixth test parameter is in a first state, the first head isolation signal and the first head un-bias signal are identical to the level of the initial isolation signal and the initial un-bias signal respectively, and if the sixth test parameter is in a second state, the first head isolation signal and the first head un-bias signal are invalid. If the seventh test parameter is in a first state, the second tail isolation signal and the second tail un-bias signal are identical to the level of the initial isolation signal and the initial un-bias signal respectively, and if the seventh test parameter is in a second state, the second tail isolation signal and the second tail un-bias signal are invalid. if the eighth test parameter is in the first state, the first tail-end isolation signal and the first tail-end deskew signal are both active and have the same level as the initial isolation signal and the initial deskew signal respectively; and if the eighth test parameter is in the second state, the first tail-end isolation signal and the first tail-end deskew signal are both inactive. wherein, during a process in which the memory is instructed to perform a bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

14. The memory of claim 10 or 13, wherein, The first state is a high level, and the second state is a low level. The second preprocessing circuit comprises: a fifth AND gate having two input terminals respectively receiving the third test parameter and the initial isolation signal, and an output terminal outputting the second internal isolation signal; a sixth AND gate having two input terminals respectively receiving the fourth test parameter and the initial isolation signal, and an output terminal outputting the first internal isolation signal; a seventh AND gate having two input terminals respectively receiving the third test parameter and the initial deskew signal, and an output terminal outputting the second internal deskew signal; an eighth AND gate having two input terminals respectively receiving the fourth test parameter and the initial deskew signal, and an output terminal outputting the first internal deskew signal.

15. The memory of claim 13, wherein, The first state is a high level, and the second state is a low level. The third preprocessing circuit comprises: a ninth AND gate having two input terminals respectively receiving the fifth test parameter and the initial isolation signal, and an output terminal outputting the second head-end isolation signal; a tenth AND gate having two input terminals respectively receiving the sixth test parameter and the initial isolation signal, and an output terminal outputting the first head-end isolation signal; an eleventh AND gate having two input terminals respectively receiving the fifth test parameter and the initial deskew signal, and an output terminal outputting the second head-end deskew signal; a twelfth AND gate having two input terminals respectively receiving the sixth test parameter and the initial deskew signal, and an output terminal outputting the first head-end deskew signal. The fourth preprocessing circuit comprises: a thirteenth AND gate having two input terminals respectively receiving the seventh test parameter and the initial isolation signal, and an output terminal outputting the second tail-end isolation signal; a fourteenth AND gate having two input terminals respectively receiving the eighth test parameter and the initial isolation signal, and an output terminal outputting the first tail-end isolation signal; a fifteenth AND gate having two input terminals respectively receiving the seventh test parameter and the initial deskew signal, and an output terminal outputting the second tail-end deskew signal; a sixteenth AND gate having two input terminals respectively receiving the eighth test parameter and the initial deskew signal, and an output terminal outputting the first tail-end deskew signal.

16. The memory of claim 4, wherein, for the memory array tiles that are not head-end tiles, the bit lines in each of the memory array tiles are coupled to a respective local data line via a respective column gate switch; and wherein: the first head-end isolation signal and the first head-end deskew signal are both active and have the same level as the initial isolation signal and the initial deskew signal respectively; and if the eighth test parameter is in the second state, the first tail-end isolation signal and the first tail-end deskew signal are both inactive. for the second bit line in the non-first and non-last storage array slice with odd number and the first bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the first pre-charge source through the second test switch; for the first bit line in the non-first and non-last storage array slice with odd number and the second bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the second pre-charge source through the second test switch.

17. The memory of claim 16, wherein, for the first bit line in the non-first and non-last storage array slice with odd number and the second bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the second pre-charge source through the second test switch. for the first bit line in the non-first and non-last storage array slice with odd number and the second bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the second pre-charge source through the second test switch.

18. The memory of claim 17, wherein, the memory is configured to control all the isolation switches, the offset cancellation switches and the pre-charge switches to be in the off state, control all the column gate switches and the second test switches to be in the closed state, and control the first pre-charge source to be the first voltage value and the second pre-charge source to be the second voltage value, so as to perform a bit line stress test; or control all the isolation switches, the offset cancellation switches and the pre-charge switches to be in the off state, control all the column gate switches and the second test switches to be in the closed state, and control the first pre-charge source to be the second voltage value and the second pre-charge source to be the first voltage value, so as to perform another bit line stress test.

19. The memory of claim 5, wherein, for each of the bit lines in the non-first and non-last storage array slice, the local data line coupled thereto is connected to the first pre-charge source through the second test switch; for the second bit line in the non-first and non-last storage array slice with odd number and the first bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the first pre-charge source through the second test switch; for the first bit line in the non-first and non-last storage array slice with odd number and the second bit line in the non-first and non-last storage array slice with even number, the local data line coupled thereto is also connected to the second pre-charge source through the second test switch. ​ 20. The memory of claim 19, wherein, For the first and last storage array slices, the first bit lines are coupled to the local data lines via respective column gate switches; wherein: For the first and last storage array slices, the local data lines corresponding to the odd-numbered first bit lines are coupled to a second preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to a first preset test power source via the second test switches; Or, for the first storage array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to a second preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to a first preset test power source via the second test switches; for the last storage array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to a first preset test power source via the second test switches, and the local data lines corresponding to the even-numbered first bit lines are coupled to a second preset test power source via the second test switches.

21. The memory according to claim 20, wherein: the memory is configured to control all of the isolation switches and the cancellation switches to be in an off state, control all of the pre-charge switches to be in a closed state, and control the pre-charge power source to be a fifth voltage value; control all of the column gate switches and the second test switches to be in a closed state, and control the first preset test power source to be a first voltage value and the second preset test power source to be a second voltage value, to perform a first bit line stress test; control all of the isolation switches and the cancellation switches to be in an off state, control all of the pre-charge switches to be in a closed state, and control the pre-charge power source to be a fifth voltage value; control all of the column gate switches and the second test switches to be in a closed state, and control the first preset test power source to be a second voltage value and the second preset test power source to be a first voltage value, to perform a second bit line stress test; wherein the fifth voltage value is between the first voltage value and the second voltage value.

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