Method and device for testing DFT function of SOC chip of solid state disk

Abstract

The invention discloses a method and device for testing a DFT function of an SOC chip of a solid state disk, and the method comprises the steps: obtaining a generated ROM file which comprises pin excitation at each time point and an excitation expected value; the FPGA mainboard enables the SOC chip of the solid state disk carried on the chip product board to generate an excitation actual value according to the generated ROM file; comparing the generated actual excitation value with the expected excitation value; and recording a comparison result. By reading the ROM file by means of the FPGA mainboard and generating the DFT excitation signal according to the ROM file, a complex test scene can be accurately simulated, and an FPGA internal signal capture module is matched to collect actual values according to a preset sampling frequency and a time sequence, so that the SOC chip of the solid state disk is efficiently and accurately tested, and the response conditions of the chip under various excitation can be comprehensively detected. And the FPGA mainboard can rapidly record all inconsistent time points and corresponding signal data and send the data to the test host, so that subsequent rapid problem positioning is facilitated, the ATE debugging process is greatly shortened, time and cost are saved, and the chip production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state drives, and more specifically to a test method and device for the DFT function of the SOC chip of a solid-state drive. Background Art

[0002] For the SOC chip of SSD - Solid State Drives, in order to ensure the manufacturing quality of the SOC chip, DFT (design for test) is generally implemented inside the SOC chip to test whether there are problems with the chip. The DFT design will undergo rigorous verification before the chip tapeout to ensure that the design is problem-free. After the chip is returned, the design delivers the test vectors to the packaging and testing factory for test vector debugging. If there are problems, the efficiency of problem location is extremely low. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a test method and device for the DFT function of the SOC chip of a solid-state drive.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] The present invention provides a test method for the DFT function of the SOC chip of a solid-state drive. The method is implemented based on a test system for the DFT function of the SOC chip of a solid-state drive. The test system for the DFT function of the SOC chip of a solid-state drive includes an FPGA main board, a chip product board, and a test host. The chip product board is used to carry the SOC chip of the solid-state drive, and the chip product board and the test host are connected to the FPGA main board. The method includes:

[0006] Obtain the generated ROM file, where the ROM file includes pin excitations and excitation expected values at each time point;

[0007] The FPGA main board causes the SOC chip of the solid-state drive carried on the chip product board to generate actual excitation values according to the generated ROM file;

[0008] Compare the generated actual excitation values with the excitation expected values;

[0009] Record the comparison result.

[0010] Further, the generation of the ROM file includes:

[0011] Parse the WGL file;

[0012] Select the key information related to detection from the WGL file;

[0013] Add detection prompt flags to the selected key information related to detection;

[0014] Combine the selected key information related to detection and the added detection prompt flag to form a ROM file.

[0015] Further, the FPGA main board causes the SOC chip of the solid-state drive carried on the chip product board to generate an actual excitation value according to the generated ROM file, including:

[0016] The FPGA main board reads the ROM file;

[0017] The FPGA main board generates a DFT excitation signal according to the pin excitations at each time point in the ROM file, and sends it to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations;

[0018] After the SOC chip of the solid-state drive responds to the excitation and generates an output signal, the FPGA main board collects these output signals in real time according to the preset sampling frequency and timing as the actual excitation value.

[0019] Further, comparing the generated actual excitation value with the expected excitation value includes:

[0020] Align the captured actual excitation value with the expected excitation value in the ROM file according to the time points;

[0021] Compare the values of the actual excitation value and the expected value at each time point and signal dimension one by one;

[0022] If the actual excitation value and the expected value are exactly the same at all time points and signal dimensions, it is determined that the test passes; if there is any inconsistency, it is determined that the test fails.

[0023] In a second aspect, the present invention also provides a test device for the DFT function of the SOC chip of a solid-state drive, characterized in that when it runs, it is based on the test system for the DFT function of the SOC chip of the solid-state drive. The test system for the DFT function of the SOC chip of the solid-state drive includes an FPGA main board, a chip product board, and a test host. The chip product board is used to carry the SOC chip of the solid-state drive, and the chip product board and the test host are connected to the FPGA main board; the device includes:

[0024] An acquisition unit for acquiring the generated ROM file, where the ROM file includes pin excitations and expected excitation values at each time point;

[0025] An actual excitation value generation unit for the FPGA main board to cause the SOC chip of the solid-state drive carried on the chip product board to generate an actual excitation value according to the generated ROM file;

[0026] A comparison unit for comparing the generated actual excitation value with the expected excitation value;

[0027] A recording unit for recording the comparison result.

[0028] Furthermore, the generation of the ROM file includes:

[0029] A parsing unit for parsing the WGL file;

[0030] A selection unit for selecting key information related to detection from the WGL file;

[0031] An adding unit for adding a detection prompt flag to the selected key information related to detection;

[0032] A combining unit for combining the selected key information related to detection and the added detection prompt flag to form a ROM file.

[0033] Furthermore, the excitation actual value generation unit includes:

[0034] A reading unit for the FPGA main board to read the ROM file;

[0035] A generation module for the FPGA main board to generate a DFT excitation signal according to the pin excitations at each time point in the ROM file, and send it to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations;

[0036] A real-time acquisition module for, after the SOC chip of the solid-state drive responds to the excitation and generates an output signal, the FPGA main board to collect these output signals in real time according to the preset sampling frequency and timing as the excitation actual value.

[0037] Furthermore, the comparison unit includes:

[0038] An alignment module for aligning the captured excitation actual value with the excitation expected value in the ROM file according to the time points;

[0039] A comparison module for comparing the numerical values of the excitation actual value and the expected value one by one at each time point and signal dimension;

[0040] A determination module for determining that the test passes if the excitation actual value and the expected value are exactly the same at all time points and signal dimensions, and determining that the test fails if there is any inconsistency.

[0041] In a third aspect, the present invention also provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the test method for the DFT function of the SOC chip of the solid-state drive as described above.

[0042] Fourthly, the present invention further provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to execute the test method for the DFT function of the SOC chip of the solid-state drive as described above.

[0043] The beneficial effects of the present invention compared with the prior art are as follows: For the test method for the DFT function of the SOC chip of the solid-state drive, the method includes: obtaining a generated ROM file, the ROM file including pin excitations and excitation expected values at each time point; the FPGA main board causes the SOC chip of the solid-state drive carried on the chip product board to generate actual excitation values according to the generated ROM file; comparing the generated actual excitation values with the excitation expected values; and recording the comparison result. By means of the FPGA main board reading the ROM file and generating DFT excitation signals accordingly, complex test scenarios can be accurately simulated, and the internal signal capture module of the FPGA can collect actual values according to the preset sampling frequency and timing, making the test of the SOC chip of the solid-state drive efficient and accurate, and the response of the chip under various excitations can be comprehensively detected. Moreover, the FPGA main board can quickly record all inconsistent time points and corresponding signal data and send them to the test host, which is convenient for quickly locating problems subsequently, greatly shortening the ATE debugging process, saving time and cost, and improving the chip R & D and production efficiency.

[0044] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following preferred embodiments are specifically given and described in detail as follows. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0046] Figure 1 It is a flowchart of the test method for the DFT function of the SOC chip of the solid-state drive provided by the specific embodiment of the present invention;

[0047] Figure 2 It is a schematic block diagram of the test device for the DFT function of the SOC chip of the solid-state drive provided by the specific embodiment of the present invention;

[0048] Figure 3 It is a schematic block diagram of a computer device provided by the specific embodiment of the present invention. Detailed Embodiments

[0049] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0051] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0052] It should be further understood that the term " / and" as used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0053] For the SOC chip of SSD (Solid State Drives), in order to ensure the manufacturing quality of the SOC chip, generally, DFT (design for test, a testability structure implanted in the chip design stage) is implemented inside the SOC chip to test whether there are problems with the chip. The DFT design will be strictly verified before the chip tapeout (tapeout refers to the process of delivering the final layout data to the chip foundry for manufacturing after the chip design is completed). After the chip is returned (referring to the process of the chip foundry returning the manufactured chip to the chip design company or customer after the chip manufacturing is completed), the design delivers the test vectors to the packaging and testing factory for test vector debugging. If there are problems, the efficiency of problem location is extremely low.

[0054] To solve the above problems, the present invention is proposed, and the present invention will be introduced below through specific embodiments.

[0055] An embodiment of the present invention provides a test method for the DFT function of the SOC chip of a solid-state drive. The method is implemented based on a test system for the DFT function of the SOC chip of a solid-state drive. The test system for the DFT function of the SOC chip of a solid-state drive includes an FPGA main board, a chip product board, and a test host. The chip product board is used to carry the SOC chip of the solid-state drive, and the chip product board and the test host are connected to the FPGA main board.

[0056] Specifically, the FPGA main board serves as the core control and signal generation unit of the entire test system. It has powerful programmable logic capabilities and can be flexibly configured according to preset test logics and algorithms. On the one hand, it reads a ROM file containing excitation expected values and related configuration information from a storage device (such as a local flash chip, an external hard disk, etc.) or through a data transmission interface (such as a high-speed USB interface, an Ethernet interface, etc.). This ROM file is generated according to a standard test program format (such as the wgl format) and details the excitation settings for the SOC chip pins at each time point and the expected values. On the other hand, a module specifically used for capturing actual excitation signals is integrated inside the FPGA main board. Before the test, it needs to be initialized to ensure that the module is in a ready state for accurately collecting the output signals from the chip product board subsequently. In addition, based on the excitation information in the ROM file, the FPGA main board generates DFT excitation signals and precisely sends these signals to the chip product board to drive the SOC chip of the solid-state drive into various preset test operation states. After the chip responds to the excitation and generates output signals, the FPGA main board can also collect these output signals in real time according to the preset sampling frequency and timing, and use them as the actual values of the excitation for subsequent comparison and analysis with the expected values.

[0057] The main function of the chip product board is to provide a stable physical carrier platform for the SOC chip of the solid-state drive. Through the designed circuit wiring and interfaces, it tightly connects the SOC chip to the FPGA main board. On the one hand, the chip product board can accurately receive the DFT excitation signals sent from the FPGA main board and transmit these signals to the carried SOC chip without loss and deviation, ensuring that the chip can carry out test work under the correct excitation. On the other hand, when the SOC chip responds to the excitation and generates output signals, the chip product board can stably feedback these output signals to the FPGA main board for the FPGA main board to collect in real time.

[0058] The test host establishes a connection with the FPGA motherboard through the UART communication interface. The test host can send various control instructions to the FPGA motherboard, such as starting the test process, pausing the test, adjusting test parameters, etc., so as to achieve flexible control of the entire test process. When the test is completed, if the test passes, the FPGA motherboard will send a passlog to the test host through the serial port. After receiving this information, the test host can display a test passed prompt on its operation interface and record relevant test passed information, such as test time, test environment parameters, etc. If the test fails, the FPGA motherboard will organize all the recorded inconsistent time points and corresponding signal data and send them to the test host through the serial port.

[0059] As Figure 1 shown, the test method for the DFT function of the SOC chip of the solid-state drive includes the following steps: S10 - S40.

[0060] S10. Obtain the generated ROM file, and the ROM file includes pin excitations and excitation expected values at each time point.

[0061] The ROM file is usually generated by processing a test program file in a specific format, such as a WGL (Waveform Generation Language) file. The WGL file is a text file used to describe test waveforms and signal timings, and it details the states of each signal at different time points during the test process. In practical applications, a corresponding WGL file will be written according to the test requirements of the solid-state drive SOC chip, and this file covers the input excitations and expected output values of each pin of the chip at different test stages.

[0062] In an embodiment, the generation of the ROM file includes the following steps: S11 - S14.

[0063] S11. Parse the WGL file.

[0064] First, the WGL file needs to be parsed, and this step can be completed using a dedicated parsing tool or writing a parsing program. The parsing tool will read the text content of the WGL file and identify key information such as signal definitions, time templates, and test modes.

[0065] S12. Select key information related to detection from the WGL file.

[0066] From the parsed WGL file, select key information related to the DFT test, mainly the pin excitations and expected output values at each time point. For example, in the time template part of the WGL file, the state of each signal at different time points is defined.

[0067] S13. Add detection prompt flags to the selected key information related to detection.

[0068] To facilitate judgment and control during subsequent testing, detection prompt flags will be added to the selected key information. For example, in the information at each time point, an additional bit "check enable" flag is added to indicate whether signal comparison is required at that time point. If the flag is "1", it means that the actual output signal needs to be compared with the expected output value at that time point; if it is "0", no comparison is required.

[0069] S14. Combine the selected key information related to detection and the added detection prompt flags to form a ROM file.

[0070] Combine the selected key information and the added detection prompt flags, and store them as a ROM file in a certain format. Usually, the ROM file is a binary file, and each line corresponds to the test information at a time point, including the excitation values of each pin, the expected output value, and the detection prompt flag. For example, for a ROM file containing 5 pin signals and 1 detection prompt flag, one line may be represented as "100001", where the first 5 bits represent the pin excitation and the expected output value, and the last bit represents the detection prompt flag.

[0071] S20. The FPGA main board causes the SOC chip of the solid-state drive carried on the chip product board to generate actual excitation values according to the generated ROM file.

[0072] In one embodiment, step S20 specifically includes the following steps: S201 - S203.

[0073] S201. The FPGA main board reads the ROM file.

[0074] The FPGA main board reading the ROM file containing is the basis for carrying out subsequent test operations. The ROM file stores the key information required for testing, including the pin excitations and excitation expected values at each time point.

[0075] S202. The FPGA main board generates DFT excitation signals according to the pin excitations at each time point in the ROM file, and sends them to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations.

[0076] After the FPGA main board reads the ROM file, it needs to generate DFT excitation signals according to the pin excitation information at each time point therein.

[0077] Specifically, the FPGA motherboard will parse the data in the ROM file and extract the pin excitation information corresponding to each time point. For example, a line of data "10101" in the ROM file may indicate that at a certain time point, the excitation states of 5 different pins are high, low, high, low, and high respectively. The logic circuit inside the FPGA motherboard generates corresponding DFT excitation signals according to the parsed excitation information. The parameters such as the level and timing of these signals need to strictly follow the definitions in the ROM file. For example, for a clock signal, the FPGA motherboard will generate a corresponding clock signal through the internal clock generator according to the clock frequency and duty cycle specified in the ROM file.

[0078] The generated DFT excitation signals are sent to the chip product board through the output pins of the FPGA motherboard after appropriate level conversion and signal conditioning circuits. The chip product board transmits these excitation signals to the corresponding pins of the SOC chip of the solid-state drive to be tested, driving the chip into different test states. For example, when performing a JTAG test, the FPGA motherboard will send signals such as TMS, TCK, and TDI of the JTAG interface to the corresponding pins of the chip to control the chip to enter the test mode and execute corresponding test operations.

[0079] S203. After the SOC chip of the solid-state drive responds to the excitation and generates output signals, the FPGA motherboard samples these output signals in real time according to the preset sampling frequency and timing as the actual excitation values.

[0080] When the SOC chip receives the DFT excitation signals, it will generate corresponding output signals according to its own logic and functions. The FPGA motherboard needs to sample these output signals in real time.

[0081] The sampling frequency and timing are preset according to the test requirements and the characteristics of the SOC chip. For example, for a high-speed running SOC chip, a higher sampling frequency needs to be set to ensure that the output signals of the chip can be accurately sampled. The sampling timing needs to match the timing of the excitation signals to ensure that valid output signals are sampled at the correct time points.

[0082] The FPGA motherboard is connected to the output pins of the SOC chip on the chip product board through input pins and uses the internal sampling circuit to sample the output signals.

[0083] In practical applications, the sampling module will sample the output signals of the SOC chip at the appropriate time according to the preset sampling frequency and timing and store them in the registers or memories inside the FPGA as the actual excitation values for subsequent comparison with the expected excitation values.

[0084] S30. Compare the generated actual excitation values with the expected excitation values.

[0085] In one embodiment, step S30 specifically includes the following steps: S301 - S303.

[0086] S301. Align the captured actual excitation value with the expected excitation value in the ROM file according to time points.

[0087] The ROM file records the expected excitation value corresponding to each time point. At the same time, when the FPGA board collects the actual excitation value, it also records the time point corresponding to each actual value. These time point information can be synchronously recorded through a clock signal or a counter. For example, a counter can be used inside the FPGA. It starts counting from the beginning of the test, and for each clock cycle passed, the value of the counter is incremented by 1. In this way, each collected actual value and the expected value in the ROM file are associated with the value of the counter, thereby determining their corresponding time points.

[0088] To achieve alignment, data caching and indexing can be adopted. After the FPGA main board collects the actual excitation value, it stores it in a data buffer area and records the corresponding time point index at the same time. When making a comparison, according to the time point information in the ROM file, the corresponding actual excitation value is found from the buffer area. For example, assume that the expected value at the 10th time point in the ROM file is "101". The FPGA main board will search for the actual excitation value corresponding to time point 10 in the buffer area and then perform subsequent comparisons.

[0089] S302. Compare the actual excitation value with the expected value one by one in terms of the numerical values at each time point and signal dimension.

[0090] After completing the time point alignment, it is necessary to compare the actual excitation value and the expected value one by one at each time point and signal dimension. Specifically:

[0091] The signal dimension refers to each pin signal of the SOC chip or different test parameters. For example, for an SOC chip with 5 pins, the excitation signal at each time point has 5 dimensions. When making a comparison, it is necessary to compare the signals of each dimension separately.

[0092] During the comparison process, the FPGA main board will perform a bit - by - bit comparison of the actual excitation value and the expected value for each signal dimension at each time point. A logic circuit can be used to implement the comparison function. For example, an exclusive - OR gate can be used to determine whether two signals are the same. If a certain bit of the two signals is the same, the output of the exclusive - OR gate is at a low level; if different, the output of the exclusive - OR gate is at a high level.

[0093] S303. If the actual excitation value is completely consistent with the expected value at all time points and signal dimensions, it is determined that the test passes; if there is any inconsistent situation, it is determined that the test fails.

[0094] A flag bit can be used to record the test result. During the comparison process, if it is found that the actual value of the stimulus at any time point or signal dimension is inconsistent with the expected value, the flag bit is set to a value indicating test failure; if all comparison results are the same, the flag bit remains at a value indicating test pass.

[0095] S40. Record the comparison result.

[0096] In the DFT function test of the SOC chip of a solid-state drive, it is very important to record the comparison result after comparing the actual value of the stimulus with the expected value of the stimulus. It can not only provide a basis for the subsequent chip quality assessment, but also help engineers quickly locate faults and optimize the chip design and test process when problems occur during the test.

[0097] The content to be recorded includes:

[0098] Test time: Record the specific start and end times of the test, which helps to track the timeliness of the test and is also convenient for combining the test situations of different time periods in subsequent analysis to check whether there are problems that change over time. For example, it can be accurate to year, month, day, hour, minute, and second.

[0099] Test number: Assign a unique number to each test for easy management and query of test results. This number can be automatically generated, for example, numbered sequentially according to the order of testing.

[0100] Chip model and batch: Specify the specific model of the chip under test and the production batch it belongs to, in order to analyze the differences in the test performance of different models or batches of chips.

[0101] Time point information: Record the comparison situation of the actual value of the stimulus and the expected value of the stimulus at each time point. For example, whether the actual value and the expected value are consistent at a specific clock cycle.

[0102] Signal dimension difference: For each signal dimension (such as different pin signals), record the inconsistent situations in detail. If the actual value of a certain pin is different from the expected value, record the identification of the pin and the specific difference value.

[0103] Test pass or fail flag: Clearly mark whether this test passes or fails according to the comparison result.

[0104] By means of the FPGA main board reading the ROM file and generating the DFT excitation signal accordingly, the present invention can accurately simulate complex test scenarios, and cooperate with the internal signal capture module of the FPGA to collect actual values according to the preset sampling frequency and timing, making the test of the SOC chip of the solid-state drive efficient and accurate, and comprehensively detecting the response of the chip under various excitations. Moreover, the FPGA main board can quickly record all inconsistent time points and corresponding signal data and send them to the test host, facilitating subsequent rapid problem location, greatly shortening the ATE debugging process, saving time and cost, and improving the chip R & D and production efficiency.

[0105] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0106] The embodiment of the present invention also provides a test device for the DFT function of the SOC chip of the solid-state drive. The test device for the DFT function of the SOC chip of the solid-state drive is used to execute the steps in any one of the embodiments of the foregoing test method for the DFT function of the SOC chip of the solid-state drive. Specifically, please refer to Figure 2 , Figure 2 FIG. shows a schematic block diagram of a test device 100 for the DFT function of the SOC chip of the solid-state drive provided by the embodiment of the present application. The test device 100 for the DFT function of the SOC chip of the solid-state drive specifically includes:

[0107] An acquisition unit 110, configured to acquire the generated ROM file, where the ROM file includes pin excitations and excitation expected values at each time point; an excitation actual value generation unit 120, configured to cause the SOC chip of the solid-state drive carried on the chip product board to generate excitation actual values according to the generated ROM file by the FPGA main board; a comparison unit 130, configured to compare the generated excitation actual values with the excitation expected values; and a recording unit 140, configured to record the comparison result.

[0108] In one embodiment, the generation of the ROM file includes:

[0109] A parsing unit, configured to parse the WGL file; a selection unit, configured to select key information related to detection from the WGL file; an addition unit, configured to add a detection prompt flag to the selected key information related to detection; and a combination unit, configured to combine the selected key information related to detection and the added detection prompt flag to form a ROM file.

[0110] In one embodiment, the excitation actual value generation unit includes:

[0111] A reading unit for the FPGA main board to read the ROM file; a generating module for the FPGA main board to generate DFT excitation signals according to the pin excitations at each time point in the ROM file and send them to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations; a real-time acquisition module for the FPGA main board to real-time acquire these output signals as the actual excitation values according to the preset sampling frequency and timing after the SOC chip of the solid-state drive responds to the excitation and generates output signals.

[0112] In one embodiment, the comparison unit includes:

[0113] An alignment module for aligning the captured actual excitation values with the expected excitation values in the ROM file according to time points; a comparison module for comparing the actual excitation values with the expected values one by one in each time point and signal dimension; a determination module for determining that the test passes if the actual excitation values are exactly the same as the expected values in all time points and signal dimensions, and determining that the test fails if there is any inconsistent situation.

[0114] It should be noted that those skilled in the art can clearly understand that the specific implementation processes of the above-mentioned test device 100 for the DFT function of the SOC chip of the solid-state drive and each unit can refer to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and conciseness of description, they will not be elaborated here.

[0115] The above-mentioned test device for the DFT function of the SOC chip of the solid-state drive can be implemented in the form of a computer program, and this computer program can run on a computer device as shown in Figure 3 shown.

[0116] Please refer to Figure 3 , Figure 3 which is a schematic block diagram of a computer device provided by an embodiment of the present application. The computer device 700 can be a server. Among them, the server can be an independent server or a server cluster composed of multiple servers.

[0117] As shown in Figure 3 shown, this computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-mentioned test method for the DFT function of the SOC chip of the solid-state drive.

[0118] The computer device 700 includes a processor 720, a memory, and a network interface 750 connected through a system bus 710. Among them, the memory can include a non-volatile storage medium 730 and an internal memory 740.

[0119] The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, it can cause the processor 720 to execute a test method for the DFT function of the SOC chip of the solid-state drive.

[0120] The processor 720 is used to provide computing and control capabilities to support the operation of the entire computer device 700.

[0121] The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, it can cause the processor 720 to execute a test method for the DFT function of the SOC chip of the solid-state drive.

[0122] The network interface 750 is used for network communication, such as sending assigned tasks, etc. Those skilled in the art can understand that Figure 3 The structure shown in is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device 700 to which the solution of this application is applied. The specific computer device 700 may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements. Among them, the processor 720 is used to run the program code stored in the memory to implement a test method for the DFT function of the SOC chip of the solid-state drive.

[0123] Those skilled in the art can understand that Figure 3 The embodiments of the computer device shown in do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements. For example, in some embodiments, the computer device may only include a memory and a processor. In such an embodiment, the structures and functions of the memory and the processor are the same as those in Figure 3 the embodiment shown and will not be elaborated here.

[0124] It should be understood that in the embodiments of the present application, the processor 720 may be a central processing unit (CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0125] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the test method for the DFT function of the SOC chip of the solid-state drive disclosed in the embodiments of the present invention.

[0126] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses, and units can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again. Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0127] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. Units with the same function can also be aggregated into a single unit. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or units, and can also be electrical, mechanical, or other forms of connection.

[0128] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.

[0129] In addition, each functional unit in various embodiments of the present invention may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0130] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROMs), magnetic disks, or optical discs.

[0131] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for testing the DFT function of a SOC chip of a solid state drive, characterized in that: The method is implemented based on a test system for the SOC chip DFT function of a solid-state drive, wherein the test system for the SOC chip DFT function of the solid-state drive comprises an FPGA mainboard, a chip product board and a test host, wherein the chip product board is used to carry the SOC chip of the solid-state drive, and the chip product board and the test host are connected to the FPGA mainboard; the method comprises: Obtain a generated ROM file, wherein the ROM file includes pin excitations and excitation expected values ​​at each time point; The FPGA mainboard generates the actual value of the stimulus for the SOC chip of the solid-state drive carried on the chip product board according to the generated ROM file; Compare the actual value of the incentive generated with the expected value of the incentive; Record the comparison results.

2. The method for testing the SOC chip DFT function of a solid state drive according to claim 1, characterized in that: The generation of the ROM file includes: Parse WGL files; Extract key information related to detection from the WGL file; Add detection prompt marks for key information related to the selected detection; The selected detection-related key information and the added detection prompt mark are combined to form a ROM file.

3. The method for testing the SOC chip DFT function of a solid state drive according to claim 1, characterized in that: The FPGA mainboard causes the SOC chip of the solid-state hard disk carried on the chip product board to generate an actual value of excitation according to the generated ROM file, including: FPGA mainboard reads ROM file; The FPGA mainboard generates a DFT stimulus signal based on the pin stimulus at each time point in the ROM file, and sends it to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations; After the SOC chip of the solid-state drive responds to the stimulus and generates an output signal, the FPGA mainboard collects these output signals in real time according to the preset sampling frequency and timing as the actual value of the stimulus.

4. The method for testing the SOC chip DFT function of a solid state drive according to claim 1, characterized in that: The actual incentive value and the expected incentive value generated by the comparison include: Align the captured actual stimulus value with the stimulus expected value in the ROM file according to the time point; Compare the actual value of the stimulus with the expected value at each time point and signal dimension one by one; If the actual value of the stimulus is completely consistent with the expected value at all time points and signal dimensions, the test is considered to have passed. If there is any inconsistency, the test is considered to have failed.

5. A test device for the SOC chip DFT function of a solid state drive, characterized in that: The device is based on the SOC chip DFT function test system based on the solid state drive during operation. The SOC chip DFT function test system of the solid state drive includes an FPGA mainboard, a chip product board and a test host. The chip product board is used to carry the SOC chip of the solid state drive. The chip product board and the test host are connected to the FPGA mainboard. The device includes: An acquisition unit, used to acquire a generated ROM file, wherein the ROM file includes pin excitations and excitation expected values ​​at each time point; The excitation actual value generating unit is used for the FPGA mainboard to make the SOC chip of the solid state drive carried on the chip product board generate an excitation actual value according to the generated ROM file; A comparison unit, used to compare the actual value of the generated incentive with the expected value of the incentive; The recording unit is used to record the comparison result.

6. The device for testing the SOC chip DFT function of a solid state drive according to claim 5, characterized in that: The generation of the ROM file includes: Parsing unit, used to parse WGL files; A selection unit is used to select key information related to detection from the WGL file; An adding unit, used to add a detection prompt mark to the selected key information related to the detection; The combination unit is used to combine the selected detection-related key information and the added detection prompt mark to form a ROM file.

7. The device for testing the SOC chip DFT function of a solid state drive according to claim 5, characterized in that: The excitation actual value generating unit comprises: Reading unit, used for FPGA mainboard to read ROM files; The generation module is used for the FPGA mainboard to generate DFT stimulus signals according to the pin stimulus at each time point in the ROM file, and send them to the chip product board to drive the SOC chip of the solid-state drive to be tested to perform corresponding test operations; The real-time acquisition module is used to collect these output signals in real time as the actual value of the excitation according to the preset sampling frequency and timing after the SOC chip of the solid-state drive responds to the stimulus and generates the output signal.

8. The device for testing the SOC chip DFT function of a solid state drive according to claim 5, characterized in that: The comparison unit comprises: The alignment module is used to align the captured actual stimulus value with the stimulus expected value in the ROM file according to the time point; A comparison module is used to compare the actual value of the stimulus with the expected value at each time point and signal dimension one by one; The judgment module is used to judge that the test has passed if the actual value of the stimulus is completely consistent with the expected value at all time points and signal dimensions, and to judge that the test has failed if there is any inconsistency.

9. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for testing the SOC chip DFT function of the solid state drive as claimed in any one of claims 1 to 4 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the method for testing the SOC chip DFT function of a solid state drive as described in any one of claims 1 to 4.

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