Interface testing device and three-dimensional stacked chip

Abstract

The invention discloses an interface testing device and a three-dimensional stacked chip. The interface testing device comprises an interface module and a plurality of on-chip driving modules, the interface module is connected with a plurality of direct access interfaces in the memory, and the direct access interfaces are used for receiving test excitation sent by a test machine; the input end of the on-chip driving module is connected with the interface module, and the output end of the on-chip driving module is connected with a target test dimpling in the memory and is used for converting the target test dimpling from a one-way port to a two-way port; wherein the direct access interface sends the test excitation to the interface module after receiving the test excitation, and the interface module forwards the test excitation to the target test dimpling in the memory so as to perform target test on the memory. Therefore, not only is the dimpling test coverage rate in the memory increased, but also the dimpling simultaneous test number is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to an interface test device and a three-dimensional stacked chip. Background Art

[0002] Due to the characteristics of high bandwidth memory (HBM) with wide I / O (Input / Output) and multiple channels, taking a single channel as an example, if traditional test methods are used, up to 20 command pads and 192 data pads need to be led out from the microbumps. For 8 channels in total, 1696 pads need to be led out. Such a large number of pads is almost impossible to achieve for the design of the redistribution layer, the design of the probe card, and the test capabilities of the test needle machine. Therefore, traditional test methods can only lead out some microbumps for testing. Even so, the required number of pads is still very large, which not only results in a low test coverage rate but also makes it difficult to increase the number of simultaneous tests. Summary of the Invention

[0003] In view of the above problems, the present invention provides an interface test device and a three-dimensional stacked chip, which increase the test coverage rate of the microbumps in the high bandwidth memory and at the same time improve the number of simultaneous tests of the microbumps.

[0004] According to a first aspect of the present invention, an interface test device is provided, which is arranged in a memory. The interface test device includes:

[0005] An interface module, which is connected to a plurality of direct access interfaces in the memory. The direct access interfaces are used to receive test stimuli sent by a test machine.

[0006] A plurality of on-chip driver modules, the input ends of the on-chip driver modules are connected to the interface module, and the output ends of the on-chip driver modules are connected to target test microbumps in the memory, and are used to convert the target test microbumps from unidirectional ports to bidirectional ports.

[0007] Wherein, after receiving the test stimuli, the direct access interfaces send the test stimuli to the interface module, and the interface module forwards the test stimuli to the target test microbumps in the memory to perform target tests on the memory.

[0008] Optionally, the device further includes a clock frequency doubling module; the clock frequency doubling module includes a first frequency doubling module, a second frequency doubling module, and a third frequency doubling module; the on-chip driver modules include a first on-chip driver module, a second on-chip driver module, and a third on-chip driver module;

[0009] The input end of the first frequency doubling module is connected to the interface module, and the output end of the first frequency doubling module is connected to the input end of the first on-chip driving module;

[0010] The input end of the second frequency doubling module is connected to the interface module, and the output end of the second frequency doubling module is connected to the input end of the second on-chip driving module;

[0011] The input end of the third frequency doubling module is connected to the interface module, and the output end of the third frequency doubling module is connected to the input end of the third on-chip driving module;

[0012] Among them, the target test micro bump connected to the output end of the first on-chip driving module is used to input a clock signal to the instruction channel of the memory; the target test micro bump connected to the output end of the second on-chip driving module is used for the transmission of address data; the target test micro bump connected to the output end of the third on-chip driving module is used to input a clock signal to the write data path of the memory.

[0013] Optionally, the device further includes a latch module and a parallel-to-serial circuit;

[0014] The input end of the latch module is connected to the interface module, the output end of the latch module is connected to the input end of the parallel-to-serial circuit, the output end of the parallel-to-serial circuit is connected to the input end of the second on-chip driving module, and the output end of the second frequency doubling module is connected to the parallel-to-serial circuit; the interface module sends clock signals to the latch module and the second frequency doubling module respectively;

[0015] Among them, after the latch module receives the address data sent by the interface module, the parallel-to-serial circuit doubles the frequency-divided output data of the latch module and sends it to the second on-chip driving module connected to the parallel-to-serial circuit.

[0016] Optionally, the interface module includes multiple groups of signal interface sub-modules, and each group of signal interface sub-modules is connected to one of the direct access interfaces;

[0017] If the direct access interface is defined as a bidirectional port, the signal interface sub-module connected to the direct access interface includes a receiver and a driving unit;

[0018] If the direct access interface is defined as a unidirectional port, the signal interface sub-module connected to the direct access interface includes a receiver;

[0019] Among them, the input end of the receiver is connected to one of the direct access interfaces, and the output end of the receiver is connected to one of the frequency doubling module, the IEEE 1500 standard test module in the memory, and the latching module. The input end of the driving unit is connected to the IEEE 1500 standard test module, and the output end of the driving unit is connected to the direct access interface.

[0020] Optionally, the interface types of the direct access interface include a test enable interface type, a voltage interface type for the receiver voltage reference, a clock interface type for the frequency division clock input, and a test interface type for the memory to perform target testing.

[0021] Optionally, there are n direct access interfaces corresponding to the test interface type, where n is an integer greater than 1.

[0022] Optionally, the target testing includes a first test and a second test;

[0023] The interface types of the direct access interface further include a mode interface type for switching between the first test and the second test.

[0024] Optionally, the direct access interface corresponding to the test interface type used in the first test is multiplexed with the direct access interface corresponding to the test interface type used in the second test.

[0025] According to a second aspect of the present invention, there is provided a three-dimensional stacked chip including the foregoing interface testing device.

[0026] According to a third aspect of the present invention, there is provided a test system including a test machine platform and the foregoing three-dimensional stacked chip, and the test machine platform is used to send test stimuli to the three-dimensional stacked chip for target testing.

[0027] One or more of the above technical solutions in the embodiments of this specification have at least the following technical effects:

[0028] An interface test device and a three-dimensional stacked chip provided by an embodiment of this specification. The interface test device includes: an interface module and multiple on-chip drive modules; the interface module is connected to multiple direct access interfaces in a memory, and the direct access interfaces are used to receive test stimuli sent by a test machine; the input end of the on-chip drive module is connected to the interface module, and the output end of the on-chip drive module is connected to a target test microbump in the memory, and is used to convert the target test microbump from a unidirectional port to a bidirectional port; wherein, after receiving the test stimuli, the direct access interfaces send the test stimuli to the interface module, and the interface module forwards the test stimuli to the target test microbump in the memory to perform a target test on the memory. In this way, not only is the test coverage rate of the microbumps in the memory increased, but also the number of microbumps tested simultaneously is improved.

[0029] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically exemplified below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0031] Figure 1 A schematic diagram of an interface test device in an embodiment of the present invention is shown.

[0032] Figure 2 A schematic diagram of a direct access interface defined in an embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0035] It should be noted that like reference numerals and letters refer to like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] In the description of the present invention, it should also be noted that unless otherwise clearly defined and limited, the terms "set", "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0037] When HBM operates in task mode, up to thousands of I / Os work simultaneously. Due to the huge number of corresponding microbumps, the size and pitch will be very small. If directly testing through contacting the microbumps, it may cause damage to the microbumps, thus affecting the yield. In addition, since the microbumps are only used for short-distance signal driving, directly connecting to the test machine may have problems with insufficient driving ability. On the other hand, due to the characteristics of high-bandwidth memory with wide I / O and multiple channels, taking a single channel as an example, if using traditional testing methods, up to 20 instruction pads and 192 data pads need to be led out. For an 8-channel HBM, 1696 pads need to be led out, which is almost impossible to achieve for the design of the redistribution layer, the probe card design, and the testing ability of the test machine. Therefore, traditional testing methods can only lead out some I / Os for testing. Even so, the number of required pads is still very large, which will not only result in a low test coverage rate but also be difficult to increase the number of simultaneous tests. And due to the limited number of test channels of the test machine, connecting a large number of I / Os will make it difficult to achieve the parallel testing of HBM.

[0038] To solve the above problems and be able to test HBM without directly contacting the microbumps, the Solid State Technology Association has defined pads placed at special positions in the microbumps, which can be probed using traditional probes without causing damage to the microbumps. These pads are also called the direct access interface of HBM. In this embodiment, by setting the direct access interface in HBM and based on the defined direct access interface after setting, by adding an interface module, a latch module, a clock multiplier module, and an on-chip driver module, the data in the internal storage unit of HBM is read from the corresponding microbumps of HBM (also called the HBM I / O interface) and directly written back to the internal storage unit of HBM, reusing the original instruction decoding circuit and read / write data path of HBM, and directly sending instructions for testing from the defined direct access interface without any read / write control.

[0039] Specifically, in combination withFigure 1 As shown, this embodiment provides an interface test device, which is set in a memory. The memory can be a high-bandwidth memory. The following content of this embodiment will be described by taking the high-bandwidth memory as an example.

[0040] The above interface test device includes: an interface module and a plurality of on-chip drive modules.

[0041] Among them, the interface module is connected to a plurality of direct access interfaces (Direct Access interfaces, abbreviated as DA interfaces) in the high-bandwidth memory. The direct access interface is used to receive test stimuli sent by an external test machine.

[0042] The input end of the on-chip drive module is connected to the output end of the interface module, and the output end of the on-chip drive module is connected to the target test microbump in the high-bandwidth memory, and is used to change some target test microbumps from unidirectional ports to bidirectional ports as needed.

[0043] Among them, after receiving the test stimuli, the direct access interface sends the test stimuli to the interface module, and the interface module forwards the test stimuli to the target test microbump in the high-bandwidth memory to perform target testing on the high-bandwidth memory.

[0044] It should be noted that the target test microbump refers to the microbump point (Microbump Bonding) for target testing set inside the HBM. The size of the target test microbump is small, generally only a few micrometers. Some of the target test microbumps are unidirectional ports, and some are bidirectional ports. As shown in combination with Figure 1 Taking the microbumps of one channel of the HBM as an example, based on the actual situation of the target test in this embodiment, for some target test microbumps that need to be changed into bidirectional ports, an on-chip drive (abbreviated as OCD) module is set. In this way, the signal input from the DA interface can be sent to the on-chip drive module, then reach the target test microbump through the on-chip drive module, and then enter the internal path of the HBM through the connector (receiver, abbreviated as RCV) connected to the target test microbump, thereby realizing the target test.

[0045] In Figure 1 Among the target test microbumps shown, the clock signal microbump can include a differential clock positive input microbump and a differential clock negative input microbump. The address microbump can include a row address microbump <5:0> and a column address microbump <7:0>. The first data microbump can be represented as a data microbump <127:0>. The second data microbump can be represented as a data mask microbump <15:0>. The third data microbump can be represented as a data bus flip microbump <15:0>. The write data sampling clock microbump can include a write data sampling clock positive input microbump <3:0> and a write data sampling clock negative input microbump <3:0>.

[0046] In this embodiment, the test stimulus is sent by an external test machine. The test stimulus includes three types, namely clock signals, control signals, and data signals. The interface test device of this embodiment further includes a clock multiplier module for receiving the clock signal sent by the test machine and using it after frequency multiplication. In this way, the test machine can use a clock input with a lower frequency, thereby saving the test cost.

[0047] In this embodiment, the test machine uses three groups of divided-frequency clock signals as the clock input, namely the first divided-frequency clock signal, the second divided-frequency clock signal, and the third divided-frequency clock signal. These three groups of clock inputs are shared by all channels of the entire HBM. For any group of divided-frequency clock signals, this group of divided-frequency clock signals includes two divided-frequency clock signals with a phase difference of a quarter cycle. That is, the first divided-frequency clock signal includes the first divided-frequency clock signal_0 and the first divided-frequency clock signal_1, the second divided-frequency clock signal includes the second divided-frequency clock signal_0 and the second divided-frequency clock signal_1, and the third divided-frequency clock signal includes the third divided-frequency clock signal_0 and the third divided-frequency clock signal_1. The three groups of divided-frequency clock signals are respectively the first divided-frequency clock signal input from the DA26 interface and the DA25 interface; the second divided-frequency clock signal input from the DA24 interface and the DA22 interface; the third divided-frequency clock signal input from the DA20 interface and the DA18 interface.

[0048] In one embodiment, the clock multiplier module includes a first multiplier module, a second multiplier module, and a third multiplier module; the on-chip driving module includes a first on-chip driving module (located in the OCD module shown at the top), a second on-chip driving module (located in the OCD module shown in the middle), and a third on-chip driving module (located in the OCD module shown at the bottom); Figure 1 in the OCD module shown at the top), a second on-chip driving module (located in the OCD module shown in the middle), and a third on-chip driving module (located in the OCD module shown at the bottom); Figure 1 in the OCD module shown in the middle), and a third on-chip driving module (located in the OCD module shown at the bottom); Figure 1 in the OCD module shown at the bottom);

[0049] Among them, the input end of the first multiplier module is connected to the interface module, and the output end of the first multiplier module is connected to the input end of the first on-chip driving module;

[0050] The input end of the second multiplier module is connected to the interface module, and the output end of the second multiplier module is connected to the input end of the second on-chip driving module;

[0051] The input end of the third multiplier module is connected to the interface module, and the output end of the third multiplier module is connected to the input end of the third on-chip driving module;

[0052] Among them, the target test microbumps connected to the output ends of the first on-chip driving modules are used to input clock signals to the instruction channels (also known as instruction paths) of the high-bandwidth memory; the target test microbumps connected to the output ends of the second on-chip driving modules are used for the transmission of address data; the target test microbumps connected to the output ends of the third on-chip driving modules are used to input clock signals to the read / write data paths of the high-bandwidth memory.

[0053] In one embodiment, the interface test device further includes a latch module and a parallel-to-serial circuit.

[0054] The input end of the latch module is connected to the interface module, the output end of the latch module is connected to the input end of the parallel-to-serial circuit, the output end of the parallel-to-serial circuit is connected to the input end of the second on-chip driving module, and the output end of the second frequency doubling module is connected to the parallel-to-serial circuit; the interface module sends clock signals to the latch module and the second frequency doubling module respectively;

[0055] Among them, after the latch module receives the address data sent by the interface module, the parallel-to-serial circuit doubles the frequency of the frequency-divided output data of the latch module and sends it to the second on-chip driving module connected to the parallel-to-serial circuit.

[0056] It should be noted that the second frequency doubling module is used to increase the frequency of the input clock signal. The parallel-to-serial circuit is used to convert the input parallel data into serial data. Specifically, the second frequency-divided clock signal is frequency-doubled to generate a frequency-doubled clock, and then through a simple parallel-to-serial conversion, the column address signal, row address signal, and clock enable signal frequency-divided and output by the latch module can be frequency-doubled again and connected correspondingly to the second on-chip driving module, and then output to the corresponding target test microbumps, so as to achieve the normal frequency input of the column address signal, row address signal, and clock enable signal on the corresponding target test microbumps of the HBM.

[0057] The latch module is used to latch the output of the interface module, and its core is a group of dual-edge-triggered latches. The second frequency-divided clock signal_0 and the second frequency-divided clock signal_1 are used as the input clocks of the latch module. The latch module can sample the row address signal, column address signal, clock enable signal, etc. at the rising edge and falling edge of the second frequency-divided clock signal_0 and the second frequency-divided clock signal_1. The external input needs to ensure the sampling timing of the second frequency-divided clock signal_0 and the second frequency-divided clock signal_1 for the row address signal, column address signal, and clock enable signal. After sampling, a 2-frequency division effect of the row address signal, column address signal, and clock enable signal is achieved internally.

[0058] In this embodiment, the interface module includes multiple groups of signal interface sub-modules, and each group of signal interface sub-modules is connected to a direct access interface; the number of signal interface sub-modules is the same as the number of direct access interfaces.

[0059] Based on the target test, this embodiment pre - defines multiple direct access interfaces and determines whether each direct access interface is a unidirectional port (in) or a bidirectional port (inout).

[0060] If the direct access interface is defined as a bidirectional port, the signal interface sub - module connected to this direct access interface includes a receiver (abbreviated as RCV) and a driver unit;

[0061] If the direct access interface is defined as a unidirectional port, the signal interface sub - module connected to the direct access interface only includes a receiver;

[0062] Among them, the input end of the receiver is connected to one of the direct access interfaces, the output end of the receiver is connected to one of the frequency - doubling module, the IEEE1500 standard test module in the high - bandwidth memory, and the latch module. The input end of the driver unit is connected to the IEEE1500 standard test module, and the output end of the driver unit is connected to the direct access interface. The IEEE1500 standard test can also be called the Standard for Embedded Core Test (SECT for short), which is a test standard specifically designed for complex system - on - chip (SoC).

[0063] It should be noted that the driver unit is essentially the same as the above - mentioned on - chip driver module, both of which are used to change the connected interface from unidirectional to multi - directional.

[0064] In this embodiment, the interface types of the direct access interfaces include test enable interface type, voltage interface type for the receiver voltage reference, clock interface type for the divided - frequency clock input, and test interface type for the target test of the high - bandwidth memory.

[0065] Based on the actual test requirements, the number of direct access interfaces corresponding to each type is different. Generally, there are multiple direct access interfaces corresponding to the test interface type.

[0066] The target test of this embodiment may have one type, or may have two or even multiple types. If there are two target tests, for example, the target test includes the first test and the second test. Then the first test has multiple corresponding direct access interfaces regarding the test interface type. The second test has multiple corresponding direct access interfaces regarding the test interface type. The first test refers to the HBM task - mode test, and the second test refers to the HBM IEEE1500 standard test.

[0067] It is worth mentioning that, in order to simplify the target test, in this embodiment, the interface types of the direct access interfaces also include a mode interface type for switching between the first test and the second test. For example, the direct access interface corresponding to the mode interface type is DA40. DA40 inputs a test mode switching signal. If the test mode switching signal input by DA40 is 0, the first test can be performed at this time; if the test mode switching signal input by DA40 is 1, the second test can be performed at this time.

[0068] It should be noted that the direct access interfaces corresponding to the test interface types used in the first test can be reused as the direct access interfaces corresponding to the test interface types used in the second test.

[0069] For the convenience of those skilled in the art to understand and implement, this embodiment is illustrated by examples:

[0070] Combined with Figure 2 As shown, the direct access interfaces defined in HBM are as follows: (For the target test microbumps connected by the interfaces, the reference meaning thereof refers to the JESD235B standard)

[0071] The direct access interfaces numbered DA4, DA5, DA6, DA8, DA10, DA12, DA14, DA16, DA17, DA29, DA30, DA32, DA34, DA36, DA38 are used to access the read and write operations of the first test.

[0072] The switching between the two tests is performed through the direct access interface numbered DA40. The direct access interfaces numbered DA4, DA5, DA6, DA8, DA10, DA14 can be simultaneously reused as the inputs of the second test. DA4, DA5, DA6, DA8, DA10, DA14 are defined as the input interfaces of the standard test signals. Specifically, the DA4 interface is defined as the wrapper clock input; the DA5 interface is defined as the wrapper update input; the DA6 interface is defined as the wrapper shift input; the DA8 interface is defined as the wrapper capture input; the DA10 interface is defined as the wrapper selection input; the DA14 interface is defined as the wrapper data input; the direct access interfaces numbered DA16, DA17, DA29, DA30, DA32, DA34, DA36, DA38 are simultaneously reused as the outputs of the second test, that is, they are defined as the output interfaces of the standard output signals. Specifically, the DA16, DA17, DA29, DA30, DA32, DA34, DA36, DA38 interfaces are defined as the wrapper data outputs, and a - h represent 8 HBM channels.

[0073] The direct access interfaces numbered DA24, DA22, DA26, DA25, DA20, and DA18 are clock inputs, and they are paired in twos, all of which are divided-by-two inputs. The two clocks within a pair have a phase difference of 1 / 4 cycle. Among them, DA24 and DA22 are respectively connected to the second-divided clock signal and used as the synchronous input clocks for DA4, DA5, DA6, DA8, DA10, DA12, DA14, DA16, DA17, DA29, DA30, DA32, DA34, DA36, and DA38; DA26 and DA25 are respectively connected to the first-divided clock signal and used as the input clocks for the HBM instruction channel, and DA20 and DA18 are respectively connected to the third-divided clock signal and used as the input clocks for the HBM data channel.

[0074] DA28 is connected to the test enable signal and used as the enable for the test device; DA3 is connected to the reference voltage signal and used to provide the reference voltage for the receiver.

[0075] Among them, the first test can be the HBM task mode test, and the second test can be the HBM I EEE1500 standard test.

[0076] The test process based on this example is as follows:

[0077] 1. For the HBM task mode test

[0078] Input 1 to DA28 and 0 to DA40 to enter the HBM task mode test;

[0079] Debug the input timing relationship between the second-divided clock signal and the row address signal, column address signal, and clock enable signal, that is, ensure the setup time and hold time of the second-divided clock signal and the row address signal, column address signal, and clock enable signal;

[0080] Debug the phase relationship between the second-divided clock signal and the first-divided clock signal, and the phase relationship between the first-divided clock signal and the third-divided clock signal; among them, the phases of the second-divided clock signal and the first-divided clock signal are kept consistent, and the phase difference between the first-divided clock signal and the third-divided clock signal is greater than the data output delay of the HBM.

[0081] Send the mode register setting instruction according to the HBM instruction protocol to set the read and write delays, and send the HBM instructions (such as row activation ACT, read RD, write WR, row precharge PRE, etc.) according to a specific timing sequence, that is, the test of the read and write paths in the HBM task mode test can be realized.

[0082] 2. For the HBM I EEE1500 function test

[0083] DA28 input 1 and DA40 input 1 enter the HBM I EEE1500 functional test;

[0084] Debug the input timing relationship between each standard test signal, that is, debug the phase relationship between the wrapper clock input and the wrapper update input, wrapper shift input, wrapper capture input, wrapper select input, and wrapper data input, and ensure the setup time and hold time between the wrapper clock input and the wrapper update input, wrapper shift input, wrapper capture input, wrapper select input, wrapper data input and the wrapper clock input;

[0085] Send I EEE1500 operation instructions according to the I EEE1500 protocol;

[0086] Through the wrapper data output <a:h>The interface reads the IEEE1500 output.

[0087] In summary, an interface test device provided by an embodiment of this specification includes: an interface module and multiple on-chip drive modules; the interface module is connected to multiple direct access interfaces in a high-bandwidth memory, and the direct access interfaces are used to receive test stimuli sent by a test machine; the input end of the on-chip drive module is connected to the interface module, and the output end of the on-chip drive module is connected to a target test microbump in the high-bandwidth memory, and is used to convert the target test microbump from a unidirectional port to a bidirectional port; wherein, after receiving the test stimuli, the direct access interfaces send the test stimuli to the interface module, and the interface module forwards the test stimuli to the target test microbump in the high-bandwidth memory to perform a target test on the high-bandwidth memory. In this way, not only is the microbump test coverage rate in the high-bandwidth memory increased, but also the number of simultaneously tested microbumps is improved.

[0088] Based on the same inventive concept, an embodiment of the present invention further provides a three-dimensional stacked chip, including the foregoing interface test device.

[0089] Among them, the three-dimensional stacked chip includes a logic wafer and at least one memory wafer. The logic wafer and the memory wafer are stacked, and the logic wafer and the memory wafer are connected through a connection layer. The interface test device in this embodiment is installed in the logic wafer.

[0090] It should be noted that for the specific content of the interface test device, please refer to the foregoing embodiments, and details are not described herein again.

[0091] In summary, a three-dimensional stacked chip provided by an embodiment of this specification, the interface test device in the three-dimensional stacked chip includes: an interface module and multiple on-chip drive modules; the interface module is connected to multiple direct access interfaces in a high-bandwidth memory, and the direct access interfaces are used to receive test stimuli sent by a test machine; the input end of the on-chip drive module is connected to the interface module, and the output end of the on-chip drive module is connected to a target test microbump in the high-bandwidth memory, and is used to convert the target test microbump from a unidirectional port to a bidirectional port; wherein, after receiving the test stimuli, the direct access interfaces send the test stimuli to the interface module, and the interface module forwards the test stimuli to the target test microbump in the high-bandwidth memory to perform a target test on the high-bandwidth memory. It supports the switching of two test modes and interface multiplexing. In this way, not only is the microbump test coverage rate in the high-bandwidth memory increased, but also the number of simultaneously tested microbumps is improved.

[0092] Based on the same inventive concept, an embodiment of the present invention further provides a test system, including a test machine and the foregoing three-dimensional stacked chip, and the test machine is used to send test stimuli to the three-dimensional stacked chip for target testing.

[0093] The above are only various embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.< / a:h>

Claims

1. An interface testing device, characterized in that: Set in the memory, the interface testing device comprises: An interface module, the interface module is connected to a plurality of direct access interfaces in the memory, the direct access interfaces are used to receive test stimuli sent by a test machine; A plurality of on-chip driving modules, wherein the input end of the on-chip driving module is connected to the interface module, and the output end of the on-chip driving module is connected to the target test micro-convex in the memory, and is used to convert the target test micro-convex from a unidirectional port to a bidirectional port; After receiving the test stimulus, the direct access interface sends the test stimulus to the interface module, and the interface module forwards the test stimulus to the target test micro-convex in the memory to perform a target test on the memory.

2. The device according to claim 1, characterized in that The device further comprises a clock frequency multiplication module; the clock frequency multiplication module comprises a first frequency multiplication module, a second frequency multiplication module and a third frequency multiplication module; the on-chip driving module comprises a first on-chip driving module, a second on-chip driving module and a third on-chip driving module; The input end of the first frequency multiplication module is connected to the interface module, and the output end of the first frequency multiplication module is connected to the input end of the first on-chip driving module; The input end of the second frequency multiplication module is connected to the interface module, and the output end of the second frequency multiplication module is connected to the input end of the second on-chip driving module; The input end of the third frequency multiplication module is connected to the interface module, and the output end of the third frequency multiplication module is connected to the input end of the third on-chip driving module; Among them, the target test micro-convex connected to the output end of the first on-chip driver module is used to input a clock signal to the instruction channel of the memory; the target test micro-convex connected to the output end of the second on-chip driver module is used for transmitting address data; and the target test micro-convex connected to the output end of the third on-chip driver module is used to input a clock signal to the write data path of the memory.

3. The device according to claim 2, characterized in that The device also includes a latch module and a parallel-to-serial circuit; The input end of the latch module is connected to the interface module, the output end of the latch module is connected to the input end of the parallel-to-serial circuit, the output end of the parallel-to-serial circuit is connected to the input end of the second on-chip driver module, and the output end of the second frequency multiplication module is connected to the parallel-to-serial circuit; the interface module sends clock signals to the latch module and the second frequency multiplication module respectively; After the latch module receives the address data sent by the interface module, the parallel-to-serial circuit multiplies the frequency of the divided output data of the latch module and sends it to the second on-chip driving module connected to the parallel-to-serial circuit.

4. The device according to claim 3, characterized in that The interface module includes a plurality of groups of signal interface submodules, each group of signal interface submodules is connected to one of the direct access interfaces; If the direct access interface is defined as a bidirectional port, the signal interface submodule connected to the direct access interface includes a receiver and a driver unit; If the direct access interface is defined as a unidirectional port, the signal interface submodule connected to the direct access interface includes a receiver; Among them, the input end of the receiver is connected to one of the direct access interfaces, and the output end of the receiver is connected to the frequency multiplication module, the IEEE1500 standard test module in the memory, and one of the latch modules; the input end of the drive unit is connected to the IEEE1500 standard test module, and the output end of the drive unit is connected to the direct access interface.

5. The device according to claim 1, characterized in that The interface types of the direct access interface include a test enable interface type, a voltage interface type for a receiver voltage reference, a clock interface type for a divided clock input, and a test interface type for target testing of the memory.

6. The device according to claim 5, characterized in that There are n direct access interfaces corresponding to the test interface type, where n is an integer greater than 1.

7. The device according to claim 5 or 6, characterized in that The target test includes a first test and a second test; The interface type of the direct access interface also includes a mode interface type for switching the first test and the second test.

8. The device according to claim 7, characterized in that The direct access interface corresponding to the test interface type used in the first test reuses the direct access interface corresponding to the test interface type used in the second test.

9. A three-dimensional stacked chip, characterized in that: An interface testing device comprising any one of claims 1-8.

10. A testing system, characterized in that: It comprises a test machine and the three-dimensional stacked chip according to claim 9, wherein the test machine is used to send test stimulus to the three-dimensional stacked chip to perform target testing.

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