Industrial-level memory testing method and system

Abstract

The invention discloses a method and a system for testing an industry-level memory, and relates to the technical field of computer hardware testing, and the method comprises the following steps: collecting memory state data, and preprocessing the memory state data; based on the preprocessed memory state data, load simulation is carried out on the memory, and the memory performance level is predicted; memory errors are simulated through a fault injection method, the error detection probability of the memory is analyzed in real time, and the fault recovery level of the memory is evaluated; and generating a memory test report based on the memory performance level and the fault recovery level. According to the method, the real error response of the memory can be simulated and evaluated in an experimental environment, an important basis can be provided for optimizing the stability and reliability of the memory, and the method is particularly suitable for industrial-level memory application with high-load and high-reliability requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware testing, and particularly to a testing method and system for industrial-grade memory. Background Art

[0002] In modern computing systems, memory, as the core component for data storage and processing, its performance and reliability play a crucial role in the overall operating efficiency of the memory. With the rapid development of information technology, the application scenarios of industrial-grade memory are becoming increasingly complex, not only requiring higher read / write speeds and lower latency, but also having to possess powerful error detection and correction capabilities. Traditional memory testing methods mainly focus on the measurement of static parameters and simple load testing. Although this method can reflect the basic performance of the memory to a certain extent, it is inadequate when faced with dynamically changing workloads and complex error patterns. In recent years, with the development of technologies such as machine learning and big data analysis, more and more research has begun to focus on how to improve the effectiveness of memory testing through intelligent means to meet the growing data processing requirements.

[0003] The existing related technologies have two main deficiencies: First, traditional methods lack comprehensive preprocessing of memory state data, resulting in inaccurate and unstable test results. For example, directly analyzing raw data without standardization and noise removal may introduce a large amount of error, affecting the accuracy of the final evaluation. Second, existing technologies mostly adopt static or semi-static methods in fault injection and error detection, and do not fully consider the change of memory state over time and its impact on the error correction mechanism. This limitation makes it difficult for traditional testing methods to capture the dynamic behavior of the memory during actual operation, especially its performance under high load and complex environments. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a testing method for industrial-grade memory to solve the problems of inaccurate test results and difficulty in capturing the actual operation behavior of the memory in the prior art.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a testing method for industrial-grade memory, which includes collecting memory state data and preprocessing the memory state data; based on the preprocessed memory state data, simulating the load on the memory to predict the memory performance level; simulating memory errors through the fault injection method, analyzing the error detection probability of the memory in real time, and evaluating the fault repair level of the memory; generating a memory test report based on the memory performance level and the fault repair level.

[0008] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: the memory status data includes the temperature, voltage, frequency, read / write rate, error rate, and usage rate of the memory.

[0009] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: the preprocessing of the memory status data is specifically carried out as follows.

[0010] Standardization is adopted to adjust different types of memory status data to a unified dimension and range.

[0011] The memory status data is smoothed by the moving average method.

[0012] The memory status data is time-aligned and synchronized through timestamp alignment.

[0013] The noise data in the memory status data is removed by the outlier correction method.

[0014] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: based on the preprocessed memory status data, a load simulation is performed on the memory to predict the memory performance level, and the specific steps are as follows.

[0015] The preprocessed memory status data is used as different dimensions to define the high-dimensional space of the memory status.

[0016] Based on the high-dimensional space of the memory status, a load simulation model is constructed through a nonlinear dynamics model.

[0017] By analyzing the interaction relationship between the memory status data from historical data, the dynamic evolution law of the memory status data during the load change process is extracted, and the simulation rules are defined.

[0018] In the high-dimensional space of the memory status, based on the simulation rules, the evolution law of the memory status with the load change is simulated to predict the memory performance level, and the expression is: ; Wherein, is the memory performance level, represents the start time of the load simulation, represents the end time of the load simulation, represents the total number of the memory status data, is the weight coefficient of the th memory status data, is the non-linear attenuation factor of the influence of the th memory status data on the performance, represents the The value at is the amplitude factor of the sine function, representing the frequency factor of the load change, representing at time the overall load intensity.

[0019] As a preferred solution of the test method for the industrial - level memory described in the present invention, wherein: simulating memory errors through the fault injection method and analyzing the error detection probability of the memory in real - time, the specific steps are as follows.

[0020] Based on historical fault data and memory error patterns, define memory error types;

[0021] Adopt a random distribution method to randomly distribute memory error types at different positions in the memory, and monitor the dynamic changes of memory status data in real - time;

[0022] According to the dynamic changes of memory status data, through complex integration and multiplication operations combined with the Logistic function and power function, capture the combined influence of the dynamic changes of each memory status data on the ECC error detection efficiency and the time - cumulative effect, and analyze the error detection probability of the memory in real - time. The expression is: ; wherein, is the error detection probability of the memory at time , is the initial time point of error detection, represents the current time, represents the total number of memory status data, is the sensitivity factor of the th memory status data on error detection, is the standard value of the th memory status data, is the slope parameter of the Logistic function, is the decision threshold of the th memory status data, is the th memory status data's maximum expected value, is the weight coefficient of the th memory status data during the error detection process.

[0023] As a preferred solution of the test method for the industrial - level memory described in the present invention, wherein: evaluating the fault repair level of the memory, the specific steps are as follows.

[0024] After the memory completes error detection through ECC, combined with the error detection probability of the memory And the time from discovering a memory error to the completion of repair. By introducing logarithmic and sine-squared functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively considering the recovery time and state changes, the memory fault repair level is evaluated. The expression is as follows: ; Wherein, is the time The memory fault repair score at this time, is the total number of faults, is the weight coefficient of the th fault, is the repaired proportion of the th fault, is the proportion of the th fault that is not corrected, is the recovery time of the th fault, is the time that the memory remains unstable after the th fault occurs, is the sensitivity factor of the memory state data to the recovery time, is the change amount of the memory state before and after the

[0025] As a preferred solution of the test method for the industry-level memory described in the present invention, wherein: the memory test report includes the memory performance level, the error detection probability of the memory, the memory fault repair score, and optimization suggestions.

[0026] In a second aspect, the present invention provides a test system for industry-level memory, including a data acquisition module, a performance level prediction module, a repair level evaluation module, and a test report generation module; the data acquisition module is used to collect memory state data and preprocess the memory state data; the performance level prediction module is used to simulate the memory load based on the preprocessed memory state data and predict the memory performance level; the repair level evaluation module is used to simulate memory errors by the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the memory fault repair level; the test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

[0027] In a third aspect, the present invention provides a computer device, including a memory and a processor, wherein: when the computer program is executed by the processor, it realizes any step of the test method for the industry-level memory described in the first aspect of the present invention.

[0028] Fourthly, the present invention provides a computer-readable storage medium, on which a computer program is stored, wherein: when the computer program is executed by a processor, any step of the test method for industrial-grade memory as described in the first aspect of the present invention is implemented.

[0029] The beneficial effects of the present invention are as follows: By using the fault injection method to simulate memory errors, combining historical fault data and memory error patterns, the memory status change is monitored in real time, and the error detection probability of the memory is evaluated through complex mathematical operations. This method can accurately simulate the performance of the memory under different fault conditions, quantify the efficiency of memory error detection, and provide data support for the fault tolerance mechanism and repair ability of the memory. The present invention can not only simulate and evaluate the real error response of the memory in the experimental environment, but also provide an important basis for optimizing the stability and reliability of the memory, and is especially applicable to industrial-grade memory applications with high load and high reliability requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a flowchart of the test method for industrial-grade memory in Embodiment 1.

[0032] Figure 2 It is a schematic diagram of the test system for industrial-grade memory in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the drawings of the specification.

[0034] Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0035] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The appearances of "in one embodiment" in different places in this specification do not all refer to the same embodiment, nor are they separate or alternative embodiments that exclude other embodiments.

[0036] Embodiment 1, refer to Figure 1 andFigure 2 , which is the first embodiment of the present invention. This embodiment provides a test method for industrial-grade memory, including the following steps:

[0037] S1: Collect memory status data and preprocess the memory status data;

[0038] S1.1: The memory status data includes the temperature, voltage, frequency, read / write rate, error rate, and usage rate of the memory.

[0039] Furthermore, the memory status data is collected separately by a variety of high-precision sensors: the temperature is monitored by a thermistor, the voltage is recorded by a voltage sensor, the frequency is measured by a frequency meter, the read / write rate is obtained with the help of a performance monitoring tool, the error rate is detected by a built-in ECC module, and the usage rate is counted through system monitoring software. These sensors capture and record the key operating parameters of the memory in real time to ensure the accuracy and reliability of the data.

[0040] S1.2: Adopt standardization to adjust different types of memory status data to a unified dimension and range;

[0041] Specifically, through standardization processing, the temperature data range from 50°C to 80°C is converted to a unified dimension from 0 to 1, ensuring that different types of data can be compared and processed on the same scale.

[0042] S1.3: Smooth the memory status data by the moving average method;

[0043] Specifically, use the moving average method to smooth the temperature data at the past 10 time points to reduce sudden temperature fluctuations and obtain a more stable temperature trend.

[0044] S1.4: Align the memory status data in time and synchronize it through timestamp alignment;

[0045] Specifically, through timestamp alignment, synchronize the temperature and voltage data from different sources at the same time point so that these data can correctly reflect within the same time window.

[0046] S1.5: Adopt the outlier correction method to remove the noise data in the memory status data.

[0047] Specifically, through the outlier correction method, remove the obviously unreasonable data points, such as the abnormal voltage reading of 0V. These data points may be noise data caused by sensor failures or acquisition errors.

[0048] S2: Based on the preprocessed memory status data, simulate the load on the memory and predict the memory performance level;

[0049] S2.1: Define the high-dimensional space of the memory state by using the preprocessed memory state data as different dimensions.

[0050] Furthermore, consider the preprocessed memory state data (such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate) as multiple different dimensions, where each dimension represents a specific memory state feature. Then, map the specific value of each memory state to the corresponding dimension to form a multi-dimensional memory state vector. To ensure the consistency and comparability of the data in each dimension, all the values will be standardized to the same dimension and range. Finally, define a high-dimensional space through these standardized data, where each memory state sample corresponds to a point in this space, which can reflect the mutual relationship and dynamic evolution between different memory states.

[0051] S2.2: Based on the high-dimensional space of the memory state, construct a load simulation model through a non-linear dynamics model.

[0052] Furthermore, utilize the memory state features (such as temperature, voltage, frequency, etc.) corresponding to each dimension in the high-dimensional space and their mutual relationship to construct a dynamic equation reflecting the change of the memory state. Analyze the interaction between memory states through historical data, and extract the non-linear behavior and time-series dependence relationship that each state feature may present during the load change process. Then, describe these rules through non-linear dynamics equations (such as introducing an exponential decay term and a sine oscillation term). Finally, based on these rules, simulate the evolution process of the memory state under different loads, so as to predict the change trend of the memory performance. This model can effectively capture the dynamic response of the memory state under complex load conditions and provide accurate mathematical support for memory performance prediction.

[0053] S2.3: Analyze the interaction relationship between memory state data from historical data, extract the dynamic evolution law of memory state data during the load change process, and define the simulation rules.

[0054] Furthermore, historical memory state data covering a variety of workload conditions are collected, including multi-dimensional information such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate. Then, advanced data analysis algorithms (such as time series analysis and association rule mining) are applied to identify the complex dependencies between these state parameters and their evolution patterns under different load conditions. Based on this, a non-linear dynamics model is used to model these interaction relationships and capture the dynamic characteristics of the memory state over time. Next, according to the extracted dynamic evolution laws, detailed simulation rules are defined to describe the changes of each state parameter and their synergistic mechanism under specific load conditions. Finally, these rules are applied to the load simulation in the high-dimensional space to ensure that the simulation results can truly reflect the performance of the memory in the actual operating environment, thereby achieving accurate prediction of the memory performance level.

[0055] S2.4: In the high-dimensional space of the memory state, simulate the evolution law of the memory state with the change of load based on the simulation rules, and predict the memory performance level. The expression is: ; Where is the memory performance level, represents the start time of the load simulation, represents the end time of the load simulation, represents the total number of memory state data, is the weight coefficient of the th memory state data, is the non-linear attenuation factor of the th memory state data on the performance, represents the th memory state data at time , is the amplitude factor of the sine function, represents the frequency factor of the load change, represents the overall load intensity at time .

[0056] The specific process is as follows: Map the preprocessed multi-dimensional memory state data into a high-dimensional space to comprehensively capture various characteristics of the memory and their interactions. Then, combine the exponential decay and sine wave functions to dynamically simulate the change characteristics of the memory state and its impact on performance. Through integral operation, the time cumulative effect of the memory performance in different states and the periodic change of the overall load intensity are comprehensively considered. This method not only reflects the memory performance under the current load conditions but also considers the dynamic change trends in historical data, thereby achieving accurate prediction of the memory performance level and ensuring the authenticity and reliability of the test results.

[0057] S3: Simulate memory errors through fault injection, analyze the error detection probability of the memory in real time, and evaluate the fault repair level of the memory;

[0058] S3.1: Define memory error types based on historical fault data and memory error patterns;

[0059] It should be noted that the memory error patterns include the occurrence frequencies and distributions of single-bit errors, multi-bit errors, transient errors, permanent errors, and intermittent errors, as well as the performance characteristics of these errors under different workloads;

[0060] Memory error types include bit flips, address line faults, data line faults, uncorrectable errors (such as errors that cannot be repaired by ECC), and errors caused by other hardware defects, such as errors caused by power fluctuations or instability caused by excessive temperature.

[0061] S3.2: Adopt a random distribution method to randomly distribute memory error types at different positions in the memory and monitor the dynamic changes of memory status data in real time;

[0062] The specific process is as follows: According to the defined memory error types (such as bit flips, address line faults, etc.), inject these error types into different areas of the memory through random selection to simulate various error situations that may occur during actual operation. At the same time, use a real-time monitoring system to continuously track the changes in memory status data, including key indicators such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate, to ensure that any abnormal behavior and its impact on memory performance can be captured in a timely manner.

[0063] S3.3: According to the dynamic changes of memory status data, capture the combined impact of the dynamic changes of each memory status data on the ECC error detection efficiency and the time cumulative effect through complex integration and multiplication operations combined with the Logistic function and power function, and analyze the error detection probability of the memory in real time. The expression is: ; where, is the error detection probability of the memory at time , is the initial time point of error detection, represents the current time, represents the total number of memory status data, is the th sensitivity factor of the th memory status data on error detection, is the standard value of the th memory status data, is the slope parameter of the Logistic function, The decision threshold for memory status data is the maximum expected value of the th memory status data, and is the weight coefficient of the

[0064] th memory status data during the error detection process. It should be noted that the standard value of the memory status data is obtained by analyzing the normal operating status in historical data and determining the typical or average value of each memory status data.

[0065] The decision threshold for memory status data is set based on historical failure data and experimental tests, and is a critical value used to distinguish normal operation from potential error states;

[0066] S3.4: After the memory completes error detection through ECC, combining the error detection probability of the memory and the time from the discovery of a memory error to the completion of repair, introduce logarithmic and sine-squared functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively consider the recovery time and state changes to evaluate the memory fault repair level. The expression is: ; where is the memory fault repair score at time , is the total number of fault occurrences, is the weight coefficient of the th fault, is the proportion of the th fault that has been repaired, is the proportion of the th fault that has not been corrected, is the recovery time of the th fault, is the time that the memory remains unstable after the th fault occurs, is the sensitivity factor of the memory status data to the recovery time, is the th change in the memory status before and after the

[0067] Specifically, the error correction efficiency of each fault is evaluated based on the error detection probability, and the logarithmic function is used to capture the change in this efficiency; then, the sine-squared function is used to quantify the impact of uncorrected errors, reflecting the cumulative effect of these errors in the memory; at the same time, the recovery time of each fault and the change in the memory status are comprehensively considered to analyze the time that the memory remains unstable after the fault occurs and its impact on the overall performance; finally, these factors are integrated and a comprehensive score is obtained through mathematical operations to comprehensively evaluate the memory fault repair level.

[0068] S4: Generate a memory test report based on the memory performance level and the fault repair level.

[0069] S4.1: The memory test report includes the memory performance level, the error detection probability of the memory, the fault repair score of the memory, and optimization suggestions.

[0070] Furthermore, the memory test report reflects the operating conditions and reliability of the memory under different load conditions. Through a detailed analysis of the performance level, key parameters such as the read / write rate, temperature, and voltage of the memory are evaluated; the error detection probability reveals the efficiency of the ECC mechanism in capturing and correcting errors; the fault repair score comprehensively considers the error correction efficiency, recovery time, and state changes to ensure an accurate assessment of the memory stability. Based on these data, the report also provides targeted optimization suggestions to help users improve the memory configuration and management strategies, thereby enhancing the overall memory operation efficiency and stability.

[0071] This embodiment also provides a test system for industrial-grade memory, including: a data acquisition module, a performance level prediction module, a repair level evaluation module, and a test report generation module; the data acquisition module is used to collect memory status data and preprocess the memory status data; the performance level prediction module is used to simulate the load of the memory based on the preprocessed memory status data and predict the memory performance level; the repair level evaluation module is used to simulate memory errors through the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the fault repair level of the memory; the test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

[0072] This embodiment also provides a computer device applicable to the case of the test method for industrial-grade memory, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the test method for industrial-grade memory as proposed in the above embodiment.

[0073] The computer device may be a terminal, which includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be achieved through WIFI, carrier networks, NFC (Near Field Communication), or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads provided on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0074] This embodiment also provides a storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the method for testing industry-level memory proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, abbreviated as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, abbreviated as EEPROM), erasable programmable read-only memory (Erasable Programmable Read Only Memory, abbreviated as EPROM), programmable read-only memory (Programmable Red-Only Memory, abbreviated as PROM), read-only memory (Read-Only Memory, abbreviated as ROM), magnetic memory, flash memory, magnetic disks, or optical discs.

[0075] In summary, the present invention: simulates memory errors through the fault injection method, combines historical fault data and memory error patterns, monitors the change of memory status in real time, and evaluates the error detection probability of the memory through complex mathematical operations. This method can accurately simulate the performance of the memory under different fault conditions, quantify the efficiency of memory error detection, and provide data support for the fault tolerance mechanism and repair ability of the memory. The present invention can not only simulate and evaluate the real error response of the memory in the experimental environment, but also provide an important basis for optimizing the stability and reliability of the memory, and is especially suitable for industry-level memory applications with high load and high reliability requirements.

[0076] Example 2. Referring to Table 1, this is the second example of the present invention. To further verify the technical solution of the present invention, experimental simulation data of the testing method for industrial-grade memory is given.

[0077] To verify the effectiveness of an industrial-grade memory testing method proposed by the present invention, a set of comparative experiments was designed. The experimental objects included two different testing methods: one was traditional memory using traditional methods, and the other was improved memory applying the method of the present invention. Each memory instance was tested under the same hardware configuration and environmental conditions to ensure fairness and comparability.

[0078] First, to verify the effectiveness of the method of the present invention, a set of comparative experiments was designed. The experimental objects included traditional memory using traditional methods and improved memory applying the method of the present invention. Both were tested under the same hardware configuration and environment to ensure fairness. Data such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate were collected in real time through high-precision sensors and transmitted to the central processing unit.

[0079] Second, the method of the present invention preprocessed the collected data, including standardization, smoothing processing by the moving average method, timestamp alignment, and outlier correction. Based on these preprocessed data, a high-dimensional space was constructed, the memory state characteristics were defined, and a nonlinear dynamics model was introduced to simulate the dynamic changes under different load conditions.

[0080] Then, to evaluate the error detection and repair capabilities, a fault injection experiment was conducted. According to common memory error patterns, error types were randomly distributed and the changes in memory state data were monitored in real time. The method of the present invention used complex operations combined with the Logistic function and power function to analyze the error detection probability, and evaluated the fault repair level by introducing the logarithmic function and sine squared function.

[0081] Finally, a detailed memory test report was generated, including performance level, error detection probability, fault repair score, and optimization suggestions. The experimental data showed that the method of the present invention was significantly superior to the traditional method in terms of performance, error detection, and fault repair.

[0082] The traditional method adopted simple data aggregation and preliminary analysis, relied on preset fixed thresholds to detect abnormal situations, and used relatively static and linear models in load simulation and fault injection, unable to comprehensively capture the dynamic changes and nonlinear behaviors of the memory state.

[0083] Specifically, as shown in Table 1 below:

[0084] Table 1 Comparative data table of memory performance and fault repair

[0085] Through the data analysis of the above table, it can be clearly seen that the method of the present invention is significantly superior to the traditional method in multiple key performance indicators. By introducing comprehensive preprocessing steps, non-linear dynamic models, and complex mathematical operations, the present invention has greatly improved the accuracy and reliability of memory testing. For example, at a temperature of 63.1 °C and a voltage of 1.21 V, the read and write rate of the method of the present invention reaches 3410 MB / s, while the traditional method is only 3175 MB / s; at the same time, the error detection probability of the method of the present invention is as high as 98.4%, far higher than 94.6% of the traditional method. In addition, in terms of the fault repair score, the method of the present invention also performs excellently, with a score of 91.8, showing a significant improvement compared to 77.2 of the traditional method. These data fully demonstrate the superiority of the method of the present invention in improving memory performance, enhancing error detection ability, and optimizing fault repair.

[0086] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A method for testing industrial-grade memory, characterized in that: include, Collect memory status data and pre-process the memory status data; Based on the preprocessed memory status data, the memory load is simulated to predict the memory performance level; Simulate memory errors through fault injection, analyze the memory error detection probability in real time, and evaluate the memory fault repair level; Generate a memory test report based on memory performance level and fault recovery level.

2. The method for testing industrial-grade memory according to claim 1, characterized in that: The memory status data includes the temperature, voltage, frequency, read and write speed, error rate and usage rate of the memory.

3. The method for testing industrial-grade memory as claimed in claim 2, characterized in that: The specific steps of preprocessing the memory status data are as follows: Standardization is adopted to adjust different types of memory status data to a unified dimension and range; The memory status data is smoothed by the sliding average method; Through timestamp alignment, the memory status data is time aligned and synchronized; The outlier correction method is used to remove noise data in the memory state data.

4. The method for testing industrial-grade memory as claimed in claim 3, characterized in that: Based on the preprocessed memory status data, the memory load is simulated to predict the memory performance level. The specific steps are as follows: The preprocessed memory state data is used as different dimensions to define the high-dimensional space of memory state; Based on the high-dimensional space of memory state, a load simulation model is constructed through a nonlinear dynamic model; By analyzing the interactive relationship between memory status data from historical data, the dynamic evolution law of memory status data during load changes is extracted, and simulation rules are defined; In the high-dimensional space of memory state, the evolution law of memory state with load change is simulated based on simulation rules to predict the memory performance level. The expression is: ； in, is the memory performance level, Indicates the start time of the load simulation. Indicates the end time of the load simulation. Indicates the total number of memory status data, It is The weight coefficient of memory status data, It is The nonlinear attenuation factor of the memory state data's impact on performance, Indicates Memory status data at time The value of is the amplitude factor of the sine function, The frequency factor representing the load change, Indicates at time Under the overall load strength.

5. The method for testing industrial-grade memory according to claim 4, characterized in that: The fault injection method is used to simulate memory errors and analyze the error detection probability of memory in real time. The specific steps are as follows: Define memory error types based on historical failure data and memory error patterns; The memory error types are randomly distributed in different locations of the memory by using a random distribution method, and the dynamic changes of the memory status data are monitored in real time; According to the dynamic changes of memory status data, through complex integration and product operations combined with Logistic function and power function, the joint impact of the dynamic changes of each memory status data on the ECC error detection efficiency and the time accumulation effect are captured, and the error detection probability of the memory is analyzed in real time. The expression is: ； in, For time The probability of memory error detection is is the initial time point of error detection, Indicates the current time. Indicates the total number of memory status data. It is The sensitivity factor of the memory state data on error detection, It is The standard value of memory status data, is the slope parameter of the Logistic function, It is The decision threshold of memory status data, It is The maximum expected value of memory status data, It is The weight coefficient of each memory status data in the error detection process.

6. The method for testing industrial-grade memory according to claim 5, characterized in that: The specific steps of evaluating the fault repair level of the memory are as follows: After the memory completes error detection through ECC, combined with the memory error detection probability The time from the discovery of memory errors to the completion of repair is calculated by introducing logarithmic functions and sine square functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively consider the recovery time and state changes to evaluate the memory fault repair level. The expression is: ； in, For time The memory fault repair score, is the total number of failures, It is The weight coefficient of the secondary fault, It is The proportion of faults that are repaired, It is The proportion of failures that are not corrected, It is The recovery time of the fault, It is How long the memory remains unstable after the first failure occurs, is the sensitivity factor of the memory state data on the recovery time, It is The amount of change in memory state before and after the failure.

7. The method for testing industrial-grade memory according to claim 6, characterized in that: The memory test report includes memory performance level, memory error detection probability, memory fault repair score and optimization suggestions.

8. An industry-level memory testing system, based on the industry-level memory testing method according to any one of claims 1 to 7, characterized in that: Including, data acquisition module, performance level prediction module, repair level assessment module and test report generation module; A data acquisition module is used to collect memory status data and pre-process the memory status data; A performance level prediction module is used to simulate the memory load and predict the memory performance level based on the preprocessed memory status data; The repair level assessment module is used to simulate memory errors through fault injection, analyze the error detection probability of memory in real time, and evaluate the fault repair level of memory; The test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the industry-level memory testing method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the industry-level memory testing method described in any one of claims 1 to 7 are implemented.

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