Semiconductor device and method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device, comprising: providing one or more packages wherein each of the one or more packages comprises: a first substrate, the first substrate comprises a first surface and a second surface, a protective tape attached to the first surface of the first substrate, one or more electronic components mounted on the second surface of the first substrate, and one or more conductive structures mounted on the second surface of the second substrate; mounting the one or more packages onto a first surface of a second substrate, wherein the one or more conductive structures connect the first substrate and the second substrate; applying a molding material to cover the one or more electronic components and the one or more conductive structures; and removing the protective tape from each of the one or more packages.

Description

Technical Field

[0001] This application generally relates to semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic devices to be smaller, faster, and more performant while packing more functionality into a single device. One solution is System-in-Package (SiP). SiP is a functional electronic system or subsystem that includes two or more heterogeneous semiconductor dies, such as logic chips, memories, integrated passive devices (IPDs), RF filters, sensors, heat sinks, or antennas, in a single package. Also, double-sided mounting (DSM) packages are an option to improve the integration level of semiconductor devices.

[0003] In SiP or DSM devices, some components or packages should be covered with molding materials for protection. However, conventional molding processes may cause several problems such as mold flash. If mold flash occurs, the molding material may leak into the interface or onto the surface of the SiP and occupy some spaces where it is not desired. For example, molding material leakage may form on contact pads or other similar conductive patterns, preventing solder balls from being further mounted on the conductive patterns and electrically connected to the conductive patterns.

[0004] Therefore, there is a need for further improvement in the method for forming molding materials in semiconductor devices. Summary of the Invention

[0005] The objective of this application is to provide a method for forming a molding material in a semiconductor device to improve the quality of the molding material.

[0006] According to one aspect of this application, a method for manufacturing a semiconductor device is disclosed. The method includes: providing one or more packages, where each of the one or more packages includes: a first substrate, the first substrate including a first surface and a second surface, a protective tape attached to the first surface of the first substrate, one or more electronic components mounted on the second surface of the first substrate, and one or more conductive structures mounted on the second surface of the first substrate; mounting the one or more packages on a first surface of a second substrate, where the one or more conductive structures connect the first substrate and the second substrate; applying a molding material to cover the one or more electronic components and the one or more conductive structures; and removing the protective tape from each of the one or more packages.

[0007] According to another aspect of the present application, there is provided a semiconductor device that can be formed by the method of the above aspect.

[0008] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory, and not restrictive of the present invention. In addition, the accompanying drawings incorporated in and constituting a part of this specification illustrate embodiments of the present invention and, together with the specification, are used to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings cited herein constitute a part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless specifically stated otherwise in the detailed description, and readers of the specification should not make the opposite inference.

[0010] Figure 1 A cross-sectional view showing a semiconductor device formed by a conventional method.

[0011] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0012] Figures 3A to 3H Showing a method for manufacturing a semiconductor device Figure 2 of.

[0013] Figure 4 A flowchart showing a method for manufacturing a package according to an embodiment of the present application.

[0014] Figures 5A to 5D Showing a method for manufacturing a package Figure 4 of.

[0015] The same reference numerals will be used throughout the drawings to represent the same or similar parts. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art can further utilize other embodiments of the present application and make logical, mechanical, etc. changes without departing from the spirit or scope of the present application. Therefore, readers of the following detailed description should not interpret the description in a restrictive manner, and only the scope of the embodiments of the present application is defined by the appended claims.

[0017] In this application, unless otherwise expressly stated, the use of the singular includes the plural. In this application, unless otherwise specified, the use of "or" means "and / or". Additionally, the use of the term "comprising" and other forms such as "comprises" and "containing" is not limiting. Further, unless otherwise expressly stated, terms such as "element" or "component" cover elements and components that include one unit, as well as elements and components that include more than one subunit. Additionally, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0018] As used herein, spatially relative terms, such as "beneath", "below", "above", "over", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "side", and the like, may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or intervening elements may be present.

[0019] Figure 1 A cross-sectional view showing a semiconductor device 100 formed according to a conventional method.

[0020] As Figure 1 shown, the semiconductor device 100 includes a first substrate 101 having a first surface 102 and a second surface 103 opposite the first surface 102. The first substrate 101 may include a redistribution structure (RDS) having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. One or more electronic components 104 and conductive structures 105 are mounted on the second surface 103 of the first substrate 101. One or more conductive structures 106 are mounted on the second surface 103 of the first substrate 101 to electrically connect the semiconductor device 100 to another external device such as a main circuit board. The conductive structures 105 and 106 may include solder balls and / or metal pillars, such as copper pillars, or any other similar structures or elements that provide the function of electrical interconnection. The first substrate 101, the electronic components 104, the conductive structures 105 and 106, and the molding material 111 that seals these individual elements and structures together form a first package 107, which is part of the semiconductor device 100.

[0021] In addition, the semiconductor device 100 includes a second substrate 108 having a first surface 109 and a second surface 110 opposite the first surface 109. The second substrate 108 may include a redistribution structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. A first package 107 is mounted on the first surface 109 of the second substrate 108, wherein a conductive structure 105 electrically connects the first substrate 101 and the second substrate 108 such that electrical signals can be transmitted between the electronic components mounted on the first substrate 101 and the second substrate 108. It can be seen that a molding material 111 is formed between the first substrate 101 and the second substrate 108 to cover the electronic components 104 and the conductive structure 105, thereby achieving protection and mechanically connecting the first substrate 101 and the second substrate 108 to enhance the integrity and stability of the semiconductor device 100.

[0022] When the semiconductor device 100 is formed using a conventional process, especially when the molding material 111 is applied to cover the electronic components 104 and the conductive structure 105, a mold flash 114 may be formed on the first surface 102 of the first substrate 101 and around the edge of the first substrate 101, which is undesirable for the semiconductor device 100. The mold flash 114 may further advance along the first surface 102 and occupy some space below some of the conductive patterns on the first surface 102, and these spaces are reserved for mounting the conductive structure 106. Therefore, in some cases, the conductive structure 106 cannot be well mounted on the first surface 102, and the yield of the semiconductor device 100 may be reduced.

[0023] To solve the foregoing problems, according to some embodiments of the present application, a method for manufacturing a semiconductor device is provided. Using this method, first, a protective tape is attached to a position on the first surface of the first substrate where it is not desired to form any molding material. The protective tape can then cover the first surface and prevent the formation of molding material thereon. After the molding material is coated to cover the electronic components and the conductive structure, the protective tape can be removed from the first surface of the first substrate so that no mold flash is formed thereon.

[0024] Reference Figure 2 FIG. shows a flowchart of a method 200 for manufacturing a semiconductor device according to an embodiment of the present application. As Figure 2As shown, method 200 may begin with providing one or more packages in block 201. Each of the one or more packages may include a first substrate, a protective tape, one or more electronic components, and one or more conductive structures. Each package may include a first substrate having a first surface and a second surface, a protective tape attached to the first surface of the first substrate, one or more electronic components mounted on the second surface of the first substrate, and one or more conductive structures mounted on the second surface of the first substrate. In block 203, the one or more packages are mounted on the first surface of a second substrate. Then, in block 205, a molding material is applied to cover the one or more electronic components and the one or more conductive structures. After applying the molding material, in block 207, the protective tape is removed from each of the one or more packages.

[0025] Reference Figures 3A to 3H , which shows a cross-sectional view that illustrates various blocks of a method for manufacturing a semiconductor device. Hereinafter, the method will be described in more detail with reference to Figure 2 and Figures 3A to 3H the method will be described in more detail.

[0026] Specifically, the process begins with providing one or more packages, Figure 3AShown is an example of one of a plurality of packages 300. It will be appreciated that other packages may have the same structure or a different structure. Package 300 includes a first substrate 301, which may be a laminate interposer, a PCB, a wafer form, a strip interposer, a lead frame, or any other suitable substrate. The first substrate 301 may include one or more insulating layers or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed above or between the insulating layers. The first substrate 301 may include one or more laminated layers of pre-impregnated polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3, and a composition of phenolic cotton paper, epoxy resin, resin, glass fabric, frosted glass, polyester, or other reinforcing fibers or fabrics. The insulating layer may comprise one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other materials having similar insulating and structural properties. The first substrate 301 may also be a multi-layer flexible laminate, ceramic, copper-clad laminate, glass, or semiconductor wafer, the semiconductor wafer including an active surface containing one or more transistors, diodes, and other circuit elements to implement an analog circuit or a digital circuit. The first substrate 301 may include one or more conductive layers or redistribution layers (RDLs) formed using sputtering, electroplating, electroless plating, or other suitable deposition processes. The conductive layer may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive materials.

[0027] As Figure 3A shown, the first substrate 301 includes a first surface 302 and a second surface 303 opposite the first surface 302. Similar to Figure 1As shown, one or more electronic components 304 and one or more conductive structures 305 are mounted on the second surface 303 of the first substrate 301, and the number of the electronic components 304 and the conductive structures 305 mounted on the second surface 303 of the first substrate 301 can be adjusted according to actual needs, and the present application does not limit this. The electronic components 304 may include one or more semiconductor components or discrete electrical devices, such as resistors, capacitors, etc. In addition, a protective tape 306 is attached to the first surface 302 of the first substrate 301. In an embodiment of the present application, the protective tape 306 may be an ultraviolet tape, which can be easily removed from the first substrate 301. Specifically, the UV protective tape 306 can be hardened after being irradiated with UV light having a specific wavelength range. The hardened ultraviolet-sensitive tape can provide effective protection for the underlying first surface 302 and the conductive pattern formed thereon. In some embodiments, the UV protective layer 306 may include multiple layers of various UV-sensitive tapes or other similar tapes. In addition, the UV-sensitive tape in direct contact with the underlying first surface 302 may have high adhesion characteristics, so as to avoid vesicles or gaps between the UV protective tape 306 and the first surface 302. The upper UV-sensitive tape layer may have greater hardness after being irradiated with UV light and can therefore be easily removed. In some other embodiments, the UV protective layer 306 may include materials such as polymers, plastics, ceramics, etc.

[0028] As Figure 3B shown, a second substrate 307 is provided, which may be a substrate strip having various similar or identical sections. The one or more packages 300 are mounted on the first surface 308 of the second substrate 307, wherein the protective tape 306 faces outward and away from the second substrate 307. In Figure 3B the embodiment shown, three packages 300 are mounted on the first surface 308 of the second substrate 307, so as to form a semiconductor device array 320, and the semiconductor device array 320 can be singulated by a process to form a plurality of independent semiconductor devices, as described below. However, the number of packages 300 mounted on the first surface 308 of the second substrate 307 can be adjusted according to actual needs, and the present application does not limit this. For example, in some embodiments, only one package 300 is mounted on the first surface 308 of the second substrate 307, thus forming a single semiconductor device instead of a semiconductor device array, and no singulation process is required.

[0029] It can be seen that the conductive structure 305 of each package 300 connects the first substrate 301 of each package 300 to the second substrate 307, enabling the transmission of electrical signals between the first substrate 301 and the second substrate 307 or, specifically, the electronic components mounted on the substrates 301 and 307. In some embodiments, the conductive structure 305 can be a solder ball or other similar interconnect structure. When a solder ball is used as the conductive structure 305, a reflow process can be implemented on the first substrate, the second substrate, and the components and structures mounted thereon to reflow the solder ball and improve its attachment to the substrate. Thus, preferably, the substrate can withstand the temperature during the reflow of the solder ball.

[0030] Subsequently, referring to Figure 3C , a molding material 310 is applied on the first surface 308 of the second substrate 307 and around one or more packages 300 mounted thereon to cover one or more electronic components 304 and one or more conductive structures 305 on the package 300. Thus, one or more electronic components 304 and one or more conductive structures 305, which may be fragile and sensitive, are protected by the molding material 310. The molding material 310 can be a high-k molding material or a low-α molding material (i.e., a material with a low content of radioactive elements such as uranium, thorium, or americium, e.g., 1 ppb or less), or any other suitable molding material. In some embodiments, the molding material 310 can be formed by an injection molding process or a film-assisting molding (FAM) process. During the molding process, the protective tape 306 can be in direct contact with the mold chase used to perform the molding process, and thus it can prevent the molding material from forming on the first surface 302 of the first substrate 301. Even if the molding material may leak into the interface between the protective tape 306 and the mold, due to the presence of the protective tape 306, the molding material cannot form on the first surface 302.

[0031] Referring to Figure 3D, after the coating of the molding material 310, the protective tape is removed from each of the one or more packages 300. In some embodiments, in the case where the UV tape is used as the protective tape, before removing the protective tape, an irradiation process may be performed on the protective tape by UV light to reduce the adhesiveness of the protective tape and facilitate the removal of the protective tape. It can be seen that with the use of the protective tape, no mold flash is formed on the first surface 302 of the first substrate 301. Even if some molding material may be formed on the protective tape during the molding process, it can be removed by using the protective tape. In this way, the quality of the molding material is improved. It can be understood that although some sidewalls may be formed between the protective tapes of every two adjacent packages 300 before removing the protective tape, they do not affect the entire semiconductor device. For example, the sidewalls may be formed at the saw street between individual semiconductor devices, which can be removed when the semiconductor devices are singulated from each other. In some other cases, an additional molding removal process or a lamination process (such as by the SRT (strip router) process) may be performed to remove these sidewalls.

[0032] Figures 3E - 3H Some additional processes for the semiconductor device are shown after removing the protective tape from each of the one or more packages. These processes can be performed to obtain a semiconductor device with a more complex structure, and these processes can be omitted in some embodiments. In addition, in some other embodiments, some alternative or additional processes may be performed on the semiconductor device.

[0033] As Figure 3E shown, after removing the protective tape from each of the one or more packages 300, at least one conductive structure 311 is mounted on the first surface 302 of the first substrate 301 of each package 300 to facilitate its connection to an external device. In some embodiments, the conductive structure 311 includes solder balls and / or metal pillars. For example, the conductive structure 311 can be formed by first dispensing solder paste on the first surface 302 through a solder mask and then dispensing flux around the solder paste on the first surface 302. In some other embodiments, the conductive structure 311 can be formed by stencil printing the solder paste onto the first surface 302.

[0034] Subsequently, referring to Figure 3F, flip the semiconductor device, and mount at least one electronic component 312 and / or at least one second package 313 corresponding to each of one or more first packages 300 onto the second surface 309 of the second substrate 307. In this embodiment, one electronic component 312 and one second package 313 corresponding to each of one or more first packages 300 are mounted onto the second surface 309 of the second substrate 307. However, the number of electronic components 312 and second packages 313 corresponding to each package can be configured based on actual needs, and the present application does not limit this. For example, in some embodiments, for each package 300, no electronic component 312 is mounted on the second surface 309 of the second substrate 307, but two second packages 313 are mounted; in some other embodiments, for each package 300, three electronic components 312 are mounted on the second surface 309 of the second substrate 307, but no second package 313 is mounted. In some embodiments, the electronic component 312 and / or the second package 313 may include a semiconductor component or a discrete electrical device. In some embodiments, another molding material may be formed on the second surface 309 to at least partially seal the electronic component 312 and / or the second package 313 to achieve sealing, which is not shown in Figure 3F is not shown.

[0035] Reference Figure 3G , since more than one first package 300 is mounted onto the first surface 308 of the second substrate 307, a semiconductor device array 320 with multiple units is formed. As shown, the semiconductor device array 320 can be divided into more than one semiconductor device 330 through a singulation process, and each semiconductor device 330 includes at least one first package 300. The number of first packages 300 included in each semiconductor device 300 can be configured based on actual needs, such as one, two, or three, and the present application does not limit this. In some embodiments, the singulation process may include blade sawing, laser scribing, or SRT (strip router).

[0036] Optionally, referring to Figure 3H , the singulation process can be performed along the side surface of the first substrate 301 of each first package 300, so that the side surface of the first substrate 301 can be exposed after the singulation process.

[0037] Reference Figure 4 , according to an embodiment of the present application, a flowchart of a method 400 for manufacturing a package is shown, such as for manufacturing as Figure 3AThe first package 300 shown in

[0038] Reference Figures 5A to 5D shows a cross-sectional view, which shows the various blocks of a method for manufacturing a package. Hereinafter, reference will be made to Figure 4 and Figures 5A to 5D to describe the method in more detail.

[0039] As Figure 5A shown, a substrate 501 is provided, which includes a first surface 502 and a second surface 503 opposite to the first surface 502. The substrate 501 may be similar to Figures 3A to 3H the first substrate 301 shown in

[0040] Reference Figure 5B is made to Figures 3A to 3C where a protective tape 504 is attached to the first surface 502 of the substrate 501. The protective tape 504 may be similar to

[0041] the protective tape 306 shown in Figure 5C and will not be repeated here. Figures 3A to 3H Subsequently, as

[0042] shown, one or more electronic components 505 and one or more conductive structures 506 are mounted on the second surface 503 of the substrate 501. The electronic components 505 and the conductive structures 506 may be similar to the electronic components 304 and the conductive structures 305 shown in Figure 5D respectively, which will not be repeated here. Similarly, the number of the electronic components 505 and the conductive structures 506 mounted on the second surface 503 of the substrate 501 may be configured based on actual needs, and the present application does not limit this. In this embodiment, more than one electronic component 505 and more than one conductive structure 506 are mounted on the second surface 503 of the substrate 501 to form a package array 500 instead of a single package. Therefore, a singulation process can be performed on the package array 500 to divide the package array 500 into multiple packages. However, in some embodiments, fewer electronic components 505 and fewer conductive structures 506 are mounted on the second surface 503 of the substrate 501 to form only a single package, and then the singulation process is not required.

[0043] Reference Figures 3A to 3HThe first package 300 shown in [description] is used to form a semiconductor device without molding flash.

[0044] The discussion herein includes a number of illustrative figures that show various portions of semiconductor devices and methods of manufacturing semiconductor devices. For clarity of illustration, these figures do not show all aspects of each example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein.

[0045] Various embodiments have been described herein with reference to the accompanying figures. However, it will be apparent that various modifications and changes can be made thereto, and additional embodiments can be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Further, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Accordingly, the present application and the embodiments herein are intended to be considered only as exemplary, with the true scope and spirit of the invention being indicated by the list of appended exemplary claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, the method comprises: providing one or more packages, wherein each of the one or more packages comprises: a first substrate including a first surface and a second surface, a protective tape attached to the first surface of the first substrate, one or more electronic components mounted on the second surface of the first substrate, and one or more conductive structures mounted on the second surface of the first substrate; mounting the one or more packages on a first surface of a second substrate, wherein the one or more conductive structures connect the first substrate and the second substrate; applying a molding material to cover the one or more electronic components and the one or more conductive structures; and removing the protective tape from each of the one or more packages.

2. The method according to claim 1, characterized in that, the one or more packages are formed by the following steps: providing the first substrate; attaching the protective tape to the first surface of the first substrate; mounting the one or more electronic components and the one or more conductive structures on the second surface of the first substrate.

3. The method according to claim 2, characterized in that, each of the one or more packages is separated from a package array by a singulation process.

4. The method according to claim 1, characterized in that, the method further comprises: after removing the protective tape, mounting at least one conductive structure on the first surface of the first substrate of each package to connect the semiconductor device to another device.

5. The method according to claim 1, characterized in that, the one or more packages are one or more first packages, and the method further comprises: mounting at least one electronic component corresponding to each first package of the one or more first packages and / or at least one second package on a second surface of the second substrate.

6. The method according to claim 1, characterized in that, mounting more than one package on the first surface of the second substrate to form a semiconductor device array, and the method further comprises: dividing the semiconductor device array into more than one semiconductor device by a singulation process, wherein each semiconductor device comprises at least one package.

7. The method according to claim 1 or claim 4, characterized in that, the conductive structure is mounted via a flux or solder paste.

8. The method according to claim 1 or claim 4, characterized in that, the conductive structure comprises solder balls and / or copper pillars.

9. The method according to claim 3 or claim 6, characterized in that, the singulation process comprises blade sawing, laser scribing or strip routing SRT.

10. A method for manufacturing a semiconductor device, characterized in that, the method comprises: providing a first substrate; attaching a protective tape to the first surface of the first substrate; mounting more than one electronic component and more than one conductive structure on the second surface of the first substrate to form a package array; The encapsulation array is divided into more than one first encapsulation by a singulation process; The more than one first encapsulation is mounted on a first surface of a second substrate, wherein a conductive structure of the first encapsulation connects a first substrate of each encapsulation in the first encapsulation to the second substrate; A molding material is applied to cover the electronic components and the conductive structure of each encapsulation in the first encapsulation; The protective tape is removed from each first encapsulation in the first encapsulation; At least one conductive structure is mounted on a first surface of a first substrate of each first encapsulation in the first encapsulation; At least one electronic component and / or at least one second encapsulation corresponding to each first encapsulation in the first encapsulation is mounted on a second surface of the second substrate to form an array of semiconductor devices; and The array of semiconductor devices is divided into more than one semiconductor device by a singulation process, wherein each semiconductor device in the semiconductor devices includes at least one first encapsulation.

11. A semiconductor device, characterized in that, the semiconductor device is formed by the method according to any one of claims 1 to 10.

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