Method of manufacturing semiconductor device, corresponding substrate and semiconductor device

Abstract

The embodiment of the invention relates to a method for manufacturing a semiconductor device, a corresponding substrate and a semiconductor device. The semiconductor die is arranged at the mounting surface of the substrate via a conductive pillar protruding from the semiconductor die, wherein a distal end of the conductive pillar is in electrical contact with the mounting surface of the substrate. The substrate has two or more alignment bushings at the mounting surface, the two or more alignment bushings configured to have respective conductive posts inserted therein. Selected ones of the conductive pillars protruding from the semiconductor die are inserted into two or more alignment bushings at the mounting surface of the substrate. A post inserted into the alignment sleeve resists movement of the semiconductor die relative to the substrate.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of Italian Patent Application No. 102023000024210, filed on November 15, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] This description relates to the manufacture of semiconductor devices.

[0004] One or more embodiments can be applied to the manufacture of integrated circuit (IC) semiconductor devices, such as, for example, DC-DC converters or microcontrollers. Background Art

[0005] In current manufacturing processes of (integrated circuit IC) semiconductor devices (e.g., microcontrollers or DC-DC converters), semiconductor dies or chips can be mounted on a substrate via so-called flip-chip mounting.

[0006] In semiconductor devices processed via flip-chip mounting, a plurality of conductive pillars (or bumps) are provided on the surface of the semiconductor die.

[0007] Solder material is provided at the terminal portions of the conductive pillars, which are configured to contact the substrate to form a desired electrical coupling between the semiconductor die and the substrate after reflow.

[0008] During reflow, the semiconductor die may undesirably move relative to the substrate, resulting in an inadequate electrical coupling between the semiconductor die and the substrate.

[0009] U.S. Patent Application Publication No. 2021 / 0265247 (incorporated herein by reference) illustrates the latest progress in the manufacturing method of semiconductor devices, aiming to provide self-alignment features for flip-chip devices.

[0010] U.S. Patent Application Publication Nos. 2012 / 0326322, 2018 / 0019191, and 2017 / 0309595 (each incorporated herein by reference) provide background information in the relevant technical field.

[0011] There is a need in the art to overcome the drawbacks discussed above. Summary of the Invention

[0012] One or more embodiments relate to methods.

[0013] One or more embodiments relate to corresponding intermediate products. A substrate used in manufacturing a semiconductor device and adapted to be provided by a supplier to a semiconductor device manufacturer may exemplify such an intermediate product.

[0014] One or more embodiments relate to corresponding semiconductor devices including such a substrate.

[0015] The solution described herein involves providing an alignment formation on a substrate to facilitate aligning and mounting semiconductor dies in a flip-chip orientation on the substrate.

[0016] In the solution described herein, the alignment formation may be provided on the substrate via an additive manufacturing technique such as, for example, laser-induced forward transfer (LIFT).

[0017] In the solution described herein, the alignment formation provided on the substrate also facilitates reducing undesired displacement / movement of the semiconductor dies mounted on the substrate during handling and / or processing.

[0018] The solution described herein may be advantageously applied to flip-chip packaged devices for, e.g., DC-DC converters or microcontrollers. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0020] Figure 1 is a cross-sectional view illustrating the structure of a semiconductor device;

[0021] Figure 2 is a plan view of a substrate for a semiconductor device;

[0022] Figure 3 is a perspective view of the structure of a semiconductor device;

[0023] Figure 4 is Figure 3 an enlarged view of the portion indicated by arrow IV in

[0024] Figures 5A to 5C is a cross-sectional view illustrating a sequence of steps in a manufacturing process of a semiconductor device. DETAILED DESCRIPTION

[0025] Unless otherwise noted, corresponding reference numerals in different figures generally refer to corresponding parts.

[0026] The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0027] The edges of the features drawn in the figures do not necessarily indicate the termination of the scope of the features.

[0028] In the following description, various specific details are illustrated to provide a deeper understanding of various examples of the embodiments according to the description. The embodiments can be obtained without one or more specific details or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that aspects of the embodiments are not obscured.

[0029] Reference to "an embodiment" or "an embodiment" in the framework of this description is intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in an embodiment," etc., appearing in various points of this description do not necessarily refer to the same embodiment in their entirety. Furthermore, particular configurations, structures, or characteristics may be combined in one or more embodiments in any suitable manner. The reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0030] Figure 1 1 is a cross-sectional view of a semiconductor device 10 of the type commonly referred to as a flip chip quad flat no-lead (FC-QFN). Figure 1 The FC-QFN type semiconductor device 10 shown may be suitable for use in, for example, a DC-DC converter or a microcontroller.

[0031] Figure 1 The device 10 illustrated in includes a conductive substrate or lead frame 12 including a die pad 12A having an array of conductive leads 12B arranged around a perimeter of the die pad 12A.

[0032] The name "leadframe" or "lead frame" is currently used (see, e.g., the U.S. Patent and Trademark Office's USPC Comprehensive Glossary) to indicate the metal frame that provides support for an integrated circuit chip or die, and the electrical leads that interconnect the integrated circuits in the die or chip to other electrical components or contacts.

[0033] In some cases, the lead frame can be a molded type, that is, a type of lead frame that includes an engraved metal (e.g., copper) structure and includes empty spaces, wherein the engraved metal structure is formed by etching a metal sheet and the empty spaces are filled with a resin that is "pre-molded" on the engraved metal structure.

[0034] In such Figure 1In a flip-chip device such as the FC-QFN device 10 illustrated, an integrated circuit (IC) semiconductor die 14 can be mounted on a substrate 12 (e.g., a lead frame) via conductive pillars or bumps 120 provided on the surface of the semiconductor die 14.

[0035] The conductive pillars 120 can be formed by providing a conductive material (e.g., a metal such as copper) via a deposition process such as, for example, electroplating or any technique known to those skilled in the art.

[0036] Subsequently, with the conductive pillars 120 provided, the semiconductor die 14 is mounted on the substrate 12 (e.g., a lead frame) in a flip-chip orientation by bringing the terminal portions of the pillars 120 provided on the surface of the semiconductor die 14 into contact with the substrate 12.

[0037] As Figure 1 illustrated, a plurality of pillars 120 can contact the leads 12B and die pads 12A of the substrate 12 to provide a desired electrical coupling between the semiconductor die 14 and the die pads 12A (e.g., providing ground for the device 10) and / or the leads 12B (e.g., providing contacts for input / output I / O signals).

[0038] A solder material (e.g., tin) can be provided at the ends of the pillars 120 to facilitate the formation of an electrical coupling between the pillars 120 and the substrate / lead frame 12. The solder material (not visible in Figure 1 for simplicity) is illustrated in Figures 5A to 5C sequence and is referred to herein by the reference numeral SM.

[0039] As is known to those skilled in the art, a reflow step can be performed to form an electrical coupling between the pillars 120 and the substrate 12 (die pads 12A or leads) via the solder material provided at the terminal portions of the pillars 120 in contact with the substrate 12.

[0040] As Figure 1 illustrated and described above, mounting the semiconductor die 14 on a lead frame 12 (or more generally a substrate) is commonly referred to as flip-chip mounting.

[0041] Figure 1 The device 10 illustrated in

[0042] As Figure 1The illustrated semiconductor device 10 may be configured to be mounted on a support substrate such as a printed circuit board PCB, for example, via a solder material (such as solder paste) provided on the bottom / back surface of the device 10.

[0043] The device 10 as described above is conventional in the art, which makes it unnecessary to provide a more detailed description herein.

[0044] As described, conventional processing involves placing a semiconductor die 14 on a substrate. The semiconductor die 14 is provided with conductive pillars 120. The processing step is generally referred to as pick and place.

[0045] The pick and place operation can represent a relatively delicate processing step because misalignment of the semiconductor die 14 on the substrate 12 may cause device failure (and / or rejection).

[0046] Misalignment may cause, for example, the conductive pillars 120 not to contact the desired leads 12B of the substrate 12, thus resulting in insufficient electrical coupling between the semiconductor die 14 and the substrate 12.

[0047] In addition, even when adequately placed on the substrate, the semiconductor die 14 may undesirably move from its position during processing; for example, it has been observed that the reflow of the solder material provided at the tips of the conductive pillars 120 causes the semiconductor die 14 to rotate and move relative to the substrate 12.

[0048] According to conventional methods, the rotation (and more generally, movement) of the semiconductor die 14 during reflow can be countered via silver spots provided on the substrate 12 at positions configured to contact the conductive pillars 120. However, such conventional methods do not provide an adequate solution to the above problems.

[0049] The solution described herein involves providing an alignment structure on the substrate to facilitate the mounting of a semiconductor die with a flip-chip orientation on the substrate.

[0050] In the solution described herein, the alignment structure may include an annular enclosure provided on the surface of the substrate and configured to have conductive pillars inserted into the annular enclosure to counter the undesired movement of the semiconductor die 14 during handling / processing.

[0051] In the solution described herein, the alignment structure may be provided on the substrate via additive manufacturing techniques such as, for example, jetting or laser-induced forward transfer (LIFT).

[0052] In the solution described herein, the alignment structures provided on the substrate provide reference points for pick-and-place operations, thus facilitating the mounting operation.

[0053] The solution described herein can advantageously be applied to flip-chip package devices for, e.g., DC-DC converters or microcontrollers.

[0054] Figure 2 Illustrated are (two) substrates 12, such as lead frames, the substrates 12 being provided with alignment structures 100 according to embodiments of the present description. Figure 2 The substrate 12 illustrated in may be part of a common substrate including a plurality of individual substrates 12.

[0055] In fact, in current manufacturing processes of (integrated circuit) semiconductor devices, multiple devices / lead frames are processed concurrently. For this purpose, multiple (individual) lead frames 12 are arranged in a lead frame strip (or reel) and held together via sacrificial connecting bars CB extending at the outer periphery of the individual lead frames 12.

[0056] The sacrificial connecting bars CB can be removed (e.g., by sawing) in a final cutting separation step, thus obtaining multiple (completed) individual devices.

[0057] For simplicity and ease of explanation, the following description will refer to the manufacture of a single device.

[0058] As Figure 2 shown, two (or more) alignment structures 100 can be provided at the mounting surface of the individual substrate 12, i.e., the surface of the substrate 12 is configured to have a semiconductor die 14 mounted thereon.

[0059] The alignment structure 100 includes a sleeve that defines an internal region, the internal region being sized and dimensioned to have one conductive post 120 inserted therein.

[0060] The alignment sleeve 100 can include a raised structure that may be an electrically insulating material, such as, e.g., non-conductive adhesive (NCA), resin paste, liquid resin, organic substrate material, resist material.

[0061] As Figure 2 shown, the alignment sleeve 100 can be annular. According to other embodiments, the alignment structure 100 can include a sleeve having a different shape (such as, e.g., oval, square, or hexagonal).

[0062] In Figure 2 the example shown, two alignment structures 100 are provided on corresponding leads 12B at opposite sides of the die pad 12A.

[0063] However,Figure 2 The number and / or position of the alignment structures or sleeves 100 illustrated in Figure 2 merely illustrate possible advantageous configurations of the substrate 12 illustrated in the figures; typically, more than two alignment structures or sleeves 100 may be provided at positions in the substrate 12 that may be different from the positions illustrated in Figure 2 . Figure 2 at positions different from those illustrated in Figure 2 .

[0064] The alignment structures 100 may be provided via additive manufacturing techniques such as, for example, jetting, or advantageously via laser-induced forward transfer (LIFT).

[0065] The acronym LIFT denotes a deposition process in which material from a donor ribbon or sheet is transferred to a receptor substrate (here the substrate 12) facilitated by a laser pulse.

[0066] General information regarding the LIFT process can be found, for example, in P. Serra, et al.: “Laser-Induced Forward Transfer: Fundamentals and Applications”, Advanced Materials Technologies / Volume 4, Issue 1 (incorporated herein by reference).

[0067] Figure 3 and Figure 4 are perspective views illustrating a (integrated circuit) semiconductor die 14 mounted on the substrate 12 in a flip-chip orientation (where Figure 4 is an enlarged view of the portion indicated by arrow IV in Figure 3 ), the substrate 12 having alignment structures such as sleeves 100 provided on its surface. Figure 4 is Figure 3 an enlarged view of the portion indicated by arrow IV in Figure 4 ), the substrate 12 having alignment structures such as sleeves 100 provided on its surface.

[0068] As illustrated, the semiconductor die 14 may be provided with a plurality of conductive pillars 120 (or bumps), the plurality of conductive pillars 120 (or bumps) being configured to make electrical contact with the substrate 12 (which may be via a solder material) to provide a desired electrical coupling between the substrate 12 and the semiconductor die 14.

[0069] In Figure 3 and Figure 4 the illustrated embodiments, two alignment sleeves 100 are provided on respective leads 12B of the substrate 12.

[0070] The alignment sleeves 100 facilitate aligning the semiconductor die 14 on the substrate during pick-and-place operations.

[0071] As illustrated, the position of the alignment sleeve 100 can be selected to match the positions of the two conductive posts 120 such that when the semiconductor die 14 is mounted on the substrate 12, the posts 120 can be inserted into the alignment sleeve 100.

[0072] According to an embodiment of the present description, additional dummy posts 120, i.e., posts 120 that are not used to provide input / output signals to the semiconductor die 14, can be formed at the surface of the semiconductor die 14 to be inserted into the alignment sleeve 100, thus facilitating alignment of the semiconductor die 14 on the substrate 12.

[0073] Figures 5A to 5C is a cross-sectional view along Figure 4 line V-V, illustrating the sequence of steps for mounting the semiconductor die 14 on the substrate 12 according to an embodiment of the present description.

[0074] Figure 5A Illustrates the semiconductor die 14 aligned with the substrate 12; as illustrated, the positions of the posts 120 on the semiconductor die 14 match the positions of the alignment sleeves 100 on the substrate 12.

[0075] As shown, a solder material SM (e.g., tin) can be provided at the tip of the post 120 protruding from the semiconductor die 14. After reflow, the solder material SM facilitates the formation of an electrical coupling between the substrate 12 and the post 120.

[0076] Figure 5B Illustrates mounting the semiconductor die 14 on the substrate 12 by contacting the post with the substrate 12 (via the solder material SM), where the end of the post is inserted into the opening (inner region) provided by the alignment sleeve 100.

[0077] As illustrated, the alignment sleeve 100 provides some housing around the conductive post 120.

[0078] In other words, the conductive post 120 is inserted into the alignment sleeve 100, into the inner region 1000 of the sleeve 100. For this purpose, the size and dimensions of the sleeve 100 can be selected to match the width of the conductive post 120.

[0079] Advantageously, the alignment sleeve 100 can be formed with an inner region 1000 that is wider than the conductive post 120 to handle possible (relatively small) errors during pick-and-place operations.

[0080] For example, in current flip-chip semiconductor devices (such as, for example, microcontrollers or DC-DC converters), a solution that takes into account the internal region 1000 of the sleeve 100 that is 60 to 80 microns wide, as described herein, can sufficiently resist the movement of the semiconductor die 14 during processing (e.g., reflow) and provide sufficient tolerance to be achieved with conventional pick and place tools.

[0081] These values are described herein only by way of example and should not be construed in a limiting sense.

[0082] Figure 5C An example of a reflow step performed on the semiconductor die 14 mounted on the substrate 12 is illustrated. The reflow step facilitates the formation of a desired electrical coupling between the semiconductor die 14 and the substrate 12 via the solder material SM provided at the tip of the conductive pillar 120.

[0083] The conductive pillars 120 inserted into the alignment sleeves 100 resist the undesired movement of the semiconductor die 14 during the reflow step. It has been observed that two alignment sleeves 100 sufficiently resist the undesired movement (e.g., rotation) of the semiconductor die 14 relative to the substrate 12 during reflow.

[0084] In some embodiments, more than two alignment sleeves 100 may be provided at the surface of the substrate 12.

[0085] In summary, the solution as described herein involves arranging the semiconductor die 14 at the mounting surface of the substrate 12 via the conductive pillars 120 protruding from the semiconductor die 14, where the distal ends of the conductive pillars 120 are in electrical contact with the mounting surface of the substrate 12 (a solder material SM may be provided therebetween).

[0086] The substrate 12 has two or more alignment sleeves 100 at the mounting surface, and the two or more alignment sleeves 100 are configured to have respective conductive pillars 120 protruding from the semiconductor die 14 inserted therein.

[0087] The semiconductor die 14 is arranged at the mounting surface of the substrate 12, and selected ones of the conductive pillars 120 protruding from the semiconductor die 14 are inserted into the (at least two) alignment sleeves 100 at the mounting surface of the substrate 12.

[0088] In some embodiments, the substrate 12 may include conductive die pads 12A and an array of conductive leads 12B arranged around the periphery of the conductive die pads 12A. In this case, two alignment sleeves 100 may be arranged at two leads 12B in the array of conductive leads 12B, preferably arranged on opposite sides of the die pad 12A.

[0089] Without prejudice to the basic principles and without departing from the scope of the embodiments, details and embodiments may vary, even significantly, from what has been described only by way of example.

[0090] The claims are an integral part of the technical teaching provided by the embodiments.

[0091] The scope of protection is determined by the appended claims.

Claims

1. A method comprising: arranging the semiconductor die at a mounting surface of a lead frame via conductive pillars protruding from the semiconductor die, distal ends of the conductive pillars being in electrical contact with the mounting surface of the lead frame, wherein the lead frame has at least two alignment sleeves at the mounting surface, the at least two alignment sleeves being configured to have corresponding conductive pillars protruding from the semiconductor die, the corresponding conductive pillars of the semiconductor die being inserted into the at least two alignment sleeves; Wherein arranging the semiconductor die at the mounting surface of the lead frame comprises: inserting selected ones of the conductive posts protruding from the semiconductor die into the at least two alignment sleeves at the mounting surface of the lead frame, wherein the posts inserted into the alignment sleeves resist movement of the semiconductor die relative to the lead frame. 2 . The method of claim 1 , wherein the alignment sleeve at the mounting surface of the lead frame comprises an electrically insulating sleeve. 3 . The method of claim 2 , wherein the alignment sleeve comprises an annular configuration at the mounting surface of the lead frame. 4 . The method of claim 1 , wherein the alignment sleeve comprises a raised feature on the mounting surface of the lead frame.

5. The method of claim 1 , wherein the lead frame comprises a conductive die pad, and an array of conductive leads, the array of conductive leads being arranged at a periphery of the conductive die pad, and wherein the at least two alignment sleeves are arranged at two leads in the array of conductive leads. The method of claim 5 , wherein the two leads are located on diagonally opposite sides of the die pad.

7. The method according to claim 1, comprising: The alignment sleeve is formed at the mounting surface of the lead frame via spraying.

8. The method according to claim 1, comprising: The alignment sleeve is formed at the mounting surface of the lead frame via a laser induced forward transfer (LIFT) technique.

9. The method according to claim 1, comprising: A solder material is provided between the distal end of the conductive post inserted into the alignment sleeve and the mounting surface of the lead frame to provide electrical contact with the distal end of the conductive post and the mounting surface of the lead frame.

10. A lead frame, configured to have a semiconductor die, the semiconductor die being arranged at a mounting surface of the lead frame via conductive pillars, the conductive pillars protruding from the semiconductor die, the distal ends of the conductive pillars being in electrical contact with the mounting surface of the lead frame, wherein the lead frame has at least two alignment sleeves at the mounting surface, the at least two alignment sleeves being configured to have corresponding conductive pillars of the semiconductor die, the corresponding conductive pillars of the semiconductor die being inserted into the at least two alignment sleeves to resist movement of the semiconductor die relative to the lead frame. 11 . The lead frame of claim 10 , wherein the alignment sleeve at the mounting surface of the lead frame comprises an electrically insulating sleeve. 12 . The lead frame of claim 11 , wherein the alignment sleeve comprises an annular configuration at the mounting surface of the lead frame.

13. The lead frame of claim 11, wherein the alignment sleeve comprises a raised formation on the mounting surface of the lead frame.

14. The lead frame of claim 10, wherein the lead frame comprises a lead frame comprising a conductive die pad, and an array of conductive leads, the array of conductive leads being arranged at a periphery of the conductive die pad, wherein the at least two alignment sleeves are arranged at two leads in the array of conductive leads.

15. The lead frame of claim 14, wherein the two leads of the array of the conductive leads are on diagonally opposite sides of the die pad.

16. A device comprising: The lead frame according to claim 10; as well as A semiconductor die is arranged at the mounting surface of the lead frame via conductive pillars, the conductive pillars protruding from the semiconductor die, distal ends of the conductive pillars being in electrical contact with the mounting surface of the lead frame, wherein selected ones of the conductive pillars at the surface of the semiconductor die are inserted into the at least two alignment sleeves at the mounting surface of the lead frame.

17. The device of claim 16, comprising a solder material between the distal end of the conductive post inserted into the alignment sleeve and the mounting surface of the lead frame to provide electrical contact with the distal end of the conductive post and the mounting surface of the lead frame.

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