Circuit die with beveled passivation layer

Abstract

An integrated circuit die is provided. The integrated circuit die includes a substrate, a semiconductor device formed on the substrate, and a passivation layer formed over the substrate. The passivation layer has a chamfered corner disposed in a corner region of the integrated circuit die. The beveled corner of the passivation layer is sized to mitigate damage to the passivation layer in the corner region during die singulation.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to integrated circuits including integrated circuit dies having beveled passivation layers. Background Art

[0002] Integrated circuits are used in a wide variety of electronic components and systems. Typically, integrated circuits are formed via a wafer manufacturing process in which a number of integrated circuits are formed on a single wafer of semiconductor material. After such integrated circuits are formed, the individual integrated circuit dies are separated from the wafer via a die singulation process. Die singulation, sometimes referred to as die separation or wafer dicing, may involve scribing the perimeter of each integrated circuit die and then mechanically fracturing the wafer along the scribed lines. Die singulation processes for cutting wafers formed of relatively hard substrate materials sometimes result in the separation lines being slightly tortuous at the corners of the integrated circuits during the mechanical fracturing process, which can undesirably reduce yield. Summary of the Invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments without limiting the scope. A detailed description of the exemplary embodiments sufficient to allow one of ordinary skill in the art to make and use these concepts will follow in later sections.

[0004] In one example embodiment, an integrated circuit die includes a substrate, semiconductor devices formed on the substrate, and a passivation layer formed over the substrate. The passivation layer has a beveled corner disposed in a corner region of the integrated circuit die. The beveled corner of the passivation layer is sized to mitigate damage to the passivation layer in the corner region during die singulation.

[0005] In one or more embodiments, in a first corner region of the integrated circuit die, the passivation layer includes a first beveled surface extending between a first side surface of the passivation layer and a second side surface of the passivation layer.

[0006] In one or more embodiments, a first angle between the first side surface and the first beveled surface is between 130 degrees and 140 degrees, and a second angle between the second side surface and the first beveled surface is between 130 degrees and 140 degrees.

[0007] In one or more embodiments, the first corner region further includes a first corner of the substrate, a first side surface of the substrate, and a second side surface of the substrate, where the first and second side surfaces of the substrate intersect at the first corner of the substrate, and a first vertical distance between the first corner of the substrate and a first beveled surface of the passivation layer is greater than a second vertical distance between the first corner of the substrate and an intersection point between a first plane and a second plane, and the first side surface is located in the first plane, and the second side surface is located in the second plane.

[0008] In one or more embodiments, the first vertical distance is 1.1 times to 10 times the second vertical distance.

[0009] In one or more embodiments, the semiconductor device includes at least one gallium nitride (GaN) transistor.

[0010] In one or more embodiments, the passivation layer includes silicon nitride or silicon oxide.

[0011] In one or more embodiments, the substrate includes at least one of GaN or silicon carbide (SiC).

[0012] In an exemplary embodiment, an integrated circuit die includes a semiconductor substrate, a semiconductor device formed on the semiconductor substrate, and a passivation layer formed above the semiconductor substrate. The passivation layer includes beveled corners disposed at respective corner regions of the integrated circuit die. A first corner region of the integrated circuit die includes a first beveled corner of the beveled corners and a first corner of the semiconductor substrate, and a first vertical distance between the beveled surface of the first beveled corner and the first corner of the semiconductor substrate is greater than a second vertical distance between the first corner of the semiconductor substrate and an intersection point between a first plane and a second plane. The beveled surface extends between a first side surface of the passivation layer and a second side surface of the passivation layer, the first side surface is located in the first plane, and the second side surface is located in the second plane.

[0013] In one or more embodiments, an angle between the beveled surface and a side surface of the passivation layer adjacent to the beveled surface is between 130 degrees and 140 degrees.

[0014] In one or more embodiments, the first vertical distance is 1.1 times to 10 times the second vertical distance.

[0015] In one or more embodiments, the semiconductor device includes at least one gallium nitride (GaN) transistor.

[0016] In one or more embodiments, the passivation layer includes silicon nitride or silicon.

[0017] In one or more embodiments, the semiconductor substrate includes at least one of GaN or silicon carbide (SiC).

[0018] In one or more embodiments, the semiconductor substrate includes a SiC base substrate and at least one epitaxially grown GaN layer formed over the SiC base substrate.

[0019] In an example embodiment, a method of fabricating an integrated circuit die includes: providing a substrate; forming devices on the substrate; forming a passivation layer over the substrate; and forming beveled corners in a corner region of the integrated circuit die on the passivation layer by selectively removing portions of the passivation layer in the corner region of the integrated circuit die. The beveled corners are sized to mitigate damage to the passivation layer during die singulation.

[0020] In one or more embodiments, forming the passivation layer includes forming a dielectric material over the substrate after forming the devices.

[0021] In one or more embodiments, forming the beveled corners includes removing corner portions of the passivation layer using a patterned etching process.

[0022] In one or more embodiments, the substrate includes a semiconductor substrate, the devices include semiconductor transistors, and the passivation layer includes an oxide or nitride material.

[0023] In one or more embodiments, the method includes separating the integrated circuit die from the wafer using a laser-based dicing technique after forming the beveled corners. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings may be considered in conjunction with the following detailed description and the appended claims to derive a more complete understanding of the subject matter, in which like reference numerals throughout the drawings refer to like elements. For simplicity and clarity, the elements in the drawings are shown, and these elements are not necessarily drawn to scale. The drawings are incorporated with the detailed description and form a part of the specification, and are further used to illustrate examples, embodiments, etc. and to explain various principles and advantages in accordance with the present disclosure, wherein:

[0025] Figure 1 is a block diagram showing an example test integrated circuit die having a passivation layer with beveled corners according to one or more embodiments;

[0026] Figure 2 is a block diagram showing a top view and a perspective view of a corner region of an integrated circuit die (e.g., Figure 1 of the integrated circuit die) including beveled corners of a passivation layer according to one or more embodiments;

[0027] Figure 3is a figure showing a cross-sectional side view of an integrated circuit die according to one or more embodiments Figure 1 along line A-A; and

[0028] Figure 4 is a process flow diagram describing a method for forming and die separating an integrated circuit die having beveled corners (e.g., Figure 1 the integrated circuit die) according to one or more embodiments. DETAILED DESCRIPTION

[0029] The following detailed description is merely illustrative in nature and is not intended to limit embodiments of the subject matter or the application and uses of such embodiments. Further, there is no intention to be bound by any theory presented in the foregoing background of the disclosure or the following detailed description.

[0030] For simplicity and clarity of illustration, the figures show general constructional ways and may omit descriptions and details of well-known features and techniques for the sake of brevity. Additionally, elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of the embodiments described herein.

[0031] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims may be used to distinguish similar elements and are not necessarily intended to describe a particular sequential or temporal order. It should be understood that such terms may be interchangeable under appropriate circumstances such that the embodiments described herein (e.g.) can operate in sequences other than those illustrated or otherwise described herein. Further, the terms "comprising", "having" and any variations thereof are intended to cover non-exclusive inclusion such that a process, method, article or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article or apparatus. As used herein, the term "coupled" is defined as connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practical manner and minor deficiencies (if any) are not important for the stated purpose. As used herein, the words "exemplary" and "example" mean "serving as an example, instance or illustration". Any embodiment described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other embodiments.

[0032] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are made for illustrative purposes with reference to the orientation of the corresponding one or more figures.

[0033] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference purposes only and are not intended to be limiting. For example, unless clearly indicated by the context, the terms "first", "second", and other such numerical terms referring to structures do not imply an order or sequence.

[0034] The various embodiments described herein relate to integrated circuit dies having a passivation layer with beveled corners. Conventionally, when performing die singulation to separate an integrated circuit die from a wafer, during the mechanical fracture process, the separation line between adjacent dies often zigzags slightly at the die corners. This can cause damage to the passivation layer of the integrated circuit die, which may potentially compromise the moisture integrity of the integrated circuit die and may require the damaged die to be discarded. This problem may be more likely to occur when using an invisible dicing technique to perform die singulation on a wafer including relatively hard materials (e.g., silicon carbide (SiC), sapphire, etc.). The passivation layer damage caused by the zigzagging of the separation line during the mechanical fracture process may result in a yield loss of several percent (e.g., up to 5% or more according to various embodiments).

[0035] In one or more embodiments described herein, damage to the passivation layer in an integrated circuit die can be mitigated by beveling or chamfering the corners of the passivation layer prior to die singulation. As used herein, the terms "beveling" and "chamfering" are used interchangeably to refer to a process of changing a sharp corner or edge (e.g., a square (i.e., right-angled) corner or edge) to an inclined surface, typically by removing material at the corner to round or flatten the corner or edge. As used herein, a "beveled corner" or "chamfered corner" refers to a corner region of a layer or structure where a first surface or edge of the layer or structure transitions to a second surface or edge via an inclined surface or edge (e.g., where the first surface or edge and the second surface or edge may be vertically aligned), and the inclined surface or edge may be formed directly or by beveling or chamfering. As used herein, a "beveled surface" or "chamfered surface" refers to the inclined surface of a beveled corner or chamfered corner (e.g., an inclined surface extending between two vertical edges or surfaces such as two vertical side surfaces of a layer). In the various embodiments described herein, the beveled or chamfered surfaces and edges of the passivation layer of the integrated circuit die may be flat or substantially flat, or may be curved or rounded.

[0036] In one or more embodiments, an integrated circuit die may include a passivation layer having chamfered corners, wherein a chamfered surface of each chamfered corner extends between two side surfaces of the passivation layer. The chamfered corners of the passivation layer may be disposed in corresponding corner regions of the integrated circuit die. A first perpendicular distance between a chamfered surface of one of the chamfered corners of the passivation layer and a corresponding corner of the integrated circuit die may be greater than (e.g., by way of non-limiting example, from about 1.1 times to about 2.0 times) a second perpendicular distance between an edge or side surface of the passivation layer and an edge or side surface of the integrated circuit die that is parallel-aligned adjacent to the edge or side surface. As used herein, "perpendicular distance" means the distance measured along a line perpendicular to one or both of these from one edge, point, or line to another edge, point, or line. For example, the perpendicular distance between a point and a line is the distance from the point to the nearest point on the line.

[0037] In one or more embodiments, a chamfered surface of a chamfered corner of a passivation layer of an integrated circuit may be a generally flat surface extending from a first side surface of the passivation layer to a second side surface of the passivation layer, wherein the chamfered surface intersects the first side surface of the passivation layer at a first angle (e.g., by way of non-limiting example, between 130 degrees and 140 degrees) and intersects the second side surface of the passivation layer at a second angle (e.g., by way of non-limiting example, between 130 degrees and 140 degrees).

[0038] In one or more embodiments, the passivation layer is formed on or above a substrate, and a first perpendicular distance between the chamfered surface and a corresponding corner of the substrate is greater than (e.g., by way of non-limiting example, 1.1 times to 2.0 times) a second perpendicular distance between a corner of the substrate and an intersection point between a first plane in which a first side surface of the passivation layer lies and a second plane in which a second side surface of the passivation layer lies, wherein the first plane is generally perpendicular to the second plane. Chamfering or beveling the corners of the passivation layer increases the perpendicular distance between the corners of the passivation layer and the corners of the substrate, such that meandering of the separation line during the mechanical break process of the die singulation process is less likely to damage the passivation layer. This can in turn advantageously reduce the yield loss caused by passivation layer damage during die singulation.

[0039] Figure 1is a top view illustration of an example integrated circuit die 100 in accordance with one embodiment. In one or more embodiments, the integrated circuit die 100 includes a substrate 101 that includes silicon carbide (SiC). In one or more other embodiments, by way of non-limiting example, and in place of or in addition to SiC, the substrate 101 includes one or more layers of materials such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, boron nitride (BN), polycrystalline SiC, silicon-on-insulator, gallium arsenide (GaAs), and / or indium phosphide (InP). In one or more embodiments, the substrate 101 includes a SiC base substrate and one or more layers of GaN epitaxially grown over the SiC base substrate.

[0040] The integrated circuit die 100 may include a passivation layer 120 formed over the substrate 101. The substrate 101 may be shaped as a rectangle or generally rectangular, where side surfaces meet to form sharp corners / edges of approximately 90 degrees. The corners of the passivation layer 120 may be positioned near the corners of the substrate 101 in a corner region 114 and may be chamfered to form chamfered surfaces 116. The side surfaces of the passivation layer may intersect the chamfered surfaces 116 at an angle greater than 90 degrees. In one or more embodiments, the passivation layer 120 may include one or more layers of dielectric material. In one or more embodiments, the passivation layer 120 includes an oxide layer such as silicon oxide (e.g., SiO 2 ) layer. In one or more embodiments, the passivation layer includes a nitride layer such as a silicon nitride layer (e.g., SiN). In one or more embodiments, the passivation layer 120 may be formed directly on the upper surface of the substrate 101 (i.e., in direct physical contact with the upper surface).

[0041] The integrated circuit die 100 may include one or more active semiconductor devices (e.g., transistors) in a device region 130 and / or one or more passive devices (not illustrated) at a first surface of the integrated circuit die 100. The integrated circuit die 100 may include one or more regions external to the device region 130, and the one or more regions may include electrically isolated regions.

[0042] Device region 130 may include transistor 103. Transistor 103 may be a GaN field effect transistor (FET) defined by multiple structures (sometimes referred to as “fingers”), such as source structure 102 (“S”), gate structure 104 (“G”), and drain structure 106 (“D”), where each of source structure 102, gate structure 104, and drain structure 106 is formed of a conductive material (e.g., gold, copper, etc.) disposed at a first surface of integrated circuit die 100. One or more layers of GaN material (sometimes referred to as “GaN layers”) of substrate 101 may be disposed between the base substrate of substrate 101 and each of source structure 102, gate structure 104, and drain structure 106. For example, such GaN layers may be epitaxially grown on the base substrate of substrate 101. The drain structure 106 of transistor 103 may be electrically coupled to a drain pad 110 (e.g., a drain bond pad), and the gate structure 104 of transistor 103 may be electrically coupled to a gate pad 112 (e.g., a gate bond pad). For example, each of gate pad 112 and drain pad 110 includes a conductive material disposed at the first surface of integrated circuit die 100. In one or more embodiments, wire bonding is used to connect drain pad 110 to drain structure 106 and gate pad 112 to gate structure 104. The source structure 102 of transistor 103 may be electrically coupled to a conductive material layer, sometimes referred to herein as a “reference plane” (e.g., Figure 3 reference plane 304), which is disposed at a second surface of integrated circuit die 100 and is configured to be biased to a reference potential, such as ground voltage, during operation. As shown, device region 130 may include multiple source structures 102, gate structures 104, and drain structures 106, which together form multiple transistors. In one or more embodiments, as an alternative or addition to the transistors shown in the current example, device region 130 may include other active devices.

[0043] In one or more embodiments, each source structure 102 is coupled to the reference plane through a through-substrate via (TSV) 108. Each standard TSV 108 corresponds to an opening (e.g., a hole) in substrate 101 that extends between one of the source structures in source structure 102 and the reference plane and includes a conductive material that provides an electrical connection between source structure 102 and the reference plane.

[0044] Although device region 130 is shown in the current example as including transistors, this is illustrative and not limiting. For example, it should be understood that other active devices and / or passive devices may be included in device region 130 as an alternative or addition to such transistors.

[0045] An integrated circuit die 100 can be formed via wafer processing and separated from a host wafer via a die singulation process. This die singulation process can include a laser-based scribing process, such as a stealth scribing process, that uses laser ablation to damage the wafer along a predefined scribe line prior to mechanical fracture to separate the integrated circuit die from the wafer. A laser-based scribing process (such as stealth scribing) performed on a wafer that includes a particularly hard material (such as SiC) can cause the separation line near the corner of the integrated circuit die to be tortuous, which can result in damage to the passivation layer of the integrated circuit die. Such damage to the passivation layer can compromise the moisture integrity that is otherwise provided by the passivation layer, which can result in the integrated circuit die being discarded during testing (e.g., automated optical inspection).

[0046] In the present example, by chamfering the corner of the passivation layer 120 to form a chamfered surface 116, the distance between the corner of the passivation layer 120 and the corner of the substrate 101 is increased in the corner region 114. This increased distance advantageously reduces the likelihood that the passivation layer 120 will be damaged during the mechanical fracture process of the die singulation process, even in cases where the separation line is tortuous (e.g., bending away from the predefined scribe line and towards the passivation layer 120) at one or more corners in the corner region 114. By mitigating damage to the passivation layer 120 in this manner, yield loss during the manufacture of the integrated circuit die 100 and other similar integrated circuit dies can be advantageously reduced (e.g., by up to 5% or more according to various embodiments).

[0047] Figure 2 A top view illustration 200 and a perspective view illustration 250 of a corner region of an integrated circuit die having a chamfered passivation layer are shown (e.g., as a non-limiting example, Figure 1 any one of the corner regions 114 of the integrated circuit die 100). In Figure 2 the example, the same reference numerals are used to denote Figure 1 similar elements in

[0048] and some details already discussed above in connection with such elements need not be repeated here for the sake of brevity.

[0048] As shown in the present example, the passivation layer 120 can include side surfaces 206 and 208, where the chamfered surface 116 extends between the side surface 206 and the side surface 208. The chamfered surface 116 can meet or otherwise intersect the side surface 208 at an edge 204 at a first angle θ 1 and the chamfered surface 116 can meet or otherwise intersect the side surface 206 at an edge 202 at a second angle θ 2 In one or more embodiments, the angles θ 1 and θ 2Each of the angles can be between 130 degrees and 140 degrees. In one or more embodiments, the angle θ 1 can be equal to the angle θ 2 . In one or more embodiments, the angle θ 1 and θ 2 Each of the angles can be equal to or approximately (e.g., with a tolerance of + / - 1 degree) equal to 135 degrees.

[0049] The vertical distance D1 between the chamfered surface 116 and the corresponding corner 214 of the substrate 101 is greater than the vertical distance D2 between the corner 214 of the substrate 101 and the position where the corner of the passivation layer 120 would be without chamfering (i.e., the position where the first plane including the side surface 208 intersects the second plane including the side surface 206). The vertical distance D1 is greater than the distance D2 between the corner 214 and the intersection point of the planes of the side surfaces 206 and 208. In one or more embodiments, the vertical distance D1 is 1.1 times to 10 times the vertical distance D2. In one or more embodiments, the vertical distance D1 can be 1.2 times to 5 times the vertical distance D2. In one or more embodiments, the vertical distance D1 can be 1.3 times to 3 times the vertical distance D2. As shown, the chamfering of the corner of the passivation layer 120 also causes the passivation layer to be further away from the edges 210 and 212 of the substrate 101 in the corner region 114. By chamfering the corner of the passivation layer 120 in the corner region 114, due at least in part to the increased distance between the passivation layer 120 and the edges 210 and 212 of the substrate 101 in the corner region 114 (which also define the edges of the integrated die 100), damage to the passivation layer 120 caused by the zigzag of the scribe line is less likely to occur.

[0050] Although the chamfered surface 116 is shown as generally flat in the current example, it should be understood that this is illustrative and not restrictive. In one or more other embodiments, for example, the chamfered surface 116 can instead be curved, thereby defining an arc extending between the side surfaces 206 and 208.

[0051] Figure 3 is Figure 1 A cross-sectional view 300 of the integrated circuit die 100 taken along line A-A. In Figure 3 the example, the same reference numerals are used to denote Figure 1 similar elements in

[0052] As shown in the figure, the integrated circuit die 100 may include a substrate 101, and the substrate 101 includes a first surface and a second surface. A semiconductor device is formed adjacent to the first surface of the substrate 101 within the device region 130. In the current example, the semiconductor device includes one or more transistors, such as transistor 103, and the substrate 101 includes layers that support the operation of the transistors. For example, the transistor 103 formed in the device region 130 may include a source contact 316 (e.g., Figure 1 the source structure 102), a gate 318 (e.g., Figure 1 the gate structure 104), and a drain contact 320 (e.g., Figure 1 the drain structure 106). The gate 318 is formed between the source contact 316 and the drain contact 320. In one or more embodiments, the source contact 316 is electrically connected to a reference plane 304 via one or more standard TSVs (e.g., Figure 1 the standard TSV 108). In one or more embodiments, the gate 318 is electrically connected to a gate pad (e.g., Figure 1 the gate pad 112). In one or more embodiments, the drain contact 320 is electrically connected to a drain pad (e.g., Figure 1 the drain pad 110). As a non-limiting example, the transistor 103 may be a GaN field effect transistor (FET). The integrated circuit die 100 may include one or more transistors or other devices within the device region 130 formed adjacent to the first surface of the substrate 101.

[0053] In one or more embodiments, the substrate 101 includes a base substrate 302, a barrier layer 310, a channel layer 312, and a buffer layer 314. In one or more embodiments, as a non-limiting example, the base substrate 302 may include a semiconductor material such as Si or SiC. In one or more other embodiments, the base substrate 302 may include an insulating material, such as sapphire as a non-limiting example.

[0054] The buffer layer 314 may be formed above the first surface of the base substrate 302. The buffer layer 314 may include one or more group III nitride (sometimes referred to as "III-N group") semiconductor layers and is supported by the base substrate 302. As a non-limiting example, each semiconductor layer in the semiconductor layers of the buffer layer 314 may include one or more epitaxially grown group III nitride layers. In one or more such embodiments, the epitaxially grown group III nitride layers of the buffer layer 314 may be N-face or Ga-face materials. In one or more other embodiments, the semiconductor layers of the buffer layer 314 may be formed by a suitable process other than epitaxial growth. In one or more other embodiments, the semiconductor layers of the buffer layer 314 may include Si, GaAs, InP, or other suitable materials.

[0055] In one or more embodiments, a channel layer 312 is formed over a buffer layer 314. The channel layer 312 may include one or more III-N semiconductor layers and is supported by the buffer layer 314. For example, the channel layer 312 may include Al X Ga 1-X N layer, where X takes a value between 0 and 1. In one embodiment, the channel layer 312 is configured as GaN (X = 0), but other values of X may be used. The thickness of the channel layer 312 may be between about 50 angstroms and about 10,000 angstroms, but other thicknesses may also be used.

[0056] In one or more embodiments, a barrier layer 310 is formed over the channel layer 312. The barrier layer 310 may include one or more III-N semiconductor layers and is supported by the channel layer 312. The barrier layer 310 may have a larger bandgap and / or a larger spontaneous polarization than the channel layer 312. When the barrier layer 310 is located over the channel layer 312, a channel in the form of a two-dimensional electron gas (2-DEG) is formed adjacent to the interface between the channel layer 312 and the barrier layer 310 within the channel layer 312. Additionally, tensile strain between the barrier layer 310 and the channel layer 312 may cause additional piezoelectric charges to be introduced into the 2-DEG and the channel. In one or more embodiments, the barrier layer 310 may include at least one NID Al X Ga 1-X N layer, where X takes a value between 0 and 1 or between 0.1 and 0.35, but other values of X may be used. The NID Al X Ga 1-X N layer of the barrier layer 310 may have a thickness between about 50 angstroms and about 1000 angstroms, but other thicknesses may be used.

[0057] In one or more embodiments, a cap layer (not shown) may be formed over the barrier layer 310. The cap layer presents a stable surface and is used to protect the upper surface of the integrated circuit die 100 from chemical and environmental exposures incidental to wafer processing. The cap layer may include one or more III-N semiconductor layers and is supported by the barrier layer 310. In one embodiment, the cap layer includes GaN. The thickness of the cap layer may be between about 5 angstroms and about 100 angstroms, but other thicknesses may also be used.

[0058] In one or more embodiments, a portion of the passivation layer 120 is formed over the barrier layer 310. In one or more embodiments, the portion of the passivation layer 120 provides electrical insulation between the source contact 316 and the gate 318 and between the gate 318 and the drain contact 320.

[0059] Although the transistor 103 in the above example is described as a GaN device formed in the device region 130, it should be understood that this is illustrative and not restrictive. In one or more other embodiments, instead of or in addition to the transistor 103, other suitable active or passive devices formed of GaN or other suitable semiconductor materials (e.g., silicon, GaAs) and / or insulating materials (e.g., silicon oxide, silicon nitride, or other suitable electrical insulating materials) may be formed in the device region 130.

[0060] Outside the device region 130, the substrate 101 includes a material 306 that may be formed on the base substrate 302. In one or more embodiments, the material 306 is a high resistivity material or a semi-insulating material, such as an ion bombarded semiconductor material (e.g., as a non-limiting example, ion bombarded GaN, Si, or GaAs). In one or more other embodiments, the material 306 is a conductive semiconductor material (e.g., conductive GaN or GaAs). In one or more other embodiments, the material 306 includes silicon, metal, dielectric material, or a combination thereof. The material 306 may at least partially isolate (e.g., electrically isolate) the device region 130. A portion of the passivation layer 120 may be formed directly on the material 306. As shown, the corner region 114 of the integrated circuit die 100 may overlap with the region of the substrate 101 that includes the material 306. When a portion of the passivation layer 120 is removed (e.g., when a beveled corner of the passivation layer 120 is formed in the corner region 114), the material 306 is exposed. Beveling the passivation layer 120 in the corner region 114 increases the distance D1 between the passivation layer 120 and the corner 214 of the substrate 101, which exposes more of the upper surface of the material 306 and which further reduces the likelihood of damage to the passivation layer 120 due to a tortuous scribe line in the corner region 114 during die singulation.

[0061] Figure 4 An illustrative process flow of a method 400 is shown by which an integrated circuit die (e.g., Figure 1 the integrated circuit die 100) having a passivation layer with beveled corners is formed and then the integrated circuit die is separated from a host wafer via die singulation. The method 400 is described with reference to the elements of the integrated circuit die 100 shown in the cross-sectional views 300 of Figure 1 and Figure 3 and, for the sake of brevity, the description of such elements need not be repeated here. However, it should be understood that this is illustrative and not restrictive, at least because in one or more other embodiments, other suitable integrated circuit dies may be manufactured using the method 400.

[0062] At block 402, a substrate 101 is provided. In one or more embodiments, the substrate 101 may include a base substrate (e.g., as a non-limiting example, SiC or sapphire) and one or more semiconductor layers formed over the base substrate (e.g., as non-limiting examples, epitaxially grown GaN layers such as buffer layer 314, channel layer 312, and blocking layer 310).

[0063] At block 404, active device layers and structures are formed over and / or within the substrate 101. As non-limiting examples, such active device layers and structures may include gate, source, and drain terminal structures (e.g., gate 104 and 318, Figure 1 and 3 source structures 102 and 316, Figure 1 and 3 respectively, and Figure 1 and 3 drain structures 106 and 320). At block 404, TSVs (e.g., TSV 108 Figure 1 ) may alternatively or additionally be formed through the substrate 101. For example, the active device layers and structures formed at block 404 may be formed using any suitable combination of conventional lithography techniques, etching techniques, and material deposition techniques.

[0064] At block 406, a passivation layer 120 is formed over the substrate 101 (e.g., deposited via sputtering, plasma deposition, chemical vapor deposition, evaporation, or another suitable deposition process). In one or more embodiments, the passivation layer 120 includes one or more layers of dielectric material, such as an oxide (e.g., as a non-limiting example, SiO 2 ) or a nitride (e.g., as a non-limiting example, SiN).

[0065] At block 408, the passivation layer 120 is selectively etched to form beveled corners at the corner regions of the passivation layer. In one or more embodiments, the passivation layer 120 may be etched using a lithography process or other suitable patterning etching process to selectively remove portions of the passivation layer 120 at the corner regions 114 of the integrated circuit die 100 to a beveled surface 116. In one or more embodiments, the formation of the beveled corners of the passivation layer 120 may be performed simultaneously with the formation of openings in other regions of the passivation layer 120 (e.g., openings in the device region 130 through which device structures such as gate, source, or drain contacts may be exposed).

[0066] At block 410, die singulation is performed to separate integrated circuit die 100 from its host wafer. In one or more embodiments, the die singulation process may include a laser-based process, such as a stealth dicing process, in which laser energy is applied along a predefined scribe line of the host wafer to penetrate the material of the host wafer, followed by a mechanical fracture process in which stress is applied to the host wafer to fracture the wafer along the scribe line. Forming a passivation layer 120 with beveled corners at the corner regions 114 of the integrated circuit die 100 can advantageously mitigate or prevent damage to the passivation layer 120 that might otherwise occur during block 410 due to the serpentining of the scribe line at the corner regions, at least because the beveling increases the distance between the passivation layer 120 and the corners of the substrate 101 where scribe line serpentining may occur. In this way, yield loss of the host wafer can be advantageously reduced due to preventing passivation layer damage in integrated circuit dies formed from the host wafer, including integrated circuit die 100.

[0067] The foregoing description refers to elements or nodes or features as being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to another element (or directly communicates with another element) and need not be in a mechanical manner. Similarly, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to another element (or directly or indirectly communicates with another element) and need not be in a mechanical manner. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in one or more embodiments of the subject matter depicted.

[0068] Although the operations of the methods herein are shown and described in a particular order, the order of each method's operations may be altered such that certain operations may be performed in a reverse order, or such that certain operations may be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of disparate operations may be implemented in an intermittent and / or alternating fashion.

[0069] It should also be noted that at least some of the operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program. The computer-usable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-usable and computer-readable storage media include semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and optical disk. Current examples of optical disks include compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and digital video disk (DVD).

[0070] Alternatively, the embodiments described herein can be implemented entirely in hardware or in an implementation that includes both hardware and software elements. In embodiments using software, the software can include, but is not limited to, firmware, resident software, microcode, etc.

[0071] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. It should also be understood that one or more of the exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing one or more of the described embodiments. It should be understood that various changes can be made to the functionality and arrangement of the elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. An integrated circuit die, characterized in that: include: substrate; a semiconductor device formed on the substrate; as well as A passivation layer is formed over the substrate, the passivation layer having chamfered corners disposed in corner regions of the integrated circuit die, wherein the chamfered corners of the passivation layer are sized to mitigate damage to the passivation layer in the corner regions during die singulation.

2. The integrated circuit die according to claim 1, characterized in that: In a first corner region of the integrated circuit die, the passivation layer includes a first chamfered surface extending between a first side surface of the passivation layer and a second side surface of the passivation layer.

3. The integrated circuit die according to claim 2, characterized in that: A first angle between the first side surface and the first chamfered surface is between 130 and 140 degrees, and a second angle between the second side surface and the first chamfered surface is between 130 and 140 degrees.

4. The integrated circuit die according to claim 2, characterized in that: The first corner region further includes a first corner of the substrate, a first side surface of the substrate, and a second side surface of the substrate, the first side surface and the second side surface of the substrate intersect at the first corner of the substrate, a first vertical distance between the first corner of the substrate and the first chamfered surface of the passivation layer is greater than a second vertical distance between the first corner of the substrate and an intersection point between the first plane and the second plane, the first side surface is located in the first plane, and the second side surface is located in the second plane.

5. The integrated circuit die according to claim 4, characterized in that: The first vertical distance is 1.1 to 10 times the second vertical distance.

6. The integrated circuit die according to claim 1, characterized in that: The semiconductor device includes at least one gallium nitride (GaN) transistor.

7. The integrated circuit die according to claim 1, characterized in that: The passivation layer includes silicon nitride or silicon oxide.

8. The integrated circuit die according to claim 5, characterized in that: The substrate includes at least one of GaN or silicon carbide SiC.

9. An integrated circuit die, characterized in that: include: Semiconductor substrate; a semiconductor device formed on the semiconductor substrate; as well as A passivation layer is formed above the semiconductor substrate, the passivation layer comprising a plurality of chamfered corners disposed at corresponding corner regions of the integrated circuit die, wherein a first corner region of the integrated circuit die comprises a first chamfered corner of the plurality of chamfered corners and a first corner of the semiconductor substrate, and a first vertical distance between a chamfered surface of the first chamfered corner and the first corner of the semiconductor substrate is greater than a second vertical distance between the first corner of the semiconductor substrate and an intersection point between a first plane and a second plane, wherein the chamfered surface extends between a first side surface of the passivation layer and a second side surface of the passivation layer, the first side surface is located in the first plane, and the second side surface is located in the second plane.

10. A method for manufacturing an integrated circuit die, characterized in that: include: providing a substrate; forming a device on the substrate; forming a passivation layer over the substrate; as well as A beveled corner is formed on the passivation layer in the corner region of the integrated circuit die by selectively removing portions of the passivation layer in the corner region, wherein the beveled corner is sized to mitigate damage to the passivation layer during die singulation.

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