Semiconductor device with metal structure passivation

Abstract

The invention relates to a semiconductor device with metal structure passivation. The semiconductor device includes a semiconductor substrate. A metal structure is disposed over a semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy. A passivation layer is disposed over the metal structure, where the passivation layer includes: a first layer including CuSiN; and a second layer including Si, N, and H, where, in terms of atomic number, the ratio of Si to N is equal to or greater than 3.3 / 4.

Description

Technical Field

[0001] The present disclosure generally relates to the field of power semiconductor devices and, in particular, to a semiconductor device having passivation of a metal structure. Background Art

[0002] Semiconductor devices, and in particular power semiconductor devices, are often sensitive to environmental effects such as humidity and temperature fluctuations. These effects can cause changes in material properties and electrical characteristics, such as deviations in the breakdown voltage of the device. Additionally, the lifespan of the semiconductor device can be shortened.

[0003] Passivation layers on metal structures are used to improve the device's resistance to environmental effects. However, integrating a passivation layer on a metal can be difficult with regard to the high adhesion required and meeting electrical requirements, especially suitability for chip edge termination. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate. A metal structure is disposed on the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy. A passivation layer is disposed on the metal structure, wherein the passivation layer includes: a first layer including CuSiN; and a second layer including Si, N, and H, wherein, in terms of atomic amounts, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0005] According to another aspect of the present disclosure, a method of manufacturing a semiconductor device includes: providing a semiconductor substrate; forming a metal structure on the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy; and forming a passivation layer on the metal structure, the forming of the passivation layer including: forming a first layer including CuSiN, and forming a second layer including Si, N, and H, wherein, in terms of atomic amounts, the ratio of Si to N is equal to or greater than 3.3 / 4. Brief Description of the Drawings

[0006] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding like parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive and / or can be selectively omitted if not described as necessarily required. Embodiments are depicted in the drawings and are described in detail by way of example in the following description.

[0007] Figure 1 is a schematic cross-sectional representation of an example of a semiconductor substrate of a semiconductor device, a metal structure disposed on the substrate, and a passivation layer disposed on the metal structure.

[0008] Figure 2Is a schematic plan view of an example of a semiconductor device, showing an active region, a chip edge, and an edge termination region therebetween.

[0009] Figure 3 Is a schematic partial cross-sectional view of an example of a semiconductor device, showing an active region, a chip edge, and an edge termination region therebetween.

[0010] Figure 4 Is a schematic partial cross-sectional view of an example of a semiconductor device, including a power pad and other metal structures, such as, for example, a signal routing structure or a field plate of an exemplary semiconductor device.

[0011] Figure 5 Is a flowchart showing exemplary stages of a method of manufacturing a semiconductor device having a metal structure and a passivation layer disposed on the metal structure.

[0012] Figure 6 Is a flowchart showing Figure 5 Exemplary stages of a process of forming a passivation layer according to stage S3 of Detailed Description

[0013] It should be understood that, unless otherwise specifically indicated, the features of the various exemplary embodiments and examples described herein may be combined with each other.

[0014] As used in this specification, the terms "depositing", "being covered by", "connecting", and / or "electrically connecting" are not intended to mean that elements or layers must be in direct contact with each other; intervening elements or layers may be provided between the elements "depositing", "being covered by", "connecting", and / or "electrically connecting". However, according to the present disclosure, the above terms may optionally also have the following specific meaning: the elements or layers are in direct contact with each other, that is, intervening elements or layers are not provided between the elements "depositing", "being covered by", "connecting", and / or "electrically connecting".

[0015] In addition, the phrase "on" used with respect to a part, element, or layer of material formed or located or disposed "on a surface" may be used herein to mean that the part, element, or layer of material is "directly" located (e.g., placed, formed, disposed, deposited, etc.) "on the implied surface", e.g., in direct contact with the implied surface. The phrase "on" used with respect to a part, element, or layer of material formed or located or disposed "on a surface" may also be used herein to mean that the part, element, or layer of material is "indirectly" located (e.g., placed, formed, disposed, deposited, etc.) "on the implied surface", with one or more additional parts, elements, or layers being disposed between the implied surface and the part, element, or layer of material.

[0016] Referring toFigure 1 For example, an example of the semiconductor device 100 includes a semiconductor substrate 110. A metal structure 120 is disposed on the semiconductor substrate 110. The metal of the metal structure 120 or the metals included in the metal structure 120 is Cu or a Cu-based alloy.

[0017] A passivation layer 130 is disposed on the metal structure 120. The passivation layer 130 includes a first layer 130_1 and a second layer 130_2. The first layer 130_1 includes or has CuSiN. The second layer 130_2 includes Si, N, and H, or consists of Si, N, and H. In terms of the number of atoms, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0018] As will be described in further detail below, the passivation layer 130 can have various functions. First, the passivation layer 130 can provide high suitability for passivation (e.g., moisture protection for the underlying structure). Second, the passivation layer 130 can provide good adhesion to the underlying structure (such as, for example, the metal structure 120) and / or to the overlying structure (such as, for example, an imide layer ( Figure 1 not shown in the figure)). Third, the passivation layer 130 can be used, for example, for electrical contact with the chip edge. In a power semiconductor device, the chip edge can be at a high voltage. The passivation layer 130 can, for example, provide an electrical function to balance the voltage drop between the chip edge and the active region so that, for example, it does not adversely affect the electrical properties of the device. For this purpose, the passivation layer 130 can have a specific conductivity that is not too large but also not too small. In addition, the passivation layer 130 can form a charge shielding layer to protect the chip edge termination from external charges.

[0019] In the semiconductor device 100, the second layer 130_2 including Si, N, and H in the above composition can meet the requirements regarding protection against environmental effects, adhesion, and conductivity. However, as will be described in further detail below, the second layer 130_2 cannot be directly deposited on the metal structure 120 in a controlled manner.

[0020] The first layer 130_1 includes CuSiN to inhibit the formation of CuSi, and thus, enables the controlled deposition of the second layer 130_2. In other words, by combining the first layer 130_1 and the second layer 130_2, the metal structure 120 including or having Cu can be effectively passivated by the passivation layer 130, and the passivation layer 130 can meet all requirements and particularly meet the electrical and protection requirements for, for example, chip edge termination.

[0021] For example, the first layer 130_1 can include two layers or consist of two layers, that is: (optional) a CuSi layer 130_1a; and a CuSiN layer 130_1b, disposed above the CuSi layer 130_1a and representing, for example, the surface of the first layer 130_1.

[0022] Optionally, at least one intermediate layer 130_x can be disposed between the first layer 130_1 and the second layer 130_2. The intermediate layer 130_x can comprise or have alumina, such as Al 2 O 3 . By ALD (Atomic Layer Deposition), the (optional) intermediate layer 130_x can be deposited. The intermediate layer 130_x can have a small thickness, such as, for example, less than 1 nm or a few nm.

[0023] The metal structure 120 can be, for example, a chip pad or any other metal structure used in the semiconductor device 100. For example, the metal structure 120 can be a gate runner or a field plate of the semiconductor device 100.

[0024] Depending on whether the semiconductor device 100 is a power device and depending on the type of the metal structure 120, the metal structure 120 can have a thickness, for example, between 1 and 30 μm (in particular, between 4 and 14 μm). For example, the first layer 130_1 can have a thickness between 1 and 115 nm (depending on whether the CuSi layer 130_1a is included in the first layer 130_1 and, if the CuSi layer 130_1a is included in the first layer 130_1, how thick the CuSi layer 130_1a is, see the more detailed description below). The thickness of the first layer 130_1 can be small because the first layer 130_1 may not provide volume-related functions. Instead, the first layer 130_1 can provide a copper silicide nitride surface that prevents excessive CuSi growth when forming the second layer 130_2 of the passivation layer stack 130.

[0025] The second layer 130_2 can have a layer thickness between 40 and 500 nm. In particular, a thickness between 200 nm, 250 nm or 300 nm as the lower limit and 500 nm or 400 nm as the upper limit may be suitable. The second layer 130_2 can provide moisture protection and / or electrical characteristics of the passivation layer 130, i.e., can provide volume-related functions.

[0026] The semiconductor substrate 110 can be, for example, a Si substrate, a silicon-on-insulator (SOI) substrate, a GaN substrate, a SiC substrate, a GaAs substrate, or a substrate of any other IV-IV, III-V or II-VI semiconductor material (such as, for example, SiGe, GaAs, AlGaN, InGaAs, InAlAs, etc.). For example, the semiconductor substrate 110 can be a semiconductor body or a semiconductor chip formed of one or more of the above materials.

[0027] The semiconductor device 100 can be, for example, a vertical device or a horizontal device. In a vertical device, the main direction of the load current is in the vertical direction, while in a horizontal (or lateral) device, the main direction of the load current is in the horizontal (lateral) direction.

[0028] The semiconductor device 100 (e.g., semiconductor chip) can be configured, for example, as an IGBT (Insulated Gate Bipolar Transistor), FET (Field Effect Transistor), in particular a MOSFET (Metal Oxide Semiconductor FET), such as, for example, a P-FET (P-channel FET), N-FET (N-channel FET), AFET (Array FET), JFET (Junction Gate FET), planar gate transistor, field plate trench transistor, or SJ (Super Junction) transistor. Additionally, the semiconductor device 100 can be configured, for example, as a diode.

[0029] Figure 2 A plan view of the semiconductor device 100 is shown, depicting the functional regions of the device 100. In the example shown, the semiconductor device 100 can be a power and / or high voltage device 100.

[0030] The semiconductor device 100 can include an active region 102. The active region 102 can be bounded by a boundary 102B, at which the active region 102 transitions into an edge termination region 103. The edge termination region 103 can surround the active region 102 and terminate at the chip edge 104.

[0031] The purpose of the active region 102 is mainly to ensure load current conduction. The edge termination region 103 can be configured to reliably terminate the active region 102. More specifically, the edge termination region 103 is generally not used for load current conduction purposes, but rather to safely terminate the active region 102 and ensure robust blocking characteristics of the semiconductor device 100.

[0032] Figure 3 A cross-sectional view of a part of an exemplary semiconductor device 100 is shown. In the example shown, the semiconductor device 100 is a vertical device.

[0033] The semiconductor device 100 can include a semiconductor substrate 110 coupled to a first load terminal 310 and a second load terminal 320. Within the active region 102, the load current can conduct between the first load terminal 310 and the second load terminal 320. For example, the semiconductor substrate 110 can include a drift region for conduction of the load current. In the example shown, the load current path is in the vertical direction.

[0034] The first load terminal 310 can correspond, for example, to a metal structure 120, as combined with Figure 1As described above. That is to say, the metal structure 120 can be at least partially overlaid by the passivation layer 130. For example, the first load terminal 310 can be the source (or emitter) terminal of the semiconductor (transistor) device 100. The second load terminal 320 can be, for example, the drain (or collector) terminal of such a semiconductor device 100.

[0035] Within the edge termination region 103, the semiconductor device 100 can include an edge termination structure 330. The edge termination structure 330 can be, for example, partially or completely disposed within the semiconductor substrate 110.

[0036] On the upper surface 110A of the semiconductor substrate 110, the electric potentials of both load terminals 310, 320 can exist. For example, at the chip edge 104, along the entire vertical extension of the semiconductor substrate 110, the electric potential of the second load terminal 320 can exist. If, for example, the metal structure 120 is arranged adjacent to the chip edge 104 (as Figure 3 shown in the example), then the metal structure at the chip edge 104 is at the same electric potential as the second load terminal 320. Such an electric potential can be, for example, a high voltage electric potential equal to or greater than 0.2 kV, 0.5 kV, 0.7 kV, 1 kV, 1.5 kV, 2 kV, 3 kV or 5 kV or 7 kV.

[0037] On the other hand, the electric potential of the metal structure 120 forming the first load terminal 310 can be, for example, significantly lower, for example, approximately 0 V, or equal to or less than 10 V, 20 V or 30 V. Therefore, for a high voltage or power semiconductor device 100, the voltage applied between the first load terminal 310 and the second load terminal 320 can have a value substantially the same as the value mentioned above for the electric potential of the second load terminal 320. The voltage applied between the first load terminal 310 and the second load terminal 320 can be, for example, referred to as the "emitter-collector voltage" or the "source-drain voltage".

[0038] The edge termination region 103 can be configured to balance between these electric potentials, for example, to prevent electrical breakdown. Along the edge termination region 103, or correspondingly along the (optional) edge termination structure 330, the electric potential can transition from the electric potential of the first load terminal 310 to the electric potential of the second load terminal 320 (present at the chip edge 104). For example, on the first side of the edge termination region 103 or the corresponding (optional) edge termination structure 330, the electric potential can be equal to or similar to the electric potential of the first load terminal 310, and on the second side of the edge termination region 103 or the corresponding (optional) edge termination structure 330, the electric potential can be equal to or similar to the electric potential of the second load terminal 320. The first side of the edge termination region 103 or the corresponding edge termination structure 330 is closer to the active region 102, while the second side of the edge termination region 103 or the corresponding edge termination structure 330 is closer to the chip edge 104.

[0039] The passivation layer 130 can be arranged, for example, within a part of the active region 102, and / or within a part of the edge termination region 103 or over the entire extent of the edge termination region 103. For example, the second layer 130_2 of the passivation layer 130 can extend as a continuous layer from the chip edge 104 into the active region 102. The passivation layer 130 extends at least partially over the metal structure 120. The second layer 130_2 can, for example, partially extend over a non-metal structure (such as, for example, the edge termination structure 330). The first layer 130_1 does not extend over the non-metal structure. In other words, in the region above the non-metal structure in the vertical direction, the passivation layer 130 can include the second layer 130_2, but not the first layer 130_1. As Figure 3 illustrated by way of example, the passivation layer 130 can be arranged over the metal structure 120 within the active region 102, and / or can be arranged over the metal structure 120 within the edge termination region 103.

[0040] The edge termination structure 330 can be implemented in various different ways. For example, the edge termination structure 330 can include or embody a VLD (lateral doping variation) band. The VLD band can include a semiconductor region having a dopant concentration that decreases laterally towards the chip edge 104. Alternatively or additionally, the edge termination structure 330 can include or have an insulating layer, such as, for example, an oxide layer. For example, the edge termination structure 330 can include or be formed of a LOCOS (local oxidation of silicon) layer, which can optionally overlie a VLD band located below in the semiconductor substrate 110. In this case, the insulating layer of the edge termination structure 330 can electrically insulate the passivation layer 130 from the semiconductor substrate 110, or particularly, electrically insulate the passivation layer 130 from the VLD band formed in the semiconductor substrate 110. The insulating layer can extend along the entire extension between the metal structure 120 in the active region 102 and the metal structure 120 (if any) in the edge termination region 103 or the chip edge 104.

[0041] Since the passivation layer 130 can continuously extend from the metal structure 120 in the active region 102 to the chip edge 104 (or near the chip edge 104 or the metal structure 120 at the chip edge 104), the passivation layer 130 can provide a uniform high-ohmic conduction path between the first load terminal 310 and the chip edge 104 (and / or near the chip edge 104 or the metal structure 120 at the chip edge 104). For example, in the temperature range from 273K to 473K, the passivation layer 130 can have a conductivity equal to or greater than 1×10 -4 S or 2×10 -4 S and / or equal to or less than 5×10 -3 S. Such a high-ohmic conduction path is suitable for balancing the electric potential between the active region 102 and the chip edge 104.

[0042] The electrical properties of the passivation layer 130 are caused by a second layer 130_2. The second layer 130_2 includes or consists of silicon nitride in a modified form, which is not stoichiometric but has an increased silicon content.

[0043] More specifically, (stoichiometric) silicon nitride Si 3 N 4is an insulator. By increasing the silicon content in the second layer 130_2 such that the ratio of Si to N in terms of atomic number is equal to or greater than 3.3 / 4, the silicon nitride has a superstoichiometric Si content. The passivation properties of the superstoichiometric silicon nitride layer are still high. However, it is difficult to integrate such a superstoichiometric silicon nitride layer on a metal structure including or having Cu or a Cu-based alloy because the deposition process results in a thick CuSi layer and poor adhesion. Introducing a first layer 130_1 including, for example, a thin CuSiN layer under the superstoichiometric silicon nitride layer (the second layer 130_2) allows the integration of the second layer 130_2 on a Cu or Cu-based metal structure 120, and the passivation layer 130 has high adhesion on the metal structure 120.

[0044] For example, in at least a part of the second layer 130_2 (or in the whole second layer 130_2), in terms of atomic number, the ratio of silicon to nitride is equal to or greater than 3.3 / 4. In other examples, in terms of atomic number, the ratio of silicon to nitride in the second layer 130_2 may be equal to or greater than 3.6 / 4 or 3.8 / 4 or 1. For example, in the second layer 130_2, the number of silicon atoms may be, for example, equal to or greater than 82.5% or 90% or 100% of the number of nitrogen atoms. In some examples, in the second layer 130_2, the number of silicon atoms may be, for example, greater than the number of nitrogen atoms. In this case, in the second layer 130_2, the number of silicon atoms may be, for example, equal to or greater than 110% or 120% or 130% or 140% or 150% of the number of nitrogen atoms.

[0045] In some examples, the second layer 130_2 may include 40 to 55 at% (atomic percentage) Si. In these or other examples, the second layer 130_2 may include 30 to 45 at% N. According to a concentration, for example, between 12 and 17 at%, the second layer 130_2 may further include H. The typical values are 48 at% Si, 36 at% N, and 15 at% H. However, significant deviations from the typical values are possible.

[0046] Figure 4 A cross-sectional partial view showing an example of a semiconductor device 400. Figure 4 The part of the semiconductor device 400 shown may correspond to Figure 3 part D of. In other words, Figure 4 illustrates the transition from the active region 102 to the edge termination region 103. The chip edge 104 is not shown.

[0047] The first load terminal 310 (for example, a source pad) and the control terminal (for example, a gate pad (not shown)) may be located above the upper surface 110A of the semiconductor substrate 110.

[0048] The semiconductor substrate 110 may include: a highly doped region 412 for contacting the second load terminal 320; and a plurality of highly doped regions 414 adjacent to the upper surface 110A of the semiconductor substrate 110. The highly doped regions 414 may be located in the active region 102 and / or in the edge termination region 103.

[0049] In the active region 102, the semiconductor device 400 may include a plurality of gate contacts 410. The gate contacts 410 are illustrated as trench gates in Figure 4 . For example, polysilicon gate contacts 410 may be used. Reference numeral 440 refers to a gate dielectric that insulates the gate contact 410 from a channel region (not shown) of the (transistor) semiconductor device 400, for example. The channel region may be located in the highly doped region 414 along the gate contact 410 in the vertical direction, for example.

[0050] For example, the gate contact 410 may be connected to a gate track 420. The gate track 420 may be insulated from the semiconductor substrate 110 by an insulating layer 430. The insulating layer 430 may be an oxide layer, for example. The insulating layer 430 may be a LOCOS layer, for example. The insulating layer 430 may form part of the edge termination structure 330, for example.

[0051] The semiconductor device 400 may further include a signal routing structure and / or a field plate. Reference numeral 450 refers to such a signal routing structure and / or a field plate.

[0052] The semiconductor device 400 may include metallization M. The metallization M may include or have Cu or a Cu-based alloy, for example.

[0053] The semiconductor device 400 may include a dielectric layer 480, for example, which may also be referred to as an interlayer dielectric. The dielectric layer 480 may include or have an organic or inorganic dielectric material. The dielectric layer 480 is an electrically insulating layer.

[0054] A barrier layer 460 may be applied over the dielectric layer 480. The barrier layer 460 may be structured to cover only a portion of the surface of the dielectric layer 480. For example, in a region where the dielectric layer 480 (overlapping with the dielectric layer 480) is overlaid on the metallization M (e.g., a metal structure 120 formed by structuring the metallization M), the barrier layer 460 may completely cover the dielectric layer 480 to completely separate the dielectric layer 480 from the metallization M. In other regions where the dielectric layer 480 is not covered by the metallization M, the barrier layer 460 may be omitted or may be structured to cover only a portion of the dielectric layer 480, as shown in Figure 4 as shown.

[0055] The barrier layer 460 may include or have a copper barrier material, such as TiW and / or TiN and / or W, for example. Other types of barrier layers 460 may also be used.

[0056] For example, a passivation layer 130 is formed over metallization M and / or dielectric layer 480. It may also be formed over barrier layer 460. As Figure 4 shown and as previously described, the passivation layer 130 may be a continuous layer that extends from the metal structure 120 (e.g., source pad) across the edge termination region 103 to the chip edge 104 (not shown). In other words, the entire chip surface except for the contact regions of the metal structure 120 may be effectively sealed by the passivation layer 130 against environmental erosion.

[0057] Additionally, an organic insulating layer 470 (e.g., an imide layer) may be disposed over the passivation layer 130. For example, the organic insulating layer 470 may be a continuous layer that extends over all of the edge termination region 103 to the chip edge 104 (not shown). The organic insulating layer 470 may extend, for example, over a portion of the metal structure 120 of the metallization M and over the entire extent of the passivation layer 130 outside of the metal structure 120.

[0058] The organic insulating layer 470 may include, for example, polyimide (PI) (commonly referred to as imide) and / or polybenzoxazole (PBO) and / or epoxy resin and / or similar organic dielectrics.

[0059] The organic insulating layer 470 may have a thickness equal to or greater than 5 μm, 8 μm, or 10 μm and equal to or less than 20 μm, 15 μm, or 12 μm. For example, the thickness of the organic insulating layer 470 may be 11 μm.

[0060] For example, the organic insulating layer 470 and / or the passivation layer 130 may not reach, for example, any region between the dielectric layer 480 and the metallization M. Additionally, for example, in some regions, only the organic insulating layer 470 and the passivation layer 130 may be used to cover the dielectric layer 480.

[0061] Referring Figure 5 , exemplary stages of manufacturing semiconductor devices 100, 400 are described. In S1, a semiconductor substrate 110 is provided. The semiconductor substrate 110 (e.g., silicon body) may have undergone FEOL (front-end-of-line) processing to form integrated circuits therein.

[0062] In S2, a metal structure 120 is formed over the semiconductor substrate 110. The metal structure 120 may include or have Cu or a Cu-based alloy. As described above, the insulating layer 430 and / or the barrier layer 460 may be formed before forming the metal structure 120.

[0063] By depositing a metal layer and structuring this layer, for example, by Cu chemical wet etching, the metal structure 120 can be formed. The layer can be formed by sputtering or electroplating of a metal (e.g., Cu or a Cu-based alloy). Optionally, a chemical mechanical polishing (CMP) process can follow.

[0064] At S3, the passivation layer 130 is formed over the metal structure 120. The formation of the passivation layer 130 includes: forming a first layer 130_1 including CuSiN; and forming a second layer 130_2 including Si, N, and H.

[0065] Before forming the passivation layer 130 over the metal structure 120, a metal oxide (e.g., copper oxide) can be removed from the metal structure 120. For example, by plasma treatment, using a hydrogen precursor, the oxide removal can be carried out. The hydrogen precursor can, for example, include NH 3 and / or H 2 , or be NH3 and / or H2.

[0066] For example, a processing chamber (also known in the art as a reaction chamber) in which the semiconductor substrate 110 with the exposed metal structure 120 is placed is filled with a mixture of NH 3 and N 2 . By igniting a hydrogen plasma, the oxide is removed.

[0067] The formation of the first layer 130_1 including CuSiN can start with setting a controlled low flow rate of a gaseous Si compound (e.g., silane), at this time without plasma treatment. The silane reacts thermally with copper to produce copper silicide (CuSi) on the surface of the metal structure 120. For example, a flow rate of 34 sccm of silane (e.g., monosilane SiH 4 ) and a flow rate of 4500 sccm of N 2 can be used.

[0068] All the flow rates given here are exemplary. For example, they can refer to 300 mm wafers.

[0069] The silicidation of the metal surface can be followed by plasma treatment. The plasma treatment is used for the subsequent nitridation of the silicided metal surface. For example, plasma treatment using NH 3 is carried out to produce copper silicon nitride (CuSiN) of the first layer 130_1.

[0070] The thus-formed CuSiN surface is stable and appears inert to many chemicals. In particular, the CuSiN surface does not undergo a thermal reaction with silane. In other words, when the metal structure 120 coated with the first layer 130_1 (including the CuSiN layer) is exposed to silane or another gas Si compound for silicon deposition, no silicon is thermally deposited on such a surface.

[0071] Only a small portion of CuSi may be converted to CuSiN. For example, a CuSiN layer 130_1b with a thickness in the range between 1 and 15 nm (in particular, between 3 and 9 nm) may be formed over the (optional) CuSi layer 130_1a. The CuSi layer 130_1a may have a thickness in the range between 0 nm and 200 nm (in particular, between 0 and 100 nm).

[0072] That is to say, the first layer 130_1 may include two layers, namely, the CuSi layer 130_1a and the CuSiN layer 130_1b. The (optional) CuSi layer 130_1a may have a thickness in the range between 0 nm and 200 nm or between 0 nm and 150 nm or in the range of 50±50 nm or 50±40 nm or 50±30 nm or 50±20 nm or 50±10 nm or 50±0 nm. Above a thickness of 100 nm, a deterioration in bondability is noted. It should be noted that the term "CuSi" used here means CuSi x , since the stoichiometry (indicated by x) can be changed according to the gas flow rate used.

[0073] Subsequently, the gas flow settings in the processing chamber are adjusted to prepare for the formation of the second layer 130_2 of the passivation layer 130. This includes the flow rate setting of the gas Si compound (e.g., silane). A much higher flow rate of the silicon precursor gas (i.e., the gas Si compound) is required (e.g., about 700 sccm). Generally, it takes several seconds to reach a stable flow condition in the processing chamber for setting the appropriate gas flow, e.g., about 10 s. During this time, the CuSiN layer 130_1b prevents any thermal reaction of the Cu surface with the silicon precursor gas. In other words, CuSi will not grow during the gas flow setting process. Optionally, before the deposition of the second layer 130_2, other processes (e.g., the deposition of the intermediate layer 130_x) may be performed.

[0074] After reaching the stable flow condition, the formation of the second layer 130_2 including Si, N, and H in the aforementioned components may start with plasma ignition. The thickness of the second layer 130_2 depends on the flow rate of the process gas and the processing time in the processing chamber. For example, a relatively high gas flow of the gas Si compound between 500 sccm and 1200 sccm may be used. For example, the gas N compound (e.g., N2 and / or NH 3 ) can, for example, be set between 3000 and 5000 sccm or even 8000 sccm. The first layer 130_1 (specifically, CuSiN contained therein) allows the deposition of a second layer 130_2 with a superstoichiometric Si content in a controllable manner.

[0075] Figure 6 is a flow chart illustrating exemplary stages of forming a passivation layer 130 over a metal structure 120 according to S3.

[0076] In S3_1, a CuSi layer 130_1a can be formed by thermal decomposition of a gaseous Si compound (specifically, silane). At this stage, no plasma is ignited.

[0077] In S3_2, the CuSi layer 130_1a can be exposed to a plasma containing N. As described above, the plasma containing N passivates (nitriding) the surface of the CuSi layer 130_1a by forming a CuSiN layer 130_1b to suppress thermal decomposition of Si thereon.

[0078] In S3_3, the first layer 130_1 (including the CuSiN layer 130_1b) can be exposed to a plasma containing Si and a plasma containing N. At this processing stage, the second layer 130_2 is formed.

[0079] Example

[0080] The following examples relate to further aspects of the present disclosure:

[0081] Example 1 is a semiconductor device including a semiconductor substrate. A metal structure is disposed over the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy. A passivation layer is disposed over the metal structure, wherein the passivation layer includes: a first layer including CuSiN; and a second layer including Si, N, and H, wherein, in terms of atomic amounts, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0082] In Example 2, the subject matter of Example 1 can optionally include, wherein the ratio of Si to N is equal to or greater than 1.

[0083] In Example 3, the subject matter of Example 1 or 2 can optionally include, wherein the second layer includes 40 to 55 at% Si.

[0084] In Example 4, the subject matter of any of the preceding examples can optionally include, wherein the second layer includes 30 to 45 at% N.

[0085] In Example 5, the subject matter of any of the preceding examples can optionally include, wherein the second layer includes 12 to 17 at% H.

[0086] In Example 6, the subject matter of any of the preceding examples can optionally include, wherein the first layer includes a CuSiN layer having a thickness of 1 to 15 nm.

[0087] In Example 7, the subject matter of Example 6 can optionally include, wherein the first layer further includes a CuSi layer having a thickness of 0 to 200 nm, and the CuSi layer is disposed below the CuSiN layer.

[0088] In Example 8, the subject matter of any of the preceding examples can optionally include, wherein the second layer has a layer thickness of 40 to 500 nm.

[0089] In Example 9, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor device includes an active region, a chip edge, and an edge termination region separating the active region from the chip edge, and the second layer extends above at least a portion of the edge termination region to near the chip edge or to the chip edge.

[0090] In Example 10, the subject matter of any of the preceding examples can optionally further include: a third layer disposed between the first layer and the second layer, and the third layer includes alumina.

[0091] In Example 11, the subject matter of any of the preceding examples can optionally further include: an imide layer disposed above the passivation layer.

[0092] In Example 12, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor device is a high-voltage device.

[0093] In Example 13, the subject matter of any of the preceding examples can optionally include, wherein the metal structure includes one or more of a chip pad, a gate track, and / or a field plate of the semiconductor device.

[0094] In Example 14, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor device is a vertical device or a lateral device.

[0095] In Example 15, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor device is an IGBT, a MOSFET, a JFET, a P-FET, an N-FET, an AFET, a planar gate transistor, a field plate trench transistor, or a superjunction transistor or a diode.

[0096] Example 16 is a method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; forming a metal structure over the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy; and forming a passivation layer over the metal structure, the forming of the passivation layer comprising: forming a first layer comprising CuSiN, and forming a second layer comprising Si, N, and H, wherein, in terms of the number of atoms, the ratio of Si to N is equal to or greater than 3.3 / 4.

[0097] In Example 17, the subject matter of Example 16 can optionally include, wherein forming the first layer comprises: forming an initial CuSi layer; and exposing the CuSi layer to a plasma containing N.

[0098] In Example 18, the subject matter of Example 16 or 17 can optionally include, wherein the CuSi layer is formed by thermal decomposition of a gaseous Si compound, particularly silane.

[0099] In Example 19, the subject matter of any one of Examples 16 to 18 can optionally include, wherein forming the second layer comprises: exposing the first layer to a plasma containing Si and a plasma containing N.

[0100] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A metal structure disposed on the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy; and A passivation layer is disposed on the metal structure, wherein the passivation layer comprises: A first layer comprising CuSiN; and The second layer includes Si, N and H, wherein the ratio of Si to N in terms of atomic number is equal to or greater than 3.3 / 4. 2 . The semiconductor device according to claim 1 , wherein a ratio of Si to N is equal to or greater than 1. 3 .

3. The semiconductor device according to claim 1 or 2, wherein the second layer comprises 40 to 55 at% Si.

4. The semiconductor device as claimed in any one of the preceding claims, wherein the second layer comprises 30 to 45 at% N.

5. A semiconductor device as claimed in any one of the preceding claims, wherein the second layer comprises 12 to 17 at% H.

6. A semiconductor device as claimed in any one of the preceding claims, wherein the first layer comprises a CuSiN layer having a thickness of 1 to 15 nm. 7 . The semiconductor device according to claim 6 , wherein the first layer further comprises a CuSi layer having a thickness of 0 to 200 nm, the CuSi layer being arranged below the CuSiN layer. 8 . The semiconductor device as claimed in claim 1 , wherein the second layer has a layer thickness of 40 to 500 nm.

9. A semiconductor device as claimed in any one of the preceding claims, wherein the semiconductor device comprises an active area, a chip edge and an edge termination area separating the active area from the chip edge, and the second layer extends over at least a portion of the edge termination area to near or to the chip edge.

10. The semiconductor device according to any one of the preceding claims, further comprising: A third layer is disposed between the first layer and the second layer, and the third layer includes aluminum oxide.

11. The semiconductor device according to any one of the preceding claims, further comprising: An imide layer is disposed on the passivation layer.

12. A semiconductor device as claimed in any preceding claim, wherein the semiconductor device is a high voltage device.

13. The semiconductor device of any one of the preceding claims, wherein the metal structure comprises one or more of a chip pad, a gate track and / or a field plate of the semiconductor device.

14. The semiconductor device of any one of the preceding claims, wherein the semiconductor device is a vertical device or a lateral device.

15. The semiconductor device of any one of the preceding claims, wherein the semiconductor device is an IGBT, a MOSFET, a JFET, a P-FET, an N-FET, an AFET, a planar gate transistor, a field plate trench transistor or a super junction transistor or a diode.

16. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; forming a metal structure on the semiconductor substrate, wherein the metal of the metal structure is Cu or a Cu-based alloy; and A passivation layer is formed on the metal structure, wherein the formation of the passivation layer comprises: forming a first layer including CuSiN, and A second layer including Si, N, and H is formed, wherein a ratio of Si to N in terms of atomic number is equal to or greater than 3.3 / 4.

17. The method of claim 16, wherein forming the first layer comprises: forming an initial CuSi layer; and The CuSi layer is exposed to a plasma containing N.

18. The method as claimed in claim 17, wherein the CuSi layer is formed by thermal decomposition of a gaseous Si compound, in particular silane.

19. The method of any one of claims 16 to 18, wherein forming the second layer comprises: The first layer is exposed to a Si-containing and N-containing plasma.

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