Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a first protection layer, a first conductive layer, a second protection layer, a first seed layer and a second conductive layer. The substrate comprises a base, at least one connecting pad and an insulating layer. The first protective layer has at least one first opening exposing a portion of the connecting portion of the at least one pad. The orthographic projection of the first conductive layer on the substrate does not overlap the at least one pad. The second protection layer is provided with at least one second opening which exposes the first part of the first conductive layer and a part of the first protection layer and is communicated with the at least one first opening. The first seed layer is disposed in the at least one second opening, in the at least one first opening and on the connecting portion exposed by the at least one first opening and extends to a portion of the second protective layer. The second conductive layer contacts the at least one pad and the first conductive layer through the first seed layer. According to the semiconductor structure, the resistance value in the conductive layer can be reduced, and the semiconductor structure has better electrical reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure with better electrical reliability. Background Art

[0002] In a semiconductor structure of the prior art including two protective layers and two metal layers (2P2M), since the formation of the metal layer requires a seed layer, the test pads on the pads of the substrate are thus composed of two metal layers plus two seed layers. However, when the seed layer contains a metal with a relatively high resistance value, the contact resistance value will increase. In the design of high-end electronic products, the circuit impedance value has become one of the necessary considerations for high transmission speed. Summary of the Invention

[0003] The present invention is directed to a semiconductor structure that can reduce the resistance value in the conductive layer and can have better electrical reliability.

[0004] According to an embodiment of the present invention, the semiconductor structure includes a substrate, a first protective layer, a first conductive layer, a second protective layer, a first seed layer, and a second conductive layer. The substrate includes a base, at least one pad, and an insulating layer. At least one pad is disposed on the base. The insulating layer covers the base and at least one pad. The insulating layer exposes a connection portion of at least one pad. The first protective layer is disposed on the insulating layer of the substrate and has at least one first opening exposing a partial connection portion of at least one pad. The first conductive layer is disposed on the first protective layer, wherein a positive projection of the first conductive layer on the substrate does not overlap at least one pad. The second protective layer is disposed on the first conductive layer and the first protective layer and has at least one second opening exposing a first portion of the first conductive layer and a portion of the first protective layer and communicating with at least one first opening. The first seed layer is disposed in at least one second opening, at least one first opening, and on a connection portion exposed by at least one first opening and extends onto a portion of the second protective layer. The second conductive layer is disposed at least on the first seed layer, wherein the second conductive layer contacts at least one pad and the first conductive layer through the first seed layer.

[0005] In the semiconductor structure according to an embodiment of the present invention, the first portion of the first conductive layer, the first seed layer, and the second conductive layer on the first seed layer define at least one test pad.

[0006] In the semiconductor structure according to an embodiment of the present invention, the semiconductor structure further includes a second seed layer, wherein the second protective layer further has at least one third opening exposing a second portion of the first conductive layer. The second seed layer is disposed in at least one third opening. The second seed layer and the first seed layer belong to the same film layer. The second conductive layer is further disposed in at least one third opening and extends onto a portion of the second protective layer.

[0007] In a semiconductor structure according to an embodiment of the present invention, a second portion of the first conductive layer, the second seed layer, and the second conductive layer on the second seed layer define at least one pad.

[0008] In a semiconductor structure according to an embodiment of the present invention, the second conductive layer includes a copper layer, a nickel layer, and a gold layer. The copper layer is in direct contact with the first seed layer, and the nickel layer is located between the copper layer and the gold layer.

[0009] In a semiconductor structure according to an embodiment of the present invention, in a top view, the second conductive layer and the first conductive layer have an overlapping region. The width of the overlapping region is at least greater than 5 microns.

[0010] In a semiconductor structure according to an embodiment of the present invention, the first conductive layer includes a redistribution layer.

[0011] In a semiconductor structure according to an embodiment of the present invention, the diameter of at least one first opening is between 40 microns and 60 microns.

[0012] In a semiconductor structure according to an embodiment of the present invention, the material of the first seed layer includes titanium copper.

[0013] In a semiconductor structure according to an embodiment of the present invention, the semiconductor structure further includes a dielectric layer disposed between the first protective layer and the insulating layer of the substrate. The dielectric layer has at least one dielectric opening exposing a partial connection portion of at least one pad, and the first protective layer extends to cover at least within the dielectric opening.

[0014] Based on the above, in the design of the semiconductor structure of the present invention, the orthographic projection of the first conductive layer on the substrate does not overlap at least one pad, and the second conductive layer contacts the pad and the first conductive layer through the first seed layer. Compared with the prior art, the second conductive layer of the present invention only contacts the pad through the first seed layer, which means one less seed layer, so the resistance value within the conductive layer can be effectively reduced, and the electrical reliability of the semiconductor structure of the present invention can be improved. Description of the Drawings

[0015] Figure 1A is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0016] Figure 1B is Figure 1A a cross-sectional schematic diagram taken along line I-I;

[0017] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0018] Description of the Reference Numerals

[0019] 100a, 100b: Semiconductor structures;

[0020] 110a, 110b: Substrates;

[0021] 112: Base;

[0022] 114a, 114b, 119: Pads;

[0023] 115a: Connection portion;

[0024] 116: Insulating layer;

[0025] 118: Through-silicon via;

[0026] 120: First protective layer;

[0027] 122: First opening;

[0028] 130: First conductive layer;

[0029] 132: First part;

[0030] 134: Second part;

[0031] 140: Second protective layer;

[0032] 142: Second opening;

[0033] 144: Third opening;

[0034] 150: First seed layer;

[0035] 152: Second seed layer;

[0036] 155: Seed layer;

[0037] 160: Second conductive layer;

[0038] 162: Copper layer;

[0039] 164: Nickel layer;

[0040] 166: Gold layer;

[0041] 170: Dielectric layer;

[0042] 172: Dielectric opening;

[0043] A: Overlap region;

[0044] B: Bond pad;

[0045] D: Aperture;

[0046] T: Test pad;

[0047] W: Width. Detailed Embodiments

[0048] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0049] Embodiments of the present invention can be understood in conjunction with the accompanying drawings, and the accompanying drawings of the present invention are also regarded as part of the disclosure. It should be understood that the accompanying drawings of the present invention are not drawn to scale. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0050] Figure 1A is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1B is along Figure 1A sectional schematic diagram taken along line I-I. Please refer to Figure 1A and Figure 1B simultaneously. In this embodiment, the semiconductor structure 100a includes a substrate 110a, a first protective layer 120, a first conductive layer 130, a second protective layer 140, a first seed layer 150, and a second conductive layer 160. The substrate 110a includes a base 112, at least one pad (a pad 114a is schematically shown), and an insulating layer 116. The pad 114a is disposed on the base 112. The insulating layer 116 covers the base 112 and the pad 114a. The insulating layer 116 exposes a connection portion 115a of the pad 114a. The first protective layer 120 is disposed on the insulating layer 116 of the substrate 110 and has at least one first opening (a first opening 122 is schematically shown) that exposes a partial connection portion 115a of the pad 114a. The first conductive layer 130 is disposed on the first protective layer 120, wherein the orthographic projection of the first conductive layer 130 on the substrate 110a does not overlap the pad 114a. The second protective layer 140 is disposed on the first conductive layer 130 and the first protective layer 120 and has at least one second opening (a second opening 142 is schematically shown) that exposes a first portion 132 of the first conductive layer 130, a portion of the first protective layer 120, and communicates with the first opening 122. The first seed layer 150 is disposed in the second opening 142, in the first opening 122, and on the connection portion 115a exposed by the first opening 122 and extends onto a portion of the second protective layer 140. The second conductive layer 160 is disposed at least on the first seed layer 150, wherein the second conductive layer 160 contacts the pad 114a and the first conductive layer 130 through the first seed layer 150.

[0051] In one embodiment, the substrate 112 may be, for example, a silicon substrate such as a wafer, and the pad 114a may be, for example, an input / output pad on the wafer, and its material may be aluminum, but not limited thereto. For multi-layer protection, the semiconductor structure 100a of this embodiment may also selectively include a dielectric layer 170 disposed between the first protective layer 120 and the insulating layer 116 of the substrate 110a. The dielectric layer 170 has at least one dielectric opening (schematically showing a dielectric opening 172) exposing a partial connection portion 115a of the pad 114a, and the first protective layer 120 may extend to cover within the dielectric opening 172. In one embodiment, the diameter D of the first opening 122 of the first protective layer 120 may be, for example, between 20 micrometers and 60 micrometers.

[0052] In this embodiment, the first conductive layer 130 may be, for example, a redistribution layer. Since the orthographic projection of the first conductive layer 130 on the substrate 110a does not overlap the pad 114a, the orthographic projection of the seed layer 155 below the first conductive layer 130 on the substrate 110a will not overlap the pad 114a either. The materials of the first seed layer 150 and the seed layer 155 are respectively, for example, titanium copper, where the thickness of titanium is, for example, 1k angstroms and the thickness of copper is, for example, 1.5k angstroms, but not limited thereto. The diameter of the second opening 142 of the second protective layer 140 is larger than the diameter of the first opening 122 of the first protective layer 120. The second conductive layer 160 includes a copper layer 162, a nickel layer 164, and a gold layer 166, where the copper layer 162 directly contacts the first seed layer 150, and the nickel layer 164 is located between the copper layer 162 and the gold layer 166. In a top view, the second conductive layer 160 and the first conductive layer 130 have an overlapping area A, where the width W of the overlapping area A is, for example, at least greater than 5 micrometers.

[0053] In addition, the first portion 132 of the first conductive layer 130, the first seed layer 150, and the second conductive layer 160 on the first seed layer 150 of this embodiment may define at least one test pad (schematically showing a test pad T). In one embodiment, the top view shape of the test pad T is, for example, rectangular, where the size of the test pad T is, for example, between 30 micrometers and 70 micrometers, but not limited thereto. Furthermore, the semiconductor structure 100a of this embodiment further includes a second seed layer 152, where the second protective layer 140 also has at least one third opening (schematically showing a third opening 144) exposing the second portion 134 of the first conductive layer 130. The second seed layer 152 is disposed within the third opening 144. The second seed layer 152 and the first seed layer 150 belong to the same film layer. The second conductive layer 160 is also disposed within the third opening 144 and extends onto a part of the second protective layer 140. The second portion 134 of the first conductive layer 130, the second seed layer 152, and the second conductive layer 160 on the second seed layer 152 define at least one bonding pad (schematically showing a bonding pad B).

[0054] Generally speaking, the resistance value of the test pad T is calculated in parallel. Therefore, in this embodiment, since the orthographic projection of the first conductive layer 130 on the substrate 110a does not overlap with the pad 114a, that is, the first conductive layer 130 is offset from the pad 114a by a distance, so that the second conductive layer 140 can contact the pad 114a and the first conductive layer 130 only through the first seed layer 150. Compared with the prior art, since the second conductive layer 140 contacts the pad 114a only through the first seed layer 150, that is, one seed layer is reduced (one layer of titanium metal can be reduced), the resistance value in the conductive layer can be effectively reduced, and the electrical reliability of the semiconductor structure 100a of this embodiment can be improved.

[0055] It should be noted here that the following embodiments follow the component numbers and some contents of the foregoing embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0056] Figure 2 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention. Please also refer to Figure 1A and Figure 2 . The semiconductor structure 100b of this embodiment is similar to the above-mentioned semiconductor structure 100a. The difference between the two is that in this embodiment, the substrate 110b of the semiconductor structure 100b further includes a through-silicon via (TSV) 118 and a pad 119, wherein the through-silicon via 118 penetrates the substrate 112, and the pads 114b and 119 are respectively disposed on opposite sides of the substrate 112, and the through-silicon via 118 is structurally and electrically connected to the pads 114b and 119. In other words, the pad 114b of this embodiment is a through-silicon via pad.

[0057] In summary, in the design of the semiconductor structure of the present invention, the orthographic projection of the first conductive layer on the substrate does not overlap at least one pad, and the second conductive layer contacts the pad and the first conductive layer through the first seed layer. Compared with the prior art, the second conductive layer of the present invention contacts the pad only through the first seed layer, that is, one seed layer is reduced, so the resistance value in the conductive layer can be effectively reduced, and the electrical reliability of the semiconductor structure of the present invention can be improved.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a base, at least one pad and an insulating layer, wherein the at least one pad is disposed on the base, the insulating layer covers the base and the at least one pad, and the insulating layer exposes a connection portion of the at least one pad; A first protection layer, disposed on the insulating layer of the substrate, and having at least one first opening exposing a portion of the connecting portion of the at least one pad; A first conductive layer, disposed on the first protective layer, wherein an orthographic projection of the first conductive layer on the substrate does not overlap the at least one pad; A second protection layer is disposed on the first conductive layer and the first protection layer, and has at least one second opening exposing a first portion of the first conductive layer and a portion of the first protection layer and communicating with the at least one first opening; A first seed layer is disposed in the at least one second opening, in the at least one first opening, and on the connecting portion exposed by the at least one first opening and extends onto a portion of the second protective layer; as well as The second conductive layer is at least disposed on the first seed layer, wherein the second conductive layer contacts the at least one pad and the first conductive layer through the first seed layer.

2. The semiconductor structure according to claim 1, characterized in that: The first portion of the first conductive layer, the first seed layer, and the second conductive layer on the first seed layer define at least one test pad.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A second seed layer, wherein the second protective layer also has at least one third opening exposing a second portion of the first conductive layer, the second seed layer is arranged in the at least one third opening, the second seed layer and the first seed layer belong to the same film layer, and the second conductive layer is also arranged in the at least one third opening and extends onto a portion of the second protective layer.

4. The semiconductor structure according to claim 3, characterized in that: The second portion of the first conductive layer, the second seed layer, and the second conductive layer on the second seed layer define at least one bonding pad.

5. The semiconductor structure according to claim 1, characterized in that: The second conductive layer includes a copper layer, a nickel layer and a gold layer. The copper layer directly contacts the first seed layer, and the nickel layer is located between the copper layer and the gold layer.

6. The semiconductor structure according to claim 1, characterized in that In a plan view, the second conductive layer and the first conductive layer have an overlapping area, and the width of the overlapping area is at least greater than 5 micrometers.

7. The semiconductor structure according to claim 1, characterized in that: The first conductive layer includes a redistribution layer.

8. The semiconductor structure according to claim 1, characterized in that: The diameter of the at least one first opening is between 40 micrometers and 60 micrometers.

9. The semiconductor structure according to claim 1, characterized in that: The material of the first seed layer includes titanium copper.

10. The semiconductor structure according to claim 1, characterized in that Also includes: The dielectric layer is disposed between the first protection layer and the insulating layer of the substrate, and has at least one dielectric opening exposing a portion of the connecting portion of the at least one pad, and the first protection layer extends to cover the at least one dielectric opening.

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