Semiconductor device

Abstract

The invention provides a semiconductor device in which the thickness of a bonding member bonding a front surface of a semiconductor chip and a lead frame is controlled to be uniform. A semiconductor device includes: a semiconductor chip (12) including a main electrode on a front surface; a conductive plate (11c) having, on the front surface thereof, a chip region to which the back surface of the semiconductor chip (12) is bonded; a conductive plate (11d) provided adjacent to the conductive plate (11c) in plan view; a support conductive plate (11c2) provided on the opposite side of the chip region from the conductive plate (11d) and insulated from the conductive plate (11c); and a lead frame (13) including a wiring bonding portion (13a) bonded to the support conductive plate (11c2), a wiring bonding portion (13b) bonded to the conductive plate (11d), and an electrode bonding portion (13c) bonded to the main electrode of the semiconductor chip (12) via a bonding member (15b).

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] A semiconductor device includes two semiconductor chips and a jig that connects electrodes on the front surfaces of the two semiconductor chips (for example, refer to Patent Document 1). In addition, a semiconductor device includes two power semiconductor chips arranged on a P-potential lead and inner leads that respectively bond electrodes on the front surfaces of the two power semiconductor chips and an AC-potential lead (for example, refer to Patent Document 2).

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-251500 Patent Document 2: Japanese Unexamined Patent Application Publication No. 2021-166215 Summary of the Invention

[0004] Technical Problem An object of the present invention is to provide a semiconductor device in which the thickness of a bonding member that bonds the front surface of a semiconductor chip and a lead frame is controlled to be uniform.

[0005] Technical Solution According to one aspect of the present invention, there is provided a semiconductor device having: a semiconductor chip including a main electrode on a front surface; a first conductive plate including a first main surface on which a chip region for bonding the back surface of the semiconductor chip is set; a second conductive plate disposed adjacent to the first conductive plate in a plan view; a support portion provided on the first conductive plate, disposed on a side opposite to the second conductive plate with respect to the chip region and insulated from the first conductive plate; and a lead frame including a first bonding portion that bonds to the support portion, a second bonding portion that bonds to the second conductive plate, and an electrode bonding portion that bonds to the main electrode of the semiconductor chip via a bonding member.

[0006] In addition, the support portion may be disposed in an opening region formed in the first conductive plate so as not to contact the first conductive plate.

[0007] In addition, the support portion may be made of the same material as the first conductive plate.

[0008] In addition, in the lead frame, a first length from the electrode bonding portion to the first bonding portion may be equal to a second length from the electrode bonding portion to the second bonding portion.

[0009] Alternatively, the lead frame may include a flat first connecting portion connecting between the electrode bonding portion and the first bonding portion, and a flat second connecting portion connecting between the electrode bonding portion and the second bonding portion. A first height from the first bonding portion to the first connecting portion is higher than a third height from the electrode bonding portion to the first connecting portion, and a second height from the second bonding portion to the second connecting portion is higher than a fourth height from the electrode bonding portion to the second connecting portion.

[0010] Alternatively, when viewed from above, the lead frame may linearly extend from the electrode bonding portion to the first bonding portion.

[0011] Alternatively, when viewed from above, the lead frame may linearly extend from the electrode bonding portion to the second bonding portion.

[0012] Alternatively, when viewed from above, the lead frame may linearly extend from the first bonding portion to the second bonding portion.

[0013] Alternatively, the lead frame may include a plurality of the second bonding portions, and when viewed from above, linearly extend from the electrode bonding portion to the plurality of second bonding portions respectively.

[0014] Alternatively, when viewed from above, the electrode bonding portion may correspond to the position of the center of gravity of the lead frame.

[0015] Alternatively, the lead frame may include elastic portions between the electrode bonding portion and the first bonding portion, and between the electrode bonding portion and the second bonding portion respectively.

[0016] Alternatively, the lead frame may include a flat first connecting portion connecting between the electrode bonding portion and the first bonding portion, and a flat second connecting portion connecting between the electrode bonding portion and the second bonding portion. The elastic portions are respectively provided on the first connecting portion and the second connecting portion, and the entire widths of the elastic portions of the first connecting portion and the second connecting portion are bent in the thickness direction.

[0017] It should be noted that the above description of the invention does not list all the features required by the present invention. In addition, sub - combinations of these feature groups can also form inventions.

[0018] Technical Effects According to the technology of the present invention, it is possible to control the thickness of the bonding component that bonds the front surface of the semiconductor chip and the lead frame uniformly. Description of the Drawings

[0019] Figure 1It is a top view of the semiconductor device of the first embodiment.

[0020] Figure 2 It is a side view of the semiconductor device of the first embodiment.

[0021] Figure 3 It is a top view of the semiconductor cell included in the semiconductor device of the first embodiment.

[0022] Figure 4 It is a first cross-sectional view of the semiconductor cell included in the semiconductor device of the first embodiment.

[0023] Figure 5 It is a second cross-sectional view of the semiconductor cell included in the semiconductor device of the first embodiment.

[0024] Figure 6 It is a flowchart showing the manufacturing method of the semiconductor device of the first embodiment.

[0025] Figure 7 It is a top view of the insulating circuit board included in the semiconductor device of the first embodiment.

[0026] Figure 8 It is a view showing the placement process included in the manufacturing method of the semiconductor device of the first embodiment.

[0027] Figure 9 It is a view showing the first bonding process included in the manufacturing method of the semiconductor device of the first embodiment.

[0028] Figure 10 It is a top view of the semiconductor cell included in the semiconductor device of the reference example.

[0029] Figure 11 It is a view showing the placement process included in the manufacturing method of the semiconductor device of the reference example.

[0030] Figure 12 It is a view showing the first bonding process included in the manufacturing method of the semiconductor device of the reference example.

[0031] Figure 13 It is a top view of the semiconductor cell included in the semiconductor device of the first embodiment (modification example 1-1).

[0032] Figure 14 It is a cross-sectional view of the semiconductor cell included in the semiconductor device of the first embodiment (modification example 1-1).

[0033] Figure 15 It is a top view of the semiconductor cell included in the semiconductor device of the second embodiment.

[0034] Figure 16This is a diagram showing the first bonding process included in the manufacturing method of the semiconductor device of the third embodiment.

[0035] Symbol Explanation 1 Semiconductor device 2 Semiconductor module 3 Cooling device 10, 10a, 10b, 10c Semiconductor cells 11 Insulating circuit board 11a Insulating plate 11a1, 11a2, 11a3, 11a4 Sides 11a5, 11a6, 11a7, 11a8 Corners 11b, 11c, 11d Conductive plates 11b1, 11c1 Depressions 11b2, 11c2 Support conductive plates 11b3, 11c3 Chip areas 11b4, 11c4 Support block parts 11e Metal plate 12 Semiconductor chip 12a Control electrode 12b Main electrode 13, 14 Lead frames 13a, 13b, 14a, 14b, 13b2, 13b3, 14b2, 14b3 Wiring bonding parts 13a1, 13b1, 13c1, 14a1, 14b1 Protrusions 13c, 14c Electrode bonding parts 13d, 13e, 14d, 14e, 13e2, 13e3, 14e2, 14e3 Connection parts 13f, 13g Elastic parts 15a, 15b Bonding components 15a1, 15b1 Bonding plates 20 Housing 21 Frame part 21a, 21b, 21c, 21d Outer walls 21e, 21f, 21g Unit accommodation parts 21i Fixing holes 22a, 22b, 22c First connection terminals 23a, 23b, 23c Second connection terminals 24a U-phase output terminal 24b V-phase output terminal 24c W-phase output terminal 25a, 25b, 25c control terminals 31 top plate 32 side wall 33 cooling bottom plate 33a inlet 33b outlet 33d bottom surface Detailed implementation manners

[0036] Hereinafter, the implementation manners will be described with reference to the drawings. In the following description, "front" and "upper surface" indicate the X-Y plane facing the upper side (+Z direction) in the semiconductor device in the drawings. Similarly, "up" indicates the direction of the upper side (+Z direction) in the semiconductor device in the drawings. "Back" and "lower surface" indicate the X-Y plane facing the lower side (-Z direction) in the semiconductor device in the drawings. Similarly, "down" indicates the direction of the lower side (-Z direction) in the semiconductor device in the drawings. The same directionality as described above is also indicated in other drawings as needed. "Higher" and "upper position" indicate positions on the upper side (+Z direction) in the semiconductor device in the drawings. Similarly, "lower" and "lower position" indicate positions on the lower side (-Z direction) in the semiconductor device in the drawings. "Front", "upper surface", "up" and "back", "lower surface", "down" and "side" are just expressions for conveniently determining the relative positional relationship, and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily refer to the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. In addition, in the following description, "main component" means a case where it contains 80 vol% or more. In addition, "substantially the same" means a range within ±10%. In addition, "vertical", "orthogonal", and "parallel" mean a range within ±10°.

[0037] [First Embodiment] Use Figure 1 And Figure 2 The semiconductor device 1 of the first embodiment will be described. Figure 1 is a top view of the semiconductor device of the first embodiment, Figure 2 is a side view of the semiconductor device of the first embodiment. It should be noted that Figure 2 is in Figure 1 is a side view obtained by observing the X-Z plane along the +Y direction.

[0038] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, 10c and a housing 20 that houses the semiconductor units 10a, 10b, 10c. The semiconductor units 10a, 10b, 10c housed in the housing 20 may be sealed by a sealing member (not shown).

[0039] It should be noted that the semiconductor units 10a, 10b, and 10c have the same configuration. Without distinguishing between the semiconductor units 10a, 10b, and 10c, they will be described as the semiconductor unit 10. The details of the semiconductor unit 10 will be described later.

[0040] The housing 20 includes a frame portion 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminals 24a, V-phase output terminals 24b, W-phase output terminals 24c, and control terminals 25a, 25b, 25c.

[0041] The frame portion 21 is substantially rectangular in plan view and is surrounded by outer walls 21a, 21b, 21c, and 21d. The outer walls 21a and 21c correspond to the long sides of the frame portion 21 in plan view, and the outer walls 21b and 21d similarly correspond to the short sides of the frame portion 21. In plan view, the corners of the connecting portions of the outer walls 21a, 21b, 21c, and 21d do not have to be right angles. As Figure 1 shown, these corners can be R-chamfered. Fixing holes 21i penetrating the frame portion 21 are respectively formed at the corners on the front surface of the frame portion 21. It should be noted that the fixing holes 21i formed at such corners of the frame portion 21 can be formed at positions lower (-Z direction) than the front surface of the frame portion 21.

[0042] The frame portion 21 includes unit accommodation portions 21e, 21f, and 21g along the outer walls 21a and 21c on the front surface. The unit accommodation portions 21e, 21f, and 21g are open in a rectangular shape in plan view. The semiconductor units 10a, 10b, and 10c are respectively accommodated in the unit accommodation portions 21e, 21f, and 21g. The semiconductor units 10a, 10b, and 10c are respectively joined to the top plate 31 of the cooling device 3 described later. The frame portion 21 is mounted on the top plate 31 of such a cooling device 3. At the time of mounting, the unit accommodation portions 21e, 21f, and 21g of the frame portion 21 respectively surround (accommodate) the semiconductor units 10a, 10b, and 10c arranged in the cooling device 3. It should be noted that an inflow port 33a and an outflow port 33b are formed on the bottom surface 33d of the cooling device 3 (the opposite surface of the top plate 31 on which the semiconductor unit 10 is mounted). The details of the cooling device 3 will be described later.

[0043] In a plan view, the frame portion 21 is provided with first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c along the outer wall 21a on the front side of the outer wall 21a. The outer end portions of one side of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c are exposed on the front side of the outer wall 21a. The inner end portions of the other side are exposed in the unit accommodation portions 21e, 21f, 21g and are electrically connected to the semiconductor units 10a, 10b, 10c. It should be noted that nuts opposed to the openings of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c can be accommodated in the region of the front surface of the frame portion 21 opposed to the openings.

[0044] On the front side of the outer wall 21c, a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c are provided along the outer wall 21c respectively. The outer end portions of one side of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are exposed from the outer wall 21c. The inner end portions of the other side are exposed in the unit accommodation portions 21e, 21f, 21g and are electrically connected to the semiconductor units 10a, 10b, 10c.

[0045] Thus, on the front surface of the frame portion 21, the first connection terminal 22a and the second connection terminal 23a are provided with the U-phase output terminal 24a interposed therebetween by the unit accommodation portion 21e. The first connection terminal 22b and the second connection terminal 23b are provided with the V-phase output terminal 24b interposed therebetween by the unit accommodation portion 21f. The first connection terminal 22c and the second connection terminal 23c are provided with the W-phase output terminal 24c interposed therebetween by the unit accommodation portion 21g.

[0046] In addition, in a plan view, the frame portion 21 is provided with control terminals 25a, 25b, 25c along the outer wall 21c on the side portions in the +Y direction of the unit accommodation portions 21e, 21f, 21g respectively. The control terminals 25a, 25b, 25c can be provided by being divided into two respectively. The control terminals 25a, 25b, 25c can be, for example, L-shaped and include outer end portions and inner end portions. The outer end portions of the control terminals 25a, 25b, 25c can extend vertically upward (+Z direction) from the front surface of the frame portion 21. The inner end portions of the control terminals 25a, 25b, 25c are exposed in the unit accommodation portions 21e, 21f, 21g. It should be noted that the shapes and the number of arrangements of the control terminals 25a, 25b, 25c are not limited to this and can be appropriately changed.

[0047] Such a frame portion 21 includes first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, 25c, and is integrally formed by injection molding using a thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0048] In addition, the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy mainly composed of at least one of them. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c can also be subjected to plating treatment. At this time, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0049] The sealing member (not shown) for sealing the unit accommodation portions 21e, 21f, 21g of the housing 20 can be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenolic resin, maleimide resin, and polyester resin. Epoxy resin is preferably used. In addition, the sealing member can contain a filler. The filler can be an insulating and highly thermally conductive material. Examples of the material include silica, alumina, boron nitride, or aluminum nitride.

[0050] The housing 20 having the above-described configuration is an example. The housing 20 only needs to be able to accommodate the semiconductor units 10a, 10b, 10c and use the semiconductor units 10a, 10b, 10c to achieve a power conversion function.

[0051] The cooling device 3 has an inlet 33a through which a refrigerant flows into the interior and an outlet 33b through which the refrigerant flowing through the interior flows out to the outside. The cooling device 3 cools the semiconductor unit 10 by allowing the heat from the semiconductor unit 10 to flow out via the refrigerant. The refrigerant used here is, for example, water, antifreeze (ethylene glycol aqueous solution), or long-life coolant. In addition, the cooling device 3 can include a pump and a heat dissipation device (radiator). The pump causes the refrigerant to flow into the inlet 33a of the cooling device 3 and causes the refrigerant flowing out from the outlet 33b to flow back into the inlet 33a again, thereby circulating the refrigerant. The heat dissipation device receives the refrigerant flowing out from the cooling device 3 and dissipates the heat of the refrigerant that has conducted the heat of the semiconductor unit 10 to the outside.

[0052] Such a cooling device 3 has a top plate 31, a side wall 32 connected to the back surface of the top plate 31 in a ring shape, and a cooling bottom plate 33 opposed to the top plate 31 and connected to the back surface of the side wall 32. The top plate 31 is rectangular in plan view, surrounded by long sides and short sides, and fastening holes are formed at the four corners respectively. The corners of the top plate 31 can be chamfered with an R in plan view. Semiconductor units 10a, 10b, and 10c are joined to the front surface of the top plate 31 along the ±X direction. The side wall 32 is formed in a ring shape and continuously formed on the back surface of the top plate 31. A plurality of heat sinks (not shown) are formed in the area of the back surface of the top plate 31 corresponding to the area where the semiconductor units 10a, 10b, and 10c are arranged.

[0053] The cooling bottom plate 33 is in a flat plate shape and has the same shape as the top plate 31 in plan view. The cooling bottom plate 33 has the same rectangular shape as the top plate 31 in plan view. In addition, the corners of the cooling bottom plate 33 can also be chamfered with an R. In addition, the front surface and the bottom surface 33d of the cooling bottom plate 33 are parallel. The bottom surface 33d of the cooling bottom plate 33 is a flat surface without steps and is in the same plane. An inflow port 33a for refrigerant to flow in and an outflow port 33b for refrigerant to flow out are respectively formed on the bottom surface 33d of the cooling bottom plate 33. At the inflow port 33a and the outflow port 33b, a water supply head is installed via an annular rubber gasket in a sealing area (not shown) surrounding the inflow port 33a and the outflow port 33b. A water distribution pipe connected to a pump is installed on the water supply head.

[0054] Next, use Figures 3 to 5 to describe the semiconductor unit 10. Figure 3 is a plan view of the semiconductor unit included in the semiconductor device of the first embodiment. Figure 4 and Figure 5 are the first and second cross-sectional views of the semiconductor unit included in the semiconductor device of the first embodiment. It should be noted that Figure 4 is Figure 3 a cross-sectional view taken along the single-dot chain line X-X of Figure 5 is Figure 3 a cross-sectional view taken along the single-dot chain line Y-Y of Figures 3 to 5 In addition, in

[0055] the semiconductor unit 10 includes an insulating circuit board 11, two semiconductor chips 12, and two lead frames 13 and 14. The semiconductor chips 12 are joined to the insulating circuit board 11 by joining members 15a. The lead frames 13 and 14 are joined to the main electrodes on the front surface of the semiconductor chips 12 and the insulating circuit board 11 by joining members 15b.

[0056] As Figure 4 and Figure 5As shown, the insulating circuit board 11 includes an insulating board 11a, conductive plates 11b, 11c, 11d, and a metal plate 11e. It should be noted that Figure 3 the inner ends of the second connection terminals 23a, 23b, 23c are respectively joined to the areas indicated by the dashed lines of the conductive plate 11d in Figure 3 the inner ends of the first connection terminals 22a, 22b, 22c are respectively joined to the areas indicated by the dashed lines of the conductive plate 11b in Figure 3 the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively joined to the areas indicated by the dashed lines of the conductive plate 11c in

[0057] The insulating board 11a and the metal plate 11e are rectangular in plan view. In addition, the corners of the insulating board 11a and the metal plate 11e can be R-chamfered or C-chamfered. The size of the metal plate 11e is smaller than that of the insulating board 11a in plan view, and it is formed inside the insulating board 11a.

[0058] The insulating board 11a includes side surfaces 11a1 to 11a4 that successively surround the four sides of the front surface. The side surfaces 11a1 and 11a3 correspond to the long sides of the insulating board 11a in plan view. The side surfaces 11a2 and 11a4 correspond to the short sides of the insulating board 11a in plan view. In addition, the insulating board 11a respectively includes four corners 11a5 to 11a8. The corner 11a5 is formed by the side surfaces 11a1 and 11a2. The corner 11a6 is formed by the side surfaces 11a2 and 11a3. The corner 11a7 is formed by the side surfaces 11a3 and 11a4. The corner 11a8 is formed by the side surfaces 11a4 and 11a1.

[0059] Such an insulating board 11a is made of a material with high insulation and excellent heat conductivity. Such an insulating board 11a can be made of ceramics. Examples of ceramics include alumina, aluminum nitride, and silicon nitride.

[0060] The conductive plates 11b, 11c, 11d are formed on the front surface of the insulating board 11a. The conductive plates 11b, 11c, 11d are made of a metal with excellent conductivity. Examples of such a metal include copper, aluminum, or an alloy mainly composed of at least one of them. In order to improve corrosion resistance, the surfaces of the conductive plates 11b, 11c, 11d can also be plated. At this time, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0061] The conductive plate 11b occupies half of the area on the side surface 11a4 side of the front surface of the insulating board 11a, that is, the entire area from the side surface 11a1 to the side surface 11a3. A chip area 11b3 is set on the front surface of the conductive plate 11b (refer to Figure 7). The chip region 11b3 corresponds to the top view shape of the semiconductor chip 12 and the semiconductor chip 12 is joined thereto. Further, the end edge in the -Y direction on the front surface of the conductive plate 11b and the inner end portions of the first connection terminals 22a, 22b, 22c are joined in the region indicated by the dashed line in the -X direction. The joining at this time can be a joining member, laser welding, or ultrasonic joining. Alternatively, the dashed line region shown in the conductive plate 11b and the inner end portions of the first connection terminals 22a, 22b, 22c may also be joined via a conductive block.

[0062] Further, the conductive plate 11b includes a support conductive plate 11b2, which is disposed on the opposite side (+X direction side) of the chip region 11b3 (semiconductor chip 12) opposite to the conductive plate 11c and is insulated from the conductive plate 11b.

[0063] In Figure 3 this case, the conductive plate 11b is formed with a recess 11b1 at the end edge on the opposite side (+X direction side) of the chip region 11b3 (semiconductor chip 12) opposite to the conductive plate 11c. The recess 11b1 may face the chip region 11b3 (semiconductor chip 12). In particular, here, the recess 11b1 faces the chip region 11b3 (semiconductor chip 12) along the ±X direction. The recess 11b1 is a region where a part of the end edge on the +X direction side of the conductive plate 11b is recessed in the -X direction. Examples of the shape of the recess 11b1 in a top view include a U shape, a semicircular shape, and a rectangular shape. The case where the recess 11b1 is U-shaped is shown in Figure 3 .

[0064] The support conductive plate 11b2 may be made of the same material as the conductive plate 11b, for example. The support conductive plate 11b2 is disposed in the recess 11b1 of the conductive plate 11b. That is, the support conductive plate 11b2 is formed on the insulating plate 11a without contacting the conductive plate 11b. Therefore, the support conductive plate 11b2 is electrically insulated from the conductive plate 11b. As long as the shape and size of the support conductive plate 11b2 in a top view can be arranged in the recess 11b1 and can include the end portion (wiring joining portion 14a) of the lead frame 14 described later. In Figure 3 this case, the support conductive plate 11b2 corresponds to the shape of the recess 11b1. The width of the support conductive plate 11b2 in the ±Y direction is wider than the width of the lead frame 14 in the same direction.

[0065] It should be noted that such a supporting conductive plate 11b2 does not necessarily have to be provided at the end edge of the conductive plate 11b in the +X direction. As long as the supporting conductive plate 11b2 is provided in the conductive plate 11b on the opposite side (+X direction side) to the conductive plate 11c with respect to the chip region 11b3 (semiconductor chip 12). The supporting conductive plate 11b2 can be provided, for example, between the chip region 11b3 (semiconductor chip 12) and the end edge of the conductive plate 11b in the +X direction in the conductive plate 11b. In this case, instead of forming the recess 11b1 in the conductive plate 11b, an opening region can be formed at a position corresponding to the supporting conductive plate 11b2. The opening region in this case can be a shape and size that prevent the supporting conductive plate 11b2 from contacting the conductive plate 11b.

[0066] The conductive plate 11c occupies half of the side 11a2 side of the front surface of the insulating plate 11a. In addition, the conductive plate 11c occupies the front surface of the insulating plate 11a from the side 11a3 to the vicinity of the side 11a1. A chip region 11c3 (see Figure 7 ) is set on the front surface of the conductive plate 11c. The chip region 11c3 corresponds to the top view shape of the semiconductor chip 12 and the semiconductor chip 12 is bonded thereto. In addition, the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively bonded to the end edges in the +Y direction on the front surface of the conductive plate 11c and the dotted line regions shown in the +X direction. It should be noted that here, the dotted line regions are set on the side portions on the +X direction side (the conductive plate 11b side) of the supporting conductive plate 11c2 (recess 11c1) described later. The bonding at this time can be bonding members, laser welding, or ultrasonic bonding. Alternatively, the dotted line regions shown in the conductive plate 11c and the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c can also be bonded via a conductive block.

[0067] In addition, the conductive plate 11c includes a supporting conductive plate 11c2, which is provided on the opposite side (+Y direction side) to the conductive plate 11d with respect to the chip region 11c3 (semiconductor chip 12) and is electrically insulated from the conductive plate 11c.

[0068] In Figure 3 this case, the conductive plate 11c forms a recess 11c1 at the end edge on the opposite side (+Y direction side) to the conductive plate 11d with respect to the chip region 11c3 (semiconductor chip 12). The recess 11c1 can face the chip region 11c3 (semiconductor chip 12). In particular, here, the recess 11c1 faces the chip region 11c3 (semiconductor chip 12) directly along the ±Y direction. The recess 11c1 is a region where a part of the end edge on the +Y direction side of the conductive plate 11c is recessed in the -Y direction. Examples of the shape of the recess 11c1 in top view include a U shape, a semicircle shape, and a rectangle shape. InFigure 3 The case where the recess 11c1 is shown as U-shaped is illustrated.

[0069] The support conductive plate 11c2 can be made of, for example, the same material as the conductive plate 11c. The support conductive plate 11c2 is provided in the recess 11c1 of the conductive plate 11c. That is, the support conductive plate 11c2 is formed on the insulating plate 11a without contacting the conductive plate 11c. Therefore, the support conductive plate 11c2 is electrically insulated from the conductive plate 11c. As long as the shape and size of the support conductive plate 11c2 in a plan view can be arranged within the recess 11c1, and in addition, the end portion (wiring bonding portion 13a) of the lead frame 13 described later can be included. In Figure 3 this case, the support conductive plate 11c2 corresponds to the shape of the recess 11c1. The width of the support conductive plate 11c2 in the ±X direction is wider than the width of the lead frame 13 in the same direction.

[0070] It should be noted that such a support conductive plate 11c2 does not necessarily have to be provided at the end edge in the +Y direction of the conductive plate 11c. As long as the support conductive plate 11c2 is provided on the conductive plate 11c on the opposite side (+Y direction side) to the conductive plate 11d with respect to the chip region 11c3 (semiconductor chip 12). The support conductive plate 11c2 can be provided, for example, between the chip region 11c3 (semiconductor chip 12) and the end edge in the +Y direction of the conductive plate 11c in the conductive plate 11c. In this case, instead of forming the recess 11c1, the conductive plate 11c can form an opening region at a position corresponding to the support conductive plate 11c2. The opening region in this case can be a shape and size that prevent the support conductive plate 11c2 from contacting the conductive plate 11c.

[0071] The conductive plate 11d occupies the region on the front surface of the insulating plate 11a surrounded by the conductive plates 11b and 11c. The width of the conductive plate 11d in the ±X direction is equal to the width of the conductive plate 11c in the same direction. The inner ends of the second connection terminals 23a, 23b, and 23c are joined to the region indicated by the dotted line of the conductive plate 11d. The joining at this time can be joining members, laser welding, or ultrasonic bonding. Alternatively, the region surrounded by the dotted line of the conductive plate 11d and the inner ends of the second connection terminals 23a, 23b, and 23c can also be connected via a conductive block.

[0072] Such conductive plates 11b, 11c, and 11d are formed on the front surface of the insulating plate 11a as follows. A metal layer is formed on the front surface of the insulating plate 11a, and the metal layer is etched or the like to obtain conductive plates 11b, 11c, and 11d with a predetermined shape. In addition, the periphery of a predetermined range of the conductive plates 11b and 11c can be peeled off by etching to form support conductive plates 11b2 and 11c2 separated from the conductive plates 11b and 11c.

[0073] Alternatively, the conductive plates 11b, 11c including the recesses 11b1, 11c1 pre-cut from the metal layer and the conductive plate 11d may be crimped to the front surface of the insulating plate 11a, and the supporting conductive plates 11b2, 11c2 may be crimped into the recesses 11b1, 11c1.

[0074] The corners of the conductive plates 11b, 11c, 11d may also be R-chamfered or C-chamfered. It should be noted that the conductive plates 11b, 11c, 11d are an example. According to needs, the number, shape, size, and position of the conductive plates 11b, 11c, 11d can be appropriately selected.

[0075] As Figure 4 and Figure 5 As referred to in [ ], the metal plate 11e is formed on the back surface of the insulating plate 11a. The metal plate 11e is rectangular in shape. The area of the metal plate 11e when viewed from above is smaller than the area of the insulating plate 11a and larger than the area of the region where the conductive plates 11b, 11c, 11d are formed. The corners of the metal plate 11e may also be R-chamfered or C-chamfered. The size of the metal plate 11e is smaller than the size of the insulating plate 11a and is formed on the entire surface of the insulating plate 11a except for the edge portion. The metal plate 11e is made of a metal with excellent thermal conductivity. Examples of such a metal include copper, aluminum, or an alloy containing at least one of them. In order to improve corrosion resistance, the surface of the metal plate 11e may be subjected to a plating treatment. At this time, examples of the plating material used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0076] As the insulating circuit board 11 having such a configuration, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used. The insulating circuit board 11 can be mounted on the front surface of the cooling device 3 via a bonding member (not shown). The heat generated by the semiconductor chip 12 can be conducted to the cooling device 3 via the conductive plates 11b, 11c, the insulating plate 11a, and the metal plate 11e for heat dissipation.

[0077] The bonding members 15a, 15b are solder. Lead-free solder is used. The lead-free solder may, for example, be mainly composed of an alloy containing at least two metals among tin, silver, copper, zinc, antimony, indium, and bismuth. In addition, additives may be contained in the solder. Examples of the additives are nickel, germanium, cobalt, or silicon. By containing additives, the solder can seek to improve wettability, gloss, bonding strength, and reliability.

[0078] In addition, the bonding component (not shown) that bonds the semiconductor unit 10 and the cooling device 3 can be solder, brazing filler metal, or a thermal interface material. Lead-free solder is used as the solder. The brazing filler metal can have, for example, at least any one of aluminum alloy, titanium alloy, magnesium alloy, zirconium alloy, and silicon alloy as the main component. The thermal interface material is an adhesive and can include, for example, an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, or phase change material. By mounting the semiconductor unit 10 on the cooling device 3 via such brazing filler metal or thermal interface material, the heat dissipation performance of the semiconductor unit 10 can be improved.

[0079] The semiconductor chip 12 includes a power device element. The power device element is an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor) formed mainly of silicon. The RC-IGBT has the functions of an IGBT as a switching element and an FWD (Free Wheeling Diode) as a diode element. A control electrode 12a (gate electrode) and an output electrode (emitting electrode) as a main electrode 12b are provided on the front surface of such a semiconductor chip 12. An input electrode (collecting electrode) as a main electrode (not shown) is provided on the back surface of the semiconductor chip 12. It should be noted that the control electrode 12a can be provided along one side (or at the center of one side) of the front surface of the semiconductor chip 12. The output electrode is provided at the center of the front surface of the semiconductor chip 12. The input electrode is provided in a manner that includes the center of the back surface of the semiconductor chip 12.

[0080] As other power device elements, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed mainly of silicon carbide can be cited. The body diode of the power MOSFET can also function as an FWD. Such a semiconductor chip 12 is provided with a control electrode 12a (gate electrode) and an output electrode (source electrode) as a main electrode 12b on the front surface, respectively. The semiconductor chip 12 is provided with an input electrode (drain electrode) as a main electrode on the back surface.

[0081] The lead frame 13 is wired in such a way as to electrically connect the main electrode 12b of the semiconductor chip 12 on the conductive plate 11c to the conductive plate 11d. The lead frame 14 is wired in such a way as to electrically connect the main electrode 12b of the semiconductor chip 12 on the conductive plate 11b to the conductive plate 11c. The semiconductor unit 10 can be a device that constitutes a single-phase inverter circuit.

[0082] AsFigure 4 and Figure 5 As shown in Figure 5 , the lead frames 13 and 14 include wiring joints 13a and 14a, electrode joints 13c and 14c, and wiring joints 13b and 14b. It should be noted that the wiring joints 13a and 14a are examples of the first joint, and the wiring joints 13b and 14b are examples of the second joint. In addition, the lead frames 13 and 14 respectively include connecting parts 13d and 14d that connect the wiring joints 13a and 14a and the electrode joints 13c and 14c, and connecting parts 13e and 14e that connect the electrode joints 13c and 14c and the wiring joints 13b and 14b. The lead frames 13 and 14 integrally include the connecting parts 13d and 14d and the connecting parts 13e and 14e, and are in a straight line shape when viewed from above. The lead frames 13 and 14 can have the same width as a whole when viewed from above. The thicknesses of the wiring joints 13a and 14a, the electrode joints 13c and 14c, and the wiring joints 13b and 14b (in the +Z direction) are uniform as a whole and can be the same. The thicknesses of the connecting parts 13e and 14e and the connecting parts 13d and 14d are uniform as a whole and can be the same, and can be thinner than the thicknesses of the wiring joints 13a and 14a, the electrode joints 13c and 14c, and the wiring joints 13b and 14b.

[0083] The wiring joints 13a and 14a are respectively joined to the support conductive plates 11c2 and 11b2 via joining members 15a. The wiring joints 13a and 14a are, for example, in a flat plate shape. The wiring joints 13a and 14a can have a shape and size that converge within the support conductive plates 11c2 and 11b2 when viewed from above. A plurality of bosses 13a1 and 14a1 can be formed on the back surfaces of the wiring joints 13a and 14a. It should be noted that the plurality of bosses 13a1 and 14a1 can be, for example, in a cylindrical shape or a prismatic shape. In addition, the heights of the plurality of bosses 13a1 and 14a1 are substantially uniform. The plurality of bosses 13a1 and 14a1 can keep the thickness of the joining member 15a between the wiring joints 13a and 14a and the support conductive plates 11c2 and 11b2 substantially constant.

[0084] The electrode joints 13c and 14c are respectively joined to the main electrodes 12b of the semiconductor chip 12 via joining members 15b. The electrode joints 13c and 14c are, for example, in a flat plate shape. The electrode joints 13c and 14c can have a shape and size corresponding to the main electrodes 12b of the semiconductor chip 12 when viewed from above. No bosses may be formed on the back surfaces of the electrode joints 13c and 14c.

[0085] The wiring joints 13b and 14b are respectively joined to the conductive plates 11d and 11c via the joining member 15a. The wiring joints 13b and 14b are, for example, in a flat plate shape. The wiring joints 13b and 14b may have a shape and size that converge within the conductive plates 11d and 11c when viewed from above. A plurality of bosses 13b1 and 14b1 may be formed on the back surfaces of the wiring joints 13b and 14b. It should be noted that the plurality of bosses 13b1 and 14b1 may be, for example, cylindrical or prismatic. In addition, the heights of the plurality of bosses 13b1 and 14b1 are substantially uniform. The plurality of bosses 13b1 and 14b1 can keep the thickness of the joining member 15a between the wiring joints 13b and 14b and the conductive plates 11d and 11c substantially constant.

[0086] The connecting portions 13d and 14d are in a flat plate shape. When viewed from above, the connecting portions 13d and 14d connect the end edges of the wiring joints 13a and 14a on the side of the electrode joints 13c and 14c and the end edges of the electrode joints 13c and 14c on the side of the wiring joints 13a and 14a into one body.

[0087] In addition, when viewed from the side, the connecting portions 13d and 14d extend vertically upward (+Z direction) from the end edges of the wiring joints 13a and 14a on the side of the electrode joints 13c and 14c to a predetermined height (first height), and bend at a right angle toward the electrode joints 13c and 14c. Further, the connecting portions 13d and 14d extend toward the electrode joints 13c and 14c, bend on the end edges of the electrode joints 13c and 14c on the side of the wiring joints 13a and 14a, and extend vertically downward (-Z direction) to a predetermined height (third height) and are connected to the end edges. At this time, the first height is longer (higher) than the third height and longer than the length obtained by adding the third height and the respective thicknesses (+Z direction) of the semiconductor chips 12. That is, the electrode joints 13c and 14c are located at a position higher (+Z direction) than the wiring joints 13a and 14a. The middle portions of the connecting portions 13d and 14d are parallel to the main surface of the insulating circuit board 11. It should be noted that the first height is a predetermined height from the wiring joints 13a and 14a to the connecting portions 13d and 14d (the middle portions), and the third height is a predetermined height from the electrode joints 13c and 14c to the connecting portions 13d and 14d (the middle portions).

[0088] Such a configuration of the connecting portions 13d and 14d is an example. The connecting portions 13d and 14d only need to be able to connect the wiring joints 13a and 14a and the electrode joints 13c and 14c. The connecting portions 13d and 14d may be, for example, an arch with R surfaces at the vertices. Or, the connecting portions 13d and 14d may also connect the wiring joints 13a and 14a and the electrode joints 13c and 14c with different heights in a straight line.

[0089] The connecting portions 13e and 14e are in a flat plate shape. In a plan view, the connecting portions 13e and 14e integrally connect the edges of the electrode bonding portions 13c and 14c on the side closer to the wiring bonding portions 13b and 14b and the edges of the wiring bonding portions 13b and 14b on the side closer to the electrode bonding portions 13c and 14c.

[0090] In addition, in a side view, the connecting portions 13e and 14e extend from the edges of the electrode bonding portions 13c and 14c on the side closer to the wiring bonding portions 13b and 14b upward in the vertical direction (+Z direction) to a predetermined height (the fourth height), and then bend at a right angle toward the wiring bonding portions 13b and 14b. Further, the connecting portions 13e and 14e extend toward the wiring bonding portions 13b and 14b, bend on the edges of the wiring bonding portions 13b and 14b on the side closer to the electrode bonding portions 13c and 14c, and extend downward in the vertical direction (-Z direction) to a predetermined height (the second height) and are connected to these edges. At this time, the second height is longer (higher) than the fourth height and longer than the length obtained by adding the fourth height and the respective thicknesses (+Z direction) of the semiconductor chip 12. That is, the electrode bonding portions 13c and 14c are located at a position higher (+Z direction) than the wiring bonding portions 13b and 14b. The middle portions of the connecting portions 13e and 14e are parallel to the main surface of the insulating circuit board 11. In addition, the middle portions of the connecting portions 13e and 14e may be in the same plane as the middle portions of the connecting portions 13d and 14d. It should be noted that the second height is the predetermined height from the wiring bonding portions 13b and 14b to the middle portions of the connecting portions 13e and 14e, and the fourth height is the predetermined height from the electrode bonding portions 13c and 14c to the middle portions of the connecting portions 13e and 14e.

[0091] Such a configuration of the connecting portions 13e and 14e is an example. The connecting portions 13e and 14e only need to be able to connect the electrode bonding portions 13c and 14c and the wiring bonding portions 13b and 14b. For example, the connecting portions 13e and 14e may be in an arch shape with R surfaces at the vertices. Alternatively, the connecting portions 13e and 14e may also connect the electrode bonding portions 13c and 14c with different heights and the wiring bonding portions 13b and 14b in a straight line.

[0092] Such lead frames 13 and 14 are in a straight line shape in a plan view. Therefore, the wiring bonding portions 13a and 14a, the electrode bonding portions 13c and 14c, and the wiring bonding portions 13b and 14b are also arranged in a row. At this time, the electrode bonding portions 13c and 14c may be located in the middle of the wiring bonding portions 13a and 14a and the wiring bonding portions 13b and 14b. Therefore, in a plan view, the connecting portions 13d and 14d and the connecting portions 13e and 14e may have the same length.

[0093] Next, use Figure 6A method for manufacturing a semiconductor device 1 will be described. Figure 6 It is a flowchart showing the manufacturing method of the semiconductor device of the first embodiment. First, a preparation process of preparing the constituent components of the semiconductor device 1 ( Figure 6 step S1). Examples of the prepared constituent components include an insulating circuit board 11, a semiconductor chip 12, a cooling device 3, a housing 20, and lead frames 13 and 14. In addition to these, components required as constituent components of the semiconductor device 1 can also be prepared. Further, manufacturing devices for manufacturing the semiconductor device 1 can also be prepared. Using Figure 7 The insulating circuit board 11 prepared here will be described. Figure 7 It is a top view of the insulating circuit board included in the semiconductor device of the first embodiment.

[0094] As described above, the insulating circuit board 11 includes an insulating plate 11a, conductive plates 11b, 11c, 11d, and a metal plate 11e (refer to Figure 4 and Figure 5 ). In addition, as Figure 7 shown, conductive plates 11b, 11c, 11d are formed on the front surface of the insulating plate 11a.

[0095] A chip region 11b3 for arranging the semiconductor chip 12 is set approximately at the center of the conductive plate 11b. The conductive plate 11b forms a recess 11b1 at the end edge on the opposite side (+X direction side) to the conductive plate 11c with respect to the chip region 11b3. A support conductive plate 11b2 is formed in the recess 11b1.

[0096] A chip region 11c3 for arranging the semiconductor chip 12 is set approximately at the center of the conductive plate 11c. The conductive plate 11c forms a recess 11c1 at the end edge on the opposite side (+Y direction side) to the conductive plate 11d with respect to the chip region 11c3. A support conductive plate 11c2 is formed in the recess 11c1. The conductive plate 11d is formed in the region surrounded by the conductive plates 11b and 11c on the front surface of the insulating plate 11a.

[0097] Next, a placement process of sequentially laminating and placing the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13, 14 is performed ( Figure 6 step S2). Using Figure 7 and Figure 8 the placement process will be described. Figure 8 It is a diagram showing the placement process included in the manufacturing method of the semiconductor device of the first embodiment. It should be noted that Figure 8 is a cross-sectional view of the placed components after the placement process. Figure 8 is related to Figure 4Cross-sectional views at corresponding positions. Here, the lead frame 13 will be described in detail, but the same treatment will also be applied to the lead frame 14.

[0098] First, the semiconductor chips 12 are respectively placed on the chip regions 11b3 and 11c3 of the insulating circuit board 11 via the bonding plates 15a1. In addition, as Figure 8 shown, the wiring bonding portions 13a, electrode bonding portions 13c, and wiring bonding portions 13b of the lead frame 13 are respectively placed on the main electrodes 12b of the semiconductor chips 12 on the support conductive plate 11c2 and the chip region 11c3, and the conductive plate 11d via the bonding plates 15a1, 15b1, and 15a1.

[0099] The wiring bonding portions 14a, electrode bonding portions 14c, and wiring bonding portions 14b of the lead frame 14 are respectively placed on the main electrodes 12b of the semiconductor chips 12 on the support conductive plate 11b2 and the chip region 11b3, and the conductive plate 11c via the bonding plates 15a1, 15b1, and 15a1. It should be noted that the bonding plates 15a1 and 15b1 are made of the same material as the bonding members 15a and 15b and are in a plate shape.

[0100] Next, a first bonding process (step S3 of Figure 6 ) for bonding the insulating circuit board 11, semiconductor chips 12, and lead frames 13 and 14 is performed. The first bonding process will be described using Figure 8 and Figure 9 . Figure 9 is a diagram showing the first bonding process included in the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that Figure 9 is also a cross-sectional view at the same position as Figure 8 . In addition, here, the lead frame 13 will be described, but the lead frame 14 also performs the first bonding process in the same manner.

[0101] The insulating circuit board 11, semiconductor chips 12, and lead frames 13 and 14 placed in step S2 are heated. At this time, Figure 8 the bonding plates 15a1 and 15b1 provided between the insulating circuit board 11, semiconductor chips 12, and lead frames 13 and 14 are also heated and become the molten bonding members 15a and 15b.

[0102] In addition, due to heating, the insulating circuit board 11 warps due to the difference in the thermal expansion coefficients of the insulating plate 11a, conductive plates 11b, 11c, 11d, and metal plate 11e. The warping bulges downward with the metal plate 11e side as the bottom, for example.

[0103] Thereafter, the heating is stopped, and the molten bonding members 15a and 15b start to solidify. The wiring bonding portions 13a and 13b of the lead frame 13 start to bond to the support conductive plate 11c2 and the conductive plate 11d by means of the bonding member 15a. In addition, the electrode bonding portion 13c starts to bond to the main electrode 12b of the semiconductor chip 12 by means of the bonding member 15b.

[0104] The wiring bonding portions 13a and 13b of the lead frame 13 bonded to the insulating circuit board 11 that bulges downward and warps are respectively fixed to the support conductive plate 11c2 and the conductive plate 11d. Therefore, the lead frame 13 is supported by making the two points of the wiring bonding portion 13a and the wiring bonding portion 13b as the fulcrums. As a result, the inclination of the lead frame 13 and the electrode bonding portion 13c is suppressed, and the thickness of the bonding member 15b is maintained to be substantially uniform. The bonding member 15b solidifies in a state where the thickness is controlled to be uniform, so that the electrode bonding portion 13c and the main electrode 12b of the semiconductor chip 12 are bonded. By bonding the electrode bonding portion 13c to the main electrode 12b of the semiconductor chip 12 in this way, the inclination of the electrode bonding portion 13c is prevented and the deviation of the thickness of the bonding member 15b is suppressed.

[0105] In addition, the wiring bonding portions 13a and 13b include a plurality of bosses 13a1 and 13b1. Therefore, the wiring bonding portions 13a and 13b can maintain the thickness of the bonding member 15a between the support conductive plate 11c2 and the conductive plate 11d to be substantially uniform. The semiconductor unit 10 is configured as described above.

[0106] It should be noted that in the first bonding process here, the case where the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 are bonded at one time is described. Not limited to this case, the semiconductor chip 12 can also be bonded to the insulating circuit board 11 by means of the bonding member 15a, and thereafter, the lead frames 13 and 14 can be bonded to the insulating circuit board 11 and the semiconductor chip 12 by means of the bonding member 15b.

[0107] Next, a second bonding process ( Figure 6 step S4) of bonding the semiconductor unit 10 to the cooling device 3 is performed. The semiconductor units 10a, 10b, and 10c are bonded to the front surface of the top plate 31 of the cooling device 3 along the long side direction of the top plate 31 via a bonding member (not shown).

[0108] Next, a housing mounting process ( Figure 6 step S5) of mounting the housing 20 on the cooling device 3 is performed. The housing 20 is mounted on the top plate 31 of the cooling device 3 by means of an adhesive (not shown). At this time, the semiconductor units 10a, 10b, and 10c on the top plate 31 are received in the unit receiving portions 21e, 21f, and 21g of the housing 20.

[0109] Next, a wire routing and sealing process is performed in which the semiconductor units 10a, 10b, and 10c housed in the housing 20 are wired, and the unit housing portions 21e, 21f, and 21g of the housing 20 are sealed ( Figure 6 step S6).

[0110] First, among the semiconductor units 10a, 10b, and 10c housed in the unit housing portions 21e, 21f, and 21g of the housing 20, the control electrodes 12a of the semiconductor chips 12 are connected to the inner ends of the control terminals 25a, 25b, and 25c using wires (not shown). In addition, the inner ends of the first connection terminals 22a, 22b, and 22c are respectively joined to the conductive plates 11b of the insulating circuit board 11. Similarly, the inner ends of the second connection terminals 23a, 23b, and 23c are respectively joined to the conductive plates 11d. Further, similarly, the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are respectively joined to the conductive plates 11c.

[0111] Then, a sealing member (not shown) is filled in the unit housing portions 21e, 21f, and 21g of the housing 20 to seal the semiconductor units 10a, 10b, and 10c. As described above, the Figure 1 and Figure 2 semiconductor device 1 shown is obtained.

[0112] Here, a semiconductor device of a reference example will be described. The semiconductor device of the reference example has the same configuration as the semiconductor device 1 except for the semiconductor unit 10 in the semiconductor device 1. The semiconductor unit included in the semiconductor device of the reference example is different from the semiconductor unit 10 included in the semiconductor device 1 of the first embodiment. Here, Figure 10 is used to describe the semiconductor unit included in the semiconductor device of the reference example. Figure 10 is a top view of the semiconductor unit included in the semiconductor device of the reference example. It should be noted that Figure 10 corresponds to Figure 3 of the first embodiment.

[0113] The semiconductor unit 100 of the reference example includes an insulating circuit board 11, a semiconductor chip 12, and lead frames 13 and 14, similarly to the semiconductor unit 10 of the first embodiment. However, the conductive plates 11b and 11c included in the insulating circuit board 11 do not form recesses 11b1 and 11c1 and do not include support conductive plates 11b2 and 11c2.

[0114] Accompanying this, the lead frames 13 and 14 include wiring connection portions 13b and 14b, electrode connection portions 13c and 14c, and connection portions 13e and 14e that connect the wiring connection portions 13b and 14b and the electrode connection portions 13c and 14c. That is, the lead frames 13 and 14 do not include the wiring connection portions 13a and 14a and the connection portions 13d and 14d of the first embodiment. Additionally, in the reference example, bosses are formed on the back surfaces of the electrode connection portions 13c and 14c (the boss 13c1 is shown in Figure 11 and Figure 12 ). The wiring connection portions 13b and 14b are joined to the conductive plates 11d and 11c via the joining members 15a. The electrode connection portions 13c and 14c are joined to the main electrodes 12b of the semiconductor chip 12 via the joining members 15b. It should be noted that the semiconductor chip 12 is joined to the conductive plates 11c and 11b respectively via the joining members 15a.

[0115] A semiconductor device including such a semiconductor unit 100 can also be manufactured according to the Figure 6 flowchart. Next, the manufacturing method of this semiconductor device will be described using Figure 6 . It should be noted that in the following manufacturing method, the description of the same processes as those of the first embodiment is omitted or simplified.

[0116] First, similarly to the first embodiment, a preparation process for preparing the constituent components of the semiconductor device of the reference example is performed (step S1 of Figure 6 ). Next, a placement process of sequentially placing the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 is performed (step S2 of Figure 6 ). The placement process will be described using Figure 11 . Figure 11 is a diagram showing the placement process included in the manufacturing method of the semiconductor device of the reference example. It should be noted that Figure 11 is a cross-sectional view of the placed configuration after the placement process. Figure 11 is a cross-sectional view at a position corresponding to the single dotted line X-X of Figure 10 .

[0117] Here, the semiconductor chip 12 is placed in the chip region (not shown) of the insulating circuit board 11 via the bonding plate 15a1 respectively. In addition, as Figure 11 shows, the electrode connection portion 13c and the wiring connection portion 13b of the lead frame 13 are placed on the main electrode 12b of the semiconductor chip 12 and the conductive plate 11d via the bonding plate 15b1 respectively.

[0118] Next, a first bonding process of sequentially bonding the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 is performed (step S3 of Figure 6 ). The first bonding process will be described usingFigure 11 and Figure 12 A description is given of the first bonding process. Figure 12 FIG. is a diagram showing the first bonding process included in the method of manufacturing a semiconductor device of a reference example. It should be noted that Figure 12 is also a cross-sectional view at the Figure 11 same position. In addition, the lead frame 13 is described here, but the same applies to the lead frame 14.

[0119] The insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14 placed in step S2 are heated. At this time, Figure 11 the bonding plates 15a1 and 15b1 provided between the insulating circuit board 11, the semiconductor chip 12, and the lead frames 13 and 14, as shown, are also heated and become the molten bonding members 15a and 15b.

[0120] In addition, due to heating, the insulating circuit board 11 warps due to the difference in the thermal expansion coefficients of the insulating plate 11a, the conductive plates 11b, 11c, 11d, and the metal plate 11e. The warping protrudes downward with the metal plate 11e side as the bottom, for example.

[0121] Thereafter, the heating is stopped, and the molten bonding members 15a and 15b start to solidify. The wiring bonding portion 13b of the lead frame 13 starts to bond to the conductive plate 11d using the bonding member 15a. In addition, the electrode bonding portion 13c starts to bond to the main electrode 12b of the semiconductor chip 12 using the bonding member 15b.

[0122] Since the insulating circuit board 11 warps and protrudes downward, the electrode bonding portion 13c of the lead frame 13 bonded to such an insulating circuit board 11 cannot suppress the inclination even if the boss 13c1 is formed. Therefore, a deviation occurs in the thickness of the bonding member 15b. Along with this, the semiconductor chip 12 inclines and a deviation also occurs in the thickness of the bonding member 15a.

[0123] If a deviation occurs in the thickness of the bonding member 15b and the electrode bonding portion 13c is connected to the main electrode 12b of the semiconductor chip 12 in an inclined manner, there is also a risk that the heat dissipation performance of the semiconductor chip 12 will deviate. There is a risk that the deviation in heat dissipation performance becomes a cause of reduced cooling performance and failure of the semiconductor chip 12. It should be noted that the steps Figure 6 S4, S5, and S6 are then sequentially performed to obtain a semiconductor device including the semiconductor unit 100 of the reference example.

[0124] The semiconductor device 1 described above includes a semiconductor unit 10. The semiconductor unit 10 includes: a semiconductor chip 12 having a main electrode 12b on the front surface; a conductive plate 11c (an example of a first conductive plate) having a chip region 11c3 on the front surface where the back surface of the semiconductor chip 12 is to be bonded; a conductive plate 11d (an example of a second conductive plate) disposed adjacent to the conductive plate 11c in a plan view; a support conductive plate 11c2 (an example of a support portion) disposed on the opposite side of the chip region 11c3 from the conductive plate 11d and insulated from the conductive plate 11c; and a lead frame 13 including a wiring joint portion 13a (an example of a first joint portion) bonded to the support conductive plate 11c2, a wiring joint portion 13b (an example of a second joint portion) bonded to the conductive plate 11d, and an electrode joint portion 13c bonded to the main electrode 12b of the semiconductor chip 12 via a bonding member 15b. In such a semiconductor unit 10, the lead frame 13 is in a state of being supported by the two points of the wiring joint portions 13a and 13b, suppressing the inclination of the lead frame 13, and the thickness of the bonding member 15b is maintained to be substantially uniform. The bonding member 15b is cured in a state where the thickness is controlled to be uniform, and the electrode joint portion 13c and the main electrode 12b of the semiconductor chip 12 are bonded. By bonding the electrode joint portion 13c to the main electrode 12b of the semiconductor chip 12 in this way, the inclination of the electrode joint portion 13c is prevented and the deviation of the thickness of the bonding member 15b is suppressed. Thereby, the deviation of the heat dissipation performance of the semiconductor chip 12 is suppressed, and the occurrence of failures of the semiconductor chip 12 is reduced. Therefore, the reduction of the reliability of the semiconductor device 1 is suppressed.

[0125] The support conductive plate 11c2 is disposed in a recess 11c1 (an example of an opening region) formed in the conductive plate 11c so as not to contact the conductive plate 11c. In such a configuration, for example, by connecting the control terminal 25a and the support conductive plate 11c2 using a bonding wire, the support conductive plate 11c2 can be used as a wiring path for an auxiliary emitter. In addition, by bonding the wiring joint portion 13a of the lead frame 13 and the support conductive plate 11c2, compared with the structure of Figure 10 , the contact area of the lead frame 13 with respect to the support conductive plate 11c2 increases, and thus the heat dissipation performance is improved.

[0126] In a plan view, the lead frame 13 extends linearly from the electrode joint portion 13c to the wiring joint portion 13a and extends linearly from the electrode joint portion 13c to the wiring joint portion 13b. That is, in a plan view, the lead frame 13 extends linearly from the wiring joint portion 13a to the wiring joint portion 13b. Since such a configuration can cause the electrode joint portion 13c of the lead frame 13 to float up (separate in the +Z direction) from the semiconductor chip 12, the deviation of the thickness of the bonding member 15b can be more reliably suppressed.

[0127] The lead frame 13 includes a flat connecting portion 13d (an example of a first connecting portion) that connects between the electrode bonding portion 13c and the wiring bonding portion 13a, and a flat connecting portion 13e (an example of a second connecting portion) that connects between the electrode bonding portion 13c and the wiring bonding portion 13b. The first height from the wiring bonding portion 13a to the connecting portion 13d is higher than the third height from the electrode bonding portion 13c to the connecting portion 13d, and the second height from the wiring bonding portion 13b to the connecting portion 13e is higher than the fourth height from the electrode bonding portion 13c to the connecting portion 13e. It should be noted that the second height is preferably longer than the length obtained by adding the fourth height and the thickness of the semiconductor chip 12 in the (+Z direction), and the first height is preferably longer than the length obtained by adding the third height and the thickness of the semiconductor chip 12 in the (+Z direction). In addition, it is more preferable that the first height and the second height are equal and the third height and the fourth height are equal. With such a configuration, the electrode bonding portion 13c can be more reliably lifted from the semiconductor chip 12 (separated in the +Z direction), so that the deviation of the thickness of the bonding member 15b can be suppressed.

[0128] (Modification 1-1) Use Figure 13 And Figure 14 The semiconductor unit 10 of Modification 1-1 of the first embodiment will be described. Figure 13 It is a top view of the semiconductor unit included in the semiconductor device of the first embodiment (Modification 1-1). Figure 14 It is a cross-sectional view of the semiconductor unit included in the semiconductor device of the first embodiment (Modification 1-1). It should be noted that Figure 13 And Figure 14 Corresponds to Figure 3 And Figure 4 Of the first embodiment. Figure 14 Is Figure 13 The cross-sectional view at the single dotted line X-X of.

[0129] The semiconductor device of Modification 1-1 is different from the semiconductor device 1 of the first embodiment in that the semiconductor unit 10 is different. The semiconductor unit 10 of Modification 1-1 does not form recesses 11b1 and 11c1 in the conductive plates 11b and 11c compared with the semiconductor unit 10 of the first embodiment, and further, the supporting conductive plates 11b2 and 11c2 are not provided. That is, the conductive plates 11b and 11c of the semiconductor unit 10 of Modification 1-1 have no recesses or openings, and the front surface is flat and rectangular.

[0130] In such a semiconductor unit 10 of Modification 1-1, the wiring bonding portions 13a and 14a of the lead frames 13 and 14 are bonded to the conductive plates 11c and 11b via the supporting block portions 11c4 and 11b4. For example, as Figure 14As shown, in the lead frame 13, the wiring joint portion 13b is joined to the conductive plate 11d by the joining member 15a. The wiring joint portion 13a is supported by the support block portion 11c4 disposed on the conductive plate 11c. The wiring joint portion 13a can maintain the same height as the wiring joint portion 13b. The support block portion 11c4 can be made of an insulating material. Such a material is, for example, resin. The height of the support block portion 11c4 only needs to be able to achieve any height at which the wiring joint portion 13a is desired to be maintained. Thereby, the wiring joint portion 13a is electrically insulated from the conductive plate 11c. In addition, the support block portion 11c4 can be disposed in the recess 11c1 provided in the same manner as in the first embodiment on the conductive plate 11c.

[0131] The remaining configuration of the lead frame 13 of the modification 1-1 can be the same as that of the lead frame 13 of the first embodiment. In addition, the lead frame 14 of the modification 1-1 has the same configuration as the lead frame 13 of the modification 1-1.

[0132] Similar to the first embodiment, such a semiconductor unit 10 of the modification 1-1 prevents the inclination of the electrode joint portion 13c and suppresses the deviation of the thickness of the joining member 15b. Thereby, the deviation of the heat dissipation performance of the semiconductor chip 12 is suppressed, and the occurrence of failures of the semiconductor chip 12 is reduced. Therefore, the reduction in the reliability of the semiconductor device 1 is suppressed.

[0133] [Second Embodiment] In the second embodiment, Figure 15 a case where the lead frames 13 and 14 are not in a straight line when viewed from above, as compared with the first embodiment, will be described. Figure 15 It is a top view of the semiconductor unit included in the semiconductor device of the second embodiment.

[0134] In the semiconductor unit 10 of the second embodiment, except for the lead frames 13 and 14, the configuration can be the same as that of the semiconductor unit 10 of the first embodiment. Such lead frames 13 and 14 of the second embodiment divide the wiring joint portions 13b and 14b of the lead frames 13 and 14 of the first embodiment into wiring joint portions 13b2, 13b3 and wiring joint portions 14b2, 14b3, respectively. It should be noted that in the lead frames 13 and 14 of the second embodiment, except for the wiring joint portions 13b2, 13b3 and the wiring joint portions 14b2, 14b3, the configurations of the lead frames 13 and 14 of Figure 4 and Figure 5 can be referred to. The wiring joint portions 13b2, 13b3 and the wiring joint portions 14b2, 14b3 are respectively connected to the conductive plates 11d, 11c via the joining member 15b.

[0135] Along with this, the lead frames 13 and 14 of the second embodiment include connecting portions 13e2, 13e3 and connecting portions 14e2, 14e3. The connecting portions 13e2, 13e3 and the connecting portions 14e2, 14e3 are each linear. The connecting portions 13e2, 13e3 connect between the electrode bonding portions 13c and the wiring bonding portions 13b2, 13b3. The connecting portions 14e2, 14e3 connect between the electrode bonding portions 14c and the wiring bonding portions 14b2, 14b3. Additionally, here, the lengths of the connecting portions 13e2, 13e3 and the connecting portions 14e2, 14e3 are equal.

[0136] A semiconductor device including such lead frames 13 and 14 can also be manufactured according to Figure 6 the flowchart. In Figure 6 the first bonding process of step S3 in the flowchart, heating is stopped, and when the molten bonding members 15a, 15b solidify, the electrode bonding portions 13c, 14c of the lead frames 13, 14 are supported by the wiring bonding portions 13a, 14a, the wiring bonding portions 13b2, 13b3, and the wiring bonding portions 14b2, 14b3. Therefore, in the second embodiment, compared with the case of the first embodiment, the inclination of the lead frame 13 and the electrode bonding portion 13c can be more stably suppressed. Therefore, the thickness of the bonding member 15b is also more reliably maintained to be substantially uniform.

[0137] It should be noted that in the second embodiment, the case where the lead frames 13, 14 include the wiring bonding portions 13b2, 13b3 and the wiring bonding portions 14b2, 14b3 that are divided into two is taken as an example for description. The wiring bonding portions 13b, 14b of the lead frames 13, 14 in the first embodiment are not limited to being divided into two, and may also be divided into three or more. Additionally, the wiring bonding portions 13a, 14a of the lead frames 13, 14 in the first embodiment can be divided into two or more. In this case, openings or depressions are formed in the conductive plates 11c, 11b according to the number of divisions of the wiring bonding portions 13a, 14a. Or, the wiring bonding portions divided into two or more can be respectively bonded to the conductive plates 11c, 11b via the support block portions of Modification 1-1.

[0138] Additionally, in the case where at least any one of the wiring bonding portions 13a, 14a and the wiring bonding portions 13b, 14b of the lead frames 13, 14 in the first embodiment is divided into a plurality of parts, the electrode bonding portions 13c, 14c can be provided at the centroid positions of the lead frames 13, 14. When bonding the lead frames 13, 14 to the insulating circuit board 11 and the semiconductor chip 12 ( Figure 6 step S3), the inclination of the lead frames 13, 14 and the electrode bonding portions 13c, 14c can be more stably suppressed, and the thickness of the bonding member 15b can be maintained more uniformly.

[0139] [Third Embodiment] In the third embodiment, Figure 16 a case where the lead frames 13 and 14 included in the semiconductor unit 10 of the first embodiment include elastic portions will be described. Figure 16 FIG. is a diagram showing a first bonding step included in the manufacturing method of the semiconductor device according to the third embodiment. It should be noted that the semiconductor device according to the third embodiment can also be manufactured according to the Figure 6 flowchart of the first embodiment.

[0140] The semiconductor unit 10 of the third embodiment includes elastic portions 13f and 13g in the lead frame 13 of the semiconductor unit 10 of the first embodiment. Other configurations in the semiconductor unit 10 of the third embodiment are formed the same as those of the semiconductor unit 10 of the first embodiment. In addition, the lead frame 14 of the semiconductor unit 10 of the third embodiment is also formed the same as the lead frame 13 of the third embodiment.

[0141] It should be noted that here, the elastic portions 13f and 13g included in the flat connecting portions 13d and 13e of the lead frame 13 are formed in a concave shape in which the entire width of the connecting portions 13d and 13e bends in any one of the ±Z directions in the thickness direction. It should be noted that the elastic portions 13f and 13g are Figure 16 the ranges surrounded by the dotted lines. In addition, in Figure 16 FIG., a case where one concave elastic portion 13f and 13g is provided in each of the connecting portions 13d and 13e is shown. The elastic portions 13f and 13g may be two or more. In addition, since the elastic portions 13f and 13g only need to show elasticity in the connecting portions 13d and 13e, they do not necessarily have to be concave, and other shapes may be formed. It should be noted that the lead frame 14 may also include the same elastic portions.

[0142] Thus, in the case where the lead frames 13 and 14 include elastic portions, similarly to the second embodiment, the electrode bonding portions 13c and 14c can be provided at the positions of the centers of gravity of the lead frames 13 and 14. When bonding the lead frames 13 and 14 to the insulating circuit board 11 and the semiconductor chip 12 ( Figure 6 step S3), it is possible to more stably suppress the inclination of the lead frames 13 and 14 and the electrode bonding portions 13c and 14c, and the thickness of the bonding member 15b can be maintained more uniformly.

[0143] In addition, in accordance with Figure 6When manufacturing a semiconductor device including such a semiconductor unit 10 in a flowchart, during the first bonding process in step S3 and the wire sealing process in step S6, even if the semiconductor unit 10 is impacted from the outside, the impact is alleviated by the elastic portion. Therefore, it is possible to suppress the electrode bonding portions 13c and 14c of the lead frames 13 and 14 from detaching from the semiconductor chip 12.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor chip comprising a main electrode on a front side; A first conductive plate including a first main surface having a chip region to which the back side of the semiconductor chip is bonded; a second conductive plate, disposed adjacent to the first conductive plate in a plan view; a support portion provided on the first conductive plate at an opposite side of the chip region from the second conductive plate and insulated from the first conductive plate; as well as A lead frame includes a first bonding portion bonded to the support portion, a second bonding portion bonded to the second conductive plate, and an electrode bonding portion bonded to the main electrode of the semiconductor chip via a bonding member.

2. The semiconductor device according to claim 1, wherein: The support portion is disposed in an opening region formed in the first conductive plate so as not to contact the first conductive plate.

3. The semiconductor device according to claim 2, wherein: The support portion is made of the same material as that of the first conductive plate.

4. The semiconductor device according to claim 1, wherein: In the lead frame, a first length from the electrode-joining portion to the first joining portion is equal to a second length from the electrode-joining portion to the second joining portion.

5. The semiconductor device according to claim 1, wherein: The lead frame includes a first flat-plate-shaped connecting portion connecting the electrode bonding portion and the first bonding portion, and a second flat-plate-shaped connecting portion connecting the electrode bonding portion and the second bonding portion. A first height from the first joint to the first connection portion is higher than a third height from the electrode joint to the first connection portion, and a second height from the second joint to the second connection portion is higher than a fourth height from the electrode joint to the second connection portion.

6. The semiconductor device according to claim 1, wherein: The lead frame extends linearly from the electrode joint portion to the first joint portion in a plan view.

7. The semiconductor device according to claim 6, wherein: The lead frame extends linearly from the electrode joint portion to the second joint portion in a plan view.

8. The semiconductor device according to claim 6, wherein: The lead frame extends linearly from the first joining portion to the second joining portion in a plan view.

9. The semiconductor device according to claim 6, wherein: The lead frame includes a plurality of the second bonding portions, and extends linearly from the electrode bonding portion to each of the plurality of the second bonding portions in a plan view.

10. The semiconductor device according to claim 9, wherein: The electrode-joining portion corresponds to a position of a center of gravity of the lead frame in a plan view.

11. The semiconductor device according to claim 1, wherein: The lead frame includes elastic portions between the electrode joint portion and the first joint portion, and between the electrode joint portion and the second joint portion, respectively.

12. The semiconductor device according to claim 11, wherein: The lead frame includes a first flat-plate-shaped connecting portion connecting the electrode bonding portion and the first bonding portion, and a second flat-plate-shaped connecting portion connecting the electrode bonding portion and the second bonding portion. The elastic parts are respectively arranged at the first connecting part and the second connecting part, The entire width of the first linking portion and the second linking portion of the respective elastic portions of the first linking portion and the second linking portion is bent in the thickness direction.

Images