Wiring substrate and semiconductor package including same

Abstract

The invention provides a wiring substrate and a semiconductor package including the same. The wiring substrate may include: a first substrate wiring layer including a first insulating pattern and a power pattern in the first insulating pattern; a second substrate wiring layer on the first substrate wiring layer and including a first ground pattern in the second insulating pattern; a third substrate wiring layer on the second substrate wiring layer and including a first signal pattern in a third insulating pattern; and a pad layer covering a bottom surface of the first substrate wiring layer and including a protective layer. The pad layer may include a signal pad and a ground pad in the protective layer. The ground pads may be located between the signal pads. The power pattern may vertically overlap the ground pad. The first ground pattern may vertically overlap the ground pad and the power pattern. The first signal pattern may be on the first ground pattern.

Description

Technical Field

[0001] The present disclosure relates to a wiring substrate and a semiconductor package including the wiring substrate. Background Art

[0002] With the recent progress of the electronics industry, the demand for high-performance, high-speed, and compact electronic components may be increasing. To meet this demand, packaging technologies for mounting multiple semiconductor chips in a single package are being developed.

[0003] Recently, the demand for portable electronic devices has been rapidly increasing in the market. Therefore, it may be necessary to reduce the size and weight of the electronic components that make up the portable electronic devices. To achieve this, it may be necessary to develop packaging technologies that reduce the size and weight of each component and integrate multiple individual components in a single package. In the case of a semiconductor package in which multiple devices are integrated, it may be necessary to reduce the size of the semiconductor package and improve the heat dissipation and electrical characteristics of the semiconductor package.

[0004] Multiple semiconductor chips and multiple semiconductor devices may be mounted on a printed circuit board. However, as the operating speed of the semiconductor chips increases, the influence of crosstalk problems between signals on signal integrity increases. In addition, there may be electromagnetic interference (EMI) problems between the semiconductor chips. The EMI problems may cause failures of the semiconductor chips and semiconductor devices adjacent to each other. Summary of the Invention

[0005] Embodiments of the inventive concept provide a wiring substrate having improved electrical characteristics and a semiconductor package including the wiring substrate.

[0006] According to an embodiment of the inventive concept, a wiring substrate may include: a first substrate wiring layer including a first insulating pattern and a power pattern located in the first insulating pattern; a second substrate wiring layer located on the first substrate wiring layer and including a second insulating pattern and a first ground pattern located in the second insulating pattern; a third substrate wiring layer located on the second substrate wiring layer and including a third insulating pattern and a first signal pattern located in the third insulating pattern; and a pad layer covering a bottom surface of the first substrate wiring layer, the pad layer including a protective layer, and the pad layer further including signal pads and ground pads located in the protective layer. The ground pads may be located between the signal pads. The power pattern may overlap perpendicularly with the ground pads. The first ground pattern may overlap perpendicularly with the ground pads and the power pattern. The first signal pattern may be located on the first ground pattern.

[0007] According to an embodiment of the inventive concept, a wiring substrate may include: a body layer; a ground pad and a signal pad, the ground pad and the signal pad being located on a bottom surface of the body layer; a first substrate wiring layer located in the body layer; and a second substrate wiring layer located in the body layer and on the first substrate wiring layer. The first substrate wiring layer may include a first signal pattern and a power pattern. When observed in a plan view, the power pattern may be disposed between the first signal patterns. The power pattern may be disposed on the ground pad. The second substrate wiring layer may include a second signal pattern. The second signal pattern is located on the power pattern.

[0008] According to an embodiment of the inventive concept, a semiconductor package may include: a substrate; a semiconductor chip located on the substrate; and a molding layer located on the substrate and surrounding the semiconductor chip. The substrate may include a body layer, a ground pad and a signal pad located on a bottom surface of the body layer, a first signal pattern located in the body layer, and a power pattern located in the body layer. The power pattern may be located between the ground pad and the first signal pattern. The power pattern may be located on the ground pad. The first signal pattern may be located on the power pattern. On the ground pad, a horizontal width of the power pattern may be 0.8 times to 1.2 times a horizontal width of the ground pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a wiring substrate according to an embodiment of the inventive concept.

[0010] Figure 2 is a plan view showing a wiring substrate according to an embodiment of the inventive concept.

[0011] Figure 3 and Figure 4 is showing Figure 1 an enlarged cross-sectional view of a portion “A” of

[0012] Figure 5 is a cross-sectional view showing a wiring substrate according to an embodiment of the inventive concept.

[0013] Figure 6 is showing Figure 5 an enlarged cross-sectional view of a portion “B” of

[0014] Figure 7 is a cross-sectional view showing a wiring substrate according to an embodiment of the inventive concept.

[0015] Figure 8 is showingFigure 7 A magnified cross-sectional view of part “C”.

[0016] Figure 9 FIG. 5 is a cross-sectional view of a wiring substrate showing an embodiment according to the inventive concept.

[0017] Figure 10 and Figure 11 FIG. 6 is a cross-sectional view of a semiconductor package showing an embodiment according to the inventive concept. DETAILED DESCRIPTION

[0018] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. It will be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening elements or layers may be present therebetween.

[0019] Figure 1 FIG. 5 is a cross-sectional view of a wiring substrate showing an embodiment according to the inventive concept. Figure 2 FIG. 7 is a plan view of a wiring substrate (e.g., a substrate protective layer and a substrate pad of a wiring substrate) showing an embodiment according to the inventive concept. In addition, a first power pattern of a first substrate wiring layer is also shown in FIG. 7. Figure 2 in FIG. 7 Figure 3 and Figure 4 FIG. 8 Figure 1 is a magnified cross-sectional view of part “A” of FIG. 8. Figure 1 and Figure 2 FIGS. 9 and 10 show an example of possible arrangements and shapes of substrate pads and conductive patterns prepared for ease of description, but the inventive concept is not limited to this example.

[0020] Referring Figures 1 to 3 to FIGS. 5 to 10, a wiring substrate 100 may be provided. The wiring substrate 100 may be a printed circuit board (PCB). However, the inventive concept is not limited to this example, and various substrates including a redistribution substrate may be used as the wiring substrate 100.

[0021] The wiring substrate 100 may have a structure including an insulating layer and a plurality of wiring patterns provided in the insulating layer. For example, the wiring substrate 100 may have a structure in which insulating patterns and wiring patterns are alternately stacked. Specifically, the wiring substrate 100 may include a substrate protective layer 110 and at least two substrate wiring layers RL1 and RL2 stacked on the substrate protective layer 110.

[0022] The substrate protective layer 110 may include an insulating material. For example, the substrate protective layer 110 may be formed of an insulating polymer or a photoimageable dielectric (PID) material, or include an insulating polymer or a PID material. The photoimageable dielectric material may include, for example, at least one of photoimageable polyimide, polybenzoxazole (PBO), phenolic polymer, or benzocyclobutene-based polymer.

[0023] The substrate pads 120 may be disposed in the substrate protective layer 110 and may be electrically connected to the substrate wiring layers RL1 and RL2 disposed on the substrate protective layer 110. The substrate pads 120 may be buried in the substrate protective layer 110. The substrate pads 120 may be exposed to the outside of the substrate protective layer 110 through the top surface and the bottom surface of the substrate protective layer 110. The bottom surface of the substrate pads 120 may be coplanar with the bottom surface of the substrate protective layer 110. Different from the shown structure, the substrate pads 120 may be disposed on the bottom surface of the substrate protective layer 110 and may protrude relative to the bottom surface of the substrate protective layer 110. Solder balls or the like for mounting the wiring substrate 100 on another device or another substrate may be bonded to the substrate pads 120. The substrate pads 120 may include a conductive material. For example, the substrate pads 120 may be formed of copper (Cu), or include Cu.

[0024] Although not shown, each substrate pad 120 may include a seed layer or a barrier layer, and the seed layer or the barrier layer is provided to cover the bottom surface and the side surface of the substrate pad 120. In an embodiment, the seed layer or the barrier layer may be provided only on the bottom surface of the substrate pad 120. The substrate protective layer 110 and the substrate pads 120 may constitute the pad layer of the wiring substrate 100.

[0025] As Figure 2As shown, the substrate pad 120 may include a signal pad 122, a ground pad 124, and a power pad 126. The signal pad 122 may be used to input an operation signal to a semiconductor chip mounted on the wiring substrate 100 and output an operation signal from the semiconductor chip mounted on the wiring substrate 100. The ground pad 124 may be used to apply a ground signal to the wiring substrate 100 and the semiconductor chip thereon. The power pad 126 may be used to supply power to the semiconductor chip on the wiring substrate 100. The signal pad 122 and the ground pad 124 may be provided throughout the substrate protection layer 110. As an example, the signal pad 122 and the ground pad 124 may be provided on the central region of the substrate protection layer 110 and may also be provided on the edge region surrounding the central region of the substrate protection layer 110. At least some of the ground pads 124 may be located between the signal pads 122. For example, at least some of the ground pads 124 may be provided on the central region of the substrate protection layer 110. The power pad 126 may be provided in a region adjacent to the side surface of the substrate protection layer 110. As an example, the power pad 126 may be disposed on the edge region of the substrate protection layer 110. The power pad 126 may be disposed between the signal pad 122 and the ground pad 124 and the side surface of the substrate protection layer 110.

[0026] The substrate wiring layers RL1 and RL2 may be stacked on the substrate protection layer 110. In the present specification, the substrate wiring layer may mean a substrate wiring layer formed by patterning an insulating layer and a conductive layer, respectively, of the wiring substrate 100. That is, the conductive patterns in the substrate wiring layer RL1 or RL2 may be wiring lines that extend horizontally and overlap each other non-perpendicularly. Each of the substrate wiring layers RL1 and RL2 may include an insulating pattern 210 or 310 and a conductive pattern 220 or 320 provided in the insulating pattern 210 or 310. The conductive pattern 220 or 320 in one of the substrate wiring layers RL1 and RL2 may be electrically connected to the conductive pattern 220 or 320 in the other of the substrate wiring layers RL1 and RL2. Hereinafter, the schematic structure of the substrate wiring layers RL1 and RL2 will be described in more detail with reference to the first substrate wiring layer RL1 disposed on the substrate protection layer 110.

[0027] The first substrate wiring layer RL1 may include a first insulating pattern 210 and a first conductive pattern 220 located in the first insulating pattern 210.

[0028] The first insulating pattern 210 may be formed of an inorganic insulating material (e.g., silicon oxide (SiO x )) or silicon nitride (SiN x ), or include an inorganic insulating material (e.g., silicon oxide (SiO x )) or silicon nitride (SiN x)) In an embodiment, the first insulating pattern 210 may be formed of at least one polymeric material or include at least one polymeric material. The first insulating pattern 210 may be formed of an insulating polymer or a photoimageable dielectric (PID) material, or include an insulating polymer or a PID material. The photoimageable dielectric material may include, for example, at least one of photoimageable polyimide, polybenzoxazole (PBO), phenol-based polymer, or benzocyclobutene-based polymer.

[0029] The first conductive pattern 220 may be disposed in the first insulating pattern 210. The first conductive pattern 220 may be exposed to the outside of the first insulating pattern 210 near the top surface of the first insulating pattern 210. The first conductive pattern 220 may be covered by the second insulating pattern 310 of the second substrate wiring layer RL2. The first conductive pattern 220 may extend horizontally in the first insulating pattern 210. As described above, each first conductive pattern 220 may be a pad portion or a line portion of the first substrate wiring layer RL1. That is, the first conductive pattern 220 may be used for horizontal redistribution in the wiring substrate 100. Different from the shown structure, the first conductive pattern 220 may be disposed on the top surface of the first insulating pattern 210. The first conductive pattern 220 may protrude upward relative to the top surface of the first insulating pattern 210. The first conductive pattern 220 may include a conductive material. For example, the first conductive pattern 220 may be formed of copper (Cu) or include Cu.

[0030] Although not shown, at least a portion of the first conductive pattern 220 may include a via pattern that extends from its bottom surface and has a downward protruding shape. The via pattern may be used to connect the first conductive pattern 220 to the substrate pad 120. For example, the via pattern may extend from the bottom surface of the first conductive pattern 220 to penetrate the first insulating pattern 210 and may be bonded to the top surface of the substrate pad 120. A portion of the first conductive pattern 220 may have a "T" shaped cross-section.

[0031] The first conductive pattern 220 may include a first signal pattern 222, a first ground pattern 224, and a first power pattern 226. The first signal pattern 222, the first ground pattern 224, and the first power pattern 226 may be located at the same vertical height.

[0032] The first signal pattern 222 and the first ground pattern 224 may include line patterns. In other words, the first signal pattern 222 may be composed of a plurality of wiring lines that extend horizontally in the first insulating pattern 210, and the first ground pattern 224 may be composed of a plurality of wiring lines that extend horizontally in the first insulating pattern 210. The first signal pattern 222 may be electrically connected to the signal pad 122. The first ground pattern 224 may be electrically connected to the ground pad 124.

[0033] The first power pattern 226 may be a single pattern. For example, the first power pattern 226 may be a network pattern formed by a plurality of wiring lines that horizontally extend and are connected to each other in the first insulating pattern 210. The first power pattern 226 may be electrically connected to the power pad 126. For example, the first power pattern 226 may be disposed on the power pad 126. At least a part of the first power pattern 226 may be disposed on the central region of the substrate protection layer 110. The first power pattern 226 may extend to a region disposed on at least some of the ground pads 124. The first power pattern 226 may not extend to a region disposed on the signal pad 122. That is, the first power pattern 226 may vertically overlap at least some of the ground pads 124. When observed in a plan view, the first power pattern 226 may not vertically overlap the signal pad 122 and may be spaced apart from the signal pad 122. That is, the first power pattern 226 may be positioned between the signal pads 122. The first power pattern 226 may pass through a region between the first signal patterns 222 or between the first ground patterns 224.

[0034] Figure 3 and Figure 4 FIG. is a vertical cross-section showing a region where the first power pattern 226 and the ground pad 124 overlap each other. The following description will refer to a cross-section including one ground pad 124 and the first power pattern 226 disposed thereon. The first power pattern 226 may be disposed on the ground pad 124. When observed in a plan view, the first power pattern 226 may be disposed to completely intersect the ground pad 124. The first power pattern 226 may pass through a region on the central portion of the ground pad 124. Here, as Figure 3 shown, a first width W1 of the first power pattern 226 may be smaller than a second width W2 of the ground pad 124. Here, the first width W1 of the first power pattern 226 and the second width W2 of the ground pad 124 may be measured on the ground pad 124 in a direction parallel to the top surface of the ground pad 124. For example, when observed in the width direction of the first power pattern 226 across the ground pad 124, side surfaces of the first power pattern 226 may be disposed on the ground pad 124. Or, as Figure 4 shown, the first width W1 of the first power pattern 226 may be equal to or greater than the second width W2 of the ground pad 124. For example, the entire ground pad 124 may be disposed under the first power pattern 226. Referring to Figure 3 and Figure 4 , the first width W1 of the first power pattern 226 may be similar to or smaller than the second width W2 of the ground pad 124. The first width W1 of the first power pattern 226 may be 0.8 times to 1.2 times the second width W2 of the ground pad 124.

[0035] The first power pattern 226 may be vertically spaced apart from the ground pad 124 by the first insulating pattern 210. The first power pattern 226 and the ground pad 124 may form a microstrip structure.

[0036] In an embodiment, when observed in a plan view, the first power pattern 226 may pass through an area located between the ground pad 124 and the signal pad 122. In this case, the first power pattern 226 and the ground pad 124 may form a microstrip structure, and thus, interference signals (e.g., noise signals) generated from the first power pattern 226 may be absorbed by the ground pad 124. Therefore, the interference signals generated from the first power pattern 226 do not affect the signal pad 122 or other patterns (e.g., the first signal pattern 222) in the first substrate wiring layer RL1. That is, the wiring substrate and the semiconductor package having the wiring substrate may have improved electrical characteristics.

[0037] Reference Figures 1 to 3 , the second substrate wiring layer RL2 may include a second insulating pattern 310 and a second conductive pattern 320 disposed in the second insulating pattern 310.

[0038] The second insulating pattern 310 may be formed of an inorganic insulating material (e.g., silicon oxide (SiO x ) or silicon nitride (SiN x )) or include an inorganic insulating material (e.g., silicon oxide (SiO x ) or silicon nitride (SiN x ))). Alternatively, the second insulating pattern 310 may be formed of at least one polymeric material or include at least one polymeric material. The second insulating pattern 310 may be formed of an insulating polymer or a photoimageable dielectric (PID) material or include an insulating polymer or a PID material. The photoimageable dielectric material may include at least one of, for example, photoimageable polyimide, polybenzoxazole (PBO), phenolic polymer, or benzocyclobutene polymer. The second insulating pattern 310 may cover the first substrate wiring layer RL1. In an embodiment, the second insulating pattern 310 may be disposed on the first insulating pattern 210 to cover the first conductive pattern 220. The first insulating pattern 210 and the second insulating pattern 310 may constitute a main layer of the wiring substrate 100. As an example, the first insulating pattern 210 and the second insulating pattern 310 may be formed of the same material and may be provided as a layer made of a single material.

[0039] The second conductive pattern 320 may be disposed in the second insulating pattern 310. The second conductive pattern 320 may be exposed to the outside of the second insulating pattern 310 near the top surface of the second insulating pattern 310. The second conductive pattern 320 may horizontally extend in the second insulating pattern 310. As described above, each second conductive pattern 320 may be a pad portion or a wiring portion of the second substrate wiring layer RL2. In other words, the second conductive pattern 320 may be used for horizontal redistribution in the wiring substrate 100. Different from the shown structure, the second conductive pattern 320 may be disposed on the top surface of the second insulating pattern 310. The second conductive pattern 320 may protrude upward with respect to the top surface of the second insulating pattern 310. The second conductive pattern 320 may include a conductive material. For example, the second conductive pattern 320 may be formed of copper (Cu) or include Cu.

[0040] Although not shown, at least a portion of the second conductive pattern 320 may include a via pattern extending from its bottom surface and having a downward protruding shape. The via pattern may be used to connect the second conductive pattern 320 to the first conductive pattern 220 of the first substrate wiring layer RL1. For example, the via pattern may extend from the bottom surface of the second conductive pattern 320 to penetrate the second insulating pattern 310 and may be bonded to the top surface of the first conductive pattern 220. A portion of the second conductive pattern 320 may have a "T" shaped cross-section.

[0041] The second conductive pattern 320 may have a second signal pattern 322 and a second ground pattern 324. Although not shown, the second conductive pattern 320 may further include a second power pattern. The second signal pattern 322, the second ground pattern 324, and the second power pattern may be located at the same vertical height.

[0042] The second signal pattern 322 and the second ground pattern 324 may include line patterns. For example, the second signal pattern 322 may be composed of a plurality of wiring lines horizontally extending in the second insulating pattern 310, and the second ground pattern 324 may be composed of a plurality of wiring lines horizontally extending in the second insulating pattern 310. The power pattern may be composed of a plurality of wiring lines horizontally extending in the second insulating pattern 310. The second signal pattern 322 may be electrically connected to the first signal pattern 222. The second ground pattern 324 may be electrically connected to the first ground pattern 224. The power pattern may be electrically connected to the first power pattern 226.

[0043] At least a portion of the second signal pattern 322 may be disposed on the first power pattern 226. The following description will refer to the second signal pattern 322 disposed on the first power pattern 226. The second signal pattern 322 may vertically overlap with the first power pattern 226. Here, as Figure 3As shown, at least a portion of each second signal pattern 322 may overlap perpendicularly with the first power pattern 226. Alternatively, as Figure 4 shown, the entire second signal pattern 322 may overlap perpendicularly with the first power pattern 226.

[0044] According to an embodiment of the inventive concept, even when the second signal pattern 322 is disposed on the first power pattern 226, the ground pad 124 may absorb interference signals generated in the first power pattern 226. Thus, the second signal pattern 322 is not affected by the interference signals. Accordingly, the second signal pattern 322 may be freely disposed regardless of the position of the first power pattern 226. In addition, the first power pattern 226 may be disposed in the central region of the wiring substrate 100 regardless of the position of the second signal pattern 322. More specifically, even when the first power pattern 226 is disposed to pass through the region between the signal pads 122 or the first signal pattern 222 or to overlap with the second signal pattern 322, the interference signals do not affect the operation signals of the signal pads 122, the first signal pattern 222, and the second signal pattern 322. Accordingly, it may not be necessary to dispose the first power pattern 226 in the edge region of the wiring substrate 100 so as to bypass the signal pads 122, the first signal pattern 222, and the second signal pattern 322. As a result, the electrical characteristics of the wiring substrate 100 can be improved, the degree of freedom in setting the wiring patterns of the wiring substrate 100 can be increased, and the sizes of the wiring substrate 100 and the semiconductor package can be reduced.

[0045] Referring to Figures 1 to 3 , the second ground pattern 324 may be disposed between the second signal patterns 322. Some of the second signal patterns 322 disposed on the first power pattern 226 may be located between the second ground patterns 324. The second ground pattern 324 may reduce the intensity of interference signals propagating toward the second signal patterns 322.

[0046] Figure 1 An example is shown in which the second substrate wiring layer RL2 is the uppermost substrate wiring layer of the wiring substrate 100, but the inventive concept is not limited to this example. In an embodiment, the wiring substrate 100 may further include an additional substrate wiring layer disposed on the second substrate wiring layer RL2.

[0047] In the description of the embodiments to be described below, for the sake of brevity of description, the elements previously referred to Figures 1 to 4 may be identified by the same reference numerals without repeating their overlapping description.

[0048] Figure 5 is a cross-sectional view of a wiring substrate according to an embodiment of the inventive concept. Figure 6 is showing Figure 5 an enlarged cross-sectional view of part “B” of

[0049] Reference Figure 5 and Figure 6 , the wiring substrate may further include a third substrate wiring layer RL3 between the first substrate wiring layer RL1 and the second substrate wiring layer RL2.

[0050] The third substrate wiring layer RL3 may include a third insulating pattern 410 and a third conductive pattern 420 located in the third insulating pattern 410.

[0051] The third insulating pattern 410 may be formed of an inorganic insulating material (e.g., silicon oxide (SiO x )) or silicon nitride (SiN x ), or include an inorganic insulating material (e.g., silicon oxide (SiO x )) or silicon nitride (SiN x ). In an embodiment, the third insulating pattern 410 may be formed of at least one polymeric material, or include at least one polymeric material. The third insulating pattern 410 may be formed of an insulating polymer or a photoimageable dielectric (PID) material, or include an insulating polymer or a PID material. The photoimageable dielectric material may include, for example, at least one of photoimageable polyimide, polybenzoxazole (PBO), phenol-based polymer, or benzocyclobutene-based polymer. The third insulating pattern 410 may cover the first substrate wiring layer RL1. In an embodiment, the third insulating pattern 410 may be disposed on the first insulating pattern 210 to cover the first conductive pattern 220. The first insulating pattern 210, the second insulating pattern 310, and the third insulating pattern 410 may constitute the main body layer of the wiring substrate 100. As an example, the first insulating pattern 210, the second insulating pattern 310, and the third insulating pattern 410 may be formed of the same material and may be provided as a layer made of a single material.

[0052] The third conductive pattern 420 may be disposed in the third insulating pattern 410. The third conductive pattern 420 may be exposed to the outside of the third insulating pattern 410 near the top surface of the third insulating pattern 410. The third conductive pattern 420 may extend horizontally in the third insulating pattern 410. Different from the shown structure, the third conductive pattern 420 may be disposed on the top surface of the third insulating pattern 410. The third conductive pattern 420 may protrude upward relative to the top surface of the third insulating pattern 410. The third conductive pattern 420 may include a conductive material. For example, the third conductive pattern 420 may be formed of copper (Cu), or include Cu.

[0053] Although not shown, at least a portion of the third conductive pattern 420 may include a via pattern extending from its bottom surface and having a downwardly protruding shape. The via pattern may be used to connect the third conductive pattern 420 to the first conductive pattern 220 of the first substrate wiring layer RL1. For example, the via pattern may extend from the bottom surface of the third conductive pattern 420 to penetrate the third insulating pattern 410 and may be bonded to the top surface of the first conductive pattern 220. The third conductive pattern 420 may have a "T" - shaped cross - section.

[0054] The third conductive pattern 420 may include a third ground pattern 424. Although not shown, the third conductive pattern 420 may further include a third signal pattern or a third power pattern. The third signal pattern, the third ground pattern 424, and the third power pattern may be disposed at the same vertical height.

[0055] The third ground pattern 424 may be a single pattern. For example, the third ground pattern 424 may be a plate - shaped pattern, a linear pattern, or a strip - shaped pattern that extends horizontally in the third insulating pattern 410. The third ground pattern 424 may be electrically connected to the first ground pattern 224. The third ground pattern 424 may be disposed between the first power pattern 226 of the first substrate wiring layer RL1 and at least some of the second signal patterns 322 of the second substrate wiring layer RL2. More specifically, the third ground pattern 424 may be disposed on the ground pad 124 to cover the entire first power pattern 226. On the ground pad 124, the entire first power pattern 226 may vertically overlap with the third ground pattern 424. The width of the first power pattern 226 may be less than the width of the third ground pattern 424. Here, the width of the first power pattern 226 and the width of the third ground pattern 424 may be measured on the ground pad 124 in a direction parallel to the top of the ground pad 124. Some of the second signal patterns 322 may be disposed on the third ground pattern 424. All of the second signal patterns 322 disposed on the first power pattern 226 may vertically overlap with the first power pattern 226. That is, the third ground pattern 424 may be arranged to pass through the region between the first power pattern 226 and the second signal patterns 322. The third ground pattern 424 may vertically overlap with the ground pad 124 disposed below the first power pattern 226.

[0056] The first power pattern 226 may be vertically spaced apart from the ground pad 124 by the first insulating pattern 210. The first power pattern 226 may be vertically spaced apart from the third ground pattern 424 by the third insulating pattern 410. The ground pad 124, the first power pattern 226, and the third ground pattern 424 may form a strip - line structure.

[0057] In an embodiment, when observed in a plan view, the first power pattern 226 may be interposed between the ground pad 124 and the third ground pattern 424. In this case, the ground pad 124, the first power pattern 226, and the third ground pattern 424 may form a strip line structure. Thus, interference signals (e.g., noise signals) generated from the first power pattern 226 may be absorbed by the ground pad 124 or the third ground pattern 424. Accordingly, the interference signals generated from the first power pattern 226 do not affect the signal pads 122 or other patterns (e.g., the first signal pattern 222) in the first substrate wiring layer RL1. That is, the wiring substrate and the semiconductor package having the wiring substrate may have improved electrical characteristics.

[0058] In addition, since the third ground pattern 424 is interposed between the first power pattern 226 and the second signal pattern 322 positioned on the first power pattern 226, the third ground pattern 424 may be used to block interference signals generated from the first power pattern 226. Even when the first power pattern 226 overlaps with the second signal pattern 322, the operation signals of the second signal pattern 322 are not affected by the interference signals.

[0059] The second substrate wiring layer RL2 may be disposed on the third substrate wiring layer RL3.

[0060] The second insulating pattern 310 may cover the third substrate wiring layer RL3. In an embodiment, the second insulating pattern 310 may be disposed on the third insulating pattern 410 to cover the third conductive pattern 420. The first insulating pattern 210, the third insulating pattern 410, and the second insulating pattern 310 may constitute the main layers of the wiring substrate 100. In an embodiment, the first insulating pattern 210, the third insulating pattern 410, and the second insulating pattern 310 may be formed of the same material and may be provided as a layer made of a single material.

[0061] The second conductive pattern 320 may be disposed in the second insulating pattern 310. The second conductive pattern 320 may be exposed to the outside of the second insulating pattern 310 near the top surface of the second insulating pattern 310.

[0062] In the description of the embodiments to be described below, for simplicity of description, the elements previously referred to Figure 5 and Figure 6 described may be identified by the same reference numerals without repeating their overlapping descriptions.

[0063] Figure 7 is a cross-sectional view of a wiring substrate according to an embodiment of the inventive concept. Figure 8 is a view showing Figure 7 an enlarged cross-sectional view of part “C” of

[0064] Referring toFigure 7 and Figure 8 In addition, the first conductive pattern 220 of the first substrate wiring layer RL1 may further include a fourth ground pattern 228. The fourth ground pattern 228 may be disposed at the same vertical height as the first signal pattern 222, the first ground pattern 224, and the first power pattern 226.

[0065] The fourth ground pattern 228 may include a line pattern. In an embodiment, the fourth ground pattern 228 may be composed of a plurality of wiring lines disposed in the first insulating pattern 210 and extending horizontally. Alternatively, the fourth ground pattern 228 may be a plate-shaped pattern or a strip-shaped pattern extending horizontally in the first insulating pattern 210. The fourth ground pattern 228 may be disposed adjacent to the first power pattern 226. The fourth ground pattern 228 may be disposed between the first power pattern 226 and the first signal pattern 222. That is, the first signal pattern 222 may be spaced apart from the first power pattern 226, and the fourth ground pattern 228 may be interposed between the first signal pattern 222 and the first power pattern 226. The fourth ground pattern 228 may be horizontally spaced apart from the first power pattern 226. The width of the fourth ground pattern 228 may be greater than the width of the first signal pattern 222 or the width of the first ground pattern 224. The first power pattern 226 may be disposed on the ground pad 124 and may be surrounded by the ground pad 124, the fourth ground pattern 228, and the third ground pattern 424.

[0066] According to an embodiment of the inventive concept, in the first substrate wiring layer RL1, the first signal pattern 222 may be spaced apart from the first power pattern 226, and the fourth ground pattern 228 may be interposed between the first signal pattern 222 and the first power pattern 226. Therefore, the fourth ground pattern 228 may be used to block interference signals generated from the first power pattern 226. That is, the electrical characteristics of the wiring substrate and the semiconductor package can be improved.

[0067] Figure 9 FIG. [FIG. NUMBER] is a cross-sectional view of a wiring substrate according to an embodiment of the inventive concept.

[0068] Referring to [[FIG. REFERENCE]] Figure 9 , different from the embodiment of [[FIG. REFERENCE]] Figure 7 and Figure 8 , the third substrate wiring layer RL3 may not be provided. That is, the second substrate wiring layer RL2 including the second signal pattern 322, the second ground pattern 324, and the second power pattern may be disposed on the first substrate wiring layer RL1 including the first signal pattern 222, the first ground pattern 224, the first power pattern 226, and the fourth ground pattern 228.

[0069] The second insulating pattern 310 may cover the first substrate wiring layer RL1. In an embodiment, the second insulating pattern 310 may be disposed on the first insulating pattern 210 to cover the first conductive pattern 220. The first insulating pattern 210 and the second insulating pattern 310 may constitute the main body layer of the wiring substrate 100. As an example, the first insulating pattern 210 and the second insulating pattern 310 may be formed of the same material and may be provided as a layer made of a single material.

[0070] The second conductive pattern 320 may be disposed in the second insulating pattern 310. The second conductive pattern 320 may be exposed to the outside of the second insulating pattern 310 near the top surface of the second insulating pattern 310. The second signal pattern 322 may be electrically connected to the first signal pattern 222. The second ground pattern 324 may be electrically connected to the first ground pattern 224 or the fourth ground pattern 228.

[0071] Figure 10 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0072] Reference Figure 10 may be provided with a wiring substrate 100. The wiring substrate 100 may have a structure that is substantially the same as or similar to the wiring substrate 100 described in reference Figures 1 to 9 In the Figure 10 embodiment of Figure 7 the wiring substrate is shown as an example of the wiring substrate 100. For example, the wiring substrate 100 may include a substrate protective layer 110, a substrate pad 120 disposed in the substrate protective layer 110, and a first substrate wiring layer, a third substrate wiring layer, and a second substrate wiring layer stacked on the substrate protective layer 110.

[0073] The substrate pad 120 may include a signal pad 122, a ground pad 124, and a power pad 126.

[0074] The first substrate wiring layer may include a first insulating pattern 210 and a first conductive pattern 220 disposed in the first insulating pattern 210. The first conductive pattern 220 may include a first signal pattern 222, a first ground pattern 224, a first power pattern 226, and a fourth ground pattern 228. The first power pattern 226 may be located on the ground pad 124. The fourth ground pattern 228 may be disposed near the first power pattern 226. The fourth ground pattern 228 may be laid between the first power pattern 226 and the first signal pattern 222.

[0075] The third substrate wiring layer may include a third insulating pattern 410 and a third conductive pattern 420 located in the third insulating pattern 410. The third conductive pattern 420 may include a third ground pattern 424. The third ground pattern 424 may be located on the first power pattern 226. The third ground pattern 424 may cover the first power pattern 226.

[0076] The second substrate wiring layer may include a second insulating pattern 310 and a second conductive pattern 320 located in the second insulating pattern 310. The second conductive pattern 320 may include a second signal pattern 322, a second ground pattern 324, and a second power pattern. At least some of the second signal patterns 322 may be disposed on the first power pattern 226. The third ground pattern 424 may be arranged to cross a region between at least some of the second signal patterns 322 and the first power pattern 226. The second conductive pattern 320 of the second substrate wiring layer may be exposed to the outside of the wiring substrate 100 near the top surface of the wiring substrate 100. The second conductive pattern 320 may be used as a pad of the wiring substrate 100.

[0077] The substrate terminal 105 may be provided under the wiring substrate 100. More specifically, the substrate terminal 105 may be provided on a substrate pad 120 disposed on the bottom surface of the wiring substrate 100. The substrate terminal 105 may include solder balls or solder bumps, and depending on the type and arrangement of the substrate terminal 105, the semiconductor package may be classified into a ball grid array (BGA) package, a fine ball grid array (FBGA) package, or a land grid array (LGA) package.

[0078] The semiconductor chip 500 may be disposed on the wiring substrate 100. The semiconductor chip 500 may include a semiconductor material (e.g., silicon (Si)). The semiconductor chip 500 may include an integrated circuit disposed on the surface of the semiconductor chip 500. The integrated circuit of the semiconductor chip 500 may include a logic circuit or a memory circuit. For example, the semiconductor chip 500 may be a logic chip or a memory chip. The bottom surface of the semiconductor chip 500 may be an active surface, and the top surface of the semiconductor chip 500 may be a passive surface. Chip pads 502 and 504 may be disposed on the bottom surface of the semiconductor chip 500, and connection terminals 512 and 514 may be disposed on the chip pads 502 and 504. The chip pads 502 and 504 may include a first chip pad 502 for delivering a driving signal to the integrated circuit in the semiconductor chip 500 and a second chip pad 504 for applying a ground signal to the integrated circuit. Although not shown, the chip pads 502 and 504 may further include a third chip pad for supplying power to the integrated circuit. The connection terminals 512 and 514 may include a first connection terminal 512 connected to the first chip pad 502 and a second connection terminal 514 connected to the second chip pad 504. The connection terminals 512 and 514 may be electrically connected to the integrated circuit of the semiconductor chip 500.

[0079] The semiconductor chip 500 may be mounted on the wiring substrate 100. For example, the semiconductor chip 500 may be mounted on the wiring substrate 100 in a flip chip manner. The semiconductor chip 500 may be bonded to the second conductive pattern 320 of the wiring substrate 100 through the connection terminals 512 and 514. For example, the first connection terminal 512 may be bonded to the second signal pattern 322, and the second connection terminal 514 may be bonded to the second ground pattern 324. The connection terminals 512 and 514 may be disposed between the second conductive pattern 320 of the wiring substrate 100 and the chip pads 502 and 504 of the semiconductor chip 500.

[0080] The underfill layer 520 may be disposed between the wiring substrate 100 and the semiconductor chip 500. The underfill layer 520 may fill the space between the wiring substrate 100 and the semiconductor chip 500 and may surround the connection terminals 512 and 514.

[0081] The molding layer 600 may be disposed on the wiring substrate 100. The molding layer 600 may cover the top surface of the wiring substrate 100. The molding layer 600 may be disposed to surround the semiconductor chip 500. The molding layer 600 may include an insulating material. For example, the molding layer 600 may be formed of an epoxy molding compound (EMC) or include EMC.

[0082] Figure 11 is a cross-sectional view showing a semiconductor package according to an embodiment of the inventive concept.

[0083] Reference Figure 11 , a packaging substrate 10 can be provided. The packaging substrate 10 may include a printed circuit board (PCB) that includes a signal pattern on its top surface. Alternatively, the packaging substrate 10 may have a structure in which insulating layers and wiring layers are alternately stacked. The packaging substrate 10 may include pads provided on its top surface.

[0084] External terminals 12 may be provided under the packaging substrate 10. Specifically, the external terminals 12 may be formed on terminal pads disposed on the bottom surface of the packaging substrate 10. The external terminals 12 may include solder balls or solder bumps, and depending on the type and arrangement of the external terminals 12, the semiconductor package may be classified into a ball grid array (BGA) package, a fine ball grid array (FBGA) package, or a land grid array (LGA) package.

[0085] The built-in layer substrate 100 may be provided on the packaging substrate 10. The built-in layer substrate 100 may have a structure that is substantially the same as or similar to the Figures 1 to 9 wiring substrate 100 described in the reference. In Figure 11 the embodiment of Figure 7 the wiring substrate is shown as an example of the built-in layer substrate 100. For example, the built-in layer substrate 100 may include a substrate protection layer 110, substrate pads located in the substrate protection layer 110, and a first substrate wiring layer RL1, a third substrate wiring layer RL3, and a second substrate wiring layer RL2 stacked on the substrate protection layer 110.

[0086] The substrate pads may include signal pads, ground pads, and power pads.

[0087] The first substrate wiring layer RL1 may include a first insulating pattern and a first signal pattern, a first ground pattern, a first power pattern, and a fourth ground pattern provided in the first insulating pattern. The first power pattern may be provided on the ground pad. The fourth ground pattern may be provided adjacent to the first power pattern. The fourth ground pattern may be disposed between the first power pattern and the first signal pattern.

[0088] The third substrate wiring layer RL3 may have a third insulating pattern and a third ground pattern located in the third insulating pattern. The third ground pattern may be disposed on the first power pattern. The third ground pattern may cover the first power pattern.

[0089] The second substrate wiring layer RL2 may include a second insulating pattern and a second signal pattern, a second ground pattern, and a second power pattern provided in the second insulating pattern. At least some of the second signal patterns may be disposed on the first power pattern. The third ground pattern may be provided to cross a region between at least some of the second signal patterns and the first power pattern.

[0090] The built-in layer substrate 100 may further include an upper substrate protective layer 112 disposed to cover the second substrate wiring layer RL2 and an upper substrate pad 114 disposed on the upper substrate protective layer 112.

[0091] The upper substrate protective layer 112 may include an insulating material. For example, the upper substrate protective layer 112 may be formed of an insulating polymer or a photoimageable dielectric (PID) material, or include an insulating polymer or a PID material. The photoimageable dielectric material may include, for example, at least one of photoimageable polyimide, polybenzoxazole (PBO), phenol-based polymer, or benzocyclobutene-based polymer.

[0092] The upper substrate pad 114 may penetrate the upper substrate protective layer 112 and may be bonded to the second signal pattern, the second ground pattern, or the second power pattern of the second substrate wiring layer RL2.

[0093] The built-in layer substrate 100 may be mounted on the top surface of the package substrate 10. Substrate terminals 105 may be disposed on the bottom surface of the built-in layer substrate 100. The substrate terminals 105 may be disposed between the pads of the package substrate 10 and the substrate pads of the built-in layer substrate 100. The substrate terminals 105 may electrically connect the built-in layer substrate 100 to the package substrate 10. For example, the built-in layer substrate 100 may be mounted on the package substrate 10 in a flip-chip manner. The substrate terminals 105 may include solder balls or solder bumps.

[0094] The first underfill layer 102 may be disposed between the package substrate 10 and the built-in layer substrate 100. The first underfill layer 102 may fill the space between the package substrate 10 and the built-in layer substrate 100 and may surround the substrate terminals 105.

[0095] A chip stack may be disposed on the built-in layer substrate 100. The chip stack may include a base substrate, a first semiconductor chip 820 stacked on the base substrate, and a first molding layer 830 surrounding the first semiconductor chip 820. Hereinafter, the structure of the chip stack will be described in more detail.

[0096] The base substrate may be a base semiconductor chip 810. For example, the base substrate may be a wafer-level semiconductor substrate formed of a semiconductor material (e.g., silicon (Si)). Hereinafter, the base semiconductor chip 810 may be the same element as the base substrate, and the base semiconductor chip and the base substrate may be identified using the same reference numeral.

[0097] The substrate semiconductor chip 810 may include a substrate circuit layer 812 and a substrate through electrode 816. The substrate circuit layer 812 may be disposed on the bottom surface of the substrate semiconductor chip 810. The substrate circuit layer 812 may include an integrated circuit. For example, the substrate circuit layer 812 may be a memory circuit. That is, the substrate semiconductor chip 810 may be a memory chip (e.g., a DRAM, SRAM, MRAM, or flash memory chip). The substrate through electrode 816 may be disposed to penetrate the substrate semiconductor chip 810 in a direction perpendicular to the top surface of the built-in layer substrate 100. The substrate through electrode 816 and the substrate circuit layer 812 may be electrically connected to each other. The bottom surface of the substrate semiconductor chip 810 may be an active surface. Figure 11 An example in which the substrate includes the substrate semiconductor chip 810 is shown, but the inventive concept is not limited to this example. In an embodiment, the substrate may not include the substrate semiconductor chip 810.

[0098] The substrate semiconductor chip 810 may further include a protective layer and a first connection terminal 814. The protective layer may be disposed on the bottom surface of the substrate semiconductor chip 810 to cover the substrate circuit layer 812. The protective layer may be formed of silicon nitride (SiN) or include SiN. The first connection terminal 814 may be disposed on the bottom surface of the substrate semiconductor chip 810. The first connection terminal 814 may be electrically connected to the input / output circuit (e.g., a memory circuit) of the substrate circuit layer 812. The first connection terminal 814 may be exposed from the protective layer.

[0099] The first semiconductor chip 820 may be mounted on the substrate semiconductor chip 810. That is, the first semiconductor chip 820 and the substrate semiconductor chip 810 may form a chip-on-wafer (COW) structure. The width of the first semiconductor chip 820 may be smaller than the width of the substrate semiconductor chip 810.

[0100] The first semiconductor chip 820 may include a first circuit layer 822 and a first through electrode 826. The first circuit layer 822 may include a memory circuit. For example, the first semiconductor chip 820 may be a memory chip (e.g., a DRAM, SRAM, MRAM, or flash memory chip). The first circuit layer 822 may include the same circuit as the substrate circuit layer 812, but the inventive concept is not limited to this example. The first through electrode 826 may penetrate the first semiconductor chip 820 in a direction perpendicular to the top surface of the built-in layer substrate 100. The first through electrode 826 and the first circuit layer 822 may be electrically connected to each other. The bottom surface of the first semiconductor chip 820 may be an active surface. Chip bumps 824 may be disposed on the bottom surface of the first semiconductor chip 820. The chip bumps 824 may be disposed between the substrate semiconductor chip 810 and the first semiconductor chip 820 to electrically connect the substrate semiconductor chip 810 to the first semiconductor chip 820.

[0101] In an embodiment, a plurality of first semiconductor chips 820 may be provided. For example, the plurality of first semiconductor chips 820 may be stacked on a base semiconductor chip 810. The number of the stacked first semiconductor chips 820 may be from 8 to 32. Chip bumps 824 may be provided between the first semiconductor chips 820. Here, the uppermost first semiconductor chip 820 may not include a first through electrode 826. In addition, the thickness of the uppermost first semiconductor chip 820 may be greater than the thickness of another first semiconductor chip 820 below it.

[0102] Although not shown, an adhesive layer may be provided between the first semiconductor chips 820. The adhesive layer may include a non-conductive film (NCF). The adhesive layer may be interposed between the chip bumps 824 between the first semiconductor chips 820 to limit and / or prevent a short circuit from being formed between the chip bumps 824.

[0103] A first molding layer 830 may be provided on a top surface of the base semiconductor chip 810. The first molding layer 830 may be provided to cover the base semiconductor chip 810 and surround the first semiconductor chips 820. The top surface of the first molding layer 830 may be coplanar with the top surface of the uppermost first semiconductor chip 820, and the uppermost first semiconductor chip 820 may be exposed to the outside of the first molding layer 830. The first molding layer 830 may include an insulating polymer material. For example, the first molding layer 830 may be formed of an epoxy molding compound (EMC) or include EMC.

[0104] A chip stack having the foregoing structure may be provided. The chip stack may be mounted on an embedded layer substrate 100. For example, the chip stack may be bonded to an upper substrate pad 114 of the embedded layer substrate 100 through a first connection terminal 814 of the base semiconductor chip 810. The first connection terminal 814 may be provided between the upper substrate pad 114 of the embedded layer substrate 100 and a base circuit layer 812.

[0105] A second underfill layer 806 may be provided between the embedded layer substrate 100 and the chip stack. The second underfill layer 806 may fill a space between the embedded layer substrate 100 and the base semiconductor chip 810 and may surround the first connection terminal 814.

[0106] The second semiconductor chip 700 may be disposed on the embedded layer substrate 100. The second semiconductor chip 700 may be spaced apart from the chip stack. The second semiconductor chip 700 may be thicker than the first semiconductor chip 820. The second semiconductor chip 700 may include a semiconductor material (e.g., silicon (Si)). The second semiconductor chip 700 may include a second circuit layer 702. The second circuit layer 702 may include logic circuits. In other words, the second semiconductor chip 700 may be a logic chip. The bottom surface of the second semiconductor chip 700 may be an active surface, and the top surface of the second semiconductor chip 700 may be a passive surface. Second connection terminals 704 may be disposed on the bottom surface of the second semiconductor chip 700. The second connection terminals 704 may be electrically connected to the input / output circuits (e.g., logic circuits) of the second circuit layer 702.

[0107] The second semiconductor chip 700 may be mounted on the embedded layer substrate 100. For example, the second semiconductor chip 700 may be bonded to the upper substrate pad 114 of the embedded layer substrate 100 through the second connection terminals 704. The second connection terminals 704 may be disposed between the upper substrate pad 114 of the embedded layer substrate 100 and the second circuit layer 702.

[0108] A third underfill layer 706 may be disposed between the embedded layer substrate 100 and the second semiconductor chip 700. The third underfill layer 706 may fill the space between the embedded layer substrate 100 and the second semiconductor chip 700 and may surround the second connection terminals 704.

[0109] A second molding layer 900 may be disposed on the embedded layer substrate 100. The second molding layer 900 may cover the top surface of the embedded layer substrate 100. The second molding layer 900 may surround the chip stack and the second semiconductor chip 700. The second molding layer 900 may include an insulating material. For example, the second molding layer 900 may include an epoxy molding compound (EMC).

[0110] In a wiring substrate according to an embodiment of the inventive concept and a semiconductor package including the wiring substrate, a first power pattern and a ground pad may be provided to form a microstrip structure, or a ground pad, a first power pattern, and a third ground pattern may be provided to form a strip line structure. Accordingly, interference (e.g., noise) signals generated from the first power pattern may be absorbed by the ground pad. Accordingly, it is possible to limit and / or prevent interference signals generated from the first power pattern from affecting signal pads or other patterns (e.g., a first signal pattern) in the first substrate wiring layer. That is, the wiring substrate and the semiconductor package having the same may have improved electrical characteristics.

[0111] In addition, even when the second signal pattern is disposed on the first power pattern, the ground pad can absorb the interference signal generated from the first power pattern. Therefore, the second signal pattern is not affected by the interference signal. Accordingly, even when the first power pattern is set to cross the region between the signal pads or the first signal patterns or is set to overlap with the second signal pattern, the interference signal does not affect the operation signals of the signal pads, the first signal pattern, and the second signal pattern. Therefore, it is not necessary to dispose the first power pattern in the edge region of the wiring substrate to bypass the signal pads, the first signal pattern, and the second signal pattern. In other words, the electrical characteristics of the wiring substrate can be improved, the degree of freedom in arranging the wiring structure in the wiring substrate can be increased, and the sizes of the wiring substrate and the semiconductor package can be reduced.

[0112] One or more of the elements disclosed above may include or be implemented in the following: a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0113] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A wiring substrate, comprising: a first substrate wiring layer, the first substrate wiring layer comprising a first insulation pattern and a power pattern located in the first insulation pattern; a second substrate wiring layer, the second substrate wiring layer being located on the first substrate wiring layer and comprising a second insulating pattern and a first ground pattern located in the second insulating pattern; a third substrate wiring layer, the third substrate wiring layer being located on the second substrate wiring layer and comprising a third insulation pattern and a first signal pattern located in the third insulation pattern; as well as A pad layer, the pad layer covers the bottom surface of the first substrate wiring layer, includes a protective layer and also includes a signal pad and a ground pad located in the protective layer, wherein, The ground pad is located between the signal pads. The power pattern vertically overlaps the ground pad, The first ground pattern vertically overlaps both the ground pad and the power pattern, and The first signal pattern is located on the first ground pattern.

2. The wiring substrate according to claim 1, wherein: The first substrate wiring layer further includes a second ground pattern, The power pattern is located between the second ground patterns, and The second ground pattern is spaced apart from the power pattern, and the first insulation pattern is located between the second ground pattern and the power pattern.

3. The wiring substrate according to claim 2, wherein: The first substrate wiring layer further includes a second signal pattern, and At least one of the second ground patterns is located between the power pattern and the second signal pattern.

4. The wiring substrate according to claim 1, wherein: The power pattern vertically overlaps the first signal pattern, and The first ground pattern crosses a region between the first signal pattern and the power pattern.

5. The wiring substrate according to claim 1, wherein A horizontal width of the power pattern on the ground pad is 0.8 to 1.2 times a horizontal width of the ground pad.

6. The wiring substrate according to claim 1, wherein When viewed in a plan view, the power pattern is located between the signal pads.

7. The wiring substrate according to claim 1, wherein: The ground pad is located on the central area of ​​the pad layer, The signal pad is located on an edge region of the pad layer, and The edge region of the pad layer surrounds the central region of the pad layer.

8. The wiring substrate according to claim 1, wherein A side surface of the power pattern on the ground pad in the width direction is located on the ground pad.

9. A wiring substrate, comprising: Main layer; A ground pad and a signal pad, wherein the ground pad and the signal pad are located on the bottom surface of the main body layer; a first substrate wiring layer, the first substrate wiring layer being located in the main body layer; as well as a second substrate wiring layer, the second substrate wiring layer being located in the main body layer and on the first substrate wiring layer, wherein: The first substrate wiring layer includes a first signal pattern and a power pattern, When viewed in a plan view, the power pattern is arranged between the first signal patterns, The power pattern is arranged on the ground pad, The second substrate wiring layer includes a second signal pattern, and The second signal pattern is located on the power pattern.

10. The wiring substrate according to claim 9, further comprising: a third substrate wiring layer, the third substrate wiring layer being located in the main body layer and between the first substrate wiring layer and the second substrate wiring layer, wherein: The third substrate wiring layer includes a first ground pattern, and The first ground pattern crosses a region between the power pattern and the second signal pattern.

11. The wiring substrate according to claim 9, wherein: A side surface of the power pattern in a width direction is located on the ground pad.

12. The wiring substrate according to claim 9, wherein: The first substrate wiring layer further includes a ground pattern, and The ground pattern is located between the power pattern and the first signal pattern.

13. The wiring substrate according to claim 9, wherein: A horizontal width of the power pattern on the ground pad is 0.8 to 1.2 times a horizontal width of the ground pad.

14. The wiring substrate according to claim 9, wherein: When viewed in a plan view, the ground pad is located between the signal pads.

15. The wiring substrate according to claim 9, wherein At least a portion of the second signal pattern overlaps with the power pattern.

16. A semiconductor package, comprising: substrate; a semiconductor chip, wherein the semiconductor chip is located on the substrate; as well as a molding layer, the molding layer being located on the substrate and surrounding the semiconductor chip, wherein: The substrate includes a body layer, a ground pad and a signal pad located on a bottom surface of the body layer, a first signal pattern located in the body layer, and a power pattern located in the body layer, The power pattern is located between the ground pad and the first signal pattern, The power pattern is located on the ground pad, The first signal pattern is located on the power pattern, and A horizontal width of the power pattern on the ground pad is 0.8 to 1.2 times a horizontal width of the ground pad.

17. The semiconductor package according to claim 16, further comprising: a first ground pattern, the first ground pattern being located in the body layer and crossing a region between the power pattern and the first signal pattern, wherein A width of the power pattern is smaller than a width of the first ground pattern.

18. The semiconductor package according to claim 16, further comprising: a second ground pattern, the second ground pattern being located in the body layer and at the same vertical height as the power pattern, wherein The power pattern is located between the second ground patterns.

19. The semiconductor package according to claim 16, wherein: A side surface of the power pattern on the ground pad in the width direction is located on the ground pad.

20. The semiconductor package according to claim 16, further comprising: a second signal pattern, the second signal pattern being located in the body layer and at the same vertical height as the power pattern, wherein The power pattern is arranged between the second signal patterns.

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