High voltage isolation device

Abstract

The invention relates to a high voltage isolation device. An integrated circuit (IC) (100) including a capacitive HV isolation component (102) and a method of manufacturing the same are disclosed herein. A SiN bilayer (177) is disposed directly underneath a top electrode (105) of the HV isolation component (102), where the SiN bilayer (177) includes a top layer (177A) having a first RI formed over an underlying SiN layer (177B) having a second RI greater than the first RI.

Description

Technical Field

[0001] The disclosed embodiments generally relate to the field of integrated circuits (ICs) and IC fabrication. More specifically, but not exclusively, the disclosed embodiments relate to ICs that include high-voltage isolation devices. Background Art

[0002] Current isolation is the principle of isolating functional parts of an electrical system or integrated circuit to prevent current flow while energy or information can still be exchanged between the parts by other means such as capacitance, inductance, or electromagnetic waves or by optical, acoustic, or mechanical means. Current isolation is typically used in cases where two or more circuits communicate but their ground or reference nodes can be at different potentials. This is an effective way to break ground loops by preventing unwanted current from flowing between two units sharing a reference conductor. Current isolation is also used for safety reasons to prevent current from accidentally reaching ground through a human body.

[0003] An isolator is a device designed to minimize direct current (DC) and unwanted transient currents between two systems or circuits while allowing data and power transfer between the two systems or circuits. In most applications, the isolator also acts as a barrier against high voltages in addition to allowing the systems to operate properly. Dielectric breakdown is a critical issue in cases where capacitive elements are used as isolators, especially in high-voltage (HV) applications.

[0004] With the continued development in the design of integrated circuits and semiconductor fabrication, there has also been an implementation of improvements to microelectronic devices that include current isolators. Summary of the Invention

[0005] A simplified summary of the invention is presented below to provide a basic understanding of some examples of the present disclosure. This summary of the invention is not an extensive overview of the examples and is neither intended to identify key or important elements of the examples nor to depict their scope. Indeed, the primary purpose of the summary of the invention is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description presented in the subsequent parts below.

[0006] Examples of the present disclosure relate to an IC (also referred to as an electronic device, an IC device, a semiconductor device, etc.) including a capacitive HV isolation component, where the defect level can be minimized while continuing to maintain the breakdown performance of the device. In various examples, a silicon nitride (SiN) bilayer is directly disposed under the top electrode of the HV isolation component to ensure sufficient HV isolation, where the SiN bilayer includes a top SiN layer having suitable refractive index (RI) characteristics different from the RI characteristics of the underlying SiN layer, and the differential RI characteristics of the top SiN layer contribute to reducing processing defects that can be caused by certain back-end-of-line (BEOL) stages of the manufacturing process.

[0007] In one example, an IC device is disclosed that includes, among other things: a semiconductor substrate; a metal bottom plate above the semiconductor substrate; a metal top plate above the metal bottom plate; and a dielectric structure disposed between the top plate and the bottom plate, the dielectric structure including a silicon nitride (SiN) bilayer under the top plate, where the SiN bilayer includes a first SiN layer directly contacting the top plate and having a first refractive index (RI), and a second SiN layer under the first SiN layer and having a second RI greater than the first RI. In some examples, the first SiN layer may have an RI of about 2.0 to 2.15, while the second SiN layer may have an RI of about 2.2 to 2.4. In some examples, the first SiN layer may have a thickness less than about 20% of the total thickness of the SiN bilayer.

[0008] In one example, a method of manufacturing an IC device including an isolation component is disclosed. The method may include, among other things: forming a bottom electrode of the isolation component above a semiconductor substrate; and forming a dielectric structure between the bottom electrode and the top electrode of the isolation component, where the dielectric structure includes a SiN bilayer under the top electrode, the SiN bilayer including a first SiN layer directly contacting the top electrode and having a first RI, and a second SiN layer under the first SiN layer and having a second RI greater than the first RI. In some examples, the method may further include forming an isolation break region in a portion of the SiN bilayer that extends beyond the top electrode. In some examples, the SiN bilayer is formed above a nitrogen oxide layer (e.g., a SiON layer) of a main dielectric component overlying the dielectric structure, the main dielectric component overlying the bottom electrode and having a thickness of at least 4 micrometers (μm). In some examples, the top electrode may be formed by the topmost metal layer of a multi-layer metal interconnect formed above the semiconductor substrate. In some examples, the bottom electrode may be formed by an intermediate metal layer of a multi-layer metal interconnect formed above the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the figures of the drawings, embodiments of the present disclosure are shown by way of example and not limitation. Different references to "an" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic is practicable in connection with other embodiments whether or not explicitly described.

[0010] To illustrate one or more exemplary embodiments of the present disclosure, the drawings are incorporated into and form a part of the specification. The various advantages and features of the present disclosure will be understood from the following detailed description, which is made in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0011] Figure 1A and 1B respectively show a cross-sectional and a top plan view of an electronic device in accordance with the principles of the present disclosure, including a capacitive HV isolation component implemented in a five-level metal (5LM) process;

[0012] Figures 2A to 2Q showing a Figure 1A cross-sectional view of the device at progressive stages of manufacture; and

[0013] Figure 3 is a flow chart of an exemplary IC manufacturing method in accordance with the present disclosure. DETAILED DESCRIPTION

[0014] Examples of the present disclosure are described with reference to the drawings, in which like reference numerals generally refer to like elements. The figures are not drawn to scale and are provided only to illustrate examples. Many specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure an understanding of the examples. Accordingly, the examples of the present disclosure may be practiced without such specific components.

[0015] Additionally, terms such as "coupled" and "connected" and their derivatives may be used in the following detailed description, the appended claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. "Connected" may be used to indicate the establishment of communication between two or more elements that are coupled to each other, i.e., a communication relationship. Additionally, in one or more examples set forth herein, generally, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, then the element, component, or module can be configured to perform the function.

[0016] Without limitation, examples of high-voltage isolation devices and methods of manufacturing the high-voltage isolation devices will be described below in the context of capacitive isolation devices in the interconnect levels of integrated circuits formed during back-end-of-line (BEOL) manufacturing.

[0017] Circuit isolation (also known as current isolation) can prevent direct current (DC) and unwanted alternating current (AC) signals from being transferred from one area or circuit of a system to another area or circuit that needs to be protected, as previously noted. In its use, isolation can maintain the signal integrity of a system or circuit by preventing the propagation of high-frequency noise, protecting sensitive circuit systems from high-voltage surges and spikes, and providing safety for human operators.

[0018] High voltages present in factory automation, motor drives, grid infrastructure, and electric vehicles (EVs), among others, can be in the hundreds or even thousands of volts. Current isolation helps address the challenge of designing a safe human-machine interface in the presence of such high voltages.

[0019] In some exemplary embodiments, a current isolator can be created by forming parallel plate capacitors using electrodes in different metallization layers of an integrated circuit, such as different metallization layers in the BEOL interconnect levels. The dielectric layers of the BEOL levels separate the electrodes to form the capacitors. For HV applications, the thickness and / or the number of BEOL dielectric layers can be increased to provide a higher breakdown voltage. In some examples, a composite dielectric layer including silicon nitride (SiN) and silicon oxynitride (SiON) can be disposed under the top electrode for improving HV isolation performance.

[0020] Chemical mechanical polishing / planarization (CMP) (including electrochemical mechanical polishing (eCMP)) can be used to smooth or planarize a material layer before forming a via through the material layer. In some instances, the planarization layer includes a composite SiON / SiN layer formed in the fabrication of HV isolation devices. The CMP process uses an abrasive slurry that typically has a diameter larger than the wafer, as well as a polishing pad and a retainer ring. The pad and the wafer are pressed together by a dynamic polishing head and held in place by the retainer ring. The dynamic polishing head rotates with different axes of rotation, which removes material from the surface of the wafer and tends to even out any irregular surface shape, thereby making the wafer surface planar.

[0021] CMP, a tribochemical and electrochemical process based on the synergistic action between various mechanical and electrochemical mechanisms, uses a variety of slurry materials and electrolytes for polishing and planarization. The slurry typically contains particles composed of, for example, alumina, silica, and / or cerium oxide (cerium dioxide) suspended in an acidic or alkaline solution. During the manufacturing process, the suspended particles can precipitate and form so-called large particle counts, which may be difficult to remove in the post-CMP cleaning process due to the complex interactions of the different materials typically present in multiple phases (such as the gas phase, liquid phase, and / or solid phase). Due to the difficulty in removing the particulate matter generated and / or introduced in CMP, any trapped particulate matter can increase the risk of defectivity in the device, which may compromise the HV breakdown performance of the device.

[0022] Examples of the present disclosure recognize the foregoing challenges and thus provide a technical solution for manufacturing IC devices (including those implementing capacitive HV isolation components) in which the defectivity associated with CMP can be advantageously reduced before or during via formation without significantly degrading the HV breakdown / isolation performance of the device. Depending on the application, examples herein include forming a SiN bilayer directly under the top electrode of a capacitive HV component, where the upper portion of the SiN bilayer includes a nitride material having a predetermined refractive index (RI) characteristic configured to enhance protection against defect formation, as will be further elaborated in detail below. While it is expected that such examples and variations will reduce manufacturing defects that may otherwise reduce yield, reliability, or electrical performance, no specific result is a requirement of the present disclosure unless explicitly recited in a particular claim.

[0023] Turning Figure 1A to, according to some examples herein, an electronic device 100 such as an IC device is shown in cross-sectional view, where a capacitive HV isolation component may be provided. Corresponding Figure 1B is shown in a top plan view taken along a horizontal plane such as the X'-X" plane, which is disposed Figure 1AAt the top metallization level such as MET5 shown. The electronic device 100 includes a semiconductor substrate 101, and a capacitor 102 and an optional transistor 103 that can be used as a current HV isolation device are formed above the semiconductor substrate. Depending on the application, in some instances, the semiconductor substrate 101 may mainly include appropriately doped silicon, but other semiconductor materials such as Ge, SiGe, GaAs, SiC, GaN, other Group III-V materials, etc. may be used in some embodiments, where in some arrangements, one or more epitaxial layers or single crystal layers may be formed or provided in certain regions of the semiconductor substrate 101.

[0024] The capacitor 102 includes a first electrode 104 and a second electrode 105. Without limitation, implication, or otherwise, the first electrode 104 may be referred to as the bottom plate / electrode or the lower plate / electrode 104, and the second electrode 105 may be referred to as the top plate / electrode or the upper plate / electrode 105. In various instances, the top plate 105 and the bottom plate 104 are approximately the same size and shape, but for the purposes of the present disclosure, this is not a necessary requirement. Additionally, in an exemplary embodiment, for example, in the case where there is or is not a varying amount of overlap between the two plates, the bottom plate 104 may be directly disposed between the top plate 105 and the substrate 101 along the surface normal. The top plate 105 may be connected to a high voltage circuit node, and in some arrangements, the bottom plate 104 and the transistor 103 may be connected to a low voltage circuit node.

[0025] In some instances, the bottom plate 104 and / or the top plate 105 may have a minimum length along the longest axis of about 30 μm. Similarly, the bottom plate 104 and / or the top plate 105 may each have a minimum length along the orthogonal shortest axis of about 30 μm. In some instances, each of the bottom plate 104 and the top plate 105 may have an aspect ratio (e.g., the length of the longest axis divided by the length of the orthogonal shortest axis) in the range of about one to about five. The plates 104 and 105 are not limited to any particular shape and may include a variety of geometries, such as square, circular, oval, elliptical, rectangular, egg-shaped, coil / snake-shaped, racetrack, oblong, trapezoidal, rhomboid, regular or irregular polygon, etc. In some other instances, the plates 104 and 105 may have a minimum lateral width (parallel to the surface of the substrate 101) sufficient to facilitate the formation of wire bonds (e.g., the bond 197) relative to the top plate 105 in order to provide connectivity to an external circuit system (not shown in this figure). Such a minimum width may depend on the wire bonding technology and may be about 80 μm without any limitation. In one non-limiting example, the plates 104 and 105 each have a short axis length of about 120 μm and a long axis length of about 160 μm. In another non-limiting example, the plates 104 and 105 both have a circular shape with a diameter of about 100 μm. In some instances, one of the bottom plate 104 and the top plate 105 may be implemented as multiple plates, such as two plates. Thus, in one non-limiting example, the bottom plate 104 may be a single continuous metal plate, while the top plate 105 may be two non-continuous metal plates. In such instances, the two or more plates do not need to be the same shape or have the same area.

[0026] Figure 1A Examples of show a five-level metal (5LM) device 100, but are not limited thereto. Thus, the device 100 includes five metal levels, designated MET1 to MET5. Each metal level includes metal features within the corresponding intermetal dielectric (IMD) layers IMD1 to IMD5. Interlayer dielectric (ILD) layers are located between each IMD layer such that in Figure 1AIn the illustrative example, there are four dielectric layers ILD1 to ILD4. A pre-metal dielectric (PMD) layer 114, which may include one or more (sub)layers, is located between the IMD1 level and the substrate 101. A passivation / protective overcoat (PO) layer, which includes one or more (sub)layers, overlies the top metal layer MET5. In some arrangements, the PMD layer 114 may be composed of a material that serves as a penetration barrier for various impurities generated by one or more CMP or other processes that can be used to fabricate the various MET layers, and of via interconnects that can be used to provide electrical connectivity between two or more MET layers disposed at different levels. Depending on the implementation, exemplary PMD materials may include low-pressure tetraethyl orthosilicate glass (LP-TEOS), Si-rich (SR) oxides, plasma-enhanced (PE) oxynitrides, PE nitrides, PE-TEOS films, etc., and may be doped with fluorine or phosphorus.

[0027] Optional isolation structures 106, such as a shallow trench isolation (STI) structure, may be disposed between the PMD layer 114 (e.g., including (sub)layers 112, 115) and the substrate 101. In some instances, the isolation structure 106 may be configured to reduce the capacitive coupling between the bottom plate 104 and the substrate 101. In other instances not shown, the isolation structure 106 (if present) may include one or more doped well regions that may provide junction isolation between the bottom plate 104 and the substrate 101. As Figure 1A depicted, the bottom plate 104 may be formed of a metal structure disposed at the MET2 level of the illustrated 5LM metal interconnect example, but in other instances may be located at another metal level. The level at which the bottom plate 104 is located may be selected, in part, based on design considerations (e.g., the desired isolation of the bottom plate 104 from the substrate 101, the expected capacitive coupling to the top plate 105, etc.).

[0028] The plates 104 and 105 may be composed of any suitable metal. The examples described herein may describe the plates 104 and 105 as being formed of aluminum (Al), but other metal interconnect systems, such as copper (Cu) or gold (Au), may be used in additional and / or alternative arrangements without undue experimentation. The top plate 105 may be configured to receive a high-voltage signal, such as via a wire ball-bonded to the top plate 105. The high-voltage signal may be received from a high-voltage source to which the device 100 is connected (e.g., another IC, a motor, etc. operating in a high-voltage domain) to provide data transmission or electronic functions, such as monitoring or control. Depending on the implementation, for the purposes of some examples herein, "high voltage" may refer to a static or RMS voltage of about 100 V or greater, and "low voltage" may refer to a static or RMS voltage of about 20 V or less, but is not limited thereto.

[0029] The top plate 105 is connected, for example, at Figure 1AILD1 to ILD4 and one or more intervening dielectric layers such as corresponding IMD1 to IMD4 in the illustrated arrangement are capacitively coupled to the bottom plate 104. The coupling can induce a weakened electrical signal on the bottom plate 104 corresponding to the high-voltage signal present at the top plate 105. The weakened signal at the bottom plate 104 can be coupled to another electronic device on another semiconductor substrate or can be routed to an electronic device located on the same substrate, such as transistor 103. In some instances, plates 104 and 105 can be located between via stacks described further below that are connected to the substrate 101. The substrate 101 can provide a ground reference for the via stacks, such that the via stacks can provide a guard ring 109 that serves as part of a Faraday cage capable of terminating or otherwise containing the electric field lines associated with the plates 104 and / or 105.

[0030] For the purposes of some examples of the present disclosure, three types of silica dielectric materials are described. Two types can be produced by a plasma-enhanced chemical vapor deposition (PECVD) process in a capacitively coupled plasma reactor using a tetraethylorthosilicate (TEOS) precursor. These dielectrics are referred to herein as "PE-TEOS", where the first type of PE-TEOS is "high-stress" PE-TEOS and the second type of PE-TEOS is "low-stress" PE-TEOS, but is not limited thereto. In a non-limiting example, the "high-stress" PE-TEOS process can be configured to produce an SiO 2 layer having a compressive stress of about 120 megapascals (MPa), while the "low-stress" PE-TEOS process can be configured to produce an SiO 2 layer having a compressive stress of about 20 MPa. The third type of silica can be produced by using a high-density plasma in an inductively coupled reactor and is referred to as "HDP oxide", but is not limited thereto. In some arrangements, HDP oxide and / or high-stress PE-TEOS can be used as the dielectric very close to or in contact with the plates 104 and 105, while one or more of the dielectric layers between the plates 104 and 105 contain low-stress PE-TEOS to reduce the effect / degree of wafer bow. Additional details regarding the formation of PE-TEOS and HDP oxide layers that can be implemented in some examples of the present disclosure can be found in U.S. Patent No. 11,495,658, which is incorporated herein by reference for all purposes.

[0031] Continuing to refer Figure 1AIn an example, the PMD layer 114 is shown as a composite layer including layers 112 and 115, where a phosphorous-doped silicate glass (PSG) material is used to form layer 112 and a high-stress PE-TEOS material is used to form layer 115, each having a suitable thickness depending on the implementation. In some other examples, the PMD layer 114 may be undoped and formed of a single dielectric type. The specific selection of the PMD layer material may depend on, for example, the type and function of the transistors included in the device 100. In some arrangements, the IMD1 layer may include an HDP oxide sublayer 121 and a high-stress PE-TEOS sublayer 127. Such a configuration may be created by first depositing the HDP oxide sublayer 121 over the MET1 features, where the MET1 features create a surface profile in the HDP oxide sublayer 121. As used herein, the term "surface profile" may be defined as a deviation of the top surface of a material layer from flatness of at least 10% of the layer thickness within a lateral distance three times the layer thickness. The high-stress PE-TEOS sublayer 127 of the IMD1 is formed over the HDP oxide sublayer 121 and planarized to create a suitable surface for subsequent processing, as will be further elaborated below. Subsequently, a high-stress PE-TEOS layer 130 is formed over the planarized surface of the high-stress PE-TEOS sublayer 127 as part of the ILD1.

[0032] In the example shown, the floor 104 is formed in the MET2 level that is formed over the high-stress PE-TEOS sublayer 130, where an HDP oxide layer 139 is formed as part of the IMD2 layer over the floor 104. Thus, the floor 104 is bounded by HDP oxide on the top and side surfaces and by high-stress PE-TEOS on the bottom surface. The floor 104 and the top plate 105 are spaced apart by a dielectric stack structure including portions of various ILD and IMD layers or portions formed of various ILD and IMD layers, where the various ILD and IMD layers may include PE-TEOS and / or HDP oxide materials, and where a silicon nitride (SiN) bilayer forming a portion of the dielectric stack structure may be formed directly under the top plate 105 for purposes of this disclosure, as will be further elaborated below.

[0033] In the example shown, portions of the ILD2, IMD3, ILD3, IMD4, and ILD4 layers are used as part of a vertical stack structure of dielectric disposed between the floor 104 and the top plate 105 (not shown) Figure 1A(Specifically marked with reference numerals in the drawings). In some arrangements, the IMD2, IMD3, and IMD4 layers or levels may each include corresponding PE-TEOS layers 141, 156, 171. The top plate 105 may be at least partially located within the IMD5 layer, and the IMD5 layer includes an HDP oxide layer 190, where the HDP oxide layer 190 covers or touches the sidewalls of the top plate 105 and a portion of the top surface, such that only the opening 199 formed for wire bonding is exposed. In a similar manner, a TEOS layer 193 having an opening corresponding to the wire bonding opening of the HDP oxide layer 190 may be formed above the top plate. A suitable PO layer 196 may be formed to cover the remaining portion of the TEOS layer 193 of the IMD5 level. Additionally, in some instances, the PE-TEOS layer 171 of IMD4 is covered by a SiN bilayer 177 and a SiON layer 174 to enhance the HV breakdown performance of the electronic device 100.

[0034] In various examples of the present disclosure, the SiN bilayer 177 may be formed as a composite bilayer having a first SiN layer 177A (also referred to as the top or upper SiN layer), the first SiN layer having a low refractive index (RI) range, in contact with and directly below the top plate 105. The upper SiN layer 177A having a low RI relative to the underlying second SiN layer 177B (also referred to as the bottom or lower SiN layer) may be provided to reduce the potential defect degree that may be caused by the upper level via processing during CMP, as described below with reference to Figures 2A to 2Q the cross-sectional view of. To maintain the desired HV breakdown performance (which requires a SiN layer with a relatively high RI value in some instances), according to the teachings herein, a second SiN layer 177B having a suitable RI and thickness relative to the first SiN layer 177A may be disposed above the SiON layer 174 and below the first SiN layer 177A. Thus, the first SiN layer 177A (or sublayer) may have a first RI, and the second SiN layer 177B (or sublayer) may have a second RI, where the first RI is less than the second RI, for example, less by a certain value depending on the implementation. In some arrangements, the first SiN layer 177A may have an RI in the range of about 2.0 to 2.15, and the second SiN layer 177B may have an RI in the range of about 2.2 to 2.4, but not limited thereto.

[0035] In some arrangements, the PE-TEOS layers 141, 156, 171 may be provided as low-stress layers, which may be encapsulated by other dielectric layers that effectively prevent moisture from diffusing into the dielectric stack and / or prevent moisture incorporated in the PE-TEOS layer during fabrication from significantly diffusing outwards. In other instances not shown that are configured to operate in relatively low-voltage applications where the risk of dielectric breakdown near the corners of the top plate 105 is reduced, the low-stress PE-TEOS layers may be replaced by high-stress PE-TEOS layers having a similar thickness, respectively.

[0036] In Figure 1A the instance of, oxide layers may be disposed in direct contact with one or more adjacent oxide layers. In other instances, thin layers of dissimilar dielectrics may be placed between some adjacent oxide layers. By way of illustration, a nitrogen-containing dielectric such as SiN or SiON may be placed between a low-stress PE-TEOS layer and a high-stress PE-TEOS layer, or between a low-stress PE-TEOS layer and an HDP oxide layer. The dissimilar dielectric (if used) may be a thin layer, such as from 30 nanometers (nm) to 300 nm, so as to minimize the contribution to the cumulative stress of the dielectric stack in some additional, alternative, and / or optional arrangements. Regarding Figure 1A the specific 5LM device 100 shown in, IMD1 is shown as layers 121, 127; ILD1 is shown as layer 130; IMD2 is shown as layers 139, 141; ILD2 is shown as layer 144; IMD3 is shown as layers 153, 156; ILD3 is shown as layer 159; IMD4 is shown as layers 168, 171; ILD4 is shown as the SiN bilayer 177 and the SiON layer 174; and IMD5 is shown as layers 190, 193. In some instances, an optional isolation break or notch 180 may be provided in the SiON / SiN composite layer 174 / 177 so as to enhance the lateral breakdown performance of the device 100, particularly in applications involving 1000V or higher, as set forth in U.S. Patent No. 9,299,697, which is incorporated herein by reference for all purposes. Additionally, the reference numerals 124, 136, 150, 165, and 187 respectively refer to various metal structures at the MET1 to MET5 levels. Additionally, in Figure 1A the instance of, contact vias 118 through the PMD 114 and interlayer vias 133, 147, 162, and 183 through the corresponding ILD1 to ILD4 layers are shown.

[0037] Figure 1B Shown in the Figure 1A is a top plan view of the device 100 along the plane X'-X" in the MET5 level shown previously. As Figure 1BAs shown, the HV isolation capacitor 102 can be provided with a racetrack shape or an oblong shape, where an opening 199 of a suitable size and shape is shown overlying the top plate 105 and passing through the topmost IMD sublayer (e.g., layer 190 of IMD5). A vertical cross-section along a normal plane Y'-Y" orthogonal to the horizontal plane of the device 100 (e.g., layer 190) produces a cross-sectional view, such as the view described in detail above with reference to Figure 1A the views described.

[0038] Figures 2A to 2Q Shown at a continuous manufacturing stage according to some examples Figure 1A of the device. In Figure 2A this, the substrate 101 is shown as having transistors 103 already formed, where the location of the capacitor 102 is shown for reference. As previously described, one or more isolation structures 106 can be formed in the substrate 101 relative to the capacitor 102 and other circuit components such as transistors 103. Additionally, in cases where some examples do not include transistors 103 or other circuitry, such examples illustrate an arrangement where the capacitor 102 can be referred to as a "standalone" capacitor. As previously noted, the substrate 101 can be any suitable substrate, such as semiconductive or insulating. In some examples, the substrate 101 is a silicon wafer or a portion of a silicon wafer, such as a semiconductor die, and can be doped with a suitable dopant, such as a p-type dopant.

[0039] Figure 2B Represents the stage where the PMD layer 114 has been formed. In the shown example, which is shown but not limited to this, a dielectric layer 112 is formed over the substrate 101, which projects a vertical and / or conformal surface shape over the transistors 103. The dielectric layer 112 can be a PSG layer, as previously noted. As Figure 2B shown, a dielectric layer 115 of high-stress PE-TEOS can be formed over the dielectric layer 112 and planarized to reduce the surface shape. In other examples, such as when the device 100 is a standalone device, an undoped dielectric can be used for the dielectric layer 112, such as high-stress PE-TEOS, and planarization can be omitted. In such examples, a SiN layer with a compressive stress of about 100 MPa can be used for layer 115.

[0040] In Figure 2CIn [description], a contact 118 (e.g., a tungsten plug) formed through dielectric layers 112 and 115 can be used to contact the substrate 101 in the region of the capacitor 102. Additional unmentioned contacts can be provided to achieve connectivity with other components of the device 100 (e.g., the source / drain regions of the transistor 103). A metal layer can be formed over the dielectric layer 115 and patterned to form a metal structure 124 connected to the contact 118, and an unmentioned interconnect connected to the source / drain contacts of the transistor 103. The exemplary metal structure 124 can be used as a landing pad for subsequent vias in a corresponding via stack, as shown in Figure 1A or can form a closed loop with corresponding other metal structures in the metal structure 124. The metal layer forming the metal structure 124 can be an Al layer, but is not limited thereto, and patterning can include baseline lithography and metal etching processes.

[0041] Figure 2D Figure [number] shows the device 100 partially formed after the deposition of the first IMD layer. An HDP oxide layer 121 with an appropriate thickness can be initially formed. In some instances, HDP oxide can be preferred when the spacing between the metal structure 124 or other metal features outside the view of the figure is small enough such that PE-TEOS may not effectively fill the space. In other instances with more generous spacing, PE-TEOS can alternatively be used. In the shown instance, a dielectric layer 127 of high stress PE-TEOS is formed over the HDP oxide layer 121. The surface profile associated with the metal structure 124 can extend to the surface of the PE-TEOS layer 127, which can be planarized using a suitable process such as CMP to remove a portion of the PE-TEOS layer 127, thereby reducing the surface profile. Figure 2E Figure [number] shows the device 100 after the planarization of the PE-TEOS layer 127 and after the deposition of a PE-TEOS layer 130 on the planarized surface. The HDP oxide layer 121 and the PE-TEOS layer 127 are designated as IMD1, and as previously noted, the PE-TEOS layer 130 is designated as ILD1. In another instance not shown, a PE-TEOS layer 127 can be deposited with a sufficient thickness to serve as both the upper portion of the IMD1 level and the ILD1 level, where the surface of the single PE-TEOS layer is then planarized. This alternative embodiment can be appropriate when the metal structure 124 has a maximum thickness of, for example, about 500 nm.

[0042] Figure 2FDevice 100 is shown after forming the MET2 layer over the PE-TEOS layer 130 and patterning the MET2 layer to create the baseplate 104 and the MET2 structure 136. Through-holes 133 are formed in the ILD1, for example using tungsten (W) metallurgy, to connect the MET2 structure 136 to the MET1 structure 124. Similar to the MET1 tier, the MET2 layer can be formed of Al. Depending on the implementation, the MET2 structure 136 can follow a layout similar to that of the MET1 structure 124.

[0043] Figure 2G A stage is shown where the HDP oxide layer 139 and the PE-TEOS layer 141 have been formed over the baseplate 104. The surface shape of the PE-TEOS layer 141 conforms to the underlying MET2 structure 136 and the baseplate 104. Thus, a CMP process can also be used at this stage to reduce the surface shape. Figure 2H Device 100 is shown after planarization of the PE-TEOS layer 141. The HDP oxide layer 139 and the remaining PE-TEOS layer 141 can be designated as IMD2 as previously indicated.

[0044] Figure 2I Device 100 is shown after forming the PE-TEOS layer 144, the HDP oxide layer 153, and the PE-TEOS layer 156 over the planarized surface, where the MET3 structure 150 and the associated vias 147 to the lower-tier MET2 structure 136 can be formed using suitable metallization processes and metallurgies (such as AL, Cu, W, etc.). The PE-TEOS layer 144 is designated as ILD2, and the HDP oxide layer 153 and the PE-TEOS layer 156 are designated as IMD3. Similar to the formation of the lower tier, the surface of the PE-TEOS layer 156 can be planarized. The sequence of manufacturing steps for producing the ILD2 and IMD3, as well as the vias 147 and the MET3 structure 150, can be repeated as needed to provide the desired distance between the baseplate 104 and the top plate 105. Appropriate adjustments can be made to accommodate the metal spacing and thickness, as well as any requirements imposed by the baseline and / or qualified processes in a particular manufacturing facility.

[0045] In the example shown, another via and metal tier are formed, as Figure 2J shown. In this example, the PE-TEOS layer 159 is formed over the planarized PE-TEOS layer 156, followed by the HDP oxide layer 168 and another PE-TEOS layer 171. The MET4 structure 165 is located within the HDP oxide layer 168, where the via 162 through the layer 159 is formed to connect the MET4 structure to the MET3 structure. As previously indicated, the PE-TEOS layer 159 is designated as ILD3, and the HDP oxide layer 168 and the low-stress dielectric layer 171 are designated as IMD4.

[0046] In Figure 2K , the SiON layer 174 is formed above the PE-TEOS layer 171 as part of the composite dielectric layer to be located under the top electrode for improving the HV breakdown performance of the capacitor structure to be formed. In some arrangements, the thickness and compressive stress of the SiON layer 174 can be matched, balanced, or otherwise optimized relative to and / or in view of the subsequent formation of the SiN bilayer with a modulated RI property, so as to achieve a composite SiON / SiN layer with the desired thermomechanical properties and HV breakdown performance, while avoiding or reducing the degree of defects that might otherwise occur when forming the vias required for the next-level metallization (e.g., MET5 metallization). Depending on the implementation, various techniques and processes can be used to form the SiON layer using precursors and reactants such as silane (SiH 4 ), hexamethyldisilazane (HMDS), ammonia gas (NH 3 ), nitrous oxide (N 2 O), oxygen gas (O 2 ), etc., such as thermal CVD or plasma-enhanced CVD, thermal atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD). Thereafter, an SiN bilayer 177 including a lower SiN layer 177B and an upper SiN layer 177A can be formed, resulting in a structure as shown in Figure 2L . As previously pointed out, the upper SiN layer 177A and the lower SiN layer 177B can each have corresponding RI properties, for example, the upper SiN layer 177A has a lower RI than the lower SiN layer 177B. Similar to the formation of the SiON layer 174, various techniques and processes can be used to form the SiN layers 177A, 177B that can be appropriately varied or modulated to achieve the desired RI properties. For example, the silane gas flow in the deposition process using SiH 4 and NH 3 can be changed such that a higher silane flow rate (e.g., about 1000 standard cubic centimeters per minute (sccm)) can be used to form an SiN film with a higher RI value, while a lower silane flow rate (e.g., about 600 sccm) can be used to form an SiN film with a lower RI value. Additionally, to match or optimize the overall compressive stress of the composite SiON / SiN structure, a high-frequency radio frequency (HFRF) plasma at 800 W to 1200 W and having a pressure in the range of about 400 pascals (Pa) to 700 Pa can be used in some arrangements. Without limitation, the SiON layer 174 can have a compressive stress of approximately zero, while in an exemplary implementation, the SiN bilayer 177 can have a compressive stress of about 100 MPa.

[0047] The SiN bilayer 177 may have a desired total target thickness, e.g., about 500 nm to 800 nm, depending on the HV application, where the thickness of the upper SiN layer 177A may be less than a fraction of one less than the thickness of the lower SiN layer 177B, e.g., about one-fifth (20%) or less. Since it is expected that the upper SiN layer 177A (with a lower RI) will be lost or sacrificed due to subsequent via CMP etching, a thicker upper SiN layer 177A may be initially deposited over the lower SiN layer 177B having the target thickness and the desired high RI characteristics. The via 183 may be formed through the composite SiON / SiN layers 174 / 177, where a metal capping layer 202 may be present, while filling the via with a suitable metal (e.g., W), as Figure 2M shown therein. A CMP / eCMP process may be used to remove the capping layer 202 and to polish the upper SiN layer 177A to the target thickness, resulting in a structure as Figure 2N shown therein.

[0048] In a BEOL process flow that includes a high RI SiN film formed directly under the top electrode of an HV isolation device, the via CMP process typically lands on the polished high RI SiN film. Since CMP (including eCMP) is generally the previously noted unclean process, various types of particulate matter, metal whiskers, metal strings, particulate metal particles, CMP slurry materials (such as aggregates, coalescences, and gels), debris generated by the normal wear and tear of equipment components (such as micro flakes, spots, fragments, etc.) (which may be broadly referred to herein as "contaminants" or "surface defects") can remain on the surface of the high RI SiN layer, even after an aggressive CMP post-cleaning process. In cases where the via is used to provide top-level connectivity, such as providing an electrical conduction path between the topmost MET level and a lower MET level, contaminants on the SiN surface can remain encapsulated by subsequent conductive and / or dielectric layers, thereby increasing the risk of defectivity, which can adversely affect the HV breakdown performance of the device. The inventors of the present disclosure have found that the surface defect level associated with CMP and the range of RI values of the SiN film on which the CMP process is performed are directly related, for example, showing a positive correlation between the two variables. It is assumed herein that an increased RI of the SiN film affects the zeta potential associated with the contaminants. The zeta potential is the net electrokinetic potential generated by van der Waals attractive forces and electrical double-layer repulsive forces, which can be established in a system containing particulate matter with a charged surface, where the charged particulate matter can be in a suspended state and / or on the surface of the material. At a sufficient zeta potential (which can be, for example, on the order of several millivolts in some instances), the particulate matter can form bonds with each other and with the material surface based on phenomena such as flocculation and / or gelation, which can make the particulate matter more resistant to the cleaning process. Since the high RI value of the SiN film is directly related to the defectivity level (e.g., in terms of surface defects, particle count, and / or defects per million parts (dppm)), the BEOL process for forming a composite SiON / SiN layer in an HV isolation device can be appropriately characterized and / or qualified such that a SiN layer with a sufficiently low RI value can be process-designed for a specific application that requires a defectivity level not exceeding a given threshold level. Since HV isolation performance requires a high RI SiN layer in some embodiments, according to the examples herein, a combination of SiN materials with different RI characteristics can be optimized and provided as a bilayer structure, where the low RI SiN material can form a thin upper layer for attenuating the CMP-based defectivity level (due to the expected reduction in zeta potential interactions, which can also contribute to better surface potential control above the layer in an electrolytic solution), while the high RI SiN material can form a lower layer with sufficient thickness to provide acceptable HV isolation performance.For a given amount of etch, e.g., a cover layer of 100 nm to 150 nm, the CMP / eCMP process can be configured to have a suitable material removal rate endpoint for landing on the low RI SiN layer, thereby reducing the incidence of surface defectivity levels according to some examples herein. The initial thickness of the low RI SiN layer can also be selected depending on how much material can be sacrificed in CMP, the thickness of the low RI SiN layer relative to the total target thickness of the SiN bilayer, etc. In additional and / or alternative arrangements, the compressive stress of the various components of the composite SiON / SiN layer can also be optimized while balancing the defectivity level and HV isolation performance of the electronic device (e.g., device 100). Unless otherwise indicated, it should be recognized that the term "CMP" includes "eCMP" at least for the purposes of some examples herein, depending on the context.

[0049] As previously elaborated, in an exemplary arrangement, the composite SiON / SiN layers 174 / 177 can be used as the ILD4. The vias 183 (e.g., tungsten) formed within the ILD4 can be used to connect the MET4 structure 165 to the upper MET5 structure 187 that can be formed at a subsequent stage. Figure 2O Depicts a manufacturing stage in which the top plate 105 has been formed as part of the MET5 process, which can include the formation of the MET5 structure 187. In some optional examples, one or more isolation breaks or cuts 180 can be formed in the ILD4 after the formation of the top plate 105 to further improve the lateral HV breakdown performance of the device 100 as elaborated above. Figure 2P Depicts a manufacturing stage in which the optional cut 180 has been formed in the ILD4 of the device 100. In some arrangements, the optional cut 180 formed in the layers 174 and 177A / 177B can expose the underlying low stress PE-TEOS layer 171. As previously noted, such cuts 180 can be formed as described in U.S. Patent No. 9,299,697 as mentioned above, and it is expected that such cuts increase the robustness of the device 100 against dielectric breakdown between the top plate 105 and the guard ring 109 through the SiN bilayer components 177A / 177B or along the interface between the SiON layer 174 and the SiN bilayer components 177A / 177B. After the formation of the top plate 105 and optionally the cut 180, the HDP oxide layer 190 is formed over the top plate 105 and fills the cut 180, as Figure 2P shown. In Figure 2QIn [the figure], a TEOS layer 193 has been formed over and planarized on an HDP oxide layer 190, and a PO layer 196 (e.g., SiON) has been formed over the TEOS layer 193. The PO layer 196 may have a compressive stress of from about 160 MPa to about 180 MPa in some instances, but is not limited thereto. A wire bond opening (e.g., opening 199) may be formed over the top plate 105 by a suitable patterning technique for connection with a bonding wire, thereby resulting in Figure 1A the device 100 shown in [the figure].

[0050] In some instances, the high-RI and low-RI SiN layers under the top electrode 105 of the device 100 may be distinguished by ellipsometry, where in-situ and / or off-line RI measurements may be obtained for process characterization, verification, and / or statistical process quality control purposes. In some instances, the physical cross-section of the device 100 may be analyzed and reverse-engineered for distinction between the high-RI and low-RI SiN layers.

[0051] The foregoing description of the exemplary 5LM process sequence is not limited to any particular thickness of the metal and / or dielectric layers. Additionally, a similar process sequence for depositing a combined SiN layer comprising two or more SiN sub-layers having different RI values, respectively, may be provided in conjunction with any multi-layer metal interconnect system having any number of MET levels (e.g., 6 to 12 MET levels or more), where the top electrode of the isolation device is configured to be in direct contact with the low-RI SiN sub-layer.

[0052] Figure 3 is a flow chart of a method of manufacturing an IC device including an HV isolation component in accordance with some instances of the present disclosure. In one arrangement, the exemplary method 300 may begin with forming a bottom electrode of the isolation component over a semiconductor substrate, where the bottom electrode may be formed of a lower-level metal layer of a multi-layer metal interconnect (MMI) formed over the semiconductor substrate (e.g., Figures 2A to 2Q the MET2 level shown in [the figure]), as set forth at block 302. At block 304, one or more dielectric layers of the main dielectric component may be formed over the bottom electrode, the one or more dielectric layers including corresponding IMD / ILD layers associated with the MMI formation. By way of illustration, Figures 2A to 2QThe portions of IMD2, ILD2, IMD3, ILD3, and IMD4 shown may include a primary dielectric assembly overlying bottom electrode 104 in an exemplary arrangement. At block 306, a nitrogen oxide layer (e.g., including SiON) may be formed over the primary dielectric assembly. And, a SiN bilayer may be formed over the nitrogen oxide layer (block 306), where the SiN bilayer includes a first SiN layer having a first RI and a second SiN layer underlying the first SiN layer, the second SiN layer having a second RI greater than the first RI. At block 308, a metal via may be formed through the SiN bilayer and the nitrogen oxide layer, where formation of the metal via may involve a CMP process for removing a metal capping layer and at least a portion of the first SiN layer, thereby leaving a thin layer of the first SiN material over the second SiN layer. As previously elaborated, the target thicknesses and RI values of the two SiN layers of the bilayer may be optimized relative to each other to achieve an acceptable balance among the desired HV breakdown performance, reduction in defectivity, and / or compressive stress performance of the film, which may be based on process characterization for the BEOL process in IC fabrication. At block 310, the top electrode of the isolation assembly may be formed of the topmost level metal layer formed by MMI, the top electrode directly contacting the remaining first SiN layer disposed over the second SiN layer for achieving proper capacitive coupling with the bottom electrode required for HV breakdown performance.

[0053] Although various examples of the present disclosure have been described above, the examples have been presented by way of example only and not limitation. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the examples described above. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0054] For example, in the present disclosure and the following claims, unless otherwise stated and / or conversely specified, any one or more of the layers set forth herein may be formed in any number of suitable ways, such as by spin coating techniques, sputtering techniques (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. The silicon nitride may contain some oxygen, but not so much as to cause the dielectric constant of the material to be significantly different from that of high-purity silicon nitride.

[0055] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowcharts. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be performed substantially simultaneously or the boxes may sometimes be performed in the reverse order. Further, the functions of a given box of a flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes of a flowchart and / or block diagram may be at least partially integrated. Additionally, some boxes in the flowcharts may optionally be omitted. Further, although some of the figures contain arrows on communication paths to show the primary direction of communication, it should be understood that communication may occur in a direction opposite to the depicted arrows. Finally, other boxes may be added / inserted between the boxes shown.

[0056] The order or sequence of actions, steps, functions, components, or boxes shown in any of the flowcharts and / or block diagrams depicted in the figures of the present disclosure may be modified, changed, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of a particular action, step, function, component, or box. Additionally, the actions, steps, functions, components, or boxes shown in a particular flowchart may be intermixed with or otherwise arranged or rearranged with the actions, steps, functions, components, or boxes shown in another flowchart so as to effect additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or required therefor.

[0057] At least some portions of the above description may include certain directional terms, such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “back,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the figures described or their illustrative elements. Since the components of some examples may be positioned in several different orientations, the directional terms are used for illustrative purposes and are in no way limiting. Similarly, references to features referred to as “first,” “second,” etc. do not indicate any particular order, importance, etc., and such references may be interchanged, depending on the context, embodiment, etc. Additionally, unless otherwise specifically indicated, the features of the examples described herein may be combined with each other.

[0058] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The specific embodiments above should not be taken to mean that any particular component, element, step, action, or function is essential such that it must be included within the scope of the claims. In the case of reciting or describing a phrase such as "at least one of A and B" or a phrase of similar import, such a phrase should be understood to mean "only A, only B, or both A and B". References to singular elements are not intended to mean "one and only one" unless explicitly stated, but rather "one or more". In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. An integrated circuit IC, comprising: Semiconductor substrate; a metal base plate above the semiconductor substrate; a metal top plate above the metal bottom plate; as well as A dielectric structure is disposed between the top plate and the bottom plate, the dielectric structure comprising a silicon nitride SiN bilayer located below the top plate, the SiN bilayer comprising a first SiN layer directly contacting the top plate and having a first refractive index RI, and a second SiN layer located below and directly contacting the first SiN layer and having a second RI greater than the first RI.

2. The IC of claim 1, wherein the first SiN layer has an RI of about 2.0 to 2.

15.

3. The IC of claim 1 , wherein the second SiN layer has an RI of about 2.2 to 2.

4.

4. The IC of claim 1 wherein the first SiN layer has a thickness less than about 20% of a total thickness of the SiN bilayer.

5. The IC of claim 1, wherein the first SiN layer has a thickness of about 50 nanometers (nm) to 100 nm.

6. The IC of claim 1 wherein the second SiN layer has a thickness of approximately 500 nm to 700 nm.

7. The IC of claim 1 wherein the SiN bilayer extends beyond the top plate.

8. The IC of claim 7 wherein the SiN bilayer includes an isolation break region in a portion extending beyond the top plate.

9. The IC of claim 1, wherein the SiN bilayer is disposed over an oxynitride layer overlying a main dielectric component of the dielectric structure, the main dielectric component having a thickness of at least 2 microns [mu]m.

10. The IC of claim 1, wherein the top plate is formed by a topmost metal layer of a multi-layer metal interconnect formed above the semiconductor substrate.

11. The IC of claim 1, wherein the bottom plate is formed by an intermediate metal layer of a multi-layer metal interconnect formed above the semiconductor substrate.

12. A method for manufacturing an integrated circuit IC, comprising: forming a bottom electrode of the isolation component over the semiconductor substrate; as well as A dielectric structure is formed between the bottom electrode and the top electrode of the isolation component, the dielectric structure comprising a silicon nitride SiN bilayer located below the top electrode, the SiN bilayer comprising a first SiN layer directly contacting the top electrode and having a first refractive index RI, and a second SiN layer located below and directly contacting the first SiN layer and having a second RI greater than the first RI.

13. The method of claim 12, wherein the first RI is in the range of about 2.0 to about 2.

15.

14. The method of claim 12, wherein the second RI is in the range of about 2.2 to about 2.

4.

15. The method of claim 12, wherein the first SiN layer has a thickness less than about 20% of a total thickness of the SiN bilayer.

16. The method of claim 12, further comprising forming an isolation fracture region in a portion of the SiN bilayer extending beyond the top electrode.

17. The method of claim 12, wherein the SiN bilayer is formed over an oxynitride layer overlying a main dielectric component of the dielectric structure, the main dielectric component overlying the bottom electrode and having a thickness of at least 2 microns [mu]m.

18. The method of claim 12, wherein the top electrode is formed of a topmost metal layer of a multi-layer metal interconnect formed above the semiconductor substrate.

19. The method of claim 12, wherein the bottom electrode is formed of an intermediate metal layer of a multi-layer metal interconnection formed above the semiconductor substrate.

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