Semiconductor structure with active region and preparation method thereof

Abstract

A semiconductor structure includes a substrate, a plurality of first dielectric structures, a plurality of second dielectric structures, a capacitor contact, a landing pad, a metal plug, and a dielectric section. The substrate includes a first active region and a second active region. A plurality of first dielectric structures is disposed in the substrate. The first active region is disposed between the plurality of first dielectric structures. A plurality of second dielectric structures is disposed in the substrate. The second active region is disposed between the plurality of second dielectric structures. A capacitor contact is disposed over and in contact with the first active region. A landing pad is disposed over the capacitor contact. A metal plug is disposed over the landing pad. The dielectric section is disposed within the substrate and extends in a first direction. The first active region and the second active region are separated by the dielectric sections along the second direction, and the first active region and the plurality of first dielectric structures are arranged along the first direction. The second active region and the plurality of second dielectric structures are arranged along the first direction. The first active area and the second active area are staggered along the second direction.

Description

[0001] This application is a divisional of Chinese Patent Application No. 202410254639.6, titled "Semiconductor Structure with Active Regions and Method of Fabricating the Same", filed on March 6, 2024. Application No. 202410254639.6 claims the priority and benefits of U.S. Provisional Application No. 18 / 522,581, filed on November 29, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor structure and a method of fabricating a semiconductor structure. In particular, the present disclosure relates to a semiconductor structure having multiple active regions and a patterning method for forming a semiconductor structure having multiple active regions. Background Art

[0003] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As the semiconductor industry moves towards advanced technology process nodes for semiconductor devices, in pursuit of greater device density, the size of the devices on a semiconductor substrate decreases, and challenges have emerged in patterning these reduced-size devices (e.g., active regions).

[0004] The above "Description of the Prior Art" provides only background art and does not admit that the above "Description of the Prior Art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of the present disclosure. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor structure, including a substrate, a plurality of first dielectric structures, a capacitor contact, and a landing pad. The substrate includes a first active region. The plurality of first dielectric structures are disposed in the substrate. The first active region is disposed between the plurality of first dielectric structures. The capacitor contact is disposed above and in contact with the first active region. The landing pad is disposed above the capacitor contact. The landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer. The contact plug is disposed above and in contact with the capacitor contact. The barrier layer is attached to a sidewall of the contact plug. The first silicide layer is disposed above and in contact with the contact plug. The second silicide layer is disposed above the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. A height of the second silicide layer is greater than a height of the first silicide layer.

[0006] Another embodiment of the present disclosure provides a semiconductor structure, including a substrate, a plurality of first dielectric structures, a plurality of second dielectric structures, a capacitor contact, a landing pad, a metal plug, and a dielectric section. The substrate includes a first active region and a second active region. The plurality of first dielectric structures are disposed in the substrate. The first active region is disposed between the plurality of first dielectric structures. The plurality of second dielectric structures are disposed in the substrate. The second active region is disposed between the plurality of second dielectric structures. The capacitor contact is disposed above the first active region and in contact with the first active region. The landing pad is disposed above the capacitor contact. The metal plug is disposed above the landing pad. The dielectric section is disposed in the substrate and extends along a first direction. The first active region and the second active region are separated along a second direction by the dielectric section. The first active region and the plurality of first dielectric structures are arranged along a first direction. The second active region and the plurality of second dielectric structures are arranged along the first direction. The first active region and the second active region are offset along a second direction perpendicular to the first direction.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The steps of the manufacturing method include: forming a first active region and a second active region in a substrate; forming a plurality of first dielectric structures, wherein the first active region is disposed between the plurality of first dielectric structures; forming a plurality of second dielectric structures, wherein the second active region is disposed between the plurality of second dielectric structures; forming a capacitor contact above the first active region; and forming a landing pad above the capacitor contact, wherein the landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer, wherein the contact plug is disposed above the capacitor contact and in contact with the capacitor contact, the barrier layer is attached to a sidewall of the contact plug, the first silicide layer is disposed above the contact plug and in contact with the contact plug, and the second silicide layer is disposed above the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. The first active region and the plurality of first dielectric structures are arranged along a first direction, the second active region and the plurality of second dielectric structures are arranged along the first direction, and the first active region and the second active region are offset along a second direction perpendicular to the first direction.

[0008] The technical features and advantages of the present disclosure have been outlined rather broadly above, so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages of the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be readily utilized as a basis for modifying or designing other structures or processes to achieve the same purposes as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the present disclosure can be obtained by reference to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers of the drawings, and the element numbers of the drawings represent similar elements throughout the description.

[0010] Figure 1 is a top view schematic diagram illustrating a substrate of some embodiments of the present disclosure.

[0011] Figure 2 is a top view schematic diagram illustrating the substrate after forming a plurality of recesses in some embodiments of the present disclosure.

[0012] Figure 3 is a cross-sectional schematic diagram illustrating the cross-section along the Figure 2 section line D-D' in some embodiments of the present disclosure.

[0013] Figure 4 is a top view schematic diagram illustrating the top view at a stage after Figure 2 in some embodiments of the present disclosure.

[0014] Figure 5 is a cross-sectional schematic diagram illustrating the cross-section along the Figure 4 section line D-D' in some embodiments of the present disclosure.

[0015] Figure 6 is a top view schematic diagram illustrating the top view after Figure 4 in some embodiments of the present disclosure.

[0016] Figure 7 is a cross-sectional schematic diagram illustrating the cross-section along the Figure 6 section line D-D' in some embodiments of the present disclosure.

[0017] Figure 8 is a top view schematic diagram illustrating the top view at a stage after Figure 7 in some embodiments of the present disclosure.

[0018] Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 19A , Figure 20A , Figure 21A , Figure 22A and Figure 24A are cross-sectional schematic diagrams illustrating different stages of the preparation method of some embodiments of the present disclosure along Figure 8The cross-section along the cutting line A-A' in

[0019] Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 19B , Figure 20B , Figure 21B , Figure 22B and Figure 24B are cross-sectional schematic diagrams, illustrating different stages of the preparation method of some embodiments of the present disclosure along the Figure 8 cross-section along the cutting line B-B' in

[0020] Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 19C , Figure 20C , Figure 21C , Figure 22C and Figure 24C are cross-sectional schematic diagrams, illustrating different stages of the preparation method of some embodiments of the present disclosure along the Figure 8 cross-section along the cutting line C-C' in

[0021] Figure 18 is a top view schematic diagram, illustrating one stage of the preparation method of some embodiments of the present disclosure as shown in Figure 17A , Figure 17B and Figure 17C shown.

[0022] Figure 23 is a top view schematic diagram, illustrating one stage of the preparation method of some embodiments of the present disclosure as shown in Figure 22A , Figure 22B and Figure 22C shown.

[0023] Figure 25 is a top view schematic diagram, illustrating one stage of the preparation method of some embodiments of the present disclosure as shown in Figure 24A , Figure 24B and Figure 24C shown.

[0024] Figure 26 and Figure 27 is a top view schematic diagram, illustrating the patterning of the photosensitive layer in one stage of the preparation method of some embodiments of the present disclosure.

[0025] Figure 28 and Figure 29 and Figure 30 are flow schematic diagrams, illustrating methods for fabricating semiconductor structures according to some embodiments of the present disclosure.

[0026] Figure 31 and Figure 32 and Figure 33 and Figure 34 and Figure 35 and Figure 36 and Figure 37 and Figure 38 and Figure 39 are cross-sectional schematic diagrams, illustrating cross-sections of forming capacitor contacts and landing pads above the active region according to some embodiments of the present disclosure.

[0027] Figure 40 and Figure 41 and Figure 42 and Figure 43 and Figure 44 and Figure 45 and Figure 46 are cross-sectional schematic diagrams, illustrating cross-sections of forming metal plugs above the landing pads according to some embodiments of the present disclosure.

[0028] Description of reference numerals:

[0029] 1: Substrate

[0030] 4: First mask layer

[0031] 5: Photoresist layer

[0032] 11: Protrusion

[0033] 12: Recessed portion

[0034] 21: First dielectric layer

[0035] 22: Second dielectric layer

[0036] 23: Third dielectric layer

[0037] 24: Second conformal layer

[0038] 25: Fourth dielectric layer

[0039] 26: First conformal layer

[0040] 31: First recess

[0041] 32: Third opening

[0042] 33: Second recess

[0043] 41: First mask layer

[0044] 42: Second mask layer

[0045] 51: First opening

[0046] 52: Second opening

[0047] 53: Portion

[0048] 111: First protruding portion

[0049] 112: Second protruding portion

[0050] 113: Third protruding portion

[0051] 114: Fourth protruding portion

[0052] 115: Fifth protruding portion

[0053] 121: First recessed portion

[0054] 122: Second recessed portion

[0055] 123: Third recessed portion

[0056] 124: Fourth recessed portion

[0057] 211~215: First section

[0058] 221~224: Second section

[0059] 231: Concave portion

[0060] 251: Concave portion

[0061] 301: First insulating film

[0062] 303: Second insulating film

[0063] 305: Third insulating film

[0064] 307: Fourth insulating film

[0065] 307S: Upper surface

[0066] 308: Buffer layer

[0067] 308A: First silicide layer (inner silicide layer)

[0068] 308B: Second silicide layer (outer silicide layer)

[0069] 310: Landing pad

[0070] 402: Contact hole

[0071] 402-1: Filling material

[0072] 403: Capacitor contact

[0073] 403-1: Narrow part (neck)

[0074] 403-2: Wide part (head)

[0075] 403-3: Curved side wall

[0076] 404: Transition hole

[0077] 411: Capacitor plug

[0078] 411A: Protruding part

[0079] 411S: Side wall

[0080] 412: Barrier layer

[0081] 412A: Upper part

[0082] 412AS: Side wall

[0083] 501: Patterned mask

[0084] 503: Dielectric layer

[0085] 505: Patterned mask

[0086] 507: Metal layer (metal plug)

[0087] 510: Opening

[0088] 511: Recess

[0089] 521: Protrusion

[0090] AA: Active area

[0091] C1: Chamber

[0092] D1: Distance

[0093] D2: Distance

[0094] D3: Distance

[0095] D11: Thickness

[0096] D12: Distance

[0097] D31: Depth

[0098] D33: Depth

[0099] D34: Total depth

[0100] D51: Depth

[0101] D52: Depth

[0102] D53: Thickness

[0103] D54: Thickness

[0104] H1: Height

[0105] H2: Height

[0106] L1: Upper width

[0107] L2: Upper width

[0108] L3: Width

[0109] L4: Width

[0110] L5: Width

[0111] L51: Length

[0112] L52: Length

[0113] L6: Width

[0114] P1: First pattern

[0115] P2: Second pattern

[0116] PM: Photomask

[0117] S1: Upper surface

[0118] S5: Wavy side wall

[0119] S10: Preparation method

[0120] S11: Upper surface

[0121] S12: Upper surface

[0122] S20: Preparation method

[0123] S21: Upper surface

[0124] S22: Upper surface

[0125] S23: Upper surface

[0126] S25: Upper surface

[0127] S30: Preparation method

[0128] S41: Upper surface

[0129] S51: Side wall

[0130] S52: Side wall

[0131] S101 - S107: Steps

[0132] S201 - S207: Steps

[0133] S241: First horizontal plane

[0134] S242: Second horizontal plane

[0135] S243: Third horizontal plane

[0136] S301 - S307: Steps

[0137] T2: Interface

[0138] W11: Width

[0139] W12: Width

[0140] W51: Width

[0141] W511: Width

[0142] W512: Width

[0143] W52: Width

[0144] W521: Width

[0145] W522: Width

[0146] W523: Width

[0147] X: Direction

[0148] Z: Direction Detailed implementation manners

[0149] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0150] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, without departing from the teachings of the inventive concept of progressiveness, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section.

[0151] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0152] Due to the shrinking trend of semiconductor device dimensions, the dimensions of the active region may be very small, making it difficult to precisely define the active region by electron beam lithography (EBL). With the advent of extreme ultraviolet lithography (EUVL), patterns with dimensions less than 37 nanometers (nm) can be achieved. However, the equipment and processes of EUVL are expensive, and their use results in an increase in process and product costs.

[0153] The present disclosure provides a method for forming a plurality of active regions on a substrate using EBL. Photosensitive materials with different sensitivities are used to define the active regions arranged in different columns, and smaller dimensions (e.g., patterns with a width or length less than 37 nm) can be achieved.

[0154] According to some embodiments, schematic diagrams of the substrate at different stages of the preparation method of the present disclosure are provided in the drawings, and descriptions of the drawings are provided in the following paragraphs to illustrate the concepts of the present disclosure.

[0155] Please refer to Figure 1, provide, form, or receive a substrate 1. The substrate 1 may include semiconductor materials. In some embodiments, the substrate 1 includes materials selected from Group III-V of the periodic table. In some embodiments, the substrate 1 is a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 1 may be of a first conductivity type, such as a P-type semiconductor substrate (acceptor type), or a second conductivity type, such as an N-type semiconductor substrate (donor type). In some embodiments, the substrate 1 may include a doped epitaxial layer, a graded semiconductor layer, or a semiconductor layer stacked on another semiconductor layer of a different form, such as a silicon layer on a silicon-germanium layer.

[0156] Please refer to Figure 2 , remove some portions of the substrate 1, thereby forming a plurality of protruding portions 11 and a plurality of recessed portions 12. The protruding portions 11 and the recessed portions 12 are alternately arranged along a first direction (e.g., the Y direction). In some embodiments, each protruding portion 11 extends along a second direction (e.g., the X direction) that is substantially orthogonal to the first direction. In some embodiments, each recessed portion 12 extends along the second direction. In some embodiments, the protruding portions 11 and the recessed portions 12 are substantially parallel. In some embodiments, a width W11 of each protruding portion 11 measured along the first direction is substantially equal to a width W12 of each recessed portion 12 measured along the first direction.

[0157] In some embodiments, the plurality of protruding portions 11 includes a first protruding portion 111, a second protruding portion 112, a third protruding portion 113, a fourth protruding portion 114, and a fifth protruding portion 115. The protruding portions 111 to 115 are continuously arranged along the first direction. Adjacent protruding portions 11 are separated by a recessed portion 12. In some embodiments, the plurality of recessed portions 12 includes a first recessed portion 121, a second recessed portion 122, a third recessed portion 123, and a fourth recessed portion 124. The recessed portions 121 to 124 are continuously arranged along the first direction. It should be understood that the number of the protruding portions 11 and the recessed portions 12 shown in the figure is only for illustrative purposes and is not limited thereto.

[0158] It should be understood that a length of the protruding portion 11 and a length of the recessed portion 12 can be adjusted according to a size of a semiconductor structure. The method of the present disclosure includes forming an active region AA of an advanced generation semiconductor structure, wherein the active region AA is formed on the protruding portion 11, and the sizes of the active region AA are substantially equal and arranged in a staggered manner along the first direction (as Figure 25 shown). More details are provided below.

[0159] Please refer to Figure 3 , Figure 3 is along Figure 2Cross-sectional view along the sectional line D-D'. In some embodiments, an upper surface S11 of the protruding portion 11 defines an upper surface S1 of the substrate 1. In some embodiments, a thickness D11 of the substrate 1 is approximately 775 micrometers (μm). In some embodiments, a distance D12 by which the recessed portion 12 recesses from the upper surface S1 of the substrate 1 is in the range of 0.1 μm to 1 μm. In other words, an upper surface S12 of the recessed portion 12 is lower than the upper surface S11 of the protruding portion 11 by the distance D12.

[0160] Please refer to Figure 4 , a first dielectric layer 21 and a second dielectric layer 22 are formed above the substrate 1. The first dielectric layer 21 and the second dielectric layer 22 include different dielectric materials. In some embodiments, the first dielectric layer 21 and the second dielectric layer 22 have different etching rates when subjected to an etchant. In some embodiments, the first dielectric layer 21 includes a nitride, and the second dielectric layer 22 includes an oxide. In some embodiments, the first dielectric layer 21 covers the protruding portion 11, and the second dielectric layer 22 covers the recessed portion 12. In some embodiments, the first dielectric layer 21 includes a plurality of first segments (e.g., 211, 212, 213, 214, and 215) disposed above and corresponding to the protruding portions 111 to 115. In some embodiments, the second dielectric layer 22 includes a plurality of second segments (e.g., 221, 222, 223, and 224) disposed above and corresponding to the recessed portions 121 to 124. As Figure 4 shown, each segment of the first dielectric layer 21 and each segment of the second dielectric layer 22 each have a strip-like structure extending in the second direction. In some embodiments, the plurality of first segments and the plurality of second segments are alternately arranged along the first direction.

[0161] In some embodiments, the first segments 211, 212, 213, 214, and 215 of the first dielectric layer 21 and the second segments 221, 222, 223, and 224 of the second dielectric layer 22 are substantially parallel along the second direction. For ease of explanation, the last digit of the element number of the first segment represents the sequential position of the first segment along the first direction; and the last digit of the element number of the second segment represents the sequential position of the second segment along the first direction. In other words, the first two digits of the element number of a segment indicate which dielectric layer (21 or 22) the segment belongs to, and the last digit of the element number of the segment represents its sequential position along the first direction.

[0162] For example, the first section 211 is the first one among the plurality of first sections 211 to 215 along the first direction; and the second section 221 is the first one among the plurality of second sections 221 to 224. The second section 221 is disposed between the first section 211 and 212 along the first direction, and the first section 212 is disposed between the second section 221 and 222 along the first direction, and so on.

[0163] Please refer to Figure 5 , Figure 5 is a cross-sectional view along the Figure 4 center line D-D' in the figure. As Figure 5 shown, an upper surface S21 of the first dielectric layer 21 can be substantially aligned or coplanar with an upper surface S22 of the second dielectric layer 22. The formation of the first dielectric layer 21 and the second dielectric layer 22 can include a plurality of operations.

[0164] In some embodiments, the first dielectric layer 21 is formed before the second dielectric layer 22. A deposition of the first dielectric layer 21 can be performed, followed by an etching operation to expose the recessed portion 12 of the substrate 1. Then a deposition of the second dielectric layer 22 can be performed, and subsequently another etching operation can be performed to remove the excess portion of the second dielectric layer 22 above the first dielectric layer 21. In some embodiments, a planarization is performed to provide the coplanar upper surfaces S21 and S22 of the first dielectric layer 21 and the second dielectric layer 22, as Figure 5 shown.

[0165] In some embodiments, the second dielectric layer 22 is formed before the first dielectric layer 21. The operations can be similar to the above operations and will not be described herein again.

[0166] Please refer to Figure 6 , a first mask layer 4 and a photoresist layer 5 are sequentially formed above the first dielectric layer 21 and the second dielectric layer 22. The first mask layer 4 can be sensitive to light irradiation. In some embodiments, the first mask layer 4 and the photoresist layer 5 are collectively referred to as a photosensitive layer or a photosensitive structure. In some embodiments, the first mask layer 4 is referred to as a sub-layer of the photosensitive layer, and the photoresist layer 5 is referred to as an upper sub-layer of the photosensitive layer. In some embodiments, the first mask layer 4 and the photoresist layer 5 include different polymers. In some embodiments, the photosensitivity (or optical sensitivity) of the photoresist layer 5 is different from the photosensitivity (or optical sensitivity) of the first mask layer 4. In some embodiments, the first mask layer 4 is also referred to as a photosensitive layer. In some embodiments, the photoresist layer 5 includes a positive photoresist material. In some embodiments, the first mask layer includes a positive photosensitive material. In some embodiments, the first mask layer 4 contacts the first dielectric layer 21 and the second dielectric layer 22. In some embodiments, the first mask layer 4 is formed above a flat surface defined by the upper surface S21 of the first dielectric layer 21 and the upper surface S22 of the second dielectric layer 22.

[0167] Please refer to Figure 8 , a plurality of openings (e.g., 51 and 52) are formed in the photoresist layer 5 and the first mask layer 4 (detailed description will be provided in the following paragraphs). The plurality of openings may include groups of openings having different depths and sizes.

[0168] From Figure 8 the top view shown, a plurality of first openings 51 are formed in the first dielectric layer 21, and a plurality of second openings 52 are formed in the first dielectric layer 21 and the second dielectric layer 22, wherein the second openings 52 are connected to the plurality of first openings along a first direction. In some embodiments, the first openings 51 are formed in the odd-numbered first sections (i.e., 211, 213, and 215). In some embodiments, the first openings 51 are formed above the odd-numbered protruding portions (i.e., Figure 2 111, 113, and 115 shown). In some embodiments, the distances (e.g., D1 and D2) between adjacent first openings 51 along a second direction are substantially equal. In other words, a spacing distance (D1 or D2) between the plurality of first openings 51 in the first sections 211, 212, 213, 214, or 215 along the second direction is substantially uniform.

[0169] The plurality of second openings 52 are disposed between the plurality of first openings 51 along the first direction. In some embodiments, the second openings 52 are formed in the even-numbered first sections (i.e., 212 and 214). In some embodiments, the second openings 52 are formed above the even-numbered protruding portions (i.e., Figure 2 112 and 114 shown). In some embodiments, the second openings 52 are formed in the second dielectric layer 22. In some embodiments, the second openings 52 are formed above the Figure 2 recessed portion 12 shown. In some embodiments, each second opening 52 connects adjacent first openings 51 along the first direction. In some embodiments, a distance D3 between two adjacent second openings 52 in the first section 212 or 214 is substantially uniform along the second direction.

[0170] A size or dimension of the second opening 52 may be greater than a size or dimension of the first opening 51. In some embodiments, a width W51 of the first opening 51 is substantially smaller than a width W52 of the second opening 52, where the widths W51 and W52 are measured along the second direction. In some embodiments, a length L51 of the first opening 51 is substantially smaller than a length L52 of the second opening 52, where the lengths L51 and L52 are measured along the first direction. In some embodiments, the length L52 of the second opening 52 is approximately three times the length L51 of the first opening 51.

[0171] In some embodiments, the first opening 51 is for defining isolation (e.g., 23 in Figure 25 ) on the odd-numbered protruding portions 111, 113, and 115, and the second opening 52 is for defining the active regions (e.g., AA in Figure 25 ) on the even-numbered protruding portions 112 and 114. In order to define active regions AA with substantially equal sizes and staggered along the first direction on different protruding portions 11, as shown in Figure 25 , the width W52 of the second opening 52 should be substantially equal to the distance D1 or D2 between adjacent first openings 51. In addition, the distance D3 between adjacent second openings 52 along the second direction should be substantially equal to the width W51 of the first opening 51. Figure 25 23), and the second opening 52 is for defining the active regions (e.g., AA in Figure 25 ) on the even-numbered protruding portions 112 and 114. Figure 25 AA) on different protruding portions 11, as shown in Figure 25 , the width W52 of the second opening 52 should be substantially equal to the distance D1 or D2 between adjacent first openings 51. Figure 25 In addition, the distance D3 between adjacent second openings 52 along the second direction should be substantially equal to the width W51 of the first opening 51.

[0172] As long as the above criteria are met, the configuration of the first opening 51 and the second opening 52 as viewed from the top view is not limited thereto. For example, the configuration of the first opening 51 can be rectangular, as shown in Figure 26 , Figure 26 which is a top view of a stage of the method of openings 51 and 52 illustrated according to some embodiments of the present disclosure. Figure 26 is a top view of a stage of the method of openings 51 and 52 illustrated according to some embodiments of the present disclosure.

[0173] Please refer back to Figure 8 , in an alternative embodiment, compared with the embodiment shown in Figure 26 , each first opening 51 can have a dumbbell-shaped structure to increase the area of an active region at a recess 511 of the first opening 51. In some embodiments, the recess 511 of the first opening 51 is disposed at or near a central axis of the first section 211, 213, or 215, where the central axis of the first section 211, 213, or 215 extends along the second direction. Figure 26 In some embodiments, the recess 511 of the first opening 51 is disposed at or near a central axis of the first section 211, 213, or 215, where the central axis of the first section 211, 213, or 215 extends along the second direction.

[0174] In some embodiments, each second opening 52 can have a regular hexagon structure, as shown in Figure 8 . In some embodiments, the width W51 of the first opening 51 is measured along the second direction at the recess 511. In some embodiments, the width W52 of the second opening 52 is measured along the second direction at a convex portion 521 of the second opening 52. In some embodiments, the convex portion 521 of the second opening 52 is disposed at or near a central axis of the first section 212 or 214, where the central axis of the first section 212 or 214 extends along the second direction. Figure 8 In some embodiments, the convex portion 521 of the second opening 52 is disposed at or near a central axis of the first section 212 or 214, where the central axis of the first section 212 or 214 extends along the second direction.

[0175] The side walls of the first opening 51 and the second opening 52 together define a corrugated side wall S5 extending in a first direction. In some embodiments, the width of the first opening 51 varies along the first direction, and the width W511 or W51 is a minimum width of the first opening 51. In some embodiments, the width of the second opening 52 varies along the first direction, and the width W521 or W52 is a maximum width of the second opening 52. In some embodiments, a width W512 of the first opening 51 at an interface T2 between the first dielectric layer 21 and the second dielectric layer 22 is substantially smaller than a width W522 of the second opening 52 at the interface T2. In other words, a stepped structure is defined at a connection between a side wall S51 of the first opening 51 and a side wall S52 of the second opening 52. However, the present disclosure is not limited thereto.

[0176] In other embodiments as shown in Figure 27 , each of the second openings 52 may have a hexagonal configuration but with different side lengths. In some embodiments, a width W512 of the first opening 51 at an interface T2 between the first dielectric layer 21 and the second dielectric layer 22 is substantially smaller than a width W522 of the second opening 52 at the interface T2. In some embodiments, a side wall S51 of the first opening 51 is smoothly connected to a side wall S52 of the second opening 52. In some embodiments, the side wall S51 of the first opening 51 and the side wall S52 of the second opening 52 together define a planar side wall. In some embodiments, the first opening 51 and the second opening 52 together have a configuration similar to end-to-end rhombuses.

[0177] For illustrative purposes, in accordance with some embodiments of the present disclosure, cross-sectional views of different stages of the manufacturing method are provided in the drawings. Drawings ending with the letter A (e.g., Figure 9A , Figure 10A , etc.) represent cross-sectional views along the cutting line A-A' in Figure 8 at different stages of the manufacturing method; drawings ending with the letter B (e.g., Figure 9B , Figure 10B , etc.) represent cross-sectional views along the cutting line B-B' in Figure 8 at different stages of the manufacturing method; and drawings ending with the letter C (e.g., Figure 9C , Figure 10C , etc.) represent cross-sectional views along the cutting line C-C' in Figure 8 at different stages of the manufacturing method.

[0178] Please refer to Figure 9A , Figure 9B and Figure 9C, sectional views along cutting lines A-A', B-B', and C-C' are provided. In some embodiments, openings 51 and 52 are defined by a photomask PM. In some embodiments, openings 51 and 52 are formed simultaneously by the same patterning operation. In some embodiments, EBL is applied in the patterning operation.

[0179] The photomask PM may include different patterns to define a first opening 51 and a second opening 52. In some embodiments, a first pattern P1 of the photomask PM is used to define the first opening 51, and a second pattern P2 of the photomask PM is used to define the second opening 52. The first pattern P1 and the second pattern P2 may include different optical transmission rates. In some embodiments, the first pattern P1 has an optical transmission rate that is substantially greater than an optical transmission rate of the second pattern P2. In some embodiments, the optical transmission rate of the second pattern P2 is 1 / 10 to 9 / 10 of the optical transmission rate of the first pattern P1. In some embodiments, the optical transmission rate of the first pattern P1 is 100%. In some embodiments, the optical transmission rate of the second pattern P2 is 1 / 3.

[0180] The formation of the first opening 51 and the second opening 52 may include multiple operations. In some embodiments, a photomask PM is used to perform an exposure operation on the photoresist layer 5. In some embodiments, a developer is applied to the photoresist layer 5 to form the first opening 51 and the second opening 52. Thereby, a first opening 51 having a depth D51 and a second opening 52 having a depth D52 are formed, wherein, due to the different optical transmission rates of the patterns P1 and P2 of the photomask PM, the depth D51 is substantially greater than the depth D52. In some embodiments, the depth D51 of the first opening 51 is substantially equal to a total thickness of the photoresist layer 5 and a first mask layer 4. In some embodiments, according to the optical transmission rate of the second pattern P2, the depth D52 of the second opening 52 is approximately 1 / 10 to 9 / 10 of the depth D51. In some embodiments, a thickness D54 of a portion of the photoresist layer 5 remaining below the second opening 52 is greater than zero.

[0181] In some embodiments, due to the high light transmittance of the first pattern P1, the first opening 51 penetrates through the photoresist layer 5 and the first mask layer 4. In some embodiments, the developer removes a part of the first mask layer 4 that overlaps with the first opening 51. In some embodiments, the second opening 52 partially penetrates the photoresist layer 5 due to its lower light transmittance. In some embodiments, the chemical properties of the part of the first mask layer 4 that overlaps with the second opening 52 are changed due to the optical irradiation during the exposure operation in the patterning process. In some embodiments, the part of the first mask layer 4 that overlaps with the second opening 52 is deteriorated due to the exposure operation, while the photoresist layer 5 is only partially deteriorated due to the difference in photosensitivity between the first mask layer 4 and the photoresist layer 5. For convenience of description, the deteriorated part of the first mask layer 4 is referred to as a second mask layer 42, and the remaining non-deteriorated part of the first mask layer 4 is referred to as the first mask layer 41. In some embodiments, according to different applications, Figure 9B a width W523 of the second opening 52 shown is generally less than or equal to Figure 9C the width W521 shown.

[0182] Please refer to Figure 10A , Figure 10B and Figure 10C , and use the photoresist layer 5 as a mask to form a first recess 31 of the protruding part 11 below the first opening 51. In some embodiments, use the photoresist layer 5 as a mask to remove a part of the first dielectric layer 21 that is exposed through the first opening 51. In some embodiments, a part of the protruding part 11 of the substrate 1 below the first opening 51 is partially removed. The removal of this part of the first dielectric layer 21 and the removal of this part of the protruding part 11 can be performed by the same etching operation or by different etching operations, and this is not limited herein. In some embodiments, the etching operation includes a dry etching operation.

[0183] In some embodiments, an etchant of the etching operation has a low selectivity for the second mask layer 42. In some embodiments, the etching operation terminates at the second mask layer 42. Therefore, the part of the second dielectric layer 22 below the second opening 52 and the part of the first dielectric layer 21 below the second opening 52 are retained. In some embodiments, a depth D31 of the first recess 31 is in the range of 0.1 μm to 1 μm. In some embodiments, the depth D31 is approximately equal to the distance D12, as Figure 2 shown. In some embodiments, a part 53 of the photoresist layer 5 is removed by the etching operation. In some embodiments, the part 53 has a thickness D53 that is approximately equal to as Figure 9B and 9C shown by the thickness D54.

[0184] Please refer to Figure 11A , 11Band 11C to form a first conformal layer 26 lining the first recess 31 and the first dielectric layer 21. In some embodiments, the fabrication technique of the first conformal layer 26 includes the oxidation of the materials of the first dielectric layer 21 and the substrate 1. In some embodiments, the first conformal layer 26 includes an oxide. In some embodiments, the portion of the first conformal layer 26 in contact with the substrate 1 includes silicon oxide, and the portion of the first conformal layer 26 in contact with the first dielectric layer 21 includes a nitrogen oxide.

[0185] Please refer to Figure 12A , Figure 12B and Figure 12C , remove a portion of the second mask layer 42 exposed through the second opening 52, and thereby form a plurality of third openings 32. In some embodiments, the second mask layer 42 is removed by a developer. In some embodiments, a sidewall of the first mask layer 41 is aligned or coplanar with a sidewall of the photoresist layer 5. In some embodiments, the plurality of third openings 32 are respectively connected to the plurality of second openings 52. In some embodiments, the third opening 32 is a through hole of the first mask layer 41. In some embodiments, the second dielectric layer 22 is partially exposed through the third opening 32 as shown in Figure 12B . In some embodiments, the first dielectric layer 21 is partially exposed through the third opening 32 as shown in Figure 12C .

[0186] Please refer to Figure 13A , Figure 13B and Figure 13C , partially remove the first dielectric layer 21. In some embodiments, a wet etching operation is performed, and a plurality of exposed portions of the first dielectric layer 21 are removed. In some embodiments, an etchant for the wet etching operation includes a high etching rate selectivity of a material of the first dielectric layer 21 with respect to a material of the first conformal layer 26. In some embodiments, the even-numbered first segments (e.g., 212 and 214) of the first dielectric layer 21 are removed due to being exposed to the etchant via the third opening 32. In some embodiments, after partially removing the first dielectric layer 21, the even-numbered protruding portions 112 and 114 (as shown in Figure 2 ) are exposed to the air in a processing chamber. In some embodiments, the odd-numbered first segments (e.g., 211, 213, and 215) of the first dielectric layer 21 are retained due to avoiding the influence of the etchant on the first conformal layer 26. In some embodiments, the second dielectric layer 22 is also retained due to a high etching rate selectivity of a material of the first dielectric layer 21 with respect to a material of the second dielectric layer 22.

[0187] Please refer to Figure 14A , Figure 14B and Figure 14C, the photoresist layer 5 is removed, and a third dielectric layer 23 is formed over the substrate 1. In some embodiments, a gap filling operation is performed. In some embodiments, the gap filling operation is achieved by a deposition. In some embodiments, the deposition includes chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or a combination thereof.

[0188] In some embodiments, the third dielectric layer 23 fills the first recess 31 and an opening in the first mask layer 41 over the first recess 31. In some embodiments, the third dielectric layer 23 contacts the first conformal layer 26. In some embodiments, the third dielectric layer 23 fills the third opening 32 over the second dielectric layer 22. In some embodiments, the third dielectric layer 23 contacts the second dielectric layer 22. In some embodiments, a dielectric material of the third dielectric layer 23 is the same as a dielectric material of the second dielectric layer 22. In some embodiments, the third dielectric layer 23 includes an oxide.

[0189] In some embodiments, the third dielectric layer 23 is directly located over portions of the even-numbered protrusions 112 and 114 (as Figure 2 shown), where the portions of the even-numbered protrusions 112, 114 overlap with the third opening 32 or are vertically exposed through the third opening 32. Due to the characteristics of the deposition, as Figure 14C shown, the third dielectric layer 23 does not completely fill the space between the protrusion 112 and the first mask layer 41. In some embodiments, the third dielectric layer 23 contacts a portion of the protrusion 112 that vertically overlaps with the third opening 32, as Figure 14C shown. Thereby, a plurality of chambers C1 are defined by the third dielectric layer 23, the first mask layer 41, and the protrusion 112 of the substrate 1. In some embodiments, due to the characteristics of the deposition, an excess portion of the third dielectric layer 23 is formed over the first mask layer 41 and covers the first mask layer 41.

[0190] Please refer to Figure 15A , Figure 15B and Figure 15C , a planarization is performed to remove the excess portion of the third dielectric layer 23 over the first mask layer 41. In some embodiments, the planarization includes chemical mechanical polishing (CMP), a time-mode etching operation, or a combination thereof. In some embodiments, the first mask layer 41 serves as a termination layer for the CMP or etching operation. In some embodiments, an upper surface S23 of the third dielectric layer 23 is substantially aligned or coplanar with an upper surface S41 of the first mask layer 41.

[0191] Please refer to Figure 16A , Figure 16B and Figure 16C, remove the first mask layer 41. In some embodiments, the first mask layer 41 is removed by an etching operation. In some embodiments, expose or uncover Figure 15C the chamber C1 shown. In some embodiments, Figure 2 the odd-numbered protruding portions 111, 113, and 115 shown are covered by the third dielectric layer 23 and the first dielectric layer 21, as Figure 16A shown. In some embodiments, Figure 2 the recessed portion 12 shown is still covered by the second dielectric layer 22, and the portions of the second dielectric layer 22 within the coverage area having the second opening 52 as Figure 8 shown are covered by the third dielectric layer 23, as Figure 16B shown. In some embodiments, the even-numbered protruding portions 112 and 114 in the coverage area of the second opening 52 as Figure 2 and Figure 8 shown are covered by the third dielectric layer 23, as Figure 16C shown. In some embodiments, the remaining portions of the even-numbered protruding portions 112 and 114 outside the coverage area of the second opening 52 as Figure 2 and Figure 8 shown are exposed via the third dielectric layer 23, as Figure 16C shown.

[0192] Please refer to Figure 17A 、 Figure 17B and Figure 17C , and perform an etching operation to remove the portions of the protruding portions 11 exposed via the third dielectric layer 23. In some embodiments, an etchant in the etching operation has a high selectivity for silicon material. In some embodiments, the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 are used as a mask in the etching operation. In some embodiments, the manufacturing technique of the plurality of second recesses 33 includes an etching operation. In some embodiments, a depth D33 of the second recess 33 is in the range of 0.1 μm to 1 μm. In some embodiments, the depth D33 is substantially equal to Figure 10A the depth D31 shown or Figure 3 the distance D12 shown.

[0193] Figure 18 is a top view of the Figure 17A 、 Figure 17B and Figure 17C stages of the preparation method of the present disclosure according to some embodiments. In some embodiments, the third dielectric layer 23 has a structure similar to or substantially the same as the structure of the first opening 51 and the second opening 52 as Figure 8 shown. In some embodiments, the odd-numbered first segments 211, 213, and 215 of the first dielectric layer 21 are retained. In some embodiments, asFigure 17A As shown, at the position of the first opening 51 as shown in Figure 8 and Figure 18 the first dielectric layer 21 is penetrated by the third dielectric layer 23. In some embodiments, portions of the even-numbered protrusions 112 and 114 are partially exposed via the third dielectric layer 23. In some embodiments, the second recesses 33 of the protrusions 112 and 114 are defined by the third dielectric layer 23.

[0194] Referring to Figure 19A and 19B and 19C, a second conformal layer 24 is formed over the first dielectric layer 21, the second dielectric layer 22, the third dielectric layer 23, and the substrate 1. In some embodiments, the fabrication technique of the second conformal layer 24 includes a conformal deposition. In some embodiments, the conformal deposition includes ALD, PEALD, or a combination thereof. In some embodiments, the second conformal layer 24 includes a dielectric material similar to or the same as the dielectric material of the first dielectric layer 21. In some embodiments, the second conformal layer 24 includes a nitride. In some embodiments, the second conformal layer 24 lines the second recesses 33.

[0195] The second conformal layer 24 includes a plurality of horizontal portions, as shown in Figure 19A and Figure 19B and Figure 19C and the plurality of horizontal portions define three horizontal planes. In some embodiments, the first horizontal plane S241 is defined by the horizontal portions of the second conformal layer 24 disposed over the third dielectric layer 23. In some embodiments, the second horizontal plane S242 is defined by the horizontal portions of the second conformal layer 24 disposed over the first dielectric layer 21 and the second dielectric layer 22. In some embodiments, the third horizontal plane S243 is defined by the horizontal portions of the second conformal layer 24 disposed at a bottom of the second recesses 33.

[0196] Please refer to Figure 20A and 20B and 20C, a fourth dielectric layer 25 is formed over the second conformal layer 24. In some embodiments, the fabrication technique of the fourth dielectric layer 25 includes a conformal deposition. In some embodiments, the conformal deposition includes CVD, ALD, PVD, PEALD, or a combination thereof. In some embodiments, the fourth dielectric layer 25 includes a dielectric material similar to or the same as the dielectric material of the second dielectric layer 22. In some embodiments, the fourth dielectric layer 25 includes an oxide. In some embodiments, the fourth dielectric layer 25 fills the second recesses 33. In some embodiments, as shown in Figure 17CAs shown, a thickness of the fourth dielectric layer 25 is substantially equal to or greater than a total depth D34 of a thickness of the third dielectric layer 23 and a depth D33 of the second recess 33 to ensure that the fourth dielectric layer 25 fills the second recess 33 and the opening in the third dielectric layer 23.

[0197] Please refer to Figure 21A 、 Figure 21B and Figure 21C , perform a planarization and terminate at a second horizontal plane S242 of the second conformal layer 24. In some embodiments, the planarization includes CMP, an etching operation, or a combination thereof. In some embodiments, an etchant of the etching operation has a high selectivity for an oxide material and a low selectivity for a nitride material. In some embodiments, since a coverage area of a portion of the second conformal layer 24 above the second horizontal plane S242 is small, the etching operation removes the portion of the second conformal layer 24 above the second horizontal plane S242. In some embodiments, Figure 20A 、 Figure 20B and Figure 20C A ratio of a surface area of the second conformal layer 24 at a first horizontal plane S241 as shown in

[0198] Please refer to Figure 22A 、 Figure 22B and Figure 22C to the surface area of the fourth dielectric layer 25 is very small, and the etching operation can remove the portion of the second conformal layer 24 at the first horizontal plane S241. In some embodiments, due to a high ratio of the surface area of the second conformal layer 24 at the second horizontal plane S242 to the surface area of the fourth dielectric layer 25, it is easy to control the etching operation to terminate at the second horizontal plane S242.

[0198] Please refer to Figure 22A 、 Figure 22B and Figure 22C , remove the first dielectric layer 21. In some embodiments, perform an etching operation to remove the first dielectric layer 21. In some embodiments, an etchant of the etching operation includes a high selectivity for a nitride material. In some embodiments, the second conformal layer 24 remains between the third dielectric layer 23 and the fourth dielectric layer 25.

[0199] Figure 23 is a top view of a Figure 22A 、 Figure 22B and Figure 22C stage of a manufacturing method of the present disclosure according to some embodiments. In some embodiments, the odd-numbered protruding portions 111, 113, and 115 are exposed through the third dielectric layer 23. In some embodiments, the second dielectric layer 22 remains above the substrate 1. In some embodiments, Figure 2 the even-numbered protruding portions 112 and 114 as shown in

[0200] Please refer to Figure 24A 、 24Band 24C, exposing the protruding portion 11. In some embodiments, some portions of the second dielectric layer 22, the third dielectric layer 23, and the fourth dielectric layer 25 are removed to expose the protruding portion 11. In some embodiments, an etching operation is performed. In some embodiments, the etching operation terminates at the upper surface S11 of the protruding portion 11. In some embodiments, as Figure 24A shown, some portions of the third dielectric layer 23 above the odd-numbered protruding portions 111, 113, and 115 are partially removed. In some embodiments, the thickness of the second dielectric layer 22 is reduced so that the upper surface of the second dielectric layer 22 is aligned with the upper surface S11 of the protruding portion 11, as Figure 24B shown. In some embodiments, the portions of the fourth dielectric layer 25 and the second conformal layer 24 above the second recess 33 are removed. In some embodiments, the upper surface S25 of the fourth dielectric layer 25 is substantially aligned or coplanar with the upper surface S11 of the protruding portion 11.

[0201] Figure 25 is a top view of the stages of the manufacturing method of the present disclosure according to some embodiments Figure 24A , 24B and 24C. The exposed portion of the protruding portion 11 becomes the active region AA of the semiconductor structure. In some embodiments, each active region AA may have a hexagonal configuration. In some embodiments, the third dielectric layer 23 and the fourth dielectric layer 25 are for the purpose of electrically isolating between adjacent active regions AA in the second direction. In some embodiments, the second dielectric layer 22 is for the purpose of electrically isolating between the active regions AA in the first direction. It should be understood that theoretically or ideally, the active region AA is a hexagon with sharp corners. However, in practice, due to the characteristics of lithography, the corners of the hexagon of the active region should be rounded. The active region AA protrudes into the recess 231 of the third dielectric layer 23 or the recess 251 of the fourth dielectric layer 25, and the region of the active region AA protruding into the recess 231 or the recess 251 can provide additional surface area for passive components (e.g., capacitors), lines, wirings, landing pads, or other electronic components. In addition, as is well known, electric fields easily accumulate at the corners of sharp corners, and the hexagonal configuration of the active region can reduce the possibility of current leakage and electric field accumulation.

[0202] The present disclosure provides a method for defining an active region of a semiconductor structure. The method includes forming a patterned mask layer (e.g., photoresist layer 5) having an opening (e.g., openings 51 and 52), the opening having a wavy sidewall and various widths along a direction orthogonal to the extending direction of the active region to be formed. Materials with different sensitivities are used to achieve the results of multiple patterning operations on different materials, so that the active regions on different columns can be defined by different patterning operations.

[0203] To summarize the above Figures 1 to 25The operations shown provide a preparation method S10, a preparation method S20, and a preparation method S30 within the same concept as the present disclosure.

[0204] Figure 28 is a flow schematic diagram illustrating the preparation method S10 of a semiconductor structure according to some embodiments of the present disclosure. The preparation method S10 includes multiple steps (S101, S102, S103, S104, S105, S106, and S107), and the description and the drawings are not regarded as limiting the order of the steps. In step S101, a first mask layer is formed above a substrate. In step S102, a photoresist layer is formed above the first mask layer, wherein a photosensitivity of the photoresist layer is different from a photosensitivity of the first mask layer. In step S103, a first opening and a second opening are formed, wherein the first opening penetrates through the photoresist layer and the first mask layer, the second opening partially penetrates through the photoresist layer, and a part of the first mask layer overlapping with the second opening is deteriorated to form a second mask layer. In step S104, a part of the substrate exposed through the first opening is partially removed to form a first recess of the substrate. In step S105, the second mask layer is removed to form a third opening passing through the first mask layer. In step S106, a first dielectric layer is formed, wherein the first dielectric layer fills the first recess and the third opening and covers a part of the substrate overlapping with the third opening. In step S107, a patterning operation is performed on the substrate using the first dielectric layer as a mask, thereby forming a second recess of the substrate.

[0205] Figure 29It is a process flow diagram, illustrating a method S20 for fabricating a semiconductor structure according to some embodiments of the present disclosure. The fabrication method S20 includes multiple steps (S201, S202, S203, S204, S205, S206, and S207), and the description and the drawings are not regarded as limiting the order of the steps. In step S201, a substrate is provided, wherein the substrate includes a first protruding portion and a second protruding portion that are substantially parallel to each other and extend along a first direction. In step S202, the first protruding portion and the second protruding portion are covered by the first dielectric layer. In step S203, a first mask layer is formed above the first dielectric layer, and a photoresist layer is formed above the first mask layer. In step S204, a patterning operation is performed, wherein a first opening is formed in the first mask layer and the photoresist layer above the first protruding portion to expose the first dielectric layer, and a second opening is formed to partially penetrate the photoresist layer above the second protruding portion. In step S205, a chemical property of a portion of the first mask layer overlapping with the second opening is changed during the patterning operation, and thereby a second mask layer overlapping with the second opening is defined. In step S206, a first recess of the first protruding portion is formed using the photoresist layer as a mask. In step S207, a portion of the second protruding portion that does not overlap with the second mask layer is partially removed, thereby forming a second recess of the second protruding portion.

[0206] Figure 30 It is a process flow diagram, illustrating a method S30 for fabricating a semiconductor structure according to some embodiments of the present disclosure. The fabrication method S30 includes multiple steps (S301, S302, S303, S304, S305, S306, and S307), and the description and the drawings are not regarded as limiting the order of the steps. In step S301, a substrate is provided, wherein the substrate includes a first protruding portion and a second protruding portion, and the first protruding portion and the second protruding portion extend along a first direction. In step S302, a patterned photosensitive layer is formed, wherein the patterned photosensitive layer includes a first through hole located above the first protruding portion and a recess located above the second protruding portion, wherein the first through hole and the recess are connected along a second direction that is substantially orthogonal to the first direction, and a width of the first through hole is smaller than a width of the recess. In step S303, a portion of the substrate exposed through the first through hole is partially removed, thereby forming a first opening of the substrate. In step S304, a first dielectric layer is formed to line the first opening. In step S305, a portion of the patterned photosensitive layer below the recess is partially removed, thereby forming a second through hole. In step S306, a second dielectric layer is formed to be surrounded by the first dielectric layer and disposed in the second through hole. In step S307, the second dielectric layer is used as a mask to pattern the substrate.

[0207] It should be understood that the steps of Preparation Method S10, Preparation Method S20, and / or Preparation Method S30 can be reconfigured or otherwise modified within the scope of each aspect. Additional processes can be provided before, during, and after Preparation Method S10, Preparation Method S20, and / or Preparation Method S30, and some other processes can be simply described herein. Therefore, other embodiments are possible within the scope of the various aspects described herein.

[0208] In some embodiments, Figure 25 、 Figure 26 and Figure 27 the active region AA of the semiconductor structure shown is configured to be part of a capacitor, and Figure 25 、 Figure 26 and Figure 27 the semiconductor structure shown further includes a plurality of capacitor landing pads as shown in Figure 39 .

[0209] Please refer to Figures 31 to 39 . Figure 39 is a cross-sectional schematic view along the cut line C-C' in Figure 8 according to some embodiments of the present disclosure.

[0210] In some embodiments, the capacitor landing pads are disposed above the active region AA, where the active region AA can be disposed between the third dielectric layer 23 and / or between the fourth dielectric layer 25. However, for the sake of brevity, Figures 31 to 39 the cross-sectional view shown only shows the active region AA between the fourth dielectric layers 25 along the cut line C-C' in Figure 8 .

[0211] In Figure 31 , a first insulating film 301 and a second insulating film 303 are disposed above the second protruding portion 112. The second insulating film 303 is disposed above the first insulating film 301. In some embodiments, the first insulating film 301 covers the entire upper surface of the second protruding portion 112, the fourth dielectric layer 25, and the second conformal layer 24. After the first insulating film 301 and the second insulating film 303 are disposed, the upper surface S11 of the protruding portion 112 and the upper surface S25 of the fourth dielectric layer 25 are covered.

[0212] For example, the first insulating film 301 can include silicon nitride, silicon oxide, silicon oxynitride, undoped silicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or a combination thereof, but is not limited thereto. The second insulating film 303 can include a material that is the same as the material of the first insulating film 301, but is not limited thereto.

[0213] In Figure 32In [the structure], a third insulating film 305 may be formed on the second insulating film 303. The third insulating film 305 may include a material that is the same as that of the first insulating film 301, but is not limited thereto. A photolithography process may pattern the third insulating film 305 to define the positions of a plurality of contact holes 402, and an etching process may be performed to form a plurality of contact holes 402 that penetrate the third insulating film 305, the second insulating film 303, and the first insulating film 301. In some embodiments, the contact holes 402 are considered to be deep holes. After the etching process, a part of the upper surface S11 of the protruding portion 11 is exposed, but the entire upper surface S25 of the fourth dielectric layer 25 is still covered.

[0214] In Figure 33 [the structure], the contact holes 402 may be filled with a material by, for example, chemical vapor deposition, physical vapor deposition, sputtering, or a similar process. The contact holes 402 may be partially filled with a filling material 402-1. In some embodiments, the upper portions of the contact holes 402 in the third insulating film 305 are not filled with the filling material 402-1. In other words, when the material is filled into the contact holes 402, an upper surface of the material and an upper surface of the second insulating film 303 are coplanar.

[0215] In Figure 34 [the structure], an etching process, such as an anisotropic etching process, may be performed to remove a part of the third insulating film 305 around the contact holes 402 to form a plurality of via holes 404, and the via holes 404 have a narrow portion 403-1 occupied by the filling material 402-1 in the second insulating film 303 and a wide portion 403-2 in the third insulating film 305. In some embodiments, the narrow portion 403-1 is also referred to as a neck 403-1, and the wide portion 403-2 is also referred to as a head 403-2.

[0216] In Figure 35 [the structure], a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the via holes 404 by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process, to form a plurality of capacitor contacts 403. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0217] In some embodiments, each capacitor contact 403 includes a neck 403-1 and a head 403-2 above the neck 403-1, wherein an upper width L1 of the head 403-2 is greater than an upper width L2 of the neck 403-1. In some embodiments, the upper width L2 of the neck 403-1 is substantially the same as a lower width of the head 403-2. In some embodiments, the head 403-2 has a curved sidewall 403-3. In some embodiments, the head 403-2 has a tapered profile.

[0218] In Figure 36 , a fourth insulating film 307 may be formed on the third insulating film 305. The fourth insulating film 307 may include a material that is the same as the material of the first insulating film 301, but is not limited thereto. A lithography process may be used to pattern the fourth insulating film 307 to define the positions of a plurality of capacitor plugs 411. An etching process, such as an anisotropic dry etching process, may be performed after the lithography process to form a plurality of plug openings above the head 403-2 and through the fourth insulating film 307. A plurality of barrier layers 412 may be disposed in the plug openings and attached to the respective sidewalls of the plug openings. A conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the plurality of plug openings by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or a similar process, to form a plurality of capacitor plugs 411. In Figure 36 , the barrier layers 412 are attached to the respective sidewalls 411S of the capacitor plugs 411. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove the excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0219] In Figure 37 , an etch-back process is performed to remove an upper portion of the fourth insulating film 307 to expose a protruding portion 411A of the capacitor plug 411 and an upper portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, an upper surface of the capacitor plug 411 is higher than an upper surface 307S of the fourth insulating film 307, and sidewalls of the upper portion 412A are exposed.

[0220] In Figure 38 , a deposition process is performed to form a liner layer 308 that covers the upper surface of the fourth insulating film 307, the upper surface of the protruding portion 411A, and the sidewalls of the upper portion 412A. In some embodiments, the liner layer 308 is a silicon-containing layer, such as a polysilicon layer.

[0221] In Figure 39In [the above situation], a self-aligned silicidation process (thermal process) is performed to form a plurality of landing pads 310 above the third insulating film 305, where the landing pads 310 include a protruding portion 411A of the capacitor plug 411, an upper portion 412A of the barrier layer 412, a first silicide layer (metal silicide) 308A above the protruding portion 411A, and a second silicide layer (metal silicide layer (metal silicide) 308A and a second silicide layer (metal silicide) 308B on the sidewall 412AS of the protruding portion 411A. In some embodiments, the thermal process transforms the protruding portion 411A and a part of the liner layer 308 into the first silicide layer 308A. In some embodiments, the thermal process transforms the upper portion 412A of the barrier layer 412 and the liner layer 308 into the second silicide layer 308B. In other words, lithography technology is not used to form the landing pads 310, that is, the landing pads 310 are self-aligned with the capacitor plug 411. In some embodiments, the thickness and shape of the protruding portion 411A and the upper portion 412A can be changed (not shown in the figure).

[0222] Since the first silicide layer 308A is sandwiched between the second silicide layers 308B, the first silicide layer 308A is also referred to as an inner silicide layer 308A, and the second silicide layer 308B is also referred to as an outer silicide layer 308B.

[0223] In some embodiments, an etching process such as an anisotropic dry etching process is performed to remove a part of the liner layer 308 that has not been transformed into metal silicide by the thermal process. In other words, the first silicide layer 308A and the second silicide layer 308B are made of different materials. In some embodiments, the process speed of the self-aligned silicidation process between the upper portion 412A and the liner layer 308 is faster than the process speed of the self-aligned silicidation process between the protruding portion 411A and the liner layer 308. Therefore, the top of the second silicide layer 308B is higher than the top of the first silicide layer 308A, and thus a stepped structure is formed between the first silicide layer 308A and the second silicide layer 308B. In other words, a height H2 of the second silicide layer 308B is greater than a height H1 of the first silicide layer 308A. The height H1 and the height H2 are measured along the Z direction, and the height H1 is defined from the upper surface of the fourth insulating film 307 to the top of the first silicide layer 308A. In some embodiments, the second silicide layer 308B surrounds the first silicide layer 308A, and a width L4 of the second silicide layer 308B is greater than a width L3 of the first silicide layer 308A.

[0224] As Figure 39As shown, compared with the other vertex angle of the second silicide layer 308B adjacent to the first silicide layer 308A, the vertex angle of the second silicide layer 308B away from the first silicide layer 308A is etched into a curved sidewall. In other words, the second silicide layer 308B has a rounded corner.

[0225] In some embodiments, in addition to the capacitor landing pad, Figure 25 , Figure 26 and Figure 27 the semiconductor structure shown also includes metal plugs above the capacitor landing pad, as Figure 27 shown.

[0226] Please refer to Figures 40 to 46 , Figures 40 to 46 which is a cross-sectional schematic diagram along the Figure 8 section line C-C' in

[0227] As described above, the capacitor landing pad is disposed above the active region AA, where the active region AA can be disposed between the third dielectric layer 23 and / or between the fourth dielectric layer 25. Therefore, the metal plugs can also be disposed above the capacitor landing pad, where the capacitor landing pad is disposed between the third dielectric layer 23 and / or between the fourth dielectric layer 25. However, for simplicity, Figures 40 to 46 the cross-sectional view shown only shows the active region AA along the Figure 8 section line C-C' in

[0228] In Figure 40 , a patterned mask 501 is formed above the fourth insulating film 307, and the first silicide layer 308A and the second silicide layer 308B are covered by the patterned mask 501.

[0229] In Figure 41 , a planarization process is performed on the patterned mask 501. In some embodiments, the planarization process is performed until the second silicide layer 308B is exposed. The planarization process can include a CMP process that removes the excess portion of the patterned mask 501 above the second silicide layer 308B. In some embodiments, the second silicide layer 308B can be slightly etched. In these cases, the topmost surface of the second silicide layer 308B is still higher than the topmost surface of the first silicide layer 308A, and a portion of the patterned mask 501 remains on the first silicide layer 308A and is sandwiched by the second silicide layer 308B.

[0230] In Figure 42 , a dielectric layer 503 is formed above the remaining portion of the patterned mask 501. In Figure 43 , another patterned mask 505 is formed above the dielectric layer 503. In Figure 44In [description], a patterned mask 505 is used to etch a dielectric layer 503 to form an opening 510 that penetrates the dielectric layer 503.

[0231] In some embodiments, the portion of the patterned mask 501 above the first silicide layer 308A is removed, such that the upper surface of the first silicide layer 308A is exposed through the opening 510. Additionally, during the etching process for forming the opening 510, the second silicide layer 308B may be slightly etched. The fabrication technique for the opening 510 may include a wet etching process, a dry etching process, or a combination thereof.

[0232] In Figure 45 [description], a metal layer 507 is formed over the current structure and fills the opening 510. In some embodiments, the metal layer 507 includes tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination thereof, or other suitable metal materials. The formation of the metal layer 507 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, an electroplating process, or other suitable processes. In some embodiments, the metal layer 507 covers an upper surface of the patterned mask 505.

[0233] In Figure 46 [description], a planarization process is performed to remove the patterned mask 505 and a portion of the metal layer 507 to expose an upper surface of the dielectric layer 503. After the planarization process, the dielectric layer 503 and the remaining metal layer 507 are coplanar. In some embodiments, the planarization process includes a CMP process. In some embodiments, the remaining metal layer 507 is also referred to as a metal plug 507.

[0234] As Figure 46 shown, the metal plug 507 extends into the patterned mask 501, which results in a bottommost surface of the metal plug 507 being lower than an upper surface of the second silicide layer 308B. Additionally, a width L5 of the metal plug 507 in the dielectric layer 503 is greater than a width L6 of the first silicide layer 308A in the X direction, such that the first silicide layer 308A is completely covered by the metal plug 507.

[0235] An embodiment of the present disclosure provides a semiconductor structure, including a substrate, a plurality of first dielectric structures, a capacitor contact, and a landing pad. The substrate includes a first active region. The plurality of first dielectric structures are disposed in the substrate. The first active region is disposed between the plurality of first dielectric structures. The capacitor contact is disposed above and in contact with the first active region. The landing pad is disposed above the capacitor contact. The landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer. The contact plug is disposed above and in contact with the capacitor contact. The barrier layer is attached to a sidewall of the contact plug. The first silicide layer is disposed above and in contact with the contact plug. The second silicide layer is disposed above the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. A height of the second silicide layer is greater than a height of the first silicide layer.

[0236] Another embodiment of the present disclosure provides a semiconductor structure, including a substrate, a plurality of first dielectric structures, a plurality of second dielectric structures, a capacitor contact, a landing pad, and a metal plug. The substrate includes a first active region and a second active region. The plurality of first dielectric structures are disposed in the substrate. The first active region is disposed between the plurality of first dielectric structures. The plurality of second dielectric structures are disposed in the substrate. The second active region is disposed between the plurality of second dielectric structures. The capacitor contact is disposed above and in contact with the first active region. The landing pad is disposed above the capacitor contact. The metal plug is disposed above the landing pad. The first active region and the plurality of first dielectric structures are arranged along a first direction. The second active region and the plurality of second dielectric structures are arranged along the first direction. The first active region and the second active region are offset along a second direction perpendicular to the first direction.

[0237] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The steps of the manufacturing method include: forming a first active region and a second active region in a substrate; forming a plurality of first dielectric structures, wherein the first active region is disposed between the plurality of first dielectric structures; forming a plurality of second dielectric structures, wherein the second active region is disposed between the plurality of second dielectric structures; forming a capacitor contact above the first active region; and forming a landing pad above the capacitor contact, wherein the landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer, wherein the contact plug is disposed above and in contact with the capacitor contact, the barrier layer is attached to a sidewall of the contact plug, the first silicide layer is disposed above and in contact with the contact plug, and the second silicide layer is disposed above the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. The first active region and the plurality of first dielectric structures are arranged along a first direction, the second active region and the plurality of second dielectric structures are arranged along the first direction, and the first active region and the second active region are offset along a second direction perpendicular to the first direction.

[0238] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0239] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor structure comprising: A substrate including a first active region and a second active region; A plurality of first dielectric structures are disposed in the substrate, wherein the first active region is disposed between the plurality of first dielectric structures; A plurality of second dielectric structures are disposed in the substrate, wherein the second active region is disposed between the plurality of second dielectric structures; a capacitor contact disposed above the first active region and in contact with the first active region; a landing pad disposed above the capacitor contact; a metal plug disposed above the landing pad; and a dielectric section disposed in the substrate and extending along a first direction, wherein the first active region and the second active region are separated by the dielectric section along a second direction perpendicular to the first direction, The first active region and the plurality of first dielectric structures are arranged along the first direction, the second active region and the plurality of second dielectric structures are arranged along the first direction, and the first active region and the second active region are staggered along the second direction.

2. The semiconductor structure of claim 1, wherein the landing pad comprises: a contact plug disposed above the capacitor contact and in contact with the capacitor contact; a barrier layer attached to a sidewall of the contact plug; a first silicide layer disposed above the contact plug and in contact with the contact plug; as well as A second silicide layer is disposed above the contact plug and the barrier layer and contacts a side wall of the barrier layer. 3 . The semiconductor structure of claim 2 , wherein a height of the second silicide layer is greater than a height of the first silicide layer, and the first silicide layer and the second silicide layer comprise different materials.

4. The semiconductor structure of claim 2, further comprising: a first insulating film disposed above the substrate and in contact with the first active region, the second active region, the plurality of first dielectric structures, and the plurality of second dielectric structures; a second insulating film disposed above the first insulating film; as well as A third insulating film is disposed above the second insulating film.

5. The semiconductor structure of claim 4, wherein the capacitor contact comprises: a neck portion in contact with the first active region, the first insulating film and the second insulating film; as well as A head is located above the neck and contacts the third insulating film. 6 . The semiconductor structure of claim 5 , wherein a width of the head portion is greater than a width of the neck portion, and the head portion has a curved sidewall. 7 . The semiconductor structure as claimed in claim 2 , wherein the metal plug extends toward the first silicide layer and contacts the first silicide layer and the second silicide layer. 8 . The semiconductor structure as claimed in claim 7 , wherein a width of the first silicide layer is greater than a width of the second silicide layer.

9. The semiconductor structure of claim 2, further comprising: A fourth insulating film is disposed above the substrate and contacts the barrier layer, the second silicide layer and the capacitor contact. 10 . The semiconductor structure as claimed in claim 9 , wherein the contact plug and the barrier layer protrude from an upper surface of the fourth insulating film. 11 . The semiconductor structure as claimed in claim 1 , wherein the first active region protrudes toward a recessed portion of an adjacent first dielectric structure among the plurality of first dielectric structures.

12. The semiconductor structure of claim 2, further comprising: A patterned mask is disposed on the substrate and contacts the second silicide layer.

13. The semiconductor structure of claim 12, further comprising: A dielectric layer is disposed on the patterned mask and contacts the metal plug.

14. A method for preparing a semiconductor structure, comprising: forming a first active region and a second active region in a substrate; forming a plurality of first dielectric structures, wherein the first active region is disposed between the plurality of first dielectric structures; forming a plurality of second dielectric structures, wherein the second active region is disposed between the plurality of second dielectric structures; forming a capacitor contact over the first active region; as well as forming a landing pad over the capacitor contact, wherein the landing pad comprises a contact plug, a barrier layer, a first silicide layer and a second silicide layer, wherein the contact plug is disposed over and in contact with the capacitor contact, the barrier layer is attached to a sidewall of the contact plug, the first silicide layer is disposed over and in contact with the contact plug, and the second silicide layer is disposed over the contact plug and the barrier layer and in contact with a sidewall of the barrier layer, The first active region and the plurality of first dielectric structures are arranged along a first direction, the second active region and the plurality of second dielectric structures are arranged along the first direction, and the first active region and the second active region are staggered along a second direction perpendicular to the first direction.

15. The preparation method according to claim 14, further comprising: forming a first insulating film on the substrate and contacting the first active region, the second active region, the plurality of first dielectric structures and the plurality of second dielectric structures; forming a second insulating film over the first insulating film; and A third insulating film is formed over the second insulating film.

16. The method of claim 15, wherein forming the capacitor contact above the first active region comprises: Using the third insulating film as a mask, etching the first insulating film and the second insulating film to form a contact hole, wherein a portion of the first active region is exposed through the contact hole; Depositing a material into the contact hole, wherein the material is coplanar with the second insulating film; performing an anisotropic etching process to remove a portion of the third insulating film around the contact hole to widen the contact hole in the third insulating film; as well as A conductive material is deposited into the contact hole in the third insulating film.

17. The preparation method as described in claim 16, wherein after performing the anisotropic etching, the contact hole is converted to have a neck and a head, wherein the neck is in contact with the first active region, the first insulating film and the second insulating film, and the head is located above the neck and in contact with the third insulating film.

18. The method of claim 16, wherein forming the landing pad over the capacitor contact comprises: forming a fourth insulating film on the third insulating film; forming the contact plug, the barrier layer and the fourth insulating film, wherein the contact plug and the barrier layer contact the conductive material; depositing a liner layer to cover the fourth insulating film, the contact plug and the barrier layer; as well as A self-aligned silicidation process is performed to convert the liner layer into the first silicide layer and the second silicide layer.

19. The preparation method as claimed in claim 18, wherein the first silicide layer contacts the contact plug and the second silicide layer, and the second silicide layer further contacts the contact plug, the barrier layer and the fourth insulating film, wherein the second silicide layer contacts a side wall of the barrier layer. 20 . The preparation method according to claim 19 , wherein in a third direction, a height of the second silicide layer is greater than a height of the first silicide layer, wherein the third direction is perpendicular to the first direction and the second direction.

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