Chip packaging structure and electronic equipment

Abstract

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can weld a connector and a die on the same side of an adapter plate. The chip packaging structure comprises an adapter plate, at least one first chip, at least one electronic element, a communicating vessel and a first connector. Wherein the first chip is arranged on the front surface of the adapter plate and is connected with the front surface of the adapter plate. The electronic element is positioned on the back surface (far away from one side of the first chip) of the adapter plate and is electrically connected with the back surface of the adapter plate; the electronic component position is directly connected with the adapter plate and can also be connected with the adapter plate through the substrate. The communicating vessel and the first chip are plastically packaged in the plastic packaging layer; and the bottom of the communicating vessel is electrically connected with the front surface or the back surface of the adapter plate. The first connector is located on the side, away from the adapter plate, of the plastic packaging layer, and the first connector is located on the top of the communicating vessel and electrically connected with the top of the communicating vessel, so that the first connector is electrically connected with the adapter plate through the communicating vessel.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a chip packaging structure and an electronic device. Background Art

[0002] System in a package (SiP) technology is an integrated circuit packaging technology that integrates multiple dies and passive devices in a single package. In the post-Moore era, SiP technology can help increase the integration level, reduce the volume, and lower the power consumption of chip products. With the further evolution of chip manufacturing capabilities and the further increase in the number of integrated chips, more signals need to be processed, and more data needs to be transmitted outward through connectors by input / output dies (IO dies). However, the current upgrade speed of connectors in the industry cannot meet the synchronous improvement of signal transmission capabilities under the same area ratio. Therefore, it is necessary to layout more connectors in the packaging structure to transmit data externally.

[0003] In the current new system integration packaging structure, the power supply requirement of each known good die (KGD) is realized by a power supply module vertically mounted on its back, and the signal transmission requirement of each IO die is responsible for external transmission by a circle of connectors on the back. However, since the integration of the die and the interposer is achieved through semiconductor processes, after welding multiple dies, it is necessary to fill glue at the bottom of multiple dies and molding materials around the perimeter for protection. This semiconductor process is not compatible with large-size connectors. Therefore, in the current process, the connectors and the die cannot be welded to the same side of the interposer. Only multiple dies can be welded to the front side of the interposer, while the connectors are welded to the back side of the interposer. In this mode, laying out a large number of connectors will occupy the area of the interposer. On the one hand, it will lead to an increase in cost. On the other hand, it will also increase the distance between the connectors and the IO dies, resulting in serious signal attenuation. Therefore, if it is possible to assemble connectors on both sides of the interposer, it is of great significance for saving the area of the interposer. Summary of the Invention

[0004] This application provides a chip packaging structure and an electronic device that can weld connectors and chips (dies) to the same side of the interposer.

[0005] The present application provides a chip packaging structure, which includes an interposer, at least one first chip (which can be simply referred to as a chip), at least one electronic component, a via connector, and a first connector. Among them, the first chip is disposed on the front side of the interposer and connected to the front side of the interposer. The electronic component is located on the back side of the interposer (the side away from the first chip) and electrically connected to the back side of the interposer; the electronic component is directly connected to the interposer or can be connected through a substrate. The via connector and the first chip are both encapsulated in a molding compound layer, and the bottom of the via connector is electrically connected to the front side or the back side of the interposer. The first connector is located on the top of the via connector and electrically connected to the top of the via connector, so that the first connector is electrically connected to the interposer through the via connector.

[0006] In this chip packaging structure, by providing a via connector below the first connector, the signal on the interposer can be led out to the first connector above through the via connector as an intermediate connection structure. In this case, the via connector and the chip can be encapsulated in the molding compound layer. In this way, the via connector as an intermediate connection structure realizes leading out the signal to the first connector above, and at the same time avoids the molding compound layer from wrapping the first connector, so as to ensure that the first connector transmits the signal of the chip (such as an IO die) outward through the via connector, solving various problems caused by the inability to mount the connector and the chip on the same side of the interposer in the prior art.

[0007] In some possible implementation manners, the top of the via connector is flush with the surface of the first chip on the side away from the interposer.

[0008] In some possible implementation manners, the via connector includes a support plate, a first metal connection structure, and a second metal connection structure. An intermediate metal connection structure is provided in the support plate. The first metal connection structure is disposed on the top of the support plate and connected to the intermediate metal connection structure, and the second metal connection structure is disposed on the bottom of the support plate and connected to the intermediate metal connection structure. The via connector is connected to the first connector through the first metal connection structure and connected to the interposer through the second metal connection structure.

[0009] In some possible implementation manners, the chip packaging structure further includes a second connector; the second connector and the first connector are disposed on different sides of the interposer, and the second connector is directly connected to the back side of the interposer or connected through a substrate. That is to say, the first connector and the second connector are respectively disposed on the front and back sides of the interposer, realizing the layout of connectors on the front and back sides of the interposer. In this way, the layout number of connectors can be doubled, and the system data external transmission capacity can be doubled. At the same time, arranging multiple connectors on the front and back sides of the interposer also avoids the problem of increased cost caused by increasing the area of the interposer and the problem of signal attenuation caused by the increased distance between the chip and the connector.

[0010] In some possible implementations, the communicating vessel and the first chip are located on the same side of the interposer, that is, both the communicating vessel and the first chip are disposed on the front side of the interposer, and the bottom of the communicating vessel is electrically connected to the front side of the interposer. In this case, the first connector can be electrically connected to the front side of the interposer through the communicating vessel, so as to realize the transmission of the signals of the chip outward.

[0011] In some possible implementations, the interposer includes: a silicon interposer and a redistribution layer. The front side of the silicon interposer has a metal wiring layer, and through-silicon vias (TSVs) are disposed in the silicon interposer. The redistribution layer is disposed on the back side of the silicon interposer and is electrically connected to the through-silicon vias. The first chip is disposed on the front side of the silicon interposer. The edge of the redistribution layer extends beyond the edge of the silicon interposer, and the communicating vessel is disposed on the surface of the redistribution layer around the silicon interposer and is electrically connected to the redistribution layer. In this case, the first connector is electrically connected to the redistribution layer through the communicating vessel, so as to realize the transmission of the signals of the chip outward. In addition, multiple first chips are interconnected through the metal wiring layer on the front side of the silicon interposer, and the silicon interposer can be processed by a silicon-based process, which can meet the high-bandwidth density interconnection requirements between multiple chips, such as an interconnection bandwidth density of more than 2 Tbps / mm. On the back side of the interposer, multiple electronic components are connected to the redistribution layer, and the redistribution layer can adopt a thick metal layer and a thick dielectric layer with better current-sharing ability, so as to meet the requirements of the electronic components for high-speed serdes (serializer / deserializer) driving with large current-sharing ability, low impedance, and long distance. Schematically, the line width, line pitch, and line thickness of the metal wirings in the metal wiring layer on the front side of the silicon interposer are all less than 5 μm. The line width, line pitch, and line thickness of the metal wirings in the redistribution layer are all greater than 5 μm.

[0012] In some possible implementations, the interposer includes: a first redistribution layer and a second redistribution layer stacked. The chip is disposed on the surface of the first redistribution layer. The communicating vessel is disposed on the surface of the first redistribution layer, so that the first connector is electrically connected to the first redistribution layer through the communicating vessel, and further the transmission of the signals of the chip outward can be realized. Alternatively, the edge of the second redistribution layer extends beyond the edge of the first redistribution layer, and the communicating vessel is disposed on the surface of the second redistribution layer around the first redistribution layer, so that the first connector is electrically connected to the second redistribution layer through the communicating vessel, and further the transmission of the signals of the chip outward can be realized. In addition, the first redistribution layer can adopt a thin metal layer and a thin dielectric layer, which can meet the high-bandwidth density interconnection requirements between multiple chips; the second redistribution layer can adopt a thick metal layer and a thick dielectric layer with better current-sharing ability, so as to meet the requirements of the electronic components for high-speed serdes driving with large current-sharing ability, low impedance, and long distance. Schematically, the line width, line pitch, and line thickness of the metal wirings in the first redistribution layer are all less than 5 μm; the line width, line pitch, and line thickness of the metal wirings in the second redistribution layer are all greater than 5 μm.

[0013] In some possible implementations, the communicating vessel is located on the side of the adapter board, and the bottom of the communicating vessel is electrically connected to the back surface of the adapter board (i.e., the side where the electronic components are provided) through a substrate. In this way, the first connector is electrically connected to the back surface of the adapter board through the communicating vessel, so that the signal of the chip can be transmitted outward.

[0014] In some possible implementations, the adapter board includes: a silicon interposer and a redistribution layer. The front surface of the silicon interposer has a metal trace layer, and through-silicon vias (TSVs) are provided in the silicon interposer. The redistribution layer is provided on the back surface of the silicon interposer and is electrically connected to the through-silicon vias. The first chip is provided on the front surface of the silicon interposer. In this case, the edges of the silicon interposer and the redistribution layer can be flush or approximately flush. The communicating vessel is provided on the side of the silicon interposer and the redistribution layer, and the bottom of the communicating vessel is electrically connected to the back surface of the redistribution layer (i.e., the side away from the silicon interposer) through a substrate, so that the first connector is electrically connected to the back surface of the redistribution layer through the communicating vessel, and further the signal of the chip can be transmitted outward. In addition, multiple chips are interconnected through the metal trace layer on the surface of the silicon interposer, and the silicon interposer is processed by a silicon-based process, which can meet the high-bandwidth density interconnection requirements between multiple chips. On the back surface of the adapter board, multiple electronic components are connected to the redistribution layer, and the redistribution layer can adopt a thick metal layer and a thick dielectric layer with better current sharing ability, so as to meet the high-speed serdes driving requirements of electronic components for large current sharing ability, low impedance, and long distance.

[0015] In some possible implementations, the adapter board includes: a first redistribution layer and a second redistribution layer stacked. The chip is provided on the surface of the first redistribution layer. The communicating vessel is provided on the side of the first redistribution layer and the second redistribution layer; the communicating vessel is electrically connected to the back surface of the second redistribution layer through a substrate, so that the first connector can be electrically connected to the back surface of the second redistribution layer through the communicating vessel, and further the signal of the chip can be transmitted outward. In addition, the first redistribution layer can adopt a thin metal layer and a thin dielectric layer, which can meet the high-bandwidth density interconnection requirements between multiple chips; the second redistribution layer can adopt a thick metal layer and a thick dielectric layer with better current sharing ability, so as to meet the high-speed serdes driving requirements of electronic components for large current sharing ability, low impedance, and long distance. Schematically, the line width, line pitch, and line thickness of the metal traces in the first redistribution layer are all less than 5 μm; the line width, line pitch, and line thickness of the metal traces in the second redistribution layer are all greater than 5 μm.

[0016] In some possible implementations, the above-mentioned adapter board may further include: a glass wafer, and the glass wafer is provided between the first redistribution layer and the second redistribution layer. Wherein, through-glass vias (TGVs) are provided in the glass wafer, and the second redistribution layer is electrically connected to the first redistribution layer through the glass vias.

[0017] In some possible implementation manners, a bridge chip is further provided in the above-mentioned interposer; trenches are provided in the above-mentioned glass wafer, the bridge chip is embedded in the trenches, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer. In this case, since the bridge chip can be fabricated by a silicon-based process, the line width, line pitch, and line thickness on the surface of the bridge chip can meet the high-bandwidth density interconnection requirements between multiple chips.

[0018] In some possible implementation manners, a bridge chip and metal posts are further provided in the above-mentioned interposer. The bridge chip and the metal posts are connected between the first redistribution layer and the second redistribution layer and are encapsulated in the encapsulation layer. The second redistribution layer is electrically connected to the first redistribution layer through the metal posts, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer. Since the bridge chip can be fabricated by a silicon-based process, the line width, line pitch, and line thickness on the surface of the bridge chip can meet the high-bandwidth density interconnection requirements between multiple chips.

[0019] In some possible implementation manners, the above-mentioned at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0020] In some possible implementation manners, the above-mentioned at least one electronic component includes one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and resistors, capacitors, and inductors.

[0021] In some possible implementation manners, the above-mentioned chip packaging structure includes a plurality of first chips and a plurality of electronic components.

[0022] In some possible implementation manners, a plurality of power supply modules are included in the plurality of electronic components, and the plurality of power supply modules are respectively disposed opposite to the plurality of first chips. The power supply module is electrically connected to the first chip disposed opposite through the interposer and supplies power to the corresponding first chip.

[0023] In some possible implementation manners, the chip packaging structure includes a plurality of substrates; the substrates are located on the back surface of the interposer. A plurality of devices located on the back surface of the interposer are connected to the interposer through the plurality of substrates; wherein, the plurality of devices may include one or more of electronic components, connectors, and second connectors. In this way, the types of the plurality of substrates can be flexibly selected according to the electrical requirements of the devices to improve the performance of the entire system. In addition, the use of a plurality of discrete substrates can also relieve the mechanical stress caused by thermal mismatch in the assembly and service scenarios of a large continuous substrate, which is more friendly to the reliability of system assembly and service.

[0024] In some possible implementation manners, the plurality of substrates are encapsulated in a molding layer to protect the plurality of substrates through the molding layer.

[0025] In some possible implementation manners, the chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate. The first heat dissipation plate is disposed on a side of the first chip away from the adapter board, and the second heat dissipation plate is disposed on a side of the electronic component away from the adapter board. By providing two heat dissipation plates, the heat dissipation of the chip packaging structure is satisfied.

[0026] In some possible implementation manners, the chip packaging structure further includes: a fixing structure; the fixing structure penetrates and holds the first heat dissipation plate, the adapter board, and the second heat dissipation plate.

[0027] In some possible implementation manners, the chip packaging structure further includes a first electronic device on a side of the plastic encapsulation layer away from the adapter board. The first electrode device may be other devices other than a connector, such as a power supply module, etc. The first electronic device can be electrically connected to the adapter board through a connector.

[0028] This application also provides an electronic device, which includes a circuit board and the chip packaging structure provided in any of the foregoing possible implementation manners, and the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic plan view of a chip packaging structure provided by an embodiment of this application;

[0030] Figure 2 It is Figure 1 a schematic cross-sectional view along the position of AA';

[0031] Figure 3a It is a schematic plan view of a chip packaging structure provided in the prior art;

[0032] Figure 3b It is Figure 3b a cross-sectional view of;

[0033] Figure 4 It is a schematic plan view of a chip packaging structure provided by an embodiment of this application;

[0034] Figure 5 It is a schematic plan view of a chip packaging structure provided by an embodiment of this application;

[0035] Figure 6 It is a schematic plan view of a chip packaging structure provided by an embodiment of this application;

[0036] Figure 7 It is a schematic structural view of a connector provided by an embodiment of this application;

[0037] Figure 8 It is a schematic view of a chip packaging structure provided by an embodiment of this application;

[0038] Figure 9 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0039] Figure 10 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0040] Figure 11 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0041] Figure 12 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0042] Figure 13 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0043] Figure 14 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0044] Figure 15 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0045] Figure 16 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0046] Figure 17 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0047] Figure 18 Schematic diagram of a chip packaging structure provided by an embodiment of the present application during the manufacturing process;

[0048] Figure 19 Schematic diagram of a chip packaging structure provided by an embodiment of the present application during the manufacturing process;

[0049] Figure 20 Schematic diagram of a chip packaging structure provided by an embodiment of the present application during the manufacturing process;

[0050] Figure 21 Schematic diagram of a chip packaging structure provided by an embodiment of the present application during the manufacturing process;

[0051] Figure 22 Schematic diagram of a chip packaging structure provided by an embodiment of the present application during the manufacturing process;

[0052] Figure 23 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0053] Figure 24Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0054] Figure 25 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0055] Figure 26 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0056] Figure 27 Schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0057] Figure 28 Schematic diagram of a chip packaging structure provided by an embodiment of the present application. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0059] In the description embodiments, claims and drawings of the present application, terms such as "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Here, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" means one or more, and "a plurality" means two or more. Understandings of terms such as "installation", "connection", "coupling", etc. should be broad. For example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a communication inside two components. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. Terms such as "upper", "lower", "left", "right", etc. are only relative to the orientation of the components in the drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly with the change of the orientation of the components placed in the drawings.

[0060] An embodiment of the present application provides an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. The present application does not limit this.

[0061] Illustratively, the above-mentioned consumer electronics products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (such as smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can be smart door locks, TVs, smart speakers, refrigerators, floor cleaning robots, etc. Vehicle-mounted electronics products can be vehicle-mounted navigators, vehicle-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service business handling, etc. Communication electronics products can be communication devices such as servers, memories, radars, base stations, etc.

[0062] The above-mentioned electronic devices include a printed circuit board (PCB; also known as a printed wiring board) and a chip package structure electrically connected to the circuit board. The chip package structure adopts a new structure, which can meet the requirement of welding a connector and a die on the same side of an interposer. Illustratively, the chip package structure of the present application can be a system-in-package structure.

[0063] The chip package structure of the present application can realize the layout of connectors on both the front and back sides of the interposer, which can double the number of connector layouts and double the system data external transmission capacity. In addition, the layout of connectors on both the front and back sides of the interposer also avoids the problem of increased cost caused by increasing the area of the interposer, and the problem of signal attenuation caused by the increased distance between input / output dies (IO dies) and connectors.

[0064] The present application does not limit the application scenarios of the above-mentioned chip package structure. For example, the chip package structure can be applied in scenarios such as large servers, high-bandwidth switches, supercomputers for AI computing, etc.

[0065] The following specifically describes the chip package structure provided by the present application through specific embodiments.

[0066] Embodiment 1

[0067] Figure 1 This is a schematic plan view of a chip package structure provided for Embodiment 1. Figure 2 For Figure 1 a cross-sectional schematic view along the AA' position.

[0068] Illustratively, asFigure 1 and Figure 2 As shown in Figure 2 , this embodiment provides a chip packaging structure, which includes an interposer 10, at least one chip D, one or more connectors C, and one or more first connectors 21. Among them, the chip D, the connector C, and the first connector 21 are arranged on the same layer of the interposer 10.

[0069] Figure 1 In Figure 1 , only an example is given where the chip packaging structure is provided with multiple chips D, multiple first connectors 21, and multiple connectors C for illustration. Additionally, Figure 1 The distribution method of the shown chip D array is only a reference. In reality, multiple chips D can adopt different distribution methods according to needs, and the types of the D chips themselves can also be composed of multiple chip types. Figure 2 In Figure 2 , the small-sized chips around the large-sized chip array are omitted, and the same applies to the subsequent drawings. Figure 1 Figure 1

[0070] The above-mentioned multiple chips D can be a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output chip (IO die), an integrated passive device (IPD), etc., or can also be integrated with other pre-packaged functional modules, such as HBM (high bandwidth memory), DOI (die on silicon interposer), FOI (fan out RDL interpose), etc. In practice, multiple chips D can be set according to needs.

[0071] Schematically, referring to Figure 1 As shown in Figure 1 , the multiple chips D in the chip packaging structure can include: multiple first chips D1 with larger sizes and multiple second chips D2 with smaller sizes. The multiple first chips D1 can be located in the central area of the interposer 10, and the multiple second chips D2 can be distributed around the multiple first chips D1. Among them, the multiple first chips D1 can be chips in the fields of logic, computing, data exchange, etc., and the multiple second chips D2 can be input / output chips (i.e., IO chips), integrated passive devices (IPD), etc., but this application is not limited thereto.

[0072] Schematically, referring to Figure 1 and Figure 2As shown, multiple chips D and multiple connectors C are arranged on the upper surface of the adapter board 10 and are electrically connected to the adapter board 10. The first connector 21 is arranged above the connector C (i.e., on the side far from the adapter board 10) and is connected to the top of the connector C. That is, the bottom of the connector C is connected to the adapter board 10, the top of the connector C is connected to the first connector 21, and the first connector 21 is electrically connected to the adapter board 10 through the connector C. In this case, multiple connectors C and multiple chips D can be encapsulated in the encapsulation layer M1. The tops of multiple connectors C can be flush with the tops of multiple chips D and exposed from the encapsulation layer M1. The connector C, as an intermediate connection structure, can lead out signals to the first connector 21 above to ensure that the first connector 21 can transmit the signals of the chip D (such as the IO die) outward through the connector C and the adapter board 10, thus solving various problems in the prior art caused by the inability to mount the connector and the chip on the same side of the adapter board.

[0073] It should be noted that the first connector 21 and the top of the connector C can be directly connected or connected through other connecting parts. For example, the first connector 21 can be connected to the top of the connector C through a substrate (which can also be called a connector substrate). This application does not limit this, and it can be set according to actual needs in practice.

[0074] The substrate involved in this application can be made by one or several of the substrate process, the substrate-like carrier process, the printed circuit board (PCB) process, or other intermediate transition board processes. This application does not limit this.

[0075] This application does not limit the specific positions of the chip D and the connector C on the upper surface of the adapter board 10, and it can actually be set according to needs. For example, in some possible implementation manners, the connector C can be arranged in the edge area of the adapter board 10.

[0076] On this basis, in order to realize the layout of connectors on both the front and back sides of the adapter board 10, as Figure 2 shown, in some possible implementation manners, the chip packaging structure can further include one or more second connectors 22. The second connectors 22 are located below the adapter board 10 and are directly connected to the lower surface of the adapter board 10 or connected through the substrate 30. In this way, by arranging the first connector on the front side of the adapter board 10 and the second connector 22 on the back side, the layout quantity of the connectors (21, 22) can be doubled, and the ability of the system to transmit data externally can be doubled. At the same time, arranging multiple connectors (21, 22) on both the front and back sides of the adapter board 10 also avoids the problem of increased cost caused by increasing the area of the adapter board 10 and the problem of signal attenuation caused by the increased distance between the chip D and the connectors (21, 22).

[0077] Schematically, taking the example where 16 connectors need to be provided in the chip packaging structure.

[0078] Figure 3a and Figure 3b are the plan and sectional views of the existing technology for single-sided surface mounting of connectors on the back of the adapter board. Refer to Figure 3a and Figure 3b As shown, in the existing technology, setting all 16 connectors on the back of the adapter board will cause an increase in the area of the adapter board and also an increase in the distance between the connectors and the chip D.

[0079] In contrast, referring to Figure 1 and Figure 2 As shown, in the present application, 16 connectors can be arranged on the front and back sides of the adapter board 10. Eight first connectors 21 can be arranged on the front side of the adapter board 10, and eight second connectors 22 can be arranged on the back side of the adapter board 10. This not only reduces the area of the adapter board and the cost, but also shortens the distance between the chip D and the connectors (21, 22), making the signal transmission better.

[0080] Of course, when the number of connectors in the chip packaging structure is small, in some possible implementation manners, only the foregoing first connectors 21 can be provided on the same side of the chip D in the chip packaging structure to meet the signal transmission requirements. The following embodiments are all described by taking the example of arranging connectors on both the front and back sides of the adapter board 10.

[0081] The following describes the related settings of the above-mentioned connector C.

[0082] First, in the chip packaging structure, the connection between the connector C and the first connector 21 can be a one-to-one setting manner or a one-to-many setting manner, and the present application does not limit this.

[0083] For example, as Figure 4 shown, in some possible implementation manners, in the chip packaging structure, different connectors C can be provided for different first connectors 21, that is, different first connectors 21 are respectively electrically connected to the adapter board 10 through different connectors C.

[0084] Again, for example, as Figure 5 shown, in some possible implementation manners, in the chip packaging structure, different connectors C can be provided on different sides of the adapter board 10. In this case, multiple first connectors 21 on the same side can be electrically connected to the adapter board 10 through the same connector C.

[0085] Again, for example, as Figure 6As shown, in some possible implementations, in a chip packaging structure, only one connector C can be provided, and all the first connectors 21 are electrically connected to the adapter board 10 through the same connector C. Schematically, the connector C can be a ring structure (or a frame structure).

[0086] It should be understood that Figure 4 、 Figure 5 、 Figure 6 only 8 first connectors 21 located on the front side of the adapter board 10 and on the same side as the chip D are schematically shown. One or more second connectors 22 can be provided on the back side of the adapter board 10 according to actual requirements. For example, 8 second connectors 22 can be provided on the back side of the adapter board 10.

[0087] In addition, for the structure of the connector C itself, its main feature is that an electrical connection structure is formed between the bottom and the top, and there is no restriction on its constituent materials. For example, a metal connection structure with a metallization design can be adopted. There are various ways to implement such a connector C. For example, it can be a combination of a plate and a via process, a through glass via (TGV) process, etc.

[0088] Schematically, as Figure 7 shown, in some possible implementations, the connector C includes a support plate 301. A first metal connection structure P1 is provided on the top of the support plate 301, a second metal connection structure P2 is provided on the bottom, and an intermediate metal connection structure 302 is provided inside the support plate 301. The first metal connection structure P1 is connected to the second metal connection structure P2 through the intermediate metal connection structure 302. In this case, the connector C can be connected to the first connector 21 through the first metal connection structure P1 and connected to the adapter board 10 through the second metal connection structure P2, so that the first connector 21 is electrically connected to the adapter board 10 through the connector C.

[0089] Schematically, the above-mentioned first metal connection structure P1 and second metal connection structure P2 can be metal pads or metal posts, but are not limited thereto, and can be set according to actual needs in practice.

[0090] Schematically, the above-mentioned intermediate metal connection structure 302 can be a copper via or multi-layer metal traces, but are not limited thereto, and can be set according to actual needs in practice.

[0091] For example, in some embodiments, the first metal connection structure P1 and the second metal connection structure P2 can be copper posts or copper pads, and the intermediate metal connection structure 302 can be a copper via.

[0092] In addition, referring to Figure 2As shown, in the process of manufacturing the chip packaging structure, it is usually necessary to use a thermosetting material to fill the bottoms and gaps of multiple chips D and multiple connectors C, and after filling, the back surface of the chip D and the connection structures (such as pads) on the surface of the connector C can be exposed by grinding to form a molding layer M1 to protect the multiple chips D and multiple connectors C. In this case, the upper surfaces of the multiple chips D and the multiple connectors C (i.e., the surfaces on the side away from the adapter board 10) are flush.

[0093] Of course, the filling of the bottoms and gaps of the multiple chips D and the multiple connectors C can be a single filling process or a two - filling process. This application does not limit this, and it can be set according to actual needs in practice.

[0094] The thermosetting materials involved in this application can include underfill (UF), molded under fill (MUF), epoxy molding compound, etc. The thermosetting materials in the following text are all like this and will not be elaborated further.

[0095] In addition, according to actual requirements, as Figure 2 shown, on the side of the adapter board 10 where the second connector 22 is set, the chip packaging structure can also be provided with multiple electronic components 20, and the electronic components 20 are directly connected to the adapter board 10 or connected through a substrate 30.

[0096] The above - mentioned multiple electronic components 20 can be a power supply module, a control module, a connector, a clock device, a rectifier, resistors, capacitors, inductors, etc. Among them, the power supply module can be a VRM (voltage regulator module) or other related modules for electrical transmission, voltage transformation, rectification, etc.; the connector can be an electrical connector for transmitting electrical signals or an optoelectronic conversion connector for transmitting optical signals. In practice, the multiple electronic components 20 can be set according to actual needs.

[0097] Schematically, in some possible implementation manners, among the multiple electronic components 20 below the adapter board 10, there can be multiple power supply modules. The multiple power supply modules are respectively arranged opposite to the multiple chips above, that is, the multiple power supply modules are respectively located directly below the multiple chips, or the projection of the power supply module and the relatively - arranged chip on the adapter board 10 overlaps (partially or completely), and the multiple power supply modules are electrically connected to the multiple chips D above through the adapter board 10, so that the power supply modules can respectively supply power vertically to the chips D located above.

[0098] This application does not limit the connection method between the electronic component 20, the second connector 22 and the adapter board 10. The electronic component 20 and the second connector 22 can be directly connected to the adapter board 10, or can be indirectly connected through other components such as a substrate or a printed circuit board (PCB), etc. In practice, it can be set according to needs.

[0099] To meet the electrical requirements of different devices, in some possible implementation manners, such as Figure 8 As shown, multiple discrete substrates 30 can be adopted below the adapter board 10, and the number of layers and specifications of the multiple substrates 30 may not be completely the same. In this case, multiple electronic components 20 and multiple second connectors 22 can be connected to the redistribution layer RDL through the multiple discrete substrates 30. This application does not limit this, and it can be set according to needs in practice. For example, one electronic component 20 or one second connector 22 can be installed on a single substrate 30, or multiple electronic components 20 or multiple second connectors 22 can be installed, or both the electronic component 20 and the second connector 22 can be installed at the same time.

[0100] By setting multiple discrete substrates 30, the types of the multiple substrates 30 can be flexibly selected according to the electrical requirements of the devices (20, 22) to improve the performance of the entire system. For example, only the electronic components 20 that require complex multi-layer substrates can be configured with multi-layer substrates, while the electronic components 20 that require simple substrates can be configured with simple substrates.

[0101] In addition, adopting multiple discrete substrates 30 can also relieve the mechanical stress caused by thermal mismatch in the assembly and service scenarios of a large continuous substrate, which is more friendly to the system assembly and service reliability.

[0102] This application does not limit the electrical connection method between the substrate 30 and the adapter board 10, and it can be set according to needs in practice.

[0103] Schematically, in some possible implementation manners, one or a combination of connection methods such as welding, crimping, and plugging can be used to connect the multiple substrates 30 and the adapter board 10.

[0104] The multiple substrates 30 can be made by using one or several of a substrate process, a substrate-like carrier process, a printed circuit board (PCB) process, or other intermediate transition board processes. This application does not limit this.

[0105] On this basis, such as Figure 8As shown, in some possible implementations, a thermosetting material can be used to fill the bottoms of the multiple substrates 30 and the gaps, and after filling, the back surfaces of the substrates 30 and the connection structures (such as Cu Stud) can be exposed by grinding to form a molding layer M2 to protect the multiple substrates 30.

[0106] In addition, in some possible implementations, such as Figure 8 As shown, a first heat sink 41 and a second heat sink 42 can also be provided in the chip packaging structure. Among them, the first heat sink 41 is provided on the side of the multiple chips D away from the adapter board 10, and the second heat sink 42 is provided on the side of the multiple electronic components 20 away from the adapter board 10. By providing two heat sinks (41, 42), the heat dissipation of the chip packaging structure can be satisfied.

[0107] Schematically, the gap between the chip D and the first heat sink 41 can be filled with a thermal interface material (TIM, thermal interface materials). Among them, the TIM can be a heat dissipation medium such as thermal gel, thermal grease, graphene, liquid metal, etc., and there is no restriction here. Similarly, the gap between the electronic component 20 and the second heat sink 42 can also be filled with TIM.

[0108] This application does not limit the setting form of the heat sinks (41, 42), and can be set according to actual needs.

[0109] For example, in some possible implementations, the heat sinks (41, 42) can be metal covers.

[0110] For another example, in some possible implementations, the heat sinks (41, 42) can be hollow structures to support the heat dissipation methods of water cooling or liquid cooling.

[0111] For another example, the heat sinks (41, 42) can be provided with hollow structures such as through-hole structures and grids. In this case, while meeting the heat dissipation requirements, the heat sinks can support the external power supply system to be vertically interconnected with the electrical components 20 on the back of the chip through the hollow areas.

[0112] In the packaging structure, the thickness, material, and structure of the first heat sink 41 and the second heat sink 42 can be the same or different, and this application does not limit this.

[0113] In addition, referring to Figure 8 As shown, in some possible implementations, in order to ensure the balanced force inside the chip packaging structure, a support frame 43 can be provided in the chip packaging structure. The support frame 43 is located in the gap between the electronic components 20, and the upper end of the support frame 43 can be in contact with the substrate 30, and the lower end can be in contact with the second heat sink 42.

[0114] On this basis, in order to fix the first heat dissipation plate 41, the second heat dissipation plate 42 and the encapsulation system, as Figure 8 shown, in some possible implementation manners, a fixing structure 50 may be provided in the chip packaging structure. The fixing structure 50 penetrates through the first heat dissipation plate 41, the second heat dissipation plate 42 and the adapter board 10, and clamps and fixes the first heat dissipation plate 41, the second heat dissipation plate 42 and the adapter board 10.

[0115] Illustratively, as Figure 8 shown, in some possible implementation manners, the above-mentioned fixing structure 50 may include a bolt and a nut. The bolt penetrates through the first heat dissipation plate 41, the second heat dissipation plate 42 and the adapter board 10, and a nut is fixed at one end of the bolt, so as to realize the clamping and fixing of the first heat dissipation plate 41, the second heat dissipation plate 42 and the adapter board 10. In this case, the first heat dissipation plate 41 and the second heat dissipation plate 42 can not only play a role in heat dissipation, but also play a role in stabilizing the structure.

[0116] In addition, the present application does not limit the setting manner of the adapter board 10 in the chip packaging structure, and it can be set according to actual needs.

[0117] The following provides the adapter board 10 with a variety of different setting structures.

[0118] Setting structure one of the adapter board 10

[0119] Illustratively, as Figure 9 shown, in some possible implementation manners, the adapter board 10 may include a silicon interposer 1 (Si interposer) and a redistribution layer RDL (redistribution layer).

[0120] Referring to Figure 9 shown, the silicon interposer 1 (Si interposer) includes a silicon wafer a1 (wafer) and a metal wiring layer a2 provided on the surface of the silicon wafer a1 (the surface away from the RDL side). A plurality of through-silicon vias TSV (through silicon via) are provided in the silicon wafer a1. The metal wiring layer a2 is connected to the plurality of through-silicon vias TSV.

[0121] Illustratively, the line width, line pitch, and line thickness of the metal wiring in the metal wiring layer a2 may be less than 5 μm.

[0122] Illustratively, the aperture of the plurality of through-silicon vias TSV may be in the range of 1 μm to 30 μm.

[0123] Illustratively, the thickness of the silicon interposer 1 (Si interposer) may be in the range of 5 μm to 200 μm.

[0124] In the application, in the application, the front side of the silicon interposer is the surface on the side where the metal wiring layer a2 is provided. The back side of the silicon interposer is the surface of the silicon wafer a1 on the side where the metal wiring layer a2 is not provided, that is, the back side of the silicon wafer a1 (the surface far from the metal wiring layer a2).

[0125] The above-mentioned redistribution layer RDL (redistribution layer) is located on the back side of the silicon wafer a1 (wafer) (that is, the surface far from the metal wiring layer a2), and the redistribution layer RDL is connected to the metal wiring layer a2 through a plurality of through-silicon vias TSVs in the silicon wafer a1. The line width, line pitch, and line thickness of the metal wiring in the redistribution layer RDL can be greater than 5 μm.

[0126] A plurality of chips D are arranged on the upper surface of the silicon interposer and are electrically connected to the metal wiring layer a2.

[0127] The edge of the redistribution layer RDL can extend beyond the edge of the silicon interposer 1. A plurality of connectors C are arranged on the surface of the redistribution layer RDL around the silicon interposer and are electrically connected to the redistribution layer RDL. In this case, the first connector 21 is electrically connected to the redistribution layer RDL through the connector C.

[0128] It should be understood that in this application, a power supply or signal transmission path to the back side of the wafer can be provided for the chip D through the connector C. According to actual needs, other electronic devices (such as a power supply module, etc.) can also be arranged to be electrically connected to the redistribution layer RDL through the connector C. A plurality of electronic components 20 and a plurality of second connectors 22 are arranged below the redistribution layer RDL and are connected to the redistribution layer RDL through different substrates 30.

[0129] In this case, referring to Figure 9 as shown, the signal transmission path between the chip D and the first connector 21 is: chip D → silicon interposer → redistribution layer RDL → connector C → connector substrate (optional, Figure 9 not shown in the figure) → first connector 21. The signal transmission path between the chip D and the second connector 22 is: chip D → silicon interposer → redistribution layer RDL → connector substrate 30 (optional) → second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0130] The following gives a simple description of the related settings of the metal wiring layer a2 and the redistribution layer RDL.

[0131] The metal wiring layer a2 on the surface of the silicon interposer 1 can be processed by a silicon-based process, so that the line width, line pitch, and line thickness of the metal wiring in the metal wiring layer a2 are less than 5 μm, so as to meet the high-bandwidth density interconnection requirements between multiple chips D, such as an interconnection bandwidth density of more than 2 Tbps / mm.

[0132] Illustratively, in some possible implementation manners, the metal wiring layer a2 can be implemented by a damascene process including processes such as deposition, exposure, etching, electroplating, and chemical mechanical polishing (CMP).

[0133] Illustratively, the line width / line pitch / line thickness in the metal wiring layer a2 can reach 0.4 μm, and the number of layers can be processed to more than 3 layers.

[0134] Illustratively, the wiring layer in the metal wiring layer a2 can use copper (Cu), but is not limited thereto.

[0135] Illustratively, the dielectric layer in the metal wiring layer a2 can use one or more of insulating dielectric materials such as polyimide (PI), polybenzoxazoles (PBO), silicon dioxide SiO 2 , silicon nitride SiN, silicon carbonitride SiCN, etc., but is not limited thereto.

[0136] The above-mentioned redistribution layer RDL can use a thick metal layer and a thick dielectric layer with better current sharing ability. For example, the line width / line pitch / line thickness of the redistribution layer RDL can be more than 5 μm, so as to meet the high-speed serdes (serializer / deserializer) driving requirements of the electronic component 20 for large current sharing ability, low impedance, and long distance (such as more than 5 mm).

[0137] Illustratively, in some possible implementation manners, the redistribution layer RDL can be implemented by a yellow light process including processes such as coating / glue laminating, exposure, development, and curing.

[0138] Illustratively, the wiring layer in the redistribution layer RDL can use copper (Cu), but is not limited thereto.

[0139] Illustratively, the dielectric layer in the redistribution layer RDL can use one or more of dielectric materials such as polyimide-based polymers (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but is not limited thereto.

[0140] The setting structure two of the interposer 10

[0141] Schematically, such as Figure 10 As shown, in some possible implementation manners, the adapter board 10 may include: a first redistribution layer RDL1 and a second redistribution layer RDL2. The first redistribution layer RDL1 is closer to the chip D side than the second redistribution layer RDL2.

[0142] A plurality of chips D and a plurality of connectors C are both disposed on the upper surface of the first redistribution layer RDL1 (i.e., the surface on the side away from the second redistribution layer RDL2), and are electrically connected to the first redistribution layer RDL1. The first connector 21 is electrically connected to the first redistribution layer RDL1 through the connector C.

[0143] A plurality of electronic components 20 and a plurality of second connectors 22 are located below the second redistribution layer RDL2 (i.e., on the side away from the first redistribution layer RDL1), and are respectively electrically connected to the second redistribution layer RDL2 through different substrates 30.

[0144] In this case, referring to Figure 10 As shown, the signal transmission path between the chip D and the first connector 21 is: chip D → first redistribution layer RDL1 → connector C → connector substrate (optional, Figure 10 not shown in the figure) → first connector 21. The signal transmission path between the chip D and the second connector 22 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0145] The following is a simple description of the above-mentioned first redistribution layer RDL1 and second redistribution layer RDL2.

[0146] The first redistribution layer RDL1 may adopt a thin metal layer and a thin dielectric layer. For example, the line width / line pitch / line thickness may be below 5 μm. In this case, in the area of the bridge chip BG, the first redistribution layer RDL1 can lead out the pads on the surface of the bridge chip BG, and the high-bandwidth density interconnection requirements between the chips D can be met through the bridge chip BG.

[0147] Schematically, the first redistribution layer RDL1 may be implemented by a damascene process including deposition, exposure, etching, electroplating, and CMP.

[0148] The second redistribution layer RDL2 may be provided with a thick metal layer and a thick dielectric layer for the redistribution layer RDL. For example, the line width / line pitch / line thickness may be above 5 μm, so as to meet the requirements of large current sharing and long trace capabilities of the electronic components 20.

[0149] Illustratively, the wiring layers in the first redistribution layer RDL1 and the second redistribution layer RDL2 can be made of copper (Cu), but are not limited thereto.

[0150] Illustratively, the second redistribution layer RDL2 can be realized by a yellow light process including coating / resist film application, exposure, development, and curing.

[0151] Illustratively, the dielectric layers in the first redistribution layer RDL1 and the second redistribution layer RDL2 can be made of one or more of dielectric materials such as polyimide polymer (polyimide, PI), benzocyclobutene (benzocyclobutene, BCB), polybenzoxazole (polybenzoxazole, PBO), etc., but are not limited thereto.

[0152] The setting structure three of the adapter board 10

[0153] Illustratively, as Figure 11 shown, in some possible implementation manners, the adapter board 10 can be similar to the adapter board in the setting structure two, and the difference is only that the edge of the second redistribution layer RDL2 extends beyond the edge of the first redistribution layer RDL1. In this case, the connector C can be disposed on the surface of the second redistribution layer RDL2 around the first redistribution layer RDL1.

[0154] Other related settings can be referred to the description in the setting structure two correspondingly, and will not be elaborated here.

[0155] In this setting manner, referring to Figure 11 shown, the signal transmission path between the chip D and the first connector 21 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → connector C → connector substrate (optionally, Figure 11 not shown in the figure) → first connector 21. The signal transmission path between the chip D and the second connector 22 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → connector substrate 30 (optionally) → second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0156] The setting structure four of the adapter board 10

[0157] Illustratively, as Figure 12 shown, in some possible implementation manners, the adapter board 10 can include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a molding interposer 100.

[0158] The settings of the first redistribution layer RDL1 and the second redistribution layer RDL2 are basically the same as those in the setting structure two, and can be specifically referred to the corresponding description in the setting structure two, which will not be elaborated here.

[0159] The molded interposer 100 includes at least one bridge die BG encapsulated in a molding layer and a plurality of metal pillars P (such as copper pillars, Cu posts). The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the bridge die BG and the metal pillars P. According to actual needs, through-silicon vias can be provided in the bridge die BG and are electrically connected to the second redistribution layer RDL2 through the through-silicon vias.

[0160] It should be understood that the structure of the bridge die BG is similar to that of the aforementioned Si interposer. Since the bridge die BG can be fabricated by a silicon-based process, the line width / line pitch / line thickness can meet the high-bandwidth density interconnection requirements between multiple chips D. In this setting mode, referring to Figure 12 as shown, the signal transmission path from the chip D to the first connector 21 is: chip D → first redistribution layer RDL1 → metal pillar P → connector C → connector substrate (optional, Figure 12 not shown in the figure) → first connector 21. The signal transmission path from the chip D to the second connector 22 is: chip D → first redistribution layer RDL1 → metal pillar P → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. In this way, the data inside the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0161] The setting structure five of the adapter board 10

[0162] Schematically, as Figure 13 shown, this adapter board 10 is similar to the adapter board in the setting structure four, and the only difference is that the edge of the second redistribution layer RDL2 extends beyond the edge of the first redistribution layer RDL1. In this case, the connector C can be provided on the surface of the second redistribution layer RDL2 exposed around the first redistribution layer RDL1.

[0163] In this setting mode, referring to Figure 13 as shown, the signal transmission path from the chip D to the first connector 21 is: chip D → first redistribution layer RDL1 → molded interposer 100 → second redistribution layer RDL2 → connector C → connector substrate (optional, Figure 13 not shown in the figure) → first connector 21. The signal transmission path from the chip D to the second connector 22 is: chip D → first redistribution layer RDL1 → molded interposer 100 → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. In this way, the data inside the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0164] The setting structure six of the adapter board 10

[0165] Schematically, as Figure 14 shown, the interposer 10 may include: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200.

[0166] The settings of the first redistribution layer RDL1 and the second redistribution layer RDL2 are basically the same as those in the second setting structure. For specific details, reference can be made to the corresponding description in the second setting structure, which will not be elaborated here.

[0167] The glass interposer 12 includes a plurality of through glass vias (TGV) and at least one bridge die (BG). Among them, the bridge die BG is embedded in a groove formed on the glass wafer. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the bridge die BG and the through glass vias (TGV).

[0168] It should be understood that the bridge die BG is similar in structure to the aforementioned Si interposer. Since the bridge die BG can be fabricated by a silicon-based process, the line width / line pitch / line thickness can meet the high-bandwidth density interconnection requirements between multiple chips D.

[0169] Of course, as another possible implementation, as Figure 15 shown, the bridge die BG may not be provided in the glass interposer 12, and only the through glass vias (TGV) are provided.

[0170] In this setting mode, referring to Figure 14 and Figure 15 shown, the signal transmission path from the chip D to the first connector 21 is: chip D → first redistribution layer RDL1 → connector C → connector substrate (optional, Figure 14 , 15 not shown in the figure) → first connector 21. The signal transmission path from the chip D to the second connector 22 is: chip D → first redistribution layer RDL1 → through glass via (TGV) → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. In this way, the data inside the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the interposer 10.

[0171] The seventh setting structure of the interposer 10

[0172] Schematically, as Figure 16 , Figure 17 shown, this interposer 10 is similar to the interposer in the fourth setting structure, and the only difference is that the edge of the second redistribution layer RDL2 extends beyond the edge of the first redistribution layer RDL1. In this case, the connector C can be disposed on the surface of the second redistribution layer RDL2 exposed around the first redistribution layer RDL1.

[0173] In this setting mode, as Figure 16 , Figure 17 shown, the signal transmission path between the chip D and the first connector 21 is: chip D → the first redistribution layer RDL1 → the through-glass via TGV → the second redistribution layer RDL2 → the linker C → the connector substrate (optional, Figure 16 , 17 not shown in

[0174] this figure) → the first connector 21. The signal transmission path between the chip D and the second connector 22 is: chip D → the first redistribution layer RDL1 → the through-glass via TGV → the second redistribution layer RDL2 → the connector substrate 30 (optional) → the second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0175] Additionally, for the chip package structures with different structures provided in the foregoing embodiments, a suitable process can be selected according to requirements for fabrication. This application does not limit this. Figure 9 Schematically, the fabrication method of the chip package structure in

[0176] is described below, and the specific process steps can be as follows:

[0177] 1. Chip preparation: The chips D with different functions can include: single chips such as CPU, GPU, memory, IO die, IPD, etc., or can also use package modules such as HBM, DOI, FOI, etc. that have been completed with package integration. Cut into single chip particles, and there are micro solder bumps (micro bump) for interconnection on the front side of the chip, and the bump pitch can be 20μm to 200μm.

[0178] First, as shown in (a) of Figure 18 , provide a silicon wafer a1 (wafer), fabricate multiple through-silicon vias TSV in the silicon wafer a1, and use the damascene process including processes such as deposition, exposure, etching, electroplating, CMP, etc. to fabricate a metal wiring layer a2, etc. on the surface of the silicon wafer a1 to form a silicon interposer; among them, micro pads are fabricated on the surface of the metal wiring layer a2. Of course, according to actual needs, active devices, DTC (deep trench capacitor), MIM (metal-insulator-metal) capacitors, etc. can be fabricated in the silicon interposer.

[0179] Next, refer to Figure 18As shown in (b) of the figure, the above-mentioned silicon interposer is temporarily bonded to the first carrier 01 on the side of the metal wiring layer a2.

[0180] The carrier boards involved in this application (such as the first carrier board, the second carrier board, the third carrier board, the fourth carrier board, etc.) can be supports such as metal plates, glass, etc., and this application does not limit this, and can be set according to needs in practice.

[0181] The temporary bonding involved in this application can all be carried out through temporary bonding glue, but it is not limited to this, and can be set according to needs in practice.

[0182] Next, refer to Figure 18 As shown in (b) of the figure, the back surface of the silicon wafer a1 is thinned to expose the through-silicon vias TSV. The specific process can include: rough grinding - chemical mechanical polishing (CMP) - Si etching (etch) to expose copper - deposition of insulating dielectric material - CMP to expose copper, etc.

[0183] Next, refer to Figure 18 As shown in (c) of the figure, the side of the silicon interposer (Siinterposer) that exposes the through-silicon vias TSV is temporarily bonded to the second carrier 02, and the first carrier 01 is debonded to expose the micro pads on the surface of the metal wiring layer a2.

[0184] The debonding separation involved in this application can be laser debonding, thermal debonding, etc., but it is not limited to this, and can be set according to needs in practice.

[0185] 3. DOI (die on silicon interposer, silicon interposer module) post-chip (chip last) process:

[0186] First, refer to Figure 19 As shown in (a) of the figure, a plurality of chips D (such as CPU, GPU, memory, IO die, IPD or HBM chips and chip modules) are mounted on the front surface of the silicon interposer (Siinterposer), and the chips D are connected to the micro pads on the surface of the metal wiring layer a2 through micro solder bumps.

[0187] Next, refer to Figure 19 As shown in (a) of the figure, a thermal curing material is used to fill the bottom and gaps of the plurality of chips D, and then the encapsulant is ground. Among them, the thermal curing material can include underfill, molding compound, molding underfill, etc.

[0188] Next, referring to Figure 19 as shown in (b) of , the second carrier 02 is debonded from the silicon interposer, and a dicing tape is attached; then, it is cut by a blade saw to form individual DOI units.

[0189] 4. FOP (fan out RDL interpose, RDL transfer board module) chip first process:

[0190] First, a connector C is provided. The main feature of the connector C is that an electrical connection structure is formed between the bottom and the top. For the specific setting of the connector C, reference can be made to the relevant description in the previous text.

[0191] Then, referring to Figure 20 as shown in (a) of , the DOI units formed by the foregoing process and a plurality of connectors C are mounted on a third carrier 03 (such as a metal carrier).

[0192] Next, referring to Figure 20 as shown in (b) of , a secondary encapsulation is performed using a thermosetting material to wrap the DOI units and a plurality of connectors C as a whole, and the gap between the chip and the connectors C is filled; then, the encapsulant is ground to thin the chip D and the connectors C, and the connection structure (such as Cu Stud) on the back of the chip D and the connectors C is exposed.

[0193] Next, referring to Figure 20 as shown in (c) of , the back of the chip D can be temporarily bonded to the fourth carrier 04, and the third carrier 03 is debonded. Of course, in some other possible implementation manners, the fourth carrier 04 may not be required, and the third carrier 03 can be directly debonded.

[0194] Next, referring to Figure 21 as shown in (a) of , a redistribution layer RDL is fabricated on the side of the silicon wafer a1 where the through-silicon vias TSVs are exposed to lead out the signals of the through-silicon vias TSVs. Among them, the number of wiring layers in the redistribution layer RDL can be increased to 3 to 6 layers. The manufacturing process flow of a single wiring layer can include: surface pretreatment, organic material coating - exposure - development - curing - seed layer deposition - organic material coating - exposure - development - electroplating - photoresist removal - seed layer etching, etc.; after the last wiring layer is completed, a metal pad is processed as an interface for subsequent external interconnection.

[0195] Next, referring to Figure 21As shown in (b), use laser or mechanical means to process a through-hole K on the interposer system, so as to form a reliable mechanical support by passing through the through-hole K with a fixing structure 50 (such as a bolt) during subsequent system assembly. Of course, the position of the through-hole K should reasonably avoid the chip layout position.

[0196] Next, remove the invalid areas of the interposer 10 and the encapsulation structure, and cut and separate the effective areas.

[0197] 5. Mounting and mechanical fixing of connectors and electronic components:

[0198] First, as shown in (a) of Figure 22 weld multiple substrates 30 to the pads exposed on the surface of the redistribution layer RDL. Among them, the multiple substrates 30 can be processed by the substrate process of the substrate factory or may be obtained by the process of the PCB board factory, and the morphologies, layers, and materials of different substrates 30 may be different, which depends on the electrical characteristics of the devices to which the substrates 30 need to be connected. Of course, according to actual needs, after welding the multiple substrates 30 to the pads on the surface of the redistribution layer RDL, in some possible implementation methods, a thermosetting material can be used to fill the bottoms of the multiple substrates 30 and the gaps between the substrates 30, and the multiple substrates 30 are encapsulated into the encapsulation layer M2 for protection. Of course, the encapsulation layer M2 is also opened at the position of the through-hole K.

[0199] Next, as shown in (a) of Figure 22 weld multiple electronic components 20 (such as functional modules such as power modules, clocks, and passive components) to the back of the multiple substrates 30, such as vertical power supply interconnection of the front chip can be achieved by welding multiple power modules.

[0200] Next, as shown in (a) of Figure 22 perform front and back assembly of the connectors. Assemble some connectors (22) to the back of the discrete substrate 30 at the reserved position on the back of the interposer by welding or crimping; assemble another part of the connectors (21) to the ports of the connector C on the front of the interposer by welding or crimping.

[0201] Next, as shown in (a) of Figure 22 a support frame 43 matching the size of the interposer system (i.e., the system containing multiple chips D, interposer 10, multiple connectors 21 and 22, multiple electronic components 20, and multiple substrates 30) can be used to support the interposer system.

[0202] Next, as shown in (a) of Figure 22As shown in (a), with the support of the support frame 43, the first heat sink 41 is mounted on one side of the chip D, and the second heat sink 42 is mounted on one side of the electronic component 20 in the hybrid adapter board system. The heat sinks (41, 42) and the support frame 43 are also perforated at the position where the through-hole K is provided in the adapter board system. The through-hole position is penetrated by bolts (50) through the adapter board system, the support frame 43, the first heat sink 41, and the second heat sink 42 and fixed. In this case, the heat sinks (41, 42) not only play a role in heat dissipation but also can play a role in stabilizing the structure. Of course, a thermal interface material can be filled between the back of the chip and the heat sink as needed, and the thickness can be in the range of 50 μm to 150 μm.

[0203] Next, components such as bolts and clamps are used to fasten the front heat sink, the plastic package structure, and the back heat sink, and finally a system-level package structure is obtained.

[0204] Embodiment 2

[0205] This Embodiment 2 provides another chip package structure. The main difference between this chip package structure and the chip package structure in Embodiment 1 lies in the setting method of the connector C. The following mainly describes the differences between this Embodiment 2 and Embodiment 1.

[0206] Reference Figure 23 As shown, in this Embodiment 2, the connector C is located on the side of the adapter board 10. The top of the connector C is flush with the top of the chip D. The first connector 21 is disposed above the connector C and connected to the top of the connector C. The bottom of the connector C extends downward to the back surface of the adapter board 10 (i.e., the surface on the side away from the chip D) and is electrically connected to the back surface of the adapter board 10 (i.e., the side where the electronic component 20 is provided) through the substrate 30. In this way, the first connector 21 realizes electrical connection with the adapter board 10 through the connector C.

[0207] In this case, multiple connectors C and multiple chips D can be respectively encapsulated through two plastic encapsulation processes, and the tops of multiple connectors C can be flush with the tops of multiple chips D and exposed from the plastic encapsulation layer. The connector C, as an intermediate connection structure, can lead out signals to the first connector 21 above to ensure that the first connector 21 can transmit the signals of the chip D (such as an IO die) outward through the connector C and the adapter board 10, thus solving various problems in the prior art where the connector and the chip cannot be mounted on the same side of the adapter board.

[0208] In this Embodiment 2, multiple chips D and the adapter board 10 are encapsulated and integrated together through a single plastic encapsulation process (molding), and then encapsulated with the side connector C through a secondary plastic encapsulation process (molding).

[0209] In addition, in the second embodiment, in order to implement the layout of the connectors on both the front and back sides of the adapter board 10, as Figure 23 shown, in some possible implementation manners, the chip packaging structure may further include one or more second connectors 22, which are located below the adapter board 10 and are directly connected to the lower surface of the adapter board 10 or connected through the substrate 30. In this case, after the substrate 30 extracts signals from the adapter board 10, a part of the signals is output to the second connector 22, and a part is output to the first connector 21 through the connector C.

[0210] By arranging the first connector on the front side of the adapter board 10 and the second connector 22 on the back side, the layout quantity of the connectors (21, 22) can be doubled, and the external data transmission capacity of the system can be doubled. At the same time, arranging multiple connectors (21, 22) on both the front and back sides of the adapter board 10 also avoids the problems of increased cost caused by increasing the area of the adapter board 10 and signal attenuation caused by the increased distance between the chip D and the connectors (21, 22).

[0211] In the second embodiment, the signal transmission path between the chip D and the first connector 21 is: chip D → adapter board 10 → connector substrate 30 → connector C → connector substrate 30 (optionally, Figure 23 not shown in the figure) → first connector 21. The signal transmission path between the chip D and the second connector 22 is: chip D → adapter board 10 → connector substrate 30 (optional) → second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on both the front and back sides of the adapter board 10.

[0212] Compared with the first embodiment in which the connector C is arranged on the surface of the adapter board 10, in the second embodiment of the present application, by arranging the connector C on the side surface of the adapter board 10, the area overhead of the adapter board 10 can be saved, thereby reducing the manufacturing cost.

[0213] In the second embodiment, the internal structure of the adapter board 10 is not limited, and it can be set according to actual needs in practice.

[0214] Illustratively, the internal structure of the adapter board 10 in the second embodiment may be similar to that in the first embodiment.

[0215] For example, refer to Figure 24As shown, in some possible implementations, the internal structure of the interposer 10 can be similar to "the first setting structure of the interposer 10" in Embodiment 1. The interposer 10 can include a silicon interposer 1 (Si interposer) and a redistribution layer RDL. In this Embodiment 2, the area of the redistribution layer RDL can be reduced, and the edge of the redistribution layer RDL can be flush or nearly flush with the edge of the silicon interposer 1. The connector C is disposed on the side surfaces of the silicon interposer 1 (Si interposer) and the redistribution layer RDL.

[0216] Schematically, referring to Figure 24 As shown, in the actual manufacturing process, multiple different chips D can be integrated with the interposer 10 (including the Si interposer and the RDL) through a molding process according to the requirements of the product; then, cutting is performed to form a unit. Next, the unit is secondarily molded with the connector C located on its side surface through a molding process, and after the surface is thinned and flattened, the terminals of the connector C (such as pads, Cu pillars, etc.) are exposed, and the first connector 21 is connected to the exposed terminals. In this case, in the finally formed package structure, the connector C is disposed on the side surfaces of the silicon interposer 1 (Si interposer) and the redistribution layer RDL, the edges of the silicon interposer 1 (Si interposer) and the redistribution layer RDL are flush, and the area is smaller than the area of the package outline.

[0217] Regarding other related settings of the silicon interposer 1 (Si interposer) and the redistribution layer RDL, reference can be made to "the first setting structure of the interposer 10" in Embodiment 1 and the related descriptions, which will not be elaborated here.

[0218] For another example, referring to Figure 25 As shown, in some possible implementations, the internal structure of the interposer 10 can be similar to "the second setting structure of the interposer 10" in Embodiment 1. The interposer 10 can include a first redistribution layer RDL1 and a second redistribution layer RDL2, and the edges of the first redistribution layer RDL1 and the second redistribution layer RDL2 are flush or nearly flush. The connector C is disposed on the side surfaces of the first redistribution layer RDL1 and the second redistribution layer RDL2.

[0219] In this setting method, multiple chips D and the interposer 10 (including RDL1 and RDL2) are integrated together through a molding process; then cutting is performed to form units. Next, the units and the connector C located on their sides are secondarily encapsulated through a molding process, and after the surface is thinned and flattened, the terminals of the connector C (such as pads, Cu pillars, etc.) are exposed, and the first connector 21 is connected to the exposed terminals. In this case, in the finally formed packaging structure, the connector C is arranged on the sides of the first redistribution layer RDL1 and the second redistribution layer RDL2, the edges of the first redistribution layer RDL1 and the second redistribution layer RDL2 are flush, and the area is smaller than the area of the packaging outline.

[0220] For other related settings of the first redistribution layer RDL1 and the second redistribution layer RDL2, reference can be made to "Setting Structure Two of the Interposer 10" and related descriptions in the first embodiment, which will not be elaborated here.

[0221] For another example, referring to Figure 26 As shown, in some possible implementation manners, the internal structure of the interposer 10 may be similar to "Setting Structure Four of the Interposer 10" in the first embodiment. The interposer 10 may include a first redistribution layer RDL1, a second redistribution layer RDL2, and a molding interposer layer 100 disposed between the first redistribution layer RDL1 and the second redistribution layer RDL2. The molding interposer layer 100 includes at least one bridge chip BG and multiple metal pillars P encapsulated in the molding layer. In this case, the edges of the first redistribution layer RDL1, the molding interposer layer 100, and the second redistribution layer RDL2 are flush or nearly flush, and the connector C is arranged on the side of the interposer 10 formed by the first redistribution layer RDL1, the molding interposer layer 100, and the second redistribution layer RDL2.

[0222] In this setting method, multiple chips D and the interposer 10 (including RDL1, 100, RDL2) are integrated together through a molding process; then cutting is performed to form units. Next, the units and the connector C located on their sides are secondarily encapsulated through a molding process, and after the surface is thinned and flattened, the terminals of the connector C (such as pads, Cu pillars, etc.) are exposed, and the first connector 21 is connected to the exposed terminals. In this case, in the finally formed packaging structure, the connector C is arranged on the sides of the first redistribution layer RDL1, the molding interposer layer 100, and the second redistribution layer RDL2, the edges of the first redistribution layer RDL1, the molding interposer layer 100, and the second redistribution layer RDL2 are flush, and the area is smaller than the area of the packaging outline.

[0223] Regarding the relevant settings of the first redistribution layer RDL1, the molding interposer 100, the second redistribution layer RDL2, the bridge chip BG, the metal posts P, etc., reference can be made to "the fourth setting structure of the interposer 10" and the relevant descriptions in the first embodiment, which will not be elaborated here.

[0224] For another example, referring to Figure 27 , Figure 28 As shown, in some possible implementation manners, the internal structure of the interposer 10 may be similar to "the sixth setting structure of the interposer 10" in the first embodiment. The interposer 10 may include a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200 disposed between the first redistribution layer RDL1 and the second redistribution layer RDL2. Among them, a plurality of through-glass vias TGV and at least one bridge chip BG ( Figure 27 ) may be provided in the glass interposer 12. Of course, only a plurality of through-glass vias TGV ( Figure 28 ) may also be provided. In this case, the edges of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2 are flush or nearly flush, and the connector C is disposed on the side surface of the interposer 10 formed by the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2.

[0225] In this setting manner, a plurality of chips D and the interposer 10 (including RDL1, 200, RDL2) are integrated together through a molding process; then cutting is performed to form a unit. Next, the unit and the connector C located on its side surface are secondarily molded through a molding process, and the surface is thinned and flattened to expose the terminals (such as pads, Cu posts, etc.) of the connector C, and the first connector 21 is connected to the exposed terminals. In this case, in the finally formed package structure, the connector C is disposed on the side surface of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2, the edges of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2 are flush, and the area is smaller than the area of the package outline.

[0226] Regarding the relevant settings of the first redistribution layer RDL1, the glass interposer 200, the second redistribution layer RDL2, the bridge chip BG, the through-glass vias TGV, etc., reference can be made to "the sixth setting structure of the interposer 10" and the relevant descriptions in the first embodiment, which will not be elaborated here.

[0227] In addition, regarding the settings of other parts in the chip package structure provided in the second embodiment, such as the chip D, the electronic component 20, the substrate 30, the first connector 21, the second connector 22, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., corresponding reference can be made to the aforementioned first embodiment, which will not be elaborated here.

[0228] It should be noted that, with reference to Figures 23 to 28 As shown, in the second embodiment, the substrate 30 located below the communicating vessel C needs to extend from below the communicating vessel C to the surface of the adapter board 10 for electrical connection. In this case, when setting the fixing structure and making an opening at the edge of the packaging system, the substrate 30 below the communicating vessel C can be avoided, as long as the fixation of the packaging system is satisfied, and the present application does not limit this. The manufacturing method of the chip packaging structure provided in the second embodiment can refer to the foregoing first embodiment and related technologies, and appropriate processes can be selected for manufacturing, and the present application does not limit this.

[0229] It should be understood that the sequence of the manufacturing processes involved in the embodiments of the present application should be determined according to their functions and internal logics, and should not constitute any limitation to the implementation processes of the embodiments of the present application.

[0230] For other relevant contents in the manufacturing methods of the embodiments, the corresponding parts in the chip packaging structure can be referred to correspondingly, and will not be elaborated here; for other setting structures in the foregoing chip packaging structure embodiments, they can be adjusted with reference to the above manufacturing method and related manufacturing methods, and will not be elaborated one by one here.

[0231] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A chip packaging structure, characterized in that, it includes: An interposer; At least one first chip, disposed on the interposer and electrically connected to the interposer; A through - connector, encapsulated with the first chip in a molding layer, and the bottom of the through - connector is electrically connected to the interposer; A first connector, located on the side of the molding layer away from the interposer and electrically connected to the interposer through the through - connector; At least one electronic component, located on the side of the interposer away from the first chip, and connected to the interposer or connected to the interposer through a substrate.

2. The chip packaging structure according to claim 1, characterized in that, The top of the through - connector is flush with the surface of the first chip on the side away from the interposer.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The through - connector includes: A support plate, in which an intermediate metal connection structure is provided; A first metal connection structure, disposed on the top of the support plate and connected to the intermediate metal connection structure; A second metal connection structure, disposed on the bottom of the support plate and connected to the intermediate metal connection structure; The through - connector is connected to the first connector through the first metal connection structure and connected to the interposer through the second metal connection structure.

4. The chip packaging structure according to any one of claims 1 - 3, characterized in that, The chip packaging structure further includes a second connector; The second connector is located on the side of the interposer away from the first connector, and is connected to the interposer or connected to the interposer through a substrate.

5. The chip packaging structure according to any one of claims 1 - 4, characterized in that, The through - connector and the first chip are on the same side of the interposer, and the through - connector is disposed on the interposer and electrically connected to the interposer.

6. The chip packaging structure according to any one of claims 1 - 4, characterized in that, The through - connector is located on the side surface of the interposer, and the bottom of the through - connector is connected to the side of the interposer where the electronic component is provided through a substrate.

7. The chip packaging structure according to claim 5, characterized in that, The interposer includes: a silicon interposer and a redistribution layer; The front surface of the silicon interposer has a metal wiring layer, and through - silicon vias (TSVs) are provided in the silicon interposer; the redistribution layer is disposed on the back surface of the silicon interposer and is electrically connected to the through - silicon vias; The first chip is disposed on the front surface of the silicon interposer; The edge of the redistribution layer extends beyond the edge of the silicon interposer, and the through - connector is disposed on the surface of the redistribution layer around the silicon interposer and is electrically connected to the redistribution layer.

8. The chip packaging structure according to claim 5, characterized in that, The interposer includes: a first redistribution layer and a second redistribution layer stacked; The first chip is disposed on the surface of the first redistribution layer and is electrically connected to the first redistribution layer; The communicating vessel is disposed on the surface of the first redistribution layer; or, the edge of the second redistribution layer extends beyond the edge of the first redistribution layer, and the communicating vessel is disposed on the surface of the second redistribution layer around the first redistribution layer.

9. The chip packaging structure according to claim 6, wherein, the adapter board includes: a silicon interposer and a redistribution layer; the front surface of the silicon interposer has a metal wiring layer, and through-silicon vias (TSVs) are disposed in the silicon interposer; the redistribution layer is disposed on the back surface of the silicon interposer and is electrically connected to the through-silicon vias; the first chip is disposed on the front surface of the silicon interposer; the bottom of the communicating vessel is connected to the redistribution layer through the substrate.

10. The chip packaging structure according to claim 6, wherein, the adapter board includes: a first redistribution layer and a second redistribution layer stacked; the first chip is disposed on the surface of the first redistribution layer and is electrically connected to the first redistribution layer; the bottom of the communicating vessel is connected to the redistribution layer through the substrate.

11. The chip packaging structure according to claim 8 or 10, wherein, the line width, line pitch, and line thickness of the metal traces in the first redistribution layer are all less than 5 μm; the line width, line pitch, and line thickness of the metal traces in the second redistribution layer are all greater than 5 μm.

12. The chip packaging structure according to claim 8, 10 or 11, wherein, the adapter board further includes: a glass wafer; the glass wafer is disposed between the first redistribution layer and the second redistribution layer, and through-glass vias (TGVs) are disposed in the glass wafer; the second redistribution layer is electrically connected to the first redistribution layer through the through-glass vias (TGVs).

13. The chip packaging structure according to claim 12, wherein, the adapter board further includes: a bridge chip; a trench is disposed in the glass wafer, the bridge chip is embedded in the trench, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer.

14. The chip packaging structure according to claim 8, 10 or 11, wherein, the adapter board further includes: a bridge chip and metal posts; the bridge chip and the metal posts are connected between the first redistribution layer and the second redistribution layer and are encapsulated in a molding compound; the second redistribution layer is electrically connected to the first redistribution layer through the metal posts, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer.

15. The chip packaging structure according to any one of claims 1-14, wherein, the at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

16. The chip packaging structure according to any one of claims 1-15, wherein, the at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and resistors, capacitors, and inductors.

17. The chip packaging structure according to any one of claims 1-16, wherein, The chip packaging structure includes: a plurality of the first chips and a plurality of electronic components.

18. The chip packaging structure according to claim 17, wherein, a plurality of the electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively disposed opposite to the plurality of the first chips; the power supply module is electrically connected to the first chip disposed opposite thereto through the adapter board and supplies power to the first chip.

19. The chip packaging structure according to any one of claims 1-18, wherein, the chip packaging structure includes: a plurality of substrates; the substrates are located on a side of the adapter board away from the first chip, a plurality of devices located on the side of the adapter board away from the first chip are connected to the adapter board through the plurality of substrates; wherein, the plurality of devices include one or more of the electronic components, the connector, and the second connector.

20. The chip packaging structure according to any one of claims 1-19, wherein, the chip packaging structure further includes: a first heat sink and a second heat sink; the first heat sink is disposed on a side of the first chip away from the adapter board, and the second heat sink is disposed on a side of the electronic component away from the adapter board.

21. The chip packaging structure according to any one of claims 1-20, wherein, the chip packaging structure further includes a first electronic device, and the first electronic device is located on a side of the plastic encapsulation layer away from the adapter board and is electrically connected to the adapter board through the connector.

22. An electronic device, wherein, it includes a circuit board and the chip packaging structure according to any one of claims 1-21, and the chip packaging structure is electrically connected to the circuit board.

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