Microelectronic assembly with through glass via stress mitigation in glass core

Abstract

Microelectronic assemblies with through glass via stress mitigation in a glass core are disclosed herein. Various techniques for mitigating (e.g., mitigating or reducing) stresses between a glass core material and a conductive material deposited in a through glass via (TGV) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first side and a second side opposite the first side, and a TGV extending through the glass core between the first side and the second side, where the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, where the buffer layer has a CTE less than a CTE of the conductive material.

Description

BACKGROUND OF THE DISCLOSURE

[0001] In the past few decades, the scaling of feature structures in integrated circuits (ICs) has been the driving force behind the growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to ever-smaller feature structures enables an increase in the density of functional units on the limited area of a semiconductor chip. For example, shrinking the transistor size allows for an increased number of memory or logic devices to be incorporated on a chip, contributing to the manufacture of products with increased capacity. However, the drive for ever-increasing capacity is not without problems. The necessity to optimize the manufacture and performance of each component (e.g., each transistor) has become increasingly important.

[0002] Simultaneously with the optimization at the transistor level, the advanced IC packaging landscape is rapidly evolving to meet the performance expectations and requirements of transistor size shrinkage. Currently, multiple IC dies are typically coupled together in a multi-die IC package to integrate feature structures or functions and facilitate connection to other components (e.g., a package substrate). For example, an IC package can include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.

[0003] Integrating multiple dies in a single IC package offers significant benefits, but it adds additional complexity due to placing materials with different material properties in close proximity to each other. When an IC package undergoes multiple processing steps involving various temperature and pressure loads, the various materials within the package may behave differently, resulting in out-of-plane deformation of the individual layers, which is referred to as "package warpage". One way to address package warpage is to use a stiffer core to which different IC dies are attached. Recently, glass cores have been developed as an alternative to organic resin-based cores (e.g., cores based on the use of Ajinomoto Build-up Film (ABF)). Glass is considered to be more rigid than organic resin-based materials and has several advantages, such as excellent thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advanced semiconductor characteristics. However, a major challenge in the widespread adoption of glass cores is the fact that glass is prone to damage due to mechanical stress and / or thermal stress (e.g., stress caused by metal-filled through-glass vias (TGVs)). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, the same reference numerals represent the same structural elements. The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

[0005] Figure 1 is a schematic side cross-sectional view of an exemplary microelectronic component in accordance with some embodiments of the present disclosure.

[0006] Figure 2 is a schematic side cross-sectional view of another exemplary microelectronic component according to some embodiments of the present disclosure.

[0007] Figure 3 Shows the surface of a glass core from which TGV stress may be induced according to some embodiments of the present disclosure.

[0008] Figures 4A - 4D Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of depositing cationic and anionic polyelectrolytes on the sidewalls of a TGV opening to form a buffer layer.

[0009] Figure 5 Shows a cross-sectional side view of a glass core having a multilayer of cationic and anionic polyelectrolytes on the sidewalls of a TGV opening according to some embodiments of the present disclosure.

[0010] Figures 6A - 6C Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of depositing cationic π-conjugated oligomers / polymers on the sidewalls of a TGV opening to form a buffer layer.

[0011] Figures 7A - 7C Shows the structural formula of an example of a cationic π-conjugated oligomer / polymer according to some embodiments of the present disclosure.

[0012] Figures 8A - 8D Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of providing a buffer layer on the sidewalls of a TGV opening using a polymer nanoemulsion.

[0013] Figures 9A - 9D Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of providing a buffer layer on the sidewalls of a TGV opening using an organosol-gel process.

[0014] Figures 10A - 10D Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of using a vapor-permeation-based buffer layer.

[0015] Figures 11A - 11C Shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of depositing other buffer layers on the sidewalls of a TGV opening.

[0016] Figures 12A - 12D Shows a TGV with conductive materials and TGV stress-resistant materials having different patterns according to some embodiments of the present disclosure.

[0017] Figures 13A - 13CShows the use of a polymer-filled TGV to mitigate TGV stress in accordance with some embodiments of the present disclosure.

[0018] Figures 14A - 14D Shows a cross-sectional side view of a glass core in accordance with some embodiments of the present disclosure, which shows the process of patterning the glass core to form conductive traces.

[0019] Figure 15 Is a top view of a wafer and die that can be included in a microelectronic component having a glass core in accordance with any of the embodiments disclosed herein.

[0020] Figure 16 Is a side cross-sectional view of an IC device that can be included in a microelectronic component having a glass core in accordance with some embodiments of the present disclosure.

[0021] Figure 17 Is a side cross-sectional view of an IC device assembly that can include a glass core in accordance with any of the embodiments disclosed herein.

[0022] Figure 18 Is a block diagram of an exemplary communication device that can include a microelectronic component having a glass core in accordance with some embodiments of the present disclosure. Detailed Description

[0023] As described above, TGVs can cause mechanical and / or thermal stresses, making the glass vulnerable to damage. As the name implies, a TGV is a via that extends between the bottom and top (or "faces") of a glass core. Once a via opening is formed between the bottom and top faces of the glass core, one or more conductive materials (e.g., metals) are used to fill the opening so that the TGV can support electrical connections through the glass core and / or support efficient thermal management by providing a path for heat dissipation from active components to the external environment of the package. TGVs enable a more compact and efficient design of microelectronic components. However, integrating TGVs in a glass core is not straightforward. One challenge comes from the difference in CTE between the materials that can be used for the glass core and the metals deposited in the TGVs. CTE is a measure of how a material expands or contracts with temperature changes and is typically defined as the fractional increase in length per unit temperature rise, e.g., measured in parts per million (ppm) per Kelvin (K) or ppm / K. The metals and materials that can be used for the glass core have significantly different CTEs. Metals have a relatively high CTE, meaning they can expand and contract significantly with temperature changes. On the other hand, glass has a much lower CTE and is less responsive to temperature changes. For example, the CTE of glass can be on the order of about 3.5 ppm / K, while the CTE of a metal (e.g., copper) can be on the order of about 15 ppm / K. When a metal is in close contact with glass (e.g., the metal within a TGV in a glass core) and the component is exposed to temperature changes such as heating or cooling, the metal will heat up or cool down faster and to a greater extent than the glass. This results in significant thermal stresses at the interface between the two materials. The high thermal stresses can exceed the strength of the glass, causing cracks to form, which can then propagate and compromise the structural integrity of the glass. Even if cracks do not form immediately, repeated thermal cycles will gradually weaken the glass surface, potentially leading to the development of surface defects or microcracks. Prolonged exposure to stresses induced by CTE mismatch can cause the glass to gradually degrade, making it more prone to failure over time.

[0024] Embodiments of the present disclosure relate to various techniques for alleviating (e.g., reducing or decreasing) CTE mismatch-induced stress caused by the proximity of the conductive material of the TGV to the glass material of the glass core, as well as related devices and methods. As used herein, such stress is referred to as "TGV stress". As used herein, a glass core and a TGV to which one or more of the techniques for TGV stress alleviation described herein have been applied are referred to as a "glass core with TGV stress alleviation" and a "TGV with stress alleviation", respectively. In one aspect of the present disclosure, a microelectronic component includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer located between the conductive material and the glass core, and wherein the CTE of the buffer layer is less than the CTE of the conductive material. In another aspect of the present disclosure, a microelectronic component includes a via extending from a first side of a rectangular prism volume to a second side of the rectangular prism volume, the via including metal, wherein the via has a first thickness in a first plane parallel to the first side, a second thickness in a second plane parallel to the first side, and a third thickness in a third plane parallel to the first side, and wherein the second plane is between the first plane and the third plane and the second thickness is less than the first thickness and the third thickness, the via further includes a filler material, the metal is between the filler material and the glass of the rectangular prism volume, and the CTE of the filler material is less than the CTE of the metal.

[0025] Due to reasons such as CTE mismatch, the integration of the conductive material of the TGV in the glass core used in microelectronic components is challenging. It may be helpful to provide a microelectronic component having a glass core to which one or more of the techniques for TGV stress alleviation described herein are applied. Relative to conventional methods, various embodiments in the embodiments disclosed herein can contribute to achieving reliable integration of the TGV within the glass core at a lower cost and / or with greater design flexibility. Relative to conventional methods, various glass cores in the glass cores with TGV stress alleviation disclosed herein can exhibit reduced fracture sensitivity. The microelectronic components with TGV stress alleviation in the glass core disclosed herein may be particularly advantageous for small and thin applications in computers, tablets, industrial robots, and consumer electronic products (e.g., wearable devices).

[0026] In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description, wherein like reference numerals throughout the text denote like components, and wherein embodiments that may be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be considered restrictive.

[0027] If appropriate, any feature discussed with reference to any of the figures herein may be combined with any other feature to form the microelectronic component 100, the glass core 110, the IC device 1600, the IC device assembly 1700, or the communication device 1800. For convenience, the phrase "die 114" may be used to refer to the collection of dies 114-1, dies 114-2, etc. Sets of figures labeled with different letters may be referred to without the letters, e.g., Figures 4A - 4D The set of may be referred to as " Figures 4A - 4D ", Figures 6A - 6C The set of may be referred to as " Figures 6A - 6C ", etc. Multiple elements with the same reference numeral in the figures may be shared between different figures; for ease of discussion, the description of these elements provided with respect to one of the figures is not repeated for the other figures, and these elements may take the form of any of the embodiments disclosed herein. To avoid cluttering the figures, if multiple instances of certain elements are shown, only some of the elements may be labeled with the reference numeral (e.g., multiple conductive contacts 122 are shown in Figure 1 , but only one of the conductive contacts is labeled with the reference numeral). Also to avoid cluttering the figures, not all reference numerals shown in one of the figures are shown in other similar figures.

[0028] The figures are not necessarily drawn to scale. Although many of the figures show straight structures with flat walls and right-angled corners, this is for ease of illustration only and may not reflect the actual process limitations, which may result in various features not looking as "ideal" when using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images to examine any of the structures described herein. In such images of the actual structures, possible processing defects may also be visible, e.g., non-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners, or variations in the thickness of different material layers. There may be other defects not listed here but common in the field of semiconductor device fabrication and packaging. Using, for example, optical microscopy, TEM, or SEM to examine the layout and mask data and reverse engineering of the components of the device to reconstruct the circuit and / or using, for example, physical failure analysis (PFA) to examine cross-sections of the device to detect the shape and location of the various device elements described herein will allow determination of the presence of the glass core with TGV stress relief described herein.

[0029] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a dimensional range, the phrase "between X and Y" means a range that includes X and Y. When used to describe the location of an element, the phrase "between X and Y" means the region that is spatially located between element X and element Y. Based on the context of a particular value described herein or known in the art, the terms "substantially", "close to", "about", "near", and "approximately" generally mean within + / - 20% of the target value, such as within + / - 5% or within + / - 2%. Similarly, terms indicating the orientation of various elements, such as "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements generally mean within + / - 10% of the exact orientation, for example, within + / - 5% or + / - 2%.

[0030] The specification uses the phrase "in an embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous. As used herein, the terms "package" and "IC package" are synonymous, and the terms "die" and "IC die" are also synonymous. In addition, the terms "chip", "dielet", "die", and "IC die" may be used interchangeably herein.

[0031] Although certain elements are referred to in the singular in this document, such elements can include multiple sub-elements. For example, "dielectric material" can include one or more dielectric materials, or "insulating material" can include one or more insulating materials. The terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc. respectively. The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide. Unless otherwise specified, the term "insulate" and its variants (e.g., "insulating" or "insulator") mean "electrically insulate", and the term "conduct" and its variants (e.g., "conducting" or "conductor") mean "electrically conduct". With reference to optical signals and devices, components, and elements that operate or use optical signals, the term "conduct" can also mean "optically conduct". The term "insulating material" refers to a solid material (and / or a liquid material that solidifies after processing as described herein) that is substantially non-conductive. By way of example and not limitation, the solid material can include organic polymers and plastics, as well as inorganic materials (such as ionic crystals, porcelain, glass, silicon, and alumina or combinations thereof). The solid material can include dielectric materials, highly polarizable materials, and / or piezoelectric materials. Without departing from the scope of the present disclosure, the solid material can be transparent or opaque. Additional examples of insulating materials are underfills and molding or molding-like materials used in encapsulation applications, such as materials included in organic interposers, encapsulation supports, and other such components.

[0032] Figure 1FIG. 0 is a schematic side cross-sectional view of an exemplary microelectronic component 100 in accordance with some embodiments of the present disclosure in which a glass core with TGV stress relief as described herein may be implemented. The microelectronic component 100 may include a substrate 107 having a dual-sided bridge die 114-1 in a cavity 119 in the substrate 107, and the die 114-1 may be electrically coupled to a conductive path (e.g., conductive trace 108A or conductive via 108B) in a metal layer N-1 below the bottom of the cavity 119 of the substrate 107. The substrate 107 may include a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B as shown, together referred to as “one or more dielectric material layers 112”) and a conductive material 108 disposed in the one or more dielectric material layers 112 to provide a conductive path through the substrate 107 (e.g., conductive trace 108A and conductive via 108B), as well as to provide conductive pads and contacts. The substrate 107 may include a first surface 120-1 and an opposite second surface 120-2. The die 114-1 may be surrounded by the dielectric material 112 of the substrate 107. The die 114-1 may include a bottom surface (e.g., a surface facing the first surface 120-1) having a first conductive contact 122, an opposite top surface (e.g., a surface facing the second surface 120-2) having a second conductive contact 124, and a through-silicon via (TSV) 125 coupling the corresponding first conductive contact 122 and second conductive contact 124. In some embodiments, the pitch of the first conductive contacts 122 on the first die 114-1 may be between 25 micrometers and 250 micrometers. As used herein, pitch is measured center-to-center (e.g., from the center of a conductive contact to the center of an adjacent conductive contact). In some embodiments, the pitch of the second conductive contacts 124 on the first die 114-1 may be between 25 micrometers and 100 micrometers. The dies 114-2, 114-3 may include a set of conductive contacts 122 on a bottom surface of the die (e.g., a surface facing the first surface 120-1). The die 114 may include other conductive paths (e.g., including lines and vias) and / or other circuitry (not shown) coupled to the corresponding conductive contacts (e.g., conductive contact 122, conductive contact 124) on the surface of the die 114. As used herein, the terms “die,” “microelectronic component,” and like variations may be used interchangeably. As used herein, the terms “interconnect component,” “bridge die,” and like variations may be used interchangeably. The bridge die 114-1 may be electrically coupled to the dies 114-2, 114-3 at the second surface 120-2 via a die-to-die (DTD) interconnect 130.Specifically, the conductive contact portion 124 on the top surface of die 114-1 can be coupled to the conductive contact portion 122 on the bottom surface of dies 114-2 and 114-3 through the conductive vias 108B that penetrate the second dielectric material layer 112B.

[0033] As used herein, a "conductive contact portion" can refer to a portion of a conductive material (e.g., metal) that serves as an electrical interface between different components (e.g., portions of conductive interconnections); the conductive contact portion can be recessed from the surface of the component, flush with the surface of the component, or extend away from the surface of the component (e.g., having a columnar shape), and can take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or via). In a general sense, an "interconnection" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides electrical connectivity between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnection provides optical connectivity between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical interconnections and optical interconnections are included in the term "interconnection". The nature of the described interconnections will be understood with reference to the signal medium associated with the interconnections. Thus, when used in reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnection" describes any element formed of a conductive material for providing an electrical connection to and / or between one or more elements associated with the IC. In such a case, the term "interconnection" can refer to electrical traces (sometimes also referred to as "metal traces", "lines", "metal lines", "wires", "metal wires", "trenches" or "metal trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, the conductive traces and vias can be referred to as "metal traces" and "metal vias" respectively to emphasize the fact that these elements include a conductive material (e.g., metal). Similarly, when used in reference to a device that also operates on optical signals (e.g., a photonic IC (PIC)), "interconnection" can also describe any element formed of a light-conducting material for providing optical connectivity to one or more elements associated with the PIC. In such a case, the term "interconnection" can refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0034] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the die 114 may include conductive traces and / or conductive vias and may connect any conductive contact in the die 114 in any suitable manner (e.g., connecting a plurality of conductive contacts located on the same or different surfaces of the die 114). Exemplary structures that may be included in the die 114 disclosed herein are discussed below with reference to the IC device 1600. The conductive paths located in the die 114 may be bounded by a liner material (e.g., an adhesive liner and / or a barrier liner, as appropriate). In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, fan-out or fan-in packaged die, or a die stack (e.g., stacked wafers, stacked dies, or stacked multi-layer dies).

[0035] In some embodiments, the die 114 may include conductive paths to route power, ground, and / or signals to / from other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include TSVs 125 (including conductive vias, such as metal vias, isolated from the surrounding silicon or other semiconductor material by a barrier oxide) or other conductive paths through which power, ground, and / or signals may be routed between the package substrate 102 and one or more dies 114 "on top" of the die 114-1 (e.g., in Figure 1In an embodiment, it is transmitted between die 114-2 and / or 114-3. In some embodiments, die 114-1 may not route power and / or ground to die 114-2 and 114-3; instead, die 114-2 and die 114-3 may be directly coupled to the power line and / or ground line in package substrate 102 through substrate-to-package substrate (STPS) interconnect 150, the conduction path provided by conductive material 108 in substrate 107, and die-to-substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than die 114-2 and die 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes), such as a rapid peripheral component interconnect (PCI). In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 114-2 and / or die 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 114 may be the die described as die 1502 in reference to Figure 15 below.

[0036] The dielectric material 112 of substrate 107 may be formed by layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, dielectric material 112 may include an organic material, such as an organic stack film. In some embodiments, dielectric material 112 may include, for example, ceramics, an epoxy resin film with filler particles therein, glass, an inorganic material, or a combination of an organic material and an inorganic material. In some embodiments, conductive material 108 may include a metal (e.g., copper). In some embodiments, substrate 107 may include layers of dielectric material 112 / conductive material 108, where the wire / trace / pad / contact (e.g., conductive trace 108A) of conductive material 108 in one layer is electrically coupled to the wire / trace / pad / contact (e.g., conductive trace 108A) of conductive material 108 in an adjacent layer through a via (e.g., 108B) of conductive material 108 extending through dielectric material 112. The conductive element 108A may be referred to herein as a "wire", a "conductive trace", a "conductive pad", or a "conductive contact". For example, printed circuit board (PCB) manufacturing techniques may be used to form substrate 107 including such layers.

[0037] A single layer of the dielectric material 112 (e.g., the first dielectric material layer 112A) may include a cavity 119, and the bridge die 114-1 may be at least partially nested in the cavity 119. The bridge die 114-1 may be surrounded (e.g., embedded therein) by the next single layer of the dielectric material 112 (e.g., the second dielectric material layer 112B). In some embodiments, the cavity 119 is tapered and narrows towards the bottom surface of the cavity 119 (e.g., towards the surface of the first surface 120-1 of the substrate 107). The cavity 119 may be represented by a gap between the dielectric material 112A and the dielectric material 112B. As Figure 1 shown, in the case where the bridge die 114-1 is partially nested in the cavity 119, the top surface of the bridge die 114-1 may extend above the top surface of the dielectric material 112A. In the case where the bridge die 114-1 is fully nested in the cavity 119 (not shown), the top surface of the bridge die 114-1 may be flush with or lower than the top surface of the dielectric material 112A.

[0038] The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to 1. In Figure 1 this case, these layers are marked in descending order from the second surface 120-2 (e.g., the top surface) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). Specifically, as Figure 1 shown, the substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layer may include a conductive contact portion 121 at the second surface 120-2 of the substrate 107, and the conductive contact portion 121 is coupled to the conductive contact portion 122 at the bottom surface of the dies 114-2 and 114-3 through the DTS interconnect 140. The N-2 metal layer may include a conductive trace 108A having a top surface (e.g., the surface facing the second surface 120-2 of the substrate 107), an opposite bottom surface (e.g., the surface facing the first surface 120-1 of the substrate 107), and a lateral surface extending between the top surface and the bottom surface of the conductive trace 108A. The substrate 107 may further include an N-1 metal layer located above the N-2 metal layer and below the N metal layer, and a part of the N-1 metal layer includes a metal ring 118 exposed at the perimeter of the bottom of the cavity 119. As shown, the metal ring 118 may be coplanar with the conductive trace 108A of the N-1 metal layer and may be close to the edge of the cavity 119.

[0039] Although specific numbers and arrangements of layers of dielectric material 112 / conductive material 108 are shown in the various figures, these specific numbers and arrangements are merely illustrative, and any desired numbers and arrangements of dielectric material 112 / conductive material 108 may be used. Additionally, although a specific number of layers (e.g., four layers) are shown in substrate 107, these layers may only represent a portion of substrate 107, e.g., additional layers (e.g., layers N-4, N-5, N-6, etc.) may be present.

[0040] As Figure 1 shown, substrate 107 may further include a glass core 110 having TGVs 115, and additional layers 111 may be present below glass core 110 and coupled to package substrate 102 via interconnects 150. As used herein, the term "glass core" refers to a layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, borofloat glass, lead borate glass, photosensitive glass, non-photosensitive glass, or glass-ceramic. In particular, glass core 110 may be a bulk glass or a solid volume glass / glass layer, rather than a material that may include glass particles (e.g., a glass fiber reinforced polymer (e.g., a substrate / plate composed of glass fibers and an epoxy binder)). Such glass materials are typically non-crystalline and are generally transparent amorphous solids. In some embodiments, glass core 110 may be an amorphous solid glass layer. In some embodiments, glass core 110 may include a material comprising silicon and oxygen and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, glass core 110 may include a material of any of the materials described above, wherein the weight percentage of silicon is at least about 0.5%, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if glass core 110 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, glass core 110 may include a material having at least 23% silicon and / or at least 26% oxygen by weight, and in some additional embodiments, glass core 110 may further include at least 5% aluminum by weight. In some embodiments, glass core 110 may include any of the above materials and may also include one or more additives, such as Al 2 O 3 、B 2 O 3 、MgO, CaO, SrO, BaO, SnO 2 、Na 2 O、K 2 O、SrO、P2 O 3 , ZrO 2 , Li 2 O, Ti, and Zn. In some embodiments, the glass core 110 can be a glass layer that does not include an organic binder or organic material. The glass core 110 can be distinguished from, for example, a "prepreg" or "RF4" core of a PCB substrate, which typically includes glass fibers embedded in a resin organic material (such as epoxy resin). In such a conventional core / substrate that includes glass fibers and epoxy resin, the diameter of the glass fibers is typically in the range of 5 micrometers to 200 micrometers. In contrast, the glass core 110 can be a glass layer with a side length of about 10 millimeters (mm) to a side length of about 250 millimeters (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some embodiments, Figure 1 the cross-section of the glass core 110 in the x-z plane, y-z plane, and / or x-y plane of the exemplary coordinate system 105 shown in can be substantially rectangular (the axes shown in subsequent figures refer to the axes of the coordinate system 105). In such an embodiment, in a top view of the glass core 110 (e.g., the x-y plane of the coordinate system 105), the glass core 110 can have a first length in the range of 10 millimeters to 250 millimeters and a second length in the range of 10 millimeters to 250 millimeters, with the first length perpendicular to the second length. The thickness of the glass core 110 (e.g., the dimension measured along the z-axis of the coordinate system 105) can be in the range of about 50 micrometers to 1.4 millimeters. In some embodiments, the glass core 110 can be a glass core substrate, where the glass core substrate has a thickness in the range of about 50 micrometers to 1.4 millimeters. In some embodiments, the glass core 110 can be a glass layer that includes a rectangular prism volume. In some such embodiments, the rectangular prism volume can have a first side and a second side perpendicular to the first side, with the first side having a length in the range of 10 millimeters to 250 millimeters and the second side having a length in the range of 10 millimeters to 250 millimeters. In some embodiments, the glass core 110 can be a rectangular prism volume, where certain portions (e.g., vias) are removed and filled with other materials (e.g., metal), such as TGV 115. In some embodiments, the glass core 110 can be a glass layer with a thickness in the range of 50 micrometers to 1.4 millimeters, a first length in the range of 10 millimeters to 250 millimeters, and a second length in the range of 10 millimeters to 250 millimeters, with the first length perpendicular to the second length.

[0041] In some embodiments, the substrate 107 (including the glass core 110) and the die 114 may be collectively referred to as a "multi-layer die subassembly 104". The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass core 110 may reduce warping and may provide a more robust surface for attaching the multi-layer die subassembly 104 to the package substrate 102 or other substrates (e.g., an interposer or a circuit board).

[0042] In some embodiments, the glass core 110 and the dielectric material 112 of the substrate 107 may be collectively referred to as a "multi-layer glass substrate". In some such embodiments, the multi-layer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in the range of about 25 microns to 50 microns. In some embodiments, the additional layer 111 may also be part of the multi-layer glass substrate.

[0043] The TGV 115 may be a via extending between a first side and a second side of the glass core 110 (e.g., between the bottom surface and the top surface of the glass core 110), the via comprising any suitable conductive material, such as a metal (e.g., by way of example, copper, silver, nickel, gold, aluminum, or other metal or alloy). The TGV 115 may be formed using any suitable process, including, for example, direct laser drilling or laser-induced deep etching processes. In some embodiments, the TGV 115 disclosed herein may have a pitch between 50 microns and 500 microns (e.g., as measured from the center of one TGV 115 to the center of an adjacent TGV 115). The TGV 115 may have any suitable size and shape. In some embodiments, the TGV 115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, for example, as Figure 2 shown, at least some of the TGVs 115 may have a hourglass shape. In some embodiments, at least some of the TGVs 115 may taper downwards from one face of the glass core 110 to the other, e.g., from the top surface of the glass core 110 to the bottom surface of the glass core 110. Any one or more of the TGVs 115 may be a TGV with stress relief as described herein. Thus, the glass core 110 may be a glass core with TGV stress relief as described herein.

[0044] The substrate 107 (e.g., additional layer 111) can be coupled to the package substrate 102 through the STPS interconnect 150. In particular, the top surface of the package substrate 102 can include a set of conductive contacts 146. The conductive contacts 144 on the bottom surface of the substrate 107 can be electrically and mechanically coupled to the conductive contacts 146 on the top surface of the package substrate 102 through the STPS interconnect 150. The package substrate 102 can include an insulating material (e.g., a dielectric material formed of multiple layers as known in the art) and one or more conductive paths for routing power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias as shown). In some embodiments, the insulating material of the package substrate 102 can be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with inorganic fillers or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 can include FR-4, and the conductive paths in the package substrate 102 can be formed of patterned copper foils separated by stacked layers of FR-4. Where appropriate, the conductive paths in the package substrate 102 can be defined by liner materials (e.g., adhesive liners and / or barrier liners). In some embodiments, a via-encapsulation process defined by lithography can be used to form the package substrate 102. In some embodiments, the package substrate 102 can be manufactured using standard organic packaging manufacturing processes, and thus the package substrate 102 can take the form of an organic package. In some embodiments, the package substrate 102 can be a set of redistribution layers formed on a panel carrier by laminating or spin-coating on a dielectric material and forming conductive vias and lines by laser drilling and electroplating. In some embodiments, the package substrate 102 can be formed on a removable carrier using any suitable technique (e.g., redistribution layer technology). Any method known in the art for manufacturing the package substrate 102 can be used, and for the sake of brevity, such methods will not be discussed further herein.

[0045] In some embodiments, the encapsulation substrate 102 may be a low-density medium, and the die 114 may be a high-density medium or have regions containing high-density media. As used herein, the terms "low density" and "high density" are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive wires, and conductive vias) in the low-density medium are larger and / or have a larger pitch than those in the high-density medium. In some embodiments, a modified semi-additive process or a semi-additive build-up process with advanced lithography (with smaller vertical interconnect features formed by an advanced laser or lithography process) may be used to fabricate the high-density medium, while the low-density medium may be a PCB fabricated using a standard PCB process (e.g., a standard subtractive process using an etching chemistry to remove unwanted copper regions and having thick vertical interconnect features formed by a standard laser process). In other embodiments, a semiconductor manufacturing process (e.g., a single damascene process or a dual damascene process) may be used to fabricate the high-density medium. In some embodiments, additional dies may be disposed on the top surfaces of dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surfaces of dies 114-2, 114-3. Additional passive components, such as surface-mounted resistors, capacitors, and / or inductors, may be disposed on the top or bottom surface of the encapsulation substrate 102 or embedded within the encapsulation substrate 102.

[0046] Figure 1The microelectronic component 100 therein may further include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102 around the associated STPS interconnect 150. In some embodiments, the underfill material 127 may extend between the top surfaces of the top dies 114-2, 114-3 and the substrate 107 around the associated DTS interconnect 140 and between the bridge die 114-1 and the top dies 114-2, 114-3 around the DTD interconnect 130. The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that helps solder the multi-die subassembly 104 to the package substrate 102 when forming the STPS interconnect 150 and then polymerizes and encapsulates the STPS interconnect 150. The underfill material 127 may be selected to have a CTE that can relieve or minimize the stress between the substrate 107 and the package substrate 102 caused by non-uniform thermal expansion in the microelectronic component 100. In some embodiments, the CTE of the underfill material 127 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the dielectric material 112 of the die 114 and / or the substrate 107.

[0047] The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the STPS interconnects 150), e.g., as Figure 1 shown, the STPS interconnect 150 may include solder between the conductive contact 144 on the bottom surface of the substrate 107 and the conductive contact 146 on the top surface of the package substrate 102. In some embodiments, a set of STPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material.

[0048] The DTD interconnects 130 disclosed herein can take any suitable form. The DTD interconnects 130 can have a finer pitch than the STPS interconnects 150 in the microelectronic component. In some embodiments, the die 114 on either side of a set of DTD interconnects 130 can be an unpackaged die, and / or the DTD interconnects 130 can include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 can have a pitch that is too fine to be directly coupled to the package substrate 102 (e.g., too fine to be used as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 can include solder. In some embodiments, a set of DTD interconnects 130 can include anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 can be used as data transfer channels, while the STPS interconnects 150 can be used for power lines and ground lines, etc. In some embodiments, some or all of the DTD interconnects in the DTD interconnects 130 in the microelectronic component 100 can be metal-to-metal interconnects (e.g., copper-to-copper interconnects or electroplated interconnects). In such embodiments, the DTD interconnects 130 can be joined together (e.g., under elevated pressure and / or temperature) without using an intervening solder or anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) can include, for example, bonding pads, solder bumps, conductive posts, or any other suitable conductive contact. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 in the microelectronic component 100 can be solder interconnects that include solder having a higher melting point than the solder included in some or all of the STPS interconnects in the STPS interconnects 150. For example, when the DTD interconnects 130 and DTS interconnects 140 in the microelectronic component 100 are formed before the STPS interconnects 150 are formed, the solder-based DTD interconnects 130 and DTS interconnects 140 can use high-temperature solder (e.g., having a melting point above 200 degrees Celsius), while the STPS interconnects 150 can use low-temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the high-temperature solder can include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the low-temperature solder can include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, the low-temperature solder can include indium, indium and tin, or gallium.

[0049] In the microelectronic component 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a greater pitch than some or all of the DTD interconnects 130. Since the materials in the different die 114 on either side of a set of DTD interconnects 130 have a greater material similarity than between the substrate 107 and the top die 114-2, 114-3 on either side of a set of DTS interconnects 140 and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150, the DTD interconnects 130 may have a smaller pitch than the STPS interconnects 150. In particular, due to the heat generated during operation (and the heat applied during various manufacturing operations), differences in the material composition of the substrate 107 and the die 114 or the package substrate 102 may result in different expansion and contraction. To mitigate damage caused by such different expansion and contraction (e.g., cracking, solder bridging, etc.), the DTS interconnects 140 and STPS interconnects 150 may be formed to be larger and more spaced apart than the DTD interconnects 130 (which may experience less thermal stress due to the greater material similarity of a pair of die 114 on either side of the DTD interconnects). In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.

[0050] Figure 1 The microelectronic component 100 may further include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via a second-level interconnect at the bottom surface of the package substrate 102. The second-level interconnect may be any suitable second-level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. The circuit board may be, for example, a motherboard and may have other components attached to the motherboard. As is known in the art, the circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, but may instead couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, but may instead be coupled to the circuit board, such as a PCB.

[0051] Although Figure 1depicts a microelectronic component 100 having a substrate containing a specific number of die 114 and conductive paths provided by conductive material 108 coupled to other die 114, but this number and arrangement are merely illustrative, and the microelectronic component 100 can include any desired number and arrangement of die 114. Although Figure 1 die 114-1 is shown as a dual-sided die and die 114-2, 114-3 are shown as single-sided die, but die 114-2, die 114-3 can be dual-sided die, and die 114 can be single-pitch die or mixed-pitch die. In some embodiments, additional components can be provided on the top surface of die 114-2 and / or 114-3. In such a context, a dual-sided die refers to a die having connections on two surfaces. In some embodiments, a dual-sided die can include through-silicon vias to form connections on two surfaces. Depending on the design and electrical requirements, the active surface of the dual-sided die (which is the surface containing one or more active devices and most of the interconnects) can face either direction.

[0052] Figure 1 many of the elements of the microelectronic component 100 in Figure 1 are included in other figures in the drawings; these elements will not be discussed again when discussing these figures, and any of these elements can take any form disclosed herein. Additionally, various elements are

[0053] Figure 2 shown as being included in the microelectronic component 100, but in various embodiments, some of these elements may not be included. For example, in various embodiments, additional layer 111, underfill material 127, and package substrate 102 may be absent in the microelectronic component 100. In some embodiments, each of the microelectronic components 100 disclosed herein can be used as a system-in-package (SiP), which includes multiple die 114 having different functions. In such embodiments, the microelectronic component 100 can be referred to as a SiP.

[0053] Figure 2 is a schematic cross-sectional view of another exemplary microelectronic component 100 according to some embodiments of the present disclosure. Except for the differences further described, the construction of the embodiment shown in this figure is similar to that of Figure 1 Unlike including a glass core 110 as part of the substrate 107 (as shown in Figure 1 ), Figure 2 the microelectronic component 100 in Figure 2In [description], the multi-layer die sub-assembly 104 includes the glass core 110 and a plurality of dies 114 as described above. The multi-layer die sub-assembly 104 may have a first surface 160-1 (e.g., the bottom surface) and an opposite second surface 160-2 (e.g., the top surface). The glass core 110 may be Figure 2 providing mechanical stability for the multi-layer die sub-assembly 104 and / or the microelectronic assembly 100 in [description], reducing warping, and providing a more robust surface for attaching the multi-layer die sub-assembly 104 to the package substrate 102 or other substrates (e.g., an interposer or a circuit board).

[0054] The glass core 110 may include a cavity 129 having an opening facing the second surface 160-2, and the die 114-1 may be fully or at least partially nested in the cavity 129. As Figure 2 shown, in the case where the die 114-1 is fully nested in the cavity 129, the top surface of the die 114-1 may be flush with or lower than the top surface of the glass core 110. In the case where the die 114-1 is partially nested in the cavity 129, the top surface of the die 114-1 may extend above the top surface of the glass core 110. As described above, the cavity 129 may be at least partially filled with a dielectric material 112A or 112B. The die 114-1 may be attached to the bottom surface of the cavity 129 through a die attach film (DAF) 132. The DAF 132 may be any suitable material, including a non-conductive adhesive, a die attach film, a Class B underfill, or a polymer film having adhesive properties. The DAF 132 may have any suitable size. For example, in some embodiments, the DAF 132 may have a thickness (e.g., height or z-height) between 5 microns and 10 microns.

[0055] Die 114-1 can be coupled to dies 114-2, 114-3 in a layer above die 114-1 through DTD interconnect 130. The DTD interconnect 130 can be disposed between some conductive contacts 122 at the bottom of dies 114-2, 114-3 and some conductive contacts 124 at the top of die 114-1. Some other conductive contacts 122 at the bottom of die 114-2 and / or 114-3 can also couple one or more of dies 114-2, 114-3 to glass core 110 through glass core-to-die (GCTD) interconnect 142. The GCTD interconnect 142 can be disposed between some conductive contacts 122 at the bottom of dies 114-2, 114-3 and some conductive contacts 128 at the top of glass core 110. The GCTD interconnect 142 can be similar to the above-described DTS interconnect 140. In some embodiments, underfill material 127 can extend between different dies 114 in die 114 around the associated DTD interconnect 130 and / or GCTD interconnect 142. In some embodiments, die 114-2 and / or die 114-3 can be embedded in insulating material 133. In some embodiments, the total thickness (e.g., z-height) of the insulating material 133 can be between 200 microns and 800 microns (e.g., substantially equal to the thickness of die 114-2 or 114-3 and underfill material 127). In some embodiments, the insulating material 133 can form multiple layers (e.g., a dielectric material formed of multiple layers as known in the art) and can embed one or more dies 114 in the layers. In some embodiments, the insulating material 133 can be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the insulating material 133 can be a molding material, such as an organic polymer having inorganic silica particles).

[0056] As Figure 2 shown, the glass core 110 can also include conductive contacts 126 at the bottom of the glass core 110, and the TGV 115 can extend between and electrically couple the conductive contacts 126 at the bottom of the glass core 110 and the conductive contacts 128 at the top of the glass core 110. The conductive contacts 126, 128 can be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146), and can include, for example, bonding pads, solder bumps, conductive pillars, or any other suitable conductive contacts. As Figure 2As shown, in some embodiments, at least some of the TGVs 115 in the TGV 115 may have an hourglass shape. For example, at least some of the TGVs 115 in the TGV 115 may have a first width at a first side of the glass core 110 (e.g., at the bottom surface of the glass core 110), a second width at a second side of the glass core 110 (e.g., at the top surface of the glass core 110), and a third width between the first side and the second side of the glass core 110, where the third width is less than the first width and the second width.

[0057] The dies 114-2, 114-3 may be electrically coupled to the package substrate 102 through the TGV 115 and the glass core-to-package substrate (GCTPS) interconnect 152, and the GCTPS interconnect 152 may be a power delivery interconnect or a high-speed signal interconnect. The GCTPS interconnect 152 may be similar to the STPS interconnect 150 described above. The top surface of the package substrate 102 may include a set of conductive contacts 146, the multi-die subassembly 104 may include a set of conductive contacts 126 on the first surface 160-1, and the GCTPS interconnect 152 may be between and couple the corresponding conductive contacts 126 in the conductive contacts 146 and the conductive contacts 126. In some embodiments, the underfill material 127 may extend between the glass core 110 and the package substrate 102 around the associated GCTPS interconnect 152.

[0058] Included as in reference Figure 1 or Figure 2 The glass core 110 included in the microelectronic component 100 described or included in any other microelectronic component or device may be subjected to TGV stress before being included in the microelectronic component 100. For example, Figure 3 shows the surface of the glass core 110 from which TGV stress may be induced according to some embodiments of the present disclosure. As Figure 3 shown, the glass core 110 may have a first side 190-1 and an opposite second side 190-2, and when the glass core 110 is included in the microelectronic component 100, the first side 190-1 and the opposite second side 190-2 may be, for example, the bottom surface and the top surface of the glass core 110. The glass core 110 may further include a side surface 190-3, and the side surface 190-3 is the surface of the glass core 110, which may be referred to as the edge or side of the glass core 110, that is, the surface extending between the first side 190-1 and the second side 190-2. As Figure 3Further shown, the TGV opening 192 can be formed in the glass core 110, extending between the first side 190-1 and the second side 190-2. The sidewall 190-4 can then refer to one or more sidewalls of the TGV opening 192. When depositing conductive material in the TGV opening 192, due to the CTE mismatch between the glass material of the glass core 110 and the conductive material in the TGV opening 192, TGV stress may be induced from the sidewall 190-4.

[0059] Before including the glass core 110 in the microelectronic component 100, one or more techniques for TGV stress mitigation as described herein can be applied to reduce the TGV stress at the sidewall 190-4. Generally speaking, the techniques described herein can be classified into techniques based on providing a buffer layer between the glass material of the glass core 110 and the conductive material of the TGV 115 (e.g., Figures 4A - 11C the techniques shown in Figures 12A - 13C ), and techniques based on modifying the architecture and arrangement of the TGV 115 (e.g., Figures 4A - 7C the techniques shown in Figures 8A - 9D ). The techniques based on buffering the TGV stress can be further classified into techniques based on using a surface charge-driven buffer coating (e.g., Figures 10A - 11C the techniques shown in

[0060] ), techniques based on using a porous buffer layer (e.g., Figures 4A - 7C the techniques shown in Figures 4A - 5 ), and techniques based on using vapor deposition (e.g., Figures 6A - 7C the techniques shown in

[0061] Figures 4A - 4D ). In some embodiments, each of the techniques described herein can be implemented in the glass core 110 as the sole technique for helping to mitigate the TGV stress. In other embodiments, two or more different techniques described herein can be implemented in the glass core 110 in any combination. Details of the various techniques will now be described. Figure 4A Figure 4A Figure 4Aand shown in many other subsequent figures as having straight sidewalls 190-4, but in various embodiments, the shape of the TGV opening 192 can be different. For example, the shape can be an hourglass shape (as shown for the TGV 115 in Figure 2 ). Thereafter, layer-by-layer self-assembly can be performed to deposit cationic and anionic polyelectrolytes. Since the glass has a negative surface charge, layer-by-layer self-assembly can start by depositing a cationic polyelectrolyte. In some embodiments, the negative charge on the surface of the sidewalls 190-4 can be natural. In other embodiments, the glass core 110 can undergo a special treatment step after forming the TGV opening 192 and before depositing any polymer buffer layer to provide / enhance the negative charge on the surface of the sidewalls 190-4. Figure 4B shows the glass core 110 in Figure 4A after depositing the cationic polyelectrolyte 202. In some embodiments, the thickness of a single layer of the cationic polyelectrolyte 202 can be between about 1 nanometer and 500 nanometers, including all values and ranges therein. For example, between about 1 nanometer and 300 nanometers, or between about 2 nanometers and 200 nanometers. An example of a material that can be used as the cationic polyelectrolyte 202 is poly(diallyldimethylammonium chloride) (PDDA). In other embodiments, the cationic polyelectrolyte 202 can include polyethyleneimine. Figure 4C shows the glass core 110 in Figure 4B after depositing the anionic polyelectrolyte 204. In some embodiments, the thickness of a single layer of the anionic polyelectrolyte 204 can be substantially the same as the thickness of a single layer of the cationic polyelectrolyte 202. An example of a material that can be used as the anionic polyelectrolyte 204 is poly(sodium 4-styrenesulfonate) (PSS). In other embodiments, the anionic polyelectrolyte 204 can include sulfonated polysulfone (SPS). In some embodiments, processes such as slot coating, spin coating, spray coating, dip coating, or inkjet printing can be used to deposit the layers of the cationic polyelectrolyte 202 and the anionic polyelectrolyte 204, which can be simple and very cost-effective, especially when compared to vacuum-based techniques (such as chemical vapor deposition (CVD) for depositing materials). In various embodiments, the layers of the cationic polyelectrolyte 202 and the anionic polyelectrolyte 204 on the sidewalls 190-4 of the TGV opening 192 can be detected using vibrational spectroscopy (such as Fourier transform infrared spectroscopy (FTIR) and Raman spectroscopy, NMR, elemental analysis (XPS), imaging (e.g., AFM, SEM, or TEM)).

[0062] In some embodiments, a single layer of the cationic polyelectrolyte 202 and a single layer of the anionic polyelectrolyte 204 in the buffer layer 206 can be sufficient to relieve TGV stress. In such embodiments, after depositing the anionic polyelectrolyte 204, as shown in Figure 4DAs shown, a conductive material 210 can be deposited in the TGV opening 192 to form the TGV 115. The conductive material 210 can include any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, and can be deposited using techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., evaporation or sputtering), CVD, ALD, or electroplating.

[0063] In other embodiments, multiple alternating layers of a cationic polyelectrolyte 202 and an anionic polyelectrolyte 204 can be deposited, for example, to achieve a desired total thickness of the buffer layer 206 on the sidewall 190-4. Figure 5 An example thereof is shown in Figure 5 showing Figure 4D a glass core 110 similar to the glass core shown in Figure 4D but where the buffer layer 206 includes an additional pair of alternating layers of the cationic polyelectrolyte 202 and the anionic polyelectrolyte 204 added on top of that shown in 2+ In various additional embodiments, the number of alternating layers of the cationic polyelectrolyte 202 and the anionic polyelectrolyte 204 can even be greater. To this end, self-assembly provides an efficient way to easily modify the thickness of the buffer layer 206 between the sidewall 190-4 and the conductive material 210, where the total thickness 208 of the buffer layer 206 on the sidewall 190-4 can be between about 2 nanometers and 20 micrometers, such as between about 2 nanometers and 10 micrometers, or between about 2 nanometers and 5 micrometers, or between about 10 nanometers and about 20 micrometers. Additionally, if the last layer of the buffer layer 206 is a layer of the anionic polyelectrolyte 204, some additional embodiments can include depositing positively charged Pd

[0064] Figures 4A - 5 showing TGV stress reduction based on the deposition of a buffer layer 206 formed from two or more alternating layers of a cationic polyelectrolyte 202 and an anionic polyelectrolyte 204. In other embodiments, a polymer buffer layer similar to the buffer layer 206 can be formed using the deposition of cationic π-conjugated oligomers / polymers shown in reference Figures 6A - 7C

[0065] Figures 6A - 6C shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows a process of depositing a cationic π-conjugated oligomer / polymer on the sidewall of a TGV opening to form a buffer layer. Figure 6A showing that the process can start with forming a TGV opening 192 in the glass core 110 (similar to​Figure 4A the TGV openings shown in). Thereafter, due to the natural negative charge on the surface of the glass core 110 (which can be natural or supported by additional processing steps, as referenced Figures 4A - 4D as described), cationic π-conjugated oligomers and / or polymers can attach to the sidewalls 190-4 of the TGV openings 192 to form a buffer layer 216. Figure 6B shows the glass core 110 in Figure 6A after the deposition of the cationic π-conjugated oligomer / polymer 212. In various embodiments, the thickness of the layer of the cationic π-conjugated oligomer / polymer 212 can be between about 2 nanometers and 20 micrometers, for example, between about 2 nanometers and 10 micrometers, or between about 2 nanometers and 5 micrometers, and can be adjusted as needed by adjusting the concentration of the oligomers and / or polymers in the cationic π-conjugated oligomer / polymer 212. In some embodiments, other deposition processes (e.g., spin coating or dip coating) can be used to deposit the cationic π-conjugated oligomer / polymer 212. Since it is based on electrostatic interactions, this deposition can form a uniform layer on the sidewalls 190-4 and the surface of the glass core 110. As Figure 6C shown, after the deposition of the buffer layer 216, the conductive material 210 can be deposited in the TGV openings 192, thereby forming the TGV 115. Figures 7A - 7C shows the structural formula of an example of the cationic π-conjugated oligomer / polymer 212 according to some embodiments of the present disclosure. In particular, Figure 7A shows the synthesized cationic π-conjugated oligomer 2QA-CCOE, Figure 7B shows the synthesized cationic π-conjugated oligomer 4QA-CCOE, and Figure 7C shows the synthesized cationic π-conjugated polymer CCPE.

[0066] Techniques for TGV stress mitigation based on the use of a porous buffer layer can include techniques using a polymer nanoemulsion buffer liner (referenced Figures 8A - 8D as described) and techniques using a sol-gel process to provide a porous buffer layer (referenced Figures 9A - 9D as described).

[0067] Figures 8A - 8D shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows the process of using a polymer nanoemulsion to provide a buffer layer on the sidewalls of the TGV openings. Figure 8A shows that the process can start with the formation of the TGV openings 192 in the glass core 110 (similar to the Figure 4A TGV openings shown in). Thereafter, the polymer nanoemulsion can be deposited onto the surface of the glass core 110 (including the sidewalls 190-4). Figure 8B shows theFigure 8A the glass core 110 therein. In various embodiments, the thickness of the layer 223 of the polymer nanoemulsion 222 can be between about 1 nanometer and 75 micrometers, such as between about 1 nanometer and 50 micrometers, or between about 1 nanometer and 20 micrometers, and can be adjusted as needed by adjusting the concentration of the polymer in the polymer nanoemulsion 222. In various embodiments, processes such as slot coating, spin coating, spray coating, dip coating, or inkjet printing can be used to deposit the polymer nanoemulsion 222. In some embodiments, the polymer nanoemulsion 222 can include polytetrafluoroethylene (PTFE) or other porous polymers. In some embodiments, the polymer of the polymer nanoemulsion 222 can have a relatively low viscosity, such as between about 1 centipoise (cP) and 50 cP, to make the coating process easier. Next, as Figure 8C shown, sintering can be applied to convert the polymer nanoemulsion 222 into a porous polymer structure 224. In some embodiments, sintering can include heating the Figure 8B glass core therein to a temperature of about 390 degrees Celsius (°C) for at least about 5 minutes. In some embodiments, the thickness of the porous polymer structure 224 can be between about 1 nanometer and 75 micrometers, such as between about 1 nanometer and 50 micrometers, or between about 1 nanometer and 20 micrometers. As Figure 8DAs shown, the layer of the porous polymer structure 224 can form a buffer layer 226 as a polymer nanoemulsion buffer liner, which can mitigate the TGV stress between the glass of the glass core 110 and the conductive material 210 deposited in the TGV opening 192 to form the TGV 115. In some embodiments, optionally, an ABF liner 225 (e.g., a layer including ABF) can be further deposited on top of the porous polymer structure 224. In this case, the buffer layer 226 can be a combination of the porous polymer structure 224 and the ABF liner 225, where the ABF liner 225 can enhance the rigidity of the buffer layer 226. In some embodiments, the thickness of the ABF liner 225 can be between about 500 nanometers and about 10 micrometers, e.g., between about 1 micrometer and 5 micrometers. In other embodiments, as needed and as permitted by the size of the TGV opening 192, the thickness of the ABF liner 225 can be higher than 10 micrometers, as long as there is remaining space for depositing the conductive material 210. In some embodiments, the porosity of the porous polymer structure 224 can be relatively low to ensure that the dielectric constant of the porous polymer structure 224 is relatively low, e.g., less than about 2. In some embodiments, the porous polymer structure 224 can have a relatively low Poisson's ratio, e.g., less than about 0.25, where Poisson's ratio can be defined as the negative ratio of the transverse strain to the axial strain. In some embodiments, the porous polymer structure 224 can have a relatively low Young's modulus, e.g., between about 1 gigapascal (GPa) and 10 GPa, where Young's modulus can be defined as the ratio of the stress to the strain in a material subjected to deformation. In some embodiments, the porous polymer structure 224 can have a relatively low CTE, e.g., between about 2 ppm / K and 15 ppm / K.

[0068] Figures 9A - 9D A cross-sectional side view of a glass core according to some embodiments of the present disclosure is shown, which shows providing a buffer layer on the sidewalls of a TGV opening using an organosol-gel process. Figure 9A It is shown that the process can start with forming a TGV opening 192 in the glass core 110 (similar to the Figure 4A TGV opening shown). Thereafter, a solution of the sol-gel material can be deposited onto the surface of the glass core 110 (including the sidewalls 190-4). Figure 9B It is shown after depositing the sol-gel material 232 Figure 9Athe glass core 110 therein. To this end, a sol-gel process can be used to produce a solution. The sol-gel process can involve converting monomers into a colloidal solution ("sol") that serves as a precursor to an integrated network of discrete particles or polymer network ("gel"). In various embodiments, processes such as slot coating, spin coating, spray coating, dip coating, or inkjet printing can be used to deposit the sol-gel material 232. In various embodiments, the thickness of the sol-gel material 232 can range from about 2 nanometers to 100 micrometers and can be adjusted as needed by adjusting the concentration of the monomers and the process parameters of the deposition method used in preparing the sol-gel solution. In some embodiments, the sol-gel material 232 can include metal alkoxides (such as aluminates, titanates, and zirconates) or non-metal alkoxides (such as alkoxysilanes (tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, triethoxy(octyl)silane, trimethoxymethylsilane, trimethoxyphenylsilane, allyltrimethoxysilane)) as precursors. In some embodiments, the solution of the sol-gel material 232 can have a relatively low viscosity, for example, between about 1 centipoise (cP) and 50 cP, to make the coating process easier. The sol-gel process is a simple, convenient, and efficient process that only involves hydrolysis and polycondensation reactions of metal alkoxide precursors. Next, a soft bake process can be applied to evaporate the solvent from the sol-gel material 232, and then a curing process can be carried out to enhance the mechanical properties and stability of the sol-gel material 232. As Figure 9C shown, due to the application of soft bake and curing, the sol-gel material 232 can be converted into a cured sol-gel material 234. In some embodiments, the soft bake and curing can include heating the Figure 9B glass core therein to a temperature between about 200 °C and 500 °C for at least 10 minutes. In some embodiments, the thickness of the cured sol-gel material 234 can range from about 1 nanometer to 1500 nanometers, for example, between about 50 nanometers and 1200 nanometers, or between about 100 nanometers and 1000 nanometers. As Figure 9DAs shown, a layer of the cured sol-gel material 234 can form a buffer layer 236 as a sol-gel buffer liner, which can mitigate the TGV stress between the glass of the glass core 110 and the conductive material 210 deposited in the TGV opening 192 in a subsequent process. In some embodiments, the porosity of the cured sol-gel material 234 can be relatively low to ensure that the dielectric constant of the cured sol-gel material 234 is relatively low, such as between about 1.5 and 3, or between about 1.7 and 3, or between about 1.5 and 2.5. In some embodiments, the cured sol-gel material 234 can have a relatively low Poisson's ratio, such as between 0.1 and about 0.25. In some embodiments, the cured sol-gel material 234 can have a relatively low Young's modulus, such as between about 3 GPa and 10 GPa. In some embodiments, the cured sol-gel material 234 can have a relatively low CTE (e.g., lower than the CTE of the conductive material 210 deposited in the TGV 115 as shown in Figure 9D ), such as between about 3 ppm / K and 20 ppm / K, such as between about 5 ppm / K and 12 ppm / K.

[0069] Based on the techniques for TGV stress mitigation using vapor deposition, as the name implies, it can be based on the vapor deposition of one or more polymer buffer layers. Examples of such techniques are described in Figures 10A - 11C . Specifically, the techniques for TGV stress mitigation using vapor deposition can include techniques using buffer layers and vapor infiltration (as described in Figures 10A - 10D ) and techniques using initiated vapor deposition or inorganic coating buffer layers (as described in Figures 11A - 11C ).

[0070] Figures 10A - 10D FIG. shows a cross-sectional side view of a glass core according to some embodiments of the present disclosure, which shows a process using a buffer layer based on vapor infiltration. Figure 10A FIG. shows that the process can start with forming a TGV opening 192 in the glass core 110 (similar to the TGV opening 192 shown in Figure 4A ). Thereafter, a buffer material 242 can be deposited on the surface and sidewalls 190-4 of the TGV opening 192. Figure 10B FIG. shows after providing the buffer material 242 Figure 11AThe glass core 110 therein. In some embodiments, the buffer material 242 may include monomers, oligomers, or polymers. For example, the buffer material 242 may include polymers such as epoxy resin, PTFE, poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or pPFDA (poly(1H,1H,2H,2H-perfluorodecyl acrylate)). In various embodiments, the thickness of the buffer material 242 on the sidewall 190-4 may range from about 2 nanometers to 100 micrometers and may be adjusted as needed by adjusting the concentration of monomers, oligomers, and / or polymers during the deposition of the buffer material 242. In some embodiments, the buffer material 242 may be deposited by chemical vapor deposition. In other embodiments, processes such as slot coating, spin coating, spray coating, dip coating, or inkjet printing may be used to deposit the buffer material 242. Next, as Figure 10C shown, the particles 243 may be incorporated into the buffer material 242, thereby converting the buffer material 242 into a treated buffer material 244 containing the particles 243 and forming a buffer layer 246 of the treated buffer material 244. In some embodiments, the particles 243 may be deposited using vapor phase infiltration (e.g., using chemical vapor deposition with a metal-containing precursor). The particles 243 may be selected as needed to change the material properties of the buffer material 242 to (e.g.) help relieve TGV stress and / or improve (as Figure 10DAs shown, the adhesion of the conductive material 210 deposited in subsequent processes to the sidewall 190-4 of the TGV is improved, thereby improving via reliability. For example, the particles 243 can be selected to change the CTE of the buffer material 242 such that the CTE of the treated buffer material 244 is closer to the CTE of the glass material of the glass core 110. For example, in some embodiments, the CTE of the treated buffer material 244 may be relatively low and lower than the CTE of the conductive material 210 deposited in subsequent TGV processes, such as between about 3 ppm / K and 20 ppm / K, such as between about 5 ppm / K and 12 ppm / K. In some embodiments, the particles 243 can include inorganic particles, which can include silicon (e.g., as part of silica particles) or aluminum (e.g., as part of alumina particles). By utilizing the filled buffer layer 246 deposited using vapor infiltration deposition, a wider material selection can be achieved to allow for improved adhesion between the glass and the conductive material 210 and stress relief at the sidewall 190-4 of the TGV. In various embodiments, the thickness of the buffer layer 246 on the sidewall 190-4 can be in a range substantially the same as the thickness of the buffer material 242 described above. In some embodiments, the particles 243 can be incorporated into the buffer material 242 such that the concentration of the particles 243 varies throughout the thickness of the buffer layer 246. Specifically, the concentration of the particles can exhibit a gradient, where the particles 243 can have a greater concentration the farther away from the glass core 110, and the concentration can decrease in the portion of the buffer layer 246 closer to the glass core 110.

[0071] Figures 11A - 11C A cross-sectional side view of a glass core according to some embodiments of the present disclosure is shown, which shows a process of depositing other buffer layers on the sidewalls of the TGV openings. Figure 11A It is shown that the process can begin with forming a TGV opening 192 in the glass core 110 (similar to the TGV opening shown in Figure 4A ). Thereafter, a buffer material 252 can be deposited on the surface and sidewalls 190-4 of the TGV opening 192 to form a buffer layer 256. Figure 11B It is shown that after providing the buffer layer 256 Figure 11A in the glass core 110. As shown in Figure 11C , after depositing the buffer layer 256, the conductive material 210 can be deposited in the TGV opening 192, thereby forming a TGV 115.

[0072] In some embodiments, the buffer material 252 may include polymers such as PTFE, poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or pPFDA (poly(1H,1H,2H,2H-perfluorodecyl acrylate)). In such embodiments, an initiated chemical vapor deposition (iCVD) process may be used to deposit the buffer material 252. The monomers of such polymers are mainly made of carbon, nitrogen, oxygen, hydrogen, and other abundant elements, making such materials inexpensive. To complete the polymerization reaction on the surface, thermally activated initiator radicals activate the monomers on the surface (substrate), and polymerization begins on the surface. This property provides an opportunity to graft the polymer of the buffer material 252 to the substrate. In addition, due to the nature of the free radical polymerization that occurs during iCVD, it is possible to leave dangling bonds on the top surface of the buffer layer 256, thereby providing grafting sites for the next layer, which may be a metal or other type of material such as a polymer. Materials such as tert-butyl peroxide (TBPO) or perfluorobutanesulfonyl fluoride (PBSF) for PGMA can be used as initiators for the iCVD process. In various embodiments, the thickness of the buffer layer 256 formed by iCVD may be between about 1 nanometer and 75 micrometers, such as between about 1 nanometer and 50 micrometers, or between about 1 nanometer and 20 micrometers, and can be adjusted as needed by the deposition rate, deposition time, deposition pressure, and / or precursor (i.e., initiator and monomer) flow rate. In some embodiments, the buffer layer 256 may include initiator molecules for initiating the reaction, which are unique to the use of iCVD and can be detected by performing analysis, for example, by X-ray photoelectron spectroscopy (XPS) or FTIR. In various embodiments, any one of a trifluoromethyl group (e.g., -CF3 species), a carbonyl group (e.g., C=O species), an ester group (e.g., -O-C=O species), or a sulfonyl group can be detected in this way and indicates the use of iCVD.

[0073] Using the iCVD process can provide several advantages. One potential advantage is that the iCVD deposition rate can be significantly faster compared to ALD and PVD techniques. Another potential advantage is that the iCVD reactants (including monomers and initiators) can be made of abundant and cost-effective elements. Another potential advantage is that iCVD of polymers can achieve conformal deposition with a high aspect ratio (>100). In addition, since the reaction in iCVD starts on the substrate surface (e.g., glass, metal, etc.), improved chemical bonding with metal and oxide surfaces can be achieved, resulting in a very strong adhesion between the deposited buffer layer 256 and the underlying surface, regardless of substrate roughness.

[0074] In other embodiments, the buffer material 252 may include an organosilicate deposited on the sidewall 190-4 as a buffer layer 256 (e.g., a compound containing both organic groups and silicon-oxygen (Si-O) bonds in its molecular structure, such as Si x O y C z H or SiOC film). These films typically have high tensile strength, and the mechanical and dielectric properties are highly tunable based on the precursor type and ratio, process conditions, and the presence of added pore-forming agent materials, which can result in films with modulus values as low as 3-4 GPa. In such embodiments, a plasma-enhanced CVD (PECVD) process may be used to deposit the buffer material 252. In various embodiments, the thickness of the buffer layer 256 formed of the organosilicate film may range from about 250 nanometers or 500 nanometers to about 10-20 micrometers and can be adjusted as needed by deposition time, precursor gas flow rate, substrate temperature, radio frequency (RF) power, etc. In some embodiments, compared to other deposition techniques (such as spin coating or dip coating), characteristic features indicative of the use of PECVD to deposit the buffer material 252 may be present in the buffer layer 256. For example, the PECVD film of the buffer material 252 described herein may have better three-dimensional crosslinking, making the buffer material 252 mechanically stronger (e.g., tougher or harder). In another example, the conformality of the PECVD film of the buffer material 252 described herein may be much higher than that of similar films deposited by other techniques. In yet another example, the film thickness profile of the PECVD film of the buffer material 252 described herein within the TGV opening 192 may also indicate the PECVD process (if the process consists of two subsequent single-sided depositions). In this case, the film around the center / waist of the TGV will be significantly thinner.

[0075] In Figures 12A - 13C is shown a technique for alleviating TGV stress based on a modified TGV 115 architecture and arrangement, followed by an illustration of glass core patterning to form conductive traces as shown in Figures 14A - 14D using the TGV stress alleviation techniques described herein.

[0076] Figures 12A - 12D Shown are TGVs with different patterns of conductive materials and TGV stress-resistant materials according to some embodiments of the present disclosure. Specifically, Figure 12AShows a glass core 110 having TGVs 115 extending between a first side 190-1 and a second side 190-2, where the TGVs 115 are intentionally made to have an hourglass shape. This can be achieved, for example, by etching the glass to form half of the TGV opening 192 from the first side 190-1 and then etching the glass to form the other half of the TGV opening 192 from the second side 190-2. With this shape, it is possible to deposit the conductive material 210 only on the sidewalls 190-4 of the TGV 115, with a gap near the first side 190-1 and the second side 190-2 in the center of the TGV 115, which can then be filled with a filler material 260. To this end, in some embodiments, any suitable conformal plating technique can be used to deposit the conductive material 210 inside the TGV 115 such that the TGV opening has the conductive material 210 deposited on the sidewalls 190-4 without completely filling the opening. Alternatively, in some embodiments, the TGV 115 can first be completely filled with the conductive material 210, and then portions of the conductive material 210 can be removed to form a gap that will be filled with the filler material 260. As Figure 12A shown, the filler material 260 can include any suitable TGV stress-relieving material (e.g., any suitable material having a CTE less than that of the conductive material 210), and can be filled in the opening in the TGV 115. In some embodiments, the filler material 260 can include any of the materials described above as having a relatively low CTE, such as any of the materials described with reference to the buffer layers 206, 216, 226, 236, 246, and 256. Placing the filler material 260 in the center of the TGV 115 can help reduce the annealing stress and residual stress applied to the glass core 110 by reducing the radial expansion of the conductive material 210.

[0077] Figure 12A Shows an embodiment in which the conductive material 210 has substantially the same thickness (e.g., the dimension measured perpendicular to the sidewalls 190-4) from the first side 190-1 to the second side 190-2 of the glass core 110. On the other hand, Figure 12B shows an embodiment similar to Figure 12A except that the thickness of the conductive material 210 varies between the first side 190-1 and the second side 190-2. Specifically, as Figure 12B shown, the conductive material 210 can have a maximum thickness substantially in the middle of the TGV 115 (e.g., in the portion shown by the line 262-1), but the thickness can taper (i.e., gradually decrease) towards the first side 190-1 and towards the second side 190-2. Thus, the glass core 110 is in Figure 12BThe thickness of the conductive material 210 in the portion shown by line 262-2 can be less than the thickness of the conductive material 210 in the portion shown by line 262-1, and the glass core 110 is at Figure 12B The thickness of the conductive material 210 in the portion shown by line 262-3 can be less than the thickness of the conductive material 210 in the portion shown by line 262-2. The tapered profile of the conductive material 210 can help maintain a constant maximum current (Imax) that can flow through the TGV. Figure 12B The embodiment shown in can allow for a greater reduction in TGV stress than Figure 12A The reduction in TGV stress shown in, but this may come at the cost of more complex manufacturability. Figure 12A The embodiment shown in may result in a lower reduction in TGV stress than Figure 12B The reduction in TGV stress shown in, but may be easier to manufacture.

[0078] Figure 12C and Figure 12D respectively show embodiments similar to the embodiments shown in Figure 12A and Figure 12B , but further show a buffer layer 266 that can be deposited on the sidewall 190-4 before depositing the conductive material 210. Thus, the buffer layer 266 can be interposed between the conductive material 210 and the glass material of the glass core 110. In various embodiments, the buffer layer 266 can take the form of any one of the buffer layers 206, 216, 226, 236, 246, and 256 described above. Providing the buffer layer 266 can help further reduce TGV stress.

[0079] Figures 13A - 13C shows the use of polymer-filled TGVs to reduce TGV stress according to some embodiments of the present disclosure. In particular, Figure 13A shows a glass core 110 having a plurality of TGVs 115 extending between a first face 190-1 and a second face 190-2 and a plurality of compensation TGVs 215 also extending between the first face 190-1 and the second face 190-2. In Figure 13A seven TGVs 115 and four compensation TGVs 215 are shown, but in other embodiments, any other number can be used for either the TGVs 115 or the compensation TGVs 215. Any of the TGVs 115 in the TGVs 115 can be according to any of the embodiments described herein (e.g., according to reference Figures 4A - 12DThe TGV 115 of any of the described embodiments). The TGV 215 may be similar in shape and size to the TGV 115, but may be filled with a compensating material 270 having a relatively low CTE without any substantial portion of the conductive material 210. In some embodiments, the TGV 215 may be completely filled with the compensating material 270. In other embodiments, the TGV 215 may be partially filled with the compensating material 270 (e.g., only on the sidewalls, e.g., similar to the buffer layers described herein), and have a gap in the center, where the gap may be substantially empty (i.e., as a void), or may be filled with some other non-metallic material. In some embodiments, the compensating material 270 may account for at least 50% or at least 75% of the volume of the TGV 215. In some embodiments, the TGV 215 may not include any metal. As Figure 13A shown, the compensating material 270 may include any suitable material having a CTE less than that of the conductive material 210, and may be filled in the openings in the TGV 215. The compensating material 270 may include any of the materials described above as having a relatively low CTE, such as any of the materials described with reference to the buffer layers 206, 216, 226, 236, 246, and 256. In some embodiments, the compensating material 270 may include any of the filled and unfilled dielectrics (e.g., polyimide, PBO, acrylic, urethane, silicone, or epoxy-based materials). Using a higher thermal shrinkage material as the compensating material 270 may allow for further compressive forces, thus allowing for improved glass cohesion. In some embodiments, the compensating material 270 may be a material having a high tensile strength and high elongation rate relative to the glass, which may help absorb stress from the materials of the build-up layer that may be placed on the glass core 110 (e.g., the build-up layer may then pull on the compensating material 270 rather than directly pulling on the glass), while also acting as a hardener, thus potentially increasing cohesion by pulling the glass together. Filling only some of the TGVs in the glass core 110 with the compensating material 270 such that the TGV 215 is not used for its conductivity (e.g., by not including any conductive material therein) may allow for compensating the total TGV stress in the glass core 110 caused by the conductive material 210 in the TGV 115. Filling the TGV 215 completely with the compensating material 270 in the form of any suitable polymeric material may help create stress release points within the glass core 110 to reduce or eliminate cracking of the glass core 110. In some embodiments, the TGV 215 may also help increase the cohesion of the glass by utilizing a resin having a high thermal shrinkage rate.

[0080] Figure 13A It is shown that in some embodiments the TGV 215 may be placed closer to the side 190-3 of the glass core 110. Figure 13BAn embodiment is also shown in which the TGV 215 is close to the perimeter of the glass core 110, but a top view of the glass core 110 is shown. However, in other embodiments, the position and arrangement of the TGV 215, its quantity, and the quantity of the TGV 115 can be different from those shown in Figure 13A and Figure 13B what is shown. Figure 13C It is further shown that the TGV 215 itself can be modified in shape to further improve cohesion. For example, in some embodiments, as shown in Figure 13C the TGV 215 can have a wider portion 217-1 close to the first face 190-1 and / or a wider portion 217-2 close to the second face 190-2, and have a narrower portion 217-3 (e.g., substantially located in the middle of the glass core 110) between the portions 217-1 and 217-2.

[0081] Improvements in TGV stress reduction according to various embodiments described herein can allow for architectures that were not possible before. For example, for a conventional organic core substrate, it is not possible to have embedded feature structures (e.g., conductive traces) on the surface of the core. It is also not possible to fabricate precise blind feature structures on the core. Thus, conventional techniques and previous solutions did not utilize the core layer to create an interconnect / wiring layer. All wiring structures (e.g., conductive traces) in the wiring structure are typically included in stacked layers (e.g., in the layer of dielectric material 112 above the glass core 110 and in another layer 111 below the glass core 110, or more generally, as part of the substrate 107 above and below the glass core 110, as described with reference to Figure 1 ). Each additional layer is an additional cost. Different from the organic substrate, the glass core (e.g., the glass core 110) described herein can have various conductive features embedded on its back surface and front surface (e.g., on the first face 190-1 and the second face 190-2), where a buffer layer as described herein can be used for TGV stress reduction. An example of this is shown in Figures 14A - 14D wherein Figures 14A - 14D a cross-sectional side view of a glass core according to some embodiments of the present disclosure is shown, which shows the process of patterning the glass core to form conductive traces. Figure 14A It is shown that the process can start with forming one or more modified regions 280 in the glass core 110. As shown in Figure 14BAs shown, the modified region 280 can be a region of the glass core 110 that has been modified in a manner that makes it etch - selective relative to the unmodified portion of the glass core 110, such that the modified region 280 can be removed in a subsequent process to form an opening 282 in its place. In some embodiments, the modified region 280 can be a region of the glass core 110 that has been affected by a laser (i.e., where the laser is used to modify the material properties in the modified region 280 to make it etch - selective relative to the unmodified portion of the glass core 110). Next, as Figure 14C shown, a buffer layer 286 can be deposited on the exposed surface of the opening 282. The buffer layer 286 can be in the form of any one of the buffer layers 206, 216, 226, 236, 246, and 256 described above. Finally, as Figure 14D shown, a conductive material 210 can be filled in the opening 282 lined with the buffer layer 286. As described above, the buffer layer 286 can help mitigate the TGV stress between the conductive material 210 and the glass material of the glass core 110. In this way, various conductive features, such as TGVs 115, can be formed in the glass core 110, which are respectively labeled as TGV 115 - 1, 115 - 2, 115 - 3, and 115 - 4 in Figure 14D . Any one of TGVs 115 - 1, 115 - 2, 115 - 3, and 115 - 4 can be a TGV 115 according to any of the embodiments described herein (e.g., according to any of the embodiments described with reference to Figures 4A - 12D ). In addition to the TGV 115, other conductive features can be formed on the face 190 of the glass core 110, examples of which are shown by conductive traces 288 in Figure 14D , and the conductive traces 288 are respectively labeled as conductive traces 288 - 1 and 288 - 2 in Figure 14D . The conductive trace 288 - 1 can be used to provide electrical wiring at the first face 190 - 1, and the conductive trace 288 - 2 can be used to provide electrical wiring at the second face 190 - 2, similar to the conductive trace 108A described above. In some embodiments, one or more conductive traces 288 can be connected (e.g., electrically continuous and materially continuous) to one or more TGVs 115. For example, Figure 14D shows that the conductive trace 288 - 1 can be connected to the TGV 115 - 1 (e.g., can have a materially continuous conductive material 210), while the conductive trace 288 - 2 can be connected to the TGV 115 - 3 at one end and to the TGV 115 - 4 at the other end. By using the glass core 110 itself for wiring (as shown by the conductive trace 288 in Figure 14D ), the number of stacked layers can be reduced (e.g., Figure 1(the number of wiring layers in the dielectric material 112 of the substrate 107 shown). Even if there is not enough free space on the glass core 110 for a large number of conductive traces, it is still possible to have some electrical wiring on the glass core 110, which will require less wiring in the stacked layer. Further, the extra space in the stacked layer can be used for other purposes, for example, for implementing dummy metal regions to improve the plating uniformity on these layers.)

[0082] As Figures 1 - 14D shown, the various arrangements of the microelectronic component 100 and the glass core 110 do not represent an exhaustive set of microelectronic components and glass cores for which the various techniques for TGV stress reduction described herein can be used, but only provide some illustrative examples. Specifically, Figures 1 - 14D the number and position of the various elements shown in are purely illustrative, and in various other embodiments, according to the general architectural considerations described herein, other numbers of these elements provided in other positions relative to each other can be used. For example, although not specifically shown in the current figures, in some embodiments, the microelectronic component 100 can include Figure 1 and Figure 2 a redistribution layer (RDL) between any pair of layers shown, the RDL including a plurality of interconnect structures (e.g., wires and conductive vias) to assist in routing signals and / or power between components. In another example, although not specifically shown in this figure either, in some embodiments, the package substrate 102 of the microelectronic component 100 can include one or more recesses. In such an embodiment, the bottom surface of the recess in the package substrate 102 can be provided by the solid material of the package substrate 102. The recess can be formed in the package substrate 102 in any suitable manner (e.g., via three-dimensional printing, laser cutting, or drilling a recess in an existing package substrate, etc.). At least a portion of the substrate 107 or the glass core 110 can be located above or at least partially within such a recess. In yet another example, Figures 1 - 14D the features in any one of the figures in can be combined with Figures 1 - 14D the features of any other figure in.)

[0083] The microelectronic component 100 and / or the glass core 110 disclosed herein can be included in any suitable electronic component.) Figures 15 - 18 Shows various examples of devices that can include or be included in any one of the microelectronic component 100 and / or the glass core 110 disclosed herein.)

[0084] Figure 15is a top view of a wafer 1500 and dies 1502 that can be included in any microelectronic component as described herein in the microelectronic component 100. For example, die 1502 can be any of the dies 114 described herein. Wafer 1500 can be composed of a semiconductor material and can include one or more dies 1502 having IC structures formed on the surface of wafer 1500. Each die in dies 1502 can be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is completed, wafer 1500 can undergo a singulation process, in which dies 1502 are separated from each other to provide discrete "chips" of the semiconductor product. Dies 1502 can include one or more transistors (e.g., some of the transistors 1640 discussed below) and / or support circuitry for routing electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 can include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. A plurality of these devices can be combined on a single die 1502. For example, a memory array formed of a plurality of memory devices can be formed on the same die 1502 as a processing device (e.g., the processing device 1802 in) or other logic unit configured to store information in the memory device or execute instructions stored in the memory array. Figure 16 Some of the transistors in transistor 1640) and / or support circuitry for routing electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 can include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. A plurality of these devices can be combined on a single die 1502. For example, a memory array formed of a plurality of memory devices can be formed on the same die 1502 as a processing device (e.g., the processing device 1802 in) or other logic unit configured to store information in the memory device or execute instructions stored in the memory array. Figure 18 The processing device 1802 in) or other logic unit configured to store information in the memory device or execute instructions stored in the memory array.

[0085] Figure 16 is a side cross-sectional view of an IC device 1600 that can be included in any microelectronic component as described herein in the microelectronic component 100. For example, IC device 1600 can be provided on / within any of the dies 114 described herein. IC device 1600 can be formed on a substrate 1602 (e.g., Figure 15 The wafer 1500 in), and can be included in a die (e.g., Figure 15into the die 1502). The substrate 1602 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 can be formed using alternative materials that may or may not be combined with silicon, the alternative materials including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as group III-V materials (i.e., materials from groups III and V of the periodic table), group II-VI materials (i.e., materials from groups II and VI of the periodic table), or group IV materials (i.e., materials from group IV of the periodic table) can also be used to form the substrate 1602. Although some examples of materials that can form the substrate 1602 are described herein, any material that can serve as the basis for the IC device 1600 can be used. The substrate 1602 can be a singulated die (e.g., Figure 15 the die 1502) or a portion of a wafer (e.g., Figure 15 the wafer 1500).

[0086] The IC device 1600 can include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 can include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. For example, the device layer 1604 can include one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling current flow between the S / D regions 1620 in the transistor 1640, and one or more S / D contact portions 1624 for routing electrical signals to / from the S / D regions 1620. The transistor 1640 can include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1640 is not limited to Figure 16 the type and configuration depicted, and can include a wide variety of other types and configurations, e.g., planar transistors, non-planar transistors, or a combination of both. Planar transistors can include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors can include FinFET transistors (e.g., double-gate or triple-gate transistors) and gate-all-around or fully-gate-all-around transistors (e.g., nanoribbon and nanowire transistors).

[0087] Each transistor 1640 may include a gate 1622 formed of at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when using high-k materials.

[0088] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as a barrier layer. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0089] In some embodiments, when viewed in cross-section along the source-channel-drain direction of the transistor 1640, the gate electrode may be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may be only a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0090] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack therebetween. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0091] S / D regions 1620 may be formed within substrate 1602 adjacent to the gates 1422 of each transistor 1440. For example, an implantation / diffusion process or an etch / deposition process may be used to form S / D regions 1620. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into substrate 1602 to form S / D regions 1620. An annealing process may follow the ion implantation process, which activates the dopant and causes it to diffuse further into substrate 1602. In the latter process, substrate 1602 may first be etched to form a recess at the location of S / D regions 1620. Then, an epitaxial deposition process may be performed to fill the recess with the material used to fabricate S / D regions 1620. In some embodiments, an S / D region 1620 may be made of a silicon alloy (such as silicon germanium or silicon carbide). In some embodiments, an epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (such as germanium or III-V materials or alloys) may be used to form S / D regions 1620. In other embodiments, one or more layers of metal and / or metal alloy may be used to form S / D regions 1620.

[0092] Electrical signals (such as power and / or input / output (I / O) signals) may be routed to and / or from devices (such as transistors 1640) on device layer 1604 through one or more interconnect layers (shown as interconnect layers 1606, 1608, and 1610 in Figure 16 ). For example, conductive features (such as gates 1622 and S / D contacts 1624) on device layer 1604 may be electrically coupled to interconnect structures 1628 of interconnect layers 1606, 1608, and 1610. One or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an “ILD stack”) 1619 of IC device 1600.

[0093] The interconnect structure 1628 can be arranged within the interconnect layers 1606 - 1610 according to a wide variety of designs to route electrical signals (specifically, this arrangement is not limited to Figure 16 the specific configuration of the interconnect structure 1628 depicted therein). Although a specific number of interconnect layers 1606, 1608, and 1610 are depicted in Figure 16 , embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those depicted.

[0094] In some embodiments, the interconnect structure 1628 can include wires 1628a and / or vias 1628b filled with a conductive material (such as metal). The wires 1628a can be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a can route electrical signals in a direction into and out of the page from the perspective of Figure 16 . The vias 1628b can be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b can electrically couple the wires 1628a of different interconnect layers 1606, 1608, and 1610 together.

[0095] As Figure 16 shown, the interconnect layers 1606, 1608, and 1610 can include a dielectric material 1626 disposed between the interconnect structures 1628. In some embodiments, the dielectric material 1626 between the interconnect structures 1628 in different interconnect layers disposed in the interconnect layers 1606, 1608, and 1610 can have different compositions; in other embodiments, the compositions of the dielectric material 1626 between the different interconnect layers 1606, 1608, and 1610 can be the same.

[0096] A first interconnect layer 1606 can be formed above the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 can include wires 1628a and / or vias 1628b. The wires 1628a of the first interconnect layer 1606 can be coupled to the contacts (e.g., S / D contacts 1624) of the device layer 1604.

[0097] A second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 to the lines 1628a of the first interconnect layer 1606. Although, for clarity, the lines 1628a and vias 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments, the lines 1628a and vias 1628b may be continuous structurally and / or materially (e.g., filled simultaneously during a dual-damascene process).

[0098] A third interconnect layer 1610 (and additional interconnect layers as needed) may be formed continuously over the second interconnect layer 1608 according to similar techniques and constructs described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers “higher in level” (i.e., farther from the device layer 1604) in the metallization stack 1619 of the IC device 1600 may be thicker.

[0099] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed over the interconnect layers 1606, 1608, and 1610. In Figure 16 , the conductive contacts 1636 are shown as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628 and are configured to route electrical signals of the (multiple) transistors 1640 to other external devices. For example, a solder joint may be formed over one or more of the conductive contacts 1636 to mechanically couple and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for routing electrical signals from the interconnect layers 1606, 1608, and 1610; for example, the conductive contacts 1636 may include other similar features (e.g., pillars) for routing electrical signals to external components.

[0100] Figure 17Is a side cross-sectional view of an IC device assembly 1700 that may include a glass core with TGV stress relief according to any embodiment disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and on an opposite second side 1742 of the circuit board 1702; generally, components may be disposed on one or both of the sides 1740 and 1742. Any IC package in the IC package discussed below with reference to the IC device assembly 1700 may take the form of any embodiment of the microelectronic component 100 discussed above. For example, it may include one or more microelectronic components 100 as discussed with reference to Figure 1 and Figure 2 discussed, and / or may include one or more glass cores as discussed with reference to Figures 3 - 14D discussed.

[0101] In some embodiments, the circuit board 1702 may be a PCB including a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally, in combination with other metal layers) between components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0102] Figure 17 The IC device assembly 1700 shown in Figure 17 includes an on-interposer package structure 1736 coupled to the first side 1740 of the circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically couple the on-interposer package structure 1736 to the circuit board 1702 and may include solder balls (as shown in Figure 17 ), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical coupling and / or mechanical coupling structure.

[0103] The on-interposer package structure 1736 may include an IC package 1720 coupled to an interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the form discussed above with reference to the coupling component 1716. Although Figure 17 shows a single IC package 1720, multiple IC packages may be coupled to the interposer 1704; in fact, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intermediate substrate for bridging the circuit board 1702 and the IC package 1720. For example, the IC package 1720 may be or include a die ( Figure 5die 1502), an IC device (e.g., any IC device among the IC devices described herein, or any combination of such IC devices), or any other suitable component. Generally, the package interposer 1704 can extend the connections to a wider pitch or re-route the connections to different connections. For example, the package interposer 1704 can couple the IC package 1720 (e.g., die) to a set of ball grid array (BGA) conductive contacts of the coupling component 1716 for coupling to the circuit board 1702. In Figure 17 the illustrated embodiment, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 can be attached to the same side of the package interposer 1704. In some embodiments, three or more components can be interconnected by means of the package interposer 1704.

[0104] In some embodiments, the package interposer 1704 can be formed as a glass core with TGV stress relief, e.g., formed as any embodiment of the glass core 110 described herein. In some embodiments, the package interposer 1704 can be formed as a PCB. In some embodiments, the package interposer 1704 can be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material (e.g., polyimide). In some embodiments, the package interposer 1704 can be formed of alternative rigid or flexible materials that can include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the package interposer 1704 can include multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. The package interposer 1704 can include metal lines 1710 and vias 1708, which include but are not limited to conductive vias 1706. If the package interposer 1704 is a glass core, such as the glass core 110 described herein, the conductive via 1706 can be a TGV with stress relief as described herein. The package interposer 1704 can also include embedded devices 1714, including both passive and active devices. Such devices can include but are not limited to: capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the package interposer 1704. The interposer-on-package structure 1736 can take the form of any interposer structure known in the art.

[0105] The IC device assembly 1700 may include an IC package 1724 coupled to the first surface 1740 of the circuit board 1702 by a coupling component 1722. The coupling component 1722 may take the form of any of the embodiments discussed above with reference to the coupling component 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0106] Figure 17 The IC device assembly 1700 shown in includes a stacked package structure 1734 coupled to the second surface 1742 of the circuit board 1702 by a coupling component 1728. The stacked package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The stacked package structure 1734 may be configured according to any stacked package structure known in the art.

[0107] Figure 18 is a block diagram of an exemplary communication device 1800 that may include one or more microelectronic components 100 and / or one or more glass cores 110 according to any of the embodiments disclosed herein. A handheld communication device or a laptop communication device may be an example of the communication device 1800. Any suitable component of the communication device 1800 may include one or more of the microelectronic components 100, IC packages 1720, 1724, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. Specifically, any suitable component of the communication device 1800 may include one or more glass cores 110 as described herein, for example, as part of the microelectronic component 100 as described herein. Figure 18 A number of components included in the communication device 1800 are shown in, but any one or more of these components may be omitted or replicated to suit the application. In some embodiments, some or all of the components included in the communication device 1800 may be attached to one or more main boards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die.

[0108] Additionally, in various embodiments, the communication device 1800 may not include Figure 18One or more of the components shown in, but the communication device 1800 may include interface circuitry for coupling to one or more components. For example, the communication device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the communication device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0109] The communication device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The communication device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drives. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0110] In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured to manage wireless communication for transmitting data to and from the communication device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. The communication module 1812 may be or may include any of the microelectronic components 100 disclosed herein.

[0111] The communication module 1812 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates, and / or amendments (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks. WiMAX is an acronym representing Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed the compliance and interoperability tests for the IEEE 802.16 standard. The communication module 1812 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication module 1812 may operate according to Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher generations. In other embodiments, the communication module 1812 may operate according to other wireless protocols. The communication device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions). The antenna 1822 may include one or more microelectronic components 100 and / or one or more glass cores 110 as described herein, e.g., as part of the microelectronic component 100 as described herein.

[0112] In some embodiments, the communication module 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication module 1812 may include multiple communication modules. For example, a first communication module 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication module 1812 may be dedicated to wireless communications, and the second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may support millimeter-wave communications.

[0113] The communication device 1800 may include a battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the communication device 1800 to an energy source (e.g., an AC line power) that is separate from the communication device 1800.

[0114] The communication device 1800 may include a display device 1806 (or a corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0115] The communication device 1800 may include an audio output device 1808 (or a corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an auditory indicator, such as a speaker, headphones, or earbuds.

[0116] The communication device 1800 may include an audio input device 1824 (or a corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0117] The communication device 1800 may include a GPS device 1818 (or a corresponding interface circuitry, as discussed above). As is known in the art, the GPS device 1818 may communicate with a satellite-based system and may receive the location of the communication device 1800.

[0118] The communication device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0119] The communication device 1800 may include other input devices 1820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse), a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0120] The communication device 1800 may have any desired form factor, such as a handheld or mobile communication device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a ultrabook computer, a personal digital assistant (PDA), a ultra-mobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device that processes data.

[0121] The following paragraphs provide examples of various embodiments disclosed herein.

[0122] Example 1 provides a microelectronic component including a glass core having a first face and a second face opposite the first face (e.g., a glass layer including a rectangular prism volume), and including through-glass vias (TGVs) extending between the first face and the second face, wherein the TGVs include a conductive material and a buffer layer located between the conductive material and the glass core, and wherein the coefficient of thermal expansion (CTE) of the buffer layer is less than the CTE of the conductive material.

[0123] Example 2 provides the microelectronic component according to Example 1, wherein the buffer layer includes silicon and oxygen.

[0124] Example 3 provides the microelectronic component according to Example 1, wherein the buffer layer includes silicon, oxygen, and carbon.

[0125] Example 4 provides the microelectronic component according to Example 1, wherein the buffer layer includes silicon, oxygen, carbon, and hydrogen.

[0126] Example 5 provides the microelectronic component according to any of the preceding examples, wherein the buffer layer includes an organosilicate film.

[0127] Example 6 provides a microelectronic component according to any of the foregoing examples, wherein the thickness of the buffer layer is between about 250 nanometers and about 20 micrometers.

[0128] Example 7 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a cationic polyelectrolyte.

[0129] Example 8 provides a microelectronic component according to Example 7, wherein the cationic polyelectrolyte comprises poly(diallyldimethylammonium chloride) (PDDA) or polyethyleneimine.

[0130] Example 9 provides a microelectronic component according to any of Examples 7-8, wherein the thickness of the cationic polyelectrolyte is between about 1 nanometer and about 500 nanometers.

[0131] Example 10 provides a microelectronic component according to any of Examples 7-9, wherein the buffer layer further comprises an anionic polyelectrolyte.

[0132] Example 11 provides a microelectronic component according to Example 10, wherein the anionic polyelectrolyte comprises poly(sodium 4-styrenesulfonate) (PSS) or sulfonated polysulfone (SPS).

[0133] Example 12 provides a microelectronic component according to any of Examples 10-11, wherein the thickness of the anionic polyelectrolyte is between about 1 nanometer and about 500 nanometers.

[0134] Example 13 provides a microelectronic component according to any of Examples 10-12, wherein the buffer layer is a multilayer structure comprising a first layer and a second layer, the first layer comprises a cationic polyelectrolyte, the second layer comprises an anionic polyelectrolyte, and the first layer is between the glass core and the second layer.

[0135] Example 14 provides a microelectronic component according to Example 13, wherein the second layer is between the first layer and the conductive material.

[0136] Example 15 provides a microelectronic component according to Example 14, wherein the second layer is in contact with the conductive material.

[0137] Example 16 provides a microelectronic component according to any of Examples 13 to 15, wherein the multilayer structure further comprises a third layer, the third layer comprises a cationic polyelectrolyte, and the third layer is between the second layer and the conductive material.

[0138] Example 17 provides a microelectronic component according to Example 16, wherein the multilayer structure further comprises a fourth layer, the fourth layer comprises an anionic polyelectrolyte, and the fourth layer is between the third layer and the conductive material.

[0139] Example 18 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a cationic π-conjugated oligomer.

[0140] Example 19 provides a microelectronic component according to Example 1, wherein the cationic polyelectrolyte comprises a cationic π-conjugated polymer.

[0141] Example 20 provides a microelectronic component according to Example 1, wherein the cationic polyelectrolyte comprises a cationic π-conjugated oligomer and a cationic π-conjugated polymer.

[0142] Example 21 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a porous polymer structure.

[0143] Example 22 provides a microelectronic component according to Example 21, wherein the buffer layer comprises polytetrafluoroethylene (PTFE).

[0144] Example 23 provides a microelectronic component according to any one of Examples 21-22, wherein the buffer layer further comprises a liner layer, and the liner layer comprises ABF.

[0145] Example 24 provides a microelectronic component according to Example 23, wherein the thickness of the liner layer is between about 1 micron and about 10 microns.

[0146] Example 25 provides a microelectronic component according to any one of Examples 21-24, wherein the Poisson's ratio of the buffer layer is less than about 0.25.

[0147] Example 26 provides a microelectronic component according to any one of Examples 21-25, wherein the Young's modulus of the buffer layer is less than about 10 GPa.

[0148] Example 27 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a metal alkoxide.

[0149] Example 28 provides a microelectronic component according to Example 27, wherein the buffer layer comprises an aluminate, a titanate or a zirconate.

[0150] Example 29 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a non-metal alkoxide.

[0151] Example 30 provides a microelectronic component according to Example 29, wherein the buffer layer comprises an alkoxysilane.

[0152] Example 31 provides a microelectronic component according to Example 29 or 30, wherein the buffer layer comprises at least one of tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, triethoxy(octyl)silane, trimethoxymethylsilane, trimethoxyphenylsilane or allyltrimethoxysilane.

[0153] Example 32 provides a microelectronic component according to any one of Examples 27-31, wherein the Poisson's ratio of the buffer layer is less than about 0.25.

[0154] Example 33 provides a microelectronic component according to any one of Examples 27 - 32, wherein the Young's modulus of the buffer layer is less than about 10 GPa.

[0155] Example 34 provides a microelectronic component according to Example 1, wherein the buffer layer comprises a matrix, the matrix comprises a monomer, an oligomer or a polymer, and the buffer layer further comprises particles embedded in the matrix.

[0156] Example 35 provides a microelectronic component according to Example 34, wherein the particles comprise one or more inorganic materials.

[0157] Example 36 provides a microelectronic component according to any one of Examples 34 - 35, wherein the particles comprise silicon (e.g., silicon oxide).

[0158] Example 37 provides a microelectronic component according to any one of Examples 34 - 36, wherein the particles comprise aluminum (e.g., aluminum oxide).

[0159] Example 38 provides a microelectronic component according to any one of Examples 34 - 37, wherein the particles comprise zinc (e.g., zinc oxide) or titanium (e.g., titanium oxide).

[0160] Example 39 provides a microelectronic component according to any one of Examples 34 - 38, wherein the concentration of the particles decreases in the direction from the conductive material to the glass core.

[0161] Example 40 provides a microelectronic component according to any one of Examples 34 - 39, wherein the concentration of the particles is highest at the interface between the buffer layer and the conductive material.

[0162] Example 41 provides a microelectronic component according to Example 1, wherein the buffer layer comprises PTFE, poly(1,3,5 - trimethyl - 1,3,5 - trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7 - tetravinyl - 1,3,5,7 - tetramethylcyclotetrasiloxane) (pV4D4) or pPFDA (poly(1H,1H,2H,2H - perfluorodecyl acrylate)).

[0163] Example 42 provides a microelectronic component according to Example 41, wherein the buffer layer further comprises tert - butyl peroxide (TBPO for PGMA) or perfluorobutanesulfonyl fluoride (PBSF).

[0164] Example 43 provides a microelectronic component according to Example 1, wherein the buffer layer comprises one or more trifluoromethyl groups in the trifluoromethyl group.

[0165] Example 44 provides a microelectronic component according to Example 1, wherein the buffer layer comprises one or more carbonyl groups in the carbonyl group.

[0166] Example 45 provides a microelectronic component according to Example 1, wherein the buffer layer comprises one or more sulfonyl groups in a sulfonyl group.

[0167] Example 46 provides a microelectronic component according to any of the foregoing examples, further comprising a conductive trace in a recess at a first side of the glass core.

[0168] Example 47 provides a microelectronic component according to Example 46, wherein the conductive trace comprises a conductive material and a buffer layer located between the conductive material and the glass core.

[0169] Example 48 provides a microelectronic component according to Example 47, wherein the conductive material of the conductive trace is materially continuous with the conductive material of the TGV.

[0170] Example 49 provides a microelectronic component according to Example 47 or 48, wherein the buffer layer of the conductive trace is materially continuous with the buffer layer of the TGV.

[0171] Example 50 provides a microelectronic component according to any of Examples 46 - 49, further comprising a buffer layer at a first side of the glass core.

[0172] Example 51 provides a microelectronic component according to any of the foregoing examples, wherein the TGV further comprises a filler material, and wherein the conductive material is between the buffer layer and the filler material.

[0173] Example 52 provides a microelectronic component according to Example 51, wherein the CTE of the filler material is less than the CTE of the conductive material.

[0174] Example 53 provides a microelectronic component according to any of Examples 51 - 53, wherein the CTE of the filler material is less than about 15 ppm / K.

[0175] Example 54 provides a microelectronic component according to any of Examples 51 - 54, wherein the width of the TGV decreases from a first side towards a second side to a non - zero depth from the first side.

[0176] Example 55 provides a microelectronic component according to Example 54, wherein the thickness of the conductive material on the sidewall of the TGV is substantially constant between the first side and the second side.

[0177] Example 56 provides a microelectronic component according to Example 55, wherein the non - zero depth is a first non - zero depth, and wherein the width of the TGV decreases from the second side towards the first side to a second non - zero depth from the second side.

[0178] Example 57 provides a microelectronic component according to Example 54, wherein the non-zero depth is a first non-zero depth, and wherein the width of the TGV decreases from the second face to a second non-zero depth from the second face towards the first face.

[0179] Example 58 provides a microelectronic component according to Example 54, wherein the thickness of the conductive material on the sidewall of the TGV increases from the first face to a non-zero depth from the first face towards the second face.

[0180] Example 59 provides a microelectronic component according to Example 58, wherein the non-zero depth is a first non-zero depth, and wherein the thickness of the conductive material on the sidewall of the TGV increases from the second face to a second non-zero depth from the second face towards the first face.

[0181] Example 60 provides a microelectronic component according to Example 59, wherein the width of the TGV decreases from the second face to a second non-zero depth from the second face towards the first face.

[0182] Example 61 provides a microelectronic component according to any one of the foregoing examples, wherein: the TGV is a first TGV, the glass core further includes a second TGV extending through the glass core between the first face and the second face, and the compensation material occupies at least 50% of the volume of the second TGV.

[0183] Example 62 provides a microelectronic component according to Example 61, wherein the compensation material occupies at least 75% of the volume of the second TGV.

[0184] Example 63 provides a microelectronic component according to any one of Examples 61-62, wherein the CTE of the compensation material is less than the CTE of the conductive material.

[0185] Example 64 provides a microelectronic component according to any one of Examples 61-63, wherein the CTE of the compensation material is less than about 10 ppm / K.

[0186] Example 65 provides a microelectronic component according to any one of Examples 61-64, wherein the second TGV is closer to the edge of the glass core than the first TGV.

[0187] Example 66 provides a microelectronic component according to any one of the foregoing examples, wherein the CTE of the buffer layer is less than about 15 ppm / K.

[0188] Example 67 provides a microelectronic component according to any one of the foregoing examples, wherein the CTE of the buffer layer is less than about 10 ppm / K.

[0189] Example 68 provides a microelectronic component according to any one of the foregoing examples, wherein the thickness of the buffer layer is between about 10 nanometers and about 20 micrometers.

[0190] Example 69 provides a microelectronic component according to any of the preceding examples, wherein the conductive material is a metal or a metal alloy.

[0191] Example 70 provides a microelectronic component according to any of the preceding examples, wherein the conductive material comprises one or more of copper, silver, nickel, gold, or aluminum.

[0192] Example 71 provides a microelectronic component comprising: a glass layer including a rectangular prism volume; and a via extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the via including a metal, wherein: the via has a first thickness in a first plane parallel to the first side, a second thickness in a second plane parallel to the first side, and a third thickness in a third plane parallel to the first side, the second plane being between the first plane and the third plane, the second thickness being less than the first thickness and the third thickness, the via further including a filler material, the metal being between the filler material and the glass of the rectangular prism volume, and the CTE of the filler material being less than the CTE of the metal.

[0193] Example 72 provides a microelectronic component according to Example 71, wherein the CTE of the filler material is less than about 10 ppm / K.

[0194] Example 73 provides a microelectronic component according to Example 71 or 72, wherein: the via includes a first region including a filler material and a second region including a filler material, and the filler material in the first region is materially discontinuous with the filler material in the second region.

[0195] Example 74 provides a microelectronic component according to Example 73, wherein a portion of the first region is in a plane of the first side of the rectangular prism volume, and a portion of the second region is in a plane of the second side of the rectangular prism volume.

[0196] Example 75 provides a microelectronic component according to any of Examples 71 - 74, wherein the metal is located on the sidewalls of the via.

[0197] Example 76 provides a microelectronic component according to Example 75, wherein the thickness of the metal on the sidewalls of the via is substantially constant between the first side and the second side.

[0198] Example 77 provides a microelectronic component according to any of Examples 75 - 76, wherein the metal on the sidewalls of the via has a first thickness in the first plane, a second thickness in the second plane, and a third thickness in the third plane, and wherein the second thickness of the metal is greater than the first thickness of the metal and the third thickness of the metal.

[0199] Example 78 provides a microelectronic component including: a glass layer including a rectangular prism volume; a via extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the via including metal; and a conductive trace in a recess at the first side of the rectangular prism volume.

[0200] Example 79 provides the microelectronic component according to Example 78, further including metal in the conductive trace and in the via.

[0201] Example 80 provides the microelectronic component according to Example 79, wherein the metal of the conductive trace is materially continuous with the metal of the via.

[0202] Example 81 provides the microelectronic component according to any one of Examples 78 - 80, further including a buffer layer between the metal in the conductive trace and the rectangular prism volume.

[0203] Example 82 provides the microelectronic component according to Example 81, wherein the buffer layer includes a polymer.

[0204] Example 83 provides the microelectronic component according to Example 81, wherein the buffer layer is the buffer layer according to any one of Examples 1 - 70.

[0205] Example 84 provides the microelectronic component according to any one of the foregoing examples, wherein the glass core is a solid glass layer.

[0206] Example 85 provides the microelectronic component according to any one of the foregoing examples, wherein a cross - section of the glass core in a plane perpendicular to the surface of the component is substantially rectangular.

[0207] Example 86 provides the microelectronic component according to any one of the foregoing examples, wherein a cross - section of the glass core in a plane parallel to the surface of the component is substantially rectangular.

[0208] Example 87 provides the microelectronic component according to any one of the foregoing examples, wherein the glass core is a glass layer including at least 23% silicon by weight.

[0209] Example 88 provides the microelectronic component according to any one of the foregoing examples, wherein the glass core is a glass layer including at least 26% oxygen by weight.

[0210] Example 89 provides the microelectronic component according to any one of the foregoing examples, wherein the glass core is a glass layer including at least 23% silicon by weight and at least 26% oxygen by weight.

[0211] Example 90 provides the microelectronic component according to any one of the foregoing examples, wherein the glass core is a glass layer including at least 5% aluminum by weight.

[0212] Example 91 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer that does not include an organic binder or organic material.

[0213] Example 92 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a thickness in the range of 50 μm to 1.4 mm, a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0214] Example 93 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a thickness in the range of 50 μm to 1.4 mm.

[0215] Example 94 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer having a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0216] Example 95 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer including a rectangular prism volume.

[0217] Example 96 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer including a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 mm to 250 mm, and the second side having a length in the range of 10 mm to 250 mm.

[0218] Example 97 provides a microelectronic component according to any of the preceding examples, wherein the glass core is a glass layer including a rectangular prism volume and a via extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the via including metal.

[0219] The above description of the illustrated embodiments of the present disclosure (including what is described in the abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific embodiments and examples of the present disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those skilled in the art. These modifications can be made to the present disclosure in light of the above detailed description.

Claims

1. A microelectronic assembly comprising: a glass core having a first face and a second face opposite the first face and including a through glass via (TGV) extending between the first face and the second face, The TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a coefficient of thermal expansion (CTE) of the buffer layer is smaller than a CTE of the conductive material.

2. The microelectronic assembly according to claim 1, wherein: The buffer layer includes silicon and oxygen.

3. The microelectronic assembly according to claim 1, wherein: The buffer layer includes an organic silicate film.

4. The microelectronic assembly according to claim 1, wherein: The buffer layer includes one or more of polydiallyldimethylammonium chloride, polyethyleneimine, polystyrene sulfonate or sulfonated polysulfone.

5. The microelectronic assembly according to claim 1, wherein: The buffer layer is a multilayer structure including a first layer including a cationic polyelectrolyte, and a second layer including an anionic polyelectrolyte, the first layer being between the glass core and the second layer, and the second layer being between the first layer and the conductive material.

6. The microelectronic assembly according to claim 1, wherein: The buffer layer includes a cationic π-conjugated oligomer or a cationic π-conjugated polymer.

7. The microelectronic assembly of claim 1, wherein: The buffer layer includes polytetrafluoroethylene (PTFE).

8. The microelectronic assembly of claim 1, wherein: The buffer layer includes metal alkoxide or non-metal alkoxide.

9. The microelectronic assembly of claim 1, wherein: The buffer layer includes a matrix comprising a monomer, an oligomer, or a polymer, and further includes particles embedded in the matrix, wherein the particles include one or more inorganic materials.

10. The microelectronic assembly of claim 9, wherein: The concentration of the particles decreases in a direction from the conductive material to the glass core.

11. The microelectronic assembly of claim 1 , wherein: The buffer layer includes at least one of a trifluoromethyl group, a carbonyl group, or a sulfonyl group.

12. The microelectronic assembly of claim 1 further comprising a conductive trace in a recess at the first side of the glass core, wherein The conductive trace includes the conductive material and the buffer layer between the conductive material and the glass core.

13. The microelectronic assembly of claim 1, wherein: The TGV further includes a filler material, the conductive material is between the buffer layer and the filler material, and a CTE of the filler material is less than a CTE of the conductive material.

14. The microelectronic assembly of claim 13, wherein: A width of the TGV decreases from the first face to a non-zero depth from the first face toward the second face, and wherein a thickness of the conductive material on a sidewall of the TGV increases from the first face to the non-zero depth from the first face toward the second face.

15. The microelectronic assembly of claim 1, wherein: The TGV is the first TGV, The glass core further includes a second TGV extending between the first face and the second face, and The compensation material occupies at least 75% of the volume of the second TGV.

16. The microelectronic assembly of claim 15, wherein: The compensation material has a CTE of less than about 10 ppm / K, and wherein the second TGV is closer to an edge of the glass core than the first TGV.

17. A microelectronic assembly comprising: a glass layer, the glass layer comprising a rectangular prismatic volume; as well as a via extending from a first side of the rectangular prismatic volume to a second side of the rectangular prismatic volume, the via comprising metal, in: the via having a first thickness in a first plane parallel to the first side, a second thickness in a second plane parallel to the first side, and a third thickness in a third plane parallel to the first side, The second plane is between the first plane and the third plane, The second thickness is smaller than the first thickness and the third thickness, The via further comprises a filler material, The metal is between the filler material and the glass of the rectangular prismatic volume, and The filler material has a coefficient of thermal expansion (CTE) that is less than the CTE of the metal.

18. A microelectronic assembly as claimed in claim 17, wherein: The via comprises a first region including the filler material and a second region including the filler material, The filler material in the first region is materially discontinuous with the filler material in the second region, A portion of the first region is located in a plane of the first side of the rectangular prismatic volume, and A portion of the second region lies in a plane of the second side of the rectangular prism volume.

19. A microelectronic assembly comprising: a glass layer, the glass layer comprising a rectangular prismatic volume; a via extending from a first side of the rectangular prismatic volume to a second side of the rectangular prismatic volume, the via comprising metal; and A conductive trace in a recess at the first side of the rectangular prismatic volume.

20. The microelectronic assembly of claim 19, wherein: The metal is also in the conductive trace, and the metal of the conductive trace is materially continuous with the metal of the via.

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