Chip package

Abstract

A chip package is provided. The chip package includes a device substrate, at least one signal / power source pad, and a patterned metal plate. The device substrate has an active surface and a back side surface. The device substrate includes a first opening and a second opening extending through the device substrate from the backside surface to the active surface. The signal / power connection pad is arranged on the back side surface of the device substrate. The pattern metal plate is arranged on the back side surface and surrounds and separates the signal / power supply connecting pads. The pattern metal plate comprises a plurality of slit openings exposed out of the surface of the substrate, and the slit openings extend in a first direction and are arranged in parallel.

Description

Technical Field

[0001] Embodiments of the present invention relate to a packaging technology, and particularly to a wafer package having an electrical shielding structure and a mesh pad structure. Background Art

[0002] Optoelectronic components (e.g., image sensing devices) play an important role in applications such as image capture and have been widely used in electronic products such as digital cameras, digital video recorders, mobile phones, etc. The wafer packaging process is an important step in the formation of electronic products. The wafer package not only protects the sensing wafer therein from external environmental pollution but also provides an electrical connection path between the internal electronic components of the sensing wafer and the outside.

[0003] With the complication of the wafer packaging manufacturing process, many challenges have arisen. For example, electromagnetic interference (EMI) usually reduces or affects the performance of electronic devices or circuits within the wafer package. Generally, a ground plane or an additional electrical shielding plane is used to prevent electromagnetic interference during operation. However, the ground plane or the additional electrical shielding plane still faces many challenges during the manufacture of the wafer package. Summary of the Invention

[0004] According to some embodiments, an electrical shielding structure is provided, including: a substrate and a patterned metal plane. At least one signal / power pad is disposed on a surface of the substrate. The patterned metal plane is disposed on a surface of the substrate and surrounds and separates the signal / power pad. Furthermore, the patterned metal plane includes a plurality of slit openings exposing the surface of the substrate and extending in a first direction and arranged parallel to each other.

[0005] According to some embodiments, an electrical shielding structure is provided, including: a substrate and a patterned metal plane. At least one signal / power pad is disposed on a surface of the substrate. The patterned metal plane is disposed on a surface of the substrate and surrounds and separates the signal / power pad. Furthermore, the patterned metal plane includes a plurality of first slit openings and a plurality of second slit openings. The first slit openings expose the surface of the substrate and extend in a first direction and are arranged parallel to each other. Furthermore, the second slit openings expose the surface of the substrate and extend in a second direction different from the first direction and are arranged parallel to each other.

[0006] In some embodiments, a wafer package is provided, including: a substrate; an active region disposed on the substrate and including a channel region and a source / drain region; a gate structure disposed on the channel region of the active region and longitudinally extending along a first direction; a gate spacer disposed along a sidewall of the gate structure; and a source / drain feature disposed on the source / drain region of the active region. The channel region includes two sub-regions that are horizontally separated along the first direction by the gate structure.

[0007] According to some embodiments, a wafer package is provided, including: a device substrate, at least one signal / power pad, and a patterned metal plate. The device substrate has an active surface and a back surface. The device substrate includes a first opening and a second opening that extend from the back surface through the device substrate to the active surface. The signal / power pad is disposed on the back surface of the device substrate. The patterned metal plate is disposed on the back surface and surrounds and separates the signal / power pads. The patterned metal plate includes a plurality of slit openings exposing the surface of the substrate and extending parallel to each other along a first direction.

[0008] According to some embodiments, a wafer package is provided, including: a device substrate having an active surface and a back surface. The device substrate includes an opening that extends from the back surface through the device substrate to the active surface. The wafer package also includes an insulating layer disposed on the device substrate and having an upper surface defined by the active surface of the device substrate. The wafer package further includes a first metal layer and a second metal layer within the insulating layer. The first metal layer has a plurality of first vias arranged in a first array. The second metal layer is stacked on the first metal layer and has a plurality of second vias arranged in a second array. From a top view perspective, the second array is laterally offset relative to the first array such that the second vias do not overlap the first vias.

[0009] According to some embodiments, a wafer package is provided, including: a device substrate having an active surface and a back surface. The device substrate includes an opening that extends from the back surface through the device substrate to the active surface. The wafer package also includes an insulating layer disposed on the device substrate and having an upper surface defined by the active surface of the device substrate, a spacer layer disposed on the insulating layer, and a cover plate covering the spacer layer. A cavity is formed between the device substrate and the cover plate and surrounded by the spacer layer. The opening is located directly below the cavity such that from a top view perspective, the inner sidewall of the spacer layer is laterally separated from the opening. Description of the Drawings

[0010] Figure 1 A cross-sectional schematic diagram of an exemplary wafer package according to some embodiments is illustrated.

[0011] Figure 2Shows a schematic plan view of an exemplary electrical shielding structure according to some embodiments.

[0012] Figure 3 Shows a schematic plan view of an exemplary electrical shielding structure according to some embodiments.

[0013] Figure 4A Shows a schematic cross-sectional view of an exemplary wafer package according to some embodiments.

[0014] Figure 4B Shows a schematic cross-sectional view of an exemplary wafer package according to some embodiments.

[0015] Figure 5A Shows according to some embodiments Figure 4B Schematic plan view of an exemplary first metal layer of a multi-layer conductive pad structure in the wafer package shown.

[0016] Figure 5B Shows according to some embodiments Figure 4B Schematic plan view of an exemplary second metal layer of a multi-layer conductive pad structure in the wafer package shown.

[0017] Figure 5C-1 Shows according to some embodiments Figure 4B Schematic plan view of an exemplary third metal layer of a multi-layer conductive pad structure in the wafer package shown.

[0018] Figure 5C-2 Shows according to some embodiments Figure 4B Schematic plan view of an exemplary third metal layer of a multi-layer conductive pad structure in the wafer package shown.

[0019] Figure 6 Shows according to some embodiments Figure 4B Enlarged cross-sectional view of the area PS1 shown.

[0020] Figure 7 Shows according to some embodiments Figure 4B Enlarged cross-sectional view of the area PS1 shown.

[0021] Figure 8 Shows according to some embodiments Figure 4B Enlarged cross-sectional view of the area PS1 shown.

[0022] Figure 9 Shows according to some embodiments Figure 4B Enlarged cross-sectional view of the area PS1 shown.

[0023] Wherein, a brief description of the symbols in the drawings is as follows:

[0024] 10, 10a: Electrical shielding structure; 20, 20', 30: Wafer package; 100: Semiconductor substrate; 100a: Upper surface; 100b: Lower surface; 101: Insulating layer; 102: Signal / power pad; 104: Ground pad area; 105: First opening; 106: Insulating layer; 106a: Conductive pad; 107: Second opening; 108: Spacer layer; 110: Sensing area; 111: Optical component; 119: Cavity; 120: Patterned metal plate; 121: First slit opening; 121I: Inner edge; 121O: Outer edge; 122: Cover plate; 123: Second slit opening; 126: First redistribution layer; 128: Second redistribution layer; 130: Passivation layer; 132: Via hole; 140: First conductive connector; 142: Second conductive connector; 206a: Conductive layer stack; 208: First metal layer; 208a: First through hole; 210: Second metal layer; 210a: Second through hole; 212: Third metal layer; 212a: Third through hole; D1, D2: Minimum distance; E1, E2: End; PS1: Area; S1, S2: Pitch; V1, V2: Via; W1, W2: Width. Detailed implementation

[0025] The fabrication and usage methods of the embodiments of the present invention will be described in detail below. However, it should be noted that the present invention provides many applicable inventive concepts, which can be implemented in various specific forms. The specific embodiments discussed by way of example in the text are only specific ways of manufacturing and using the present invention, and are not intended to limit the scope of the present invention. In addition, repeated reference numerals or labels may be used in different embodiments. These repetitions are only for simply and clearly describing the present invention, and do not represent any association between the different embodiments and / or structures discussed. Furthermore, when it is mentioned that a first material layer is on or above a second material layer, it includes the case where the first material layer is in direct contact with the second material layer or is separated by one or more other material layers.

[0026] A wafer package according to an embodiment of the present invention can be used to package a microelectromechanical system wafer. However, its applications are not limited thereto. For example, in the embodiments of the wafer package of the present invention, it can be applied to various electronic components of integrated circuits including active or passive elements, digital or analog circuits, etc., such as optoelectronic devices, Micro Electro Mechanical System (MEMS), biometric devices, micro fluidic systems, or Physical Sensors that measure using changes in physical quantities such as heat, light, capacitance, and pressure. In particular, the wafer scale package (WSP) process can be selectively used to package semiconductor wafers such as image sensing devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, fingerprint recognition devices, microactuators, surface acoustic wave devices, pressure sensors, or ink printer heads.

[0027] The above-mentioned wafer-level packaging process mainly refers to completing the packaging steps at the wafer stage and then cutting them into independent packages. However, in a specific embodiment, for example, redistributing the separated semiconductor wafers on a carrier wafer and then performing the packaging process can also be called the wafer-level packaging process. In addition, the above-mentioned wafer-level packaging process is also applicable to forming a wafer package of multi-layer integrated circuit devices by arranging multiple wafers with integrated circuits in a stacked manner.

[0028] Please refer to Figure 1, which shows a cross-sectional schematic diagram of an exemplary wafer package 20 according to some embodiments. In some embodiments, the wafer package 20 is implemented as a front side illumination (FSI) sensing device and includes a semiconductor substrate 100. The semiconductor substrate 100 has an upper surface 100a (e.g., the active surface) and a lower surface 100b (e.g., the backside surface) opposite to the upper surface 100a. The semiconductor substrate 100 may be made of silicon or other semiconductors.

[0029] In some embodiments, a sensing region 110 is included within the semiconductor substrate 100. Furthermore, the sensing region 110 includes a sensing device (not shown), which is adjacent to the lower surface 100b of the semiconductor substrate 100. For example, the sensing region 110 may include an image sensing device or another suitable sensing device. In some other embodiments, the sensing region 110 includes a device for sensing biometrics (e.g., a fingerprint recognition device), a device for sensing environmental characteristics (e.g., a temperature sensing element, a humidity sensing element, a pressure sensing element, a capacitance sensing element) or another suitable sensing element. Therefore, the semiconductor substrate 100 is also referred to as a device substrate herein.

[0030] In some embodiments, an insulating layer 106 is disposed on a first side of the semiconductor substrate 100, and the surface of the insulating layer 106 constitutes the upper surface 100a (i.e., the active surface) of the semiconductor substrate 100. In some embodiments, the insulating layer 106 includes an interlayer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, a passivation layer or a combination thereof. In some embodiments, the insulating layer 106 includes inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide or a combination thereof or another suitable insulating material.

[0031] In some embodiments, one or more conductive pads 106a are provided within the insulating layer 106 and are adjacent to the upper surface 100a of the semiconductor substrate 100. In one embodiment, the conductive pad 106a may be a single-layer conductive layer or a multi-layer conductive layer structure. For simplicity of the drawings, only some single-layer conductive layers 106a are shown here as an example. In some embodiments, the insulating layer 106 includes openings exposing the corresponding conductive pads 106a. In one embodiment, the sensing device within the sensing region 110 may be electrically connected to the conductive pads 106a through an interconnect structure (not shown) within the semiconductor substrate 100 and the insulating layer 106.

[0032] In some embodiments, a plurality of openings extend from the lower surface 100b of the semiconductor substrate 100 through the semiconductor substrate 100 toward the upper surface 100a of the substrate 100. Furthermore, these openings expose corresponding conductive pads 106a within the insulating layer 106. For the sake of simplicity in the drawings, only a first opening 105 and a second opening 107 are shown herein. Furthermore, the first opening 105 and the second opening 107 have inclined sidewalls. For example, the first opening 105 and the second opening 107 have a first diameter (i.e., bottom width) at the lower surface 100b of the semiconductor substrate 100 that is greater than their second diameter (i.e., top width) at the upper surface 100a of the semiconductor substrate 100.

[0033] In some embodiments, the wafer package 20 further includes an insulating liner 101 that covers a second side (opposite the first side) of the semiconductor substrate 100, and the surface of the insulating liner 101 constitutes the lower surface 100b (i.e., the backside surface) of the semiconductor substrate 100. Furthermore, the insulating liner 101 extends conformally over the sidewalls and bottoms of the first opening 105 and the second opening 107. The insulating liner 101 within the first opening 105 and the second opening 107 has an opening to expose the corresponding conductive pad 106a. In some embodiments, the insulating liner 101 may include epoxy resin, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxides, or combinations thereof), organic polymer materials (e.g., polyimide resin, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, or acrylates), or other suitable insulating materials.

[0034] In some embodiments, the wafer package 20 further includes a patterned metal layer disposed on the insulating liner 101 above the lower surface 100b of the semiconductor substrate 100, such that the insulating liner 101 is located between the patterned metal layer and the semiconductor substrate 100. In some embodiments, the patterned metal layer includes a plurality of signal / power pads 102 and a patterned metal plate 120 (or referred to as a ground plane) located above the lower surface 100b of the semiconductor substrate 100. The patterned metal plate 120 surrounds and is spaced apart from the signal / power pads 102 without contact. The signal / power pads 102 and the patterned metal plate 120 are electrically isolated from the surface of the semiconductor substrate 100 via the insulating liner 101. In some embodiments, the patterned metal plate 120 (i.e., the ground plane) can act as an electrical shielding plate to prevent electromagnetic interference (EMI) during the operation of the wafer package 20.

[0035] In some embodiments, the patterned metal layer further includes a plurality of redistribution layers. The redistribution layers are electrically connected to the patterned metal plate 120 and the signal / power pads 102 respectively. Furthermore, the redistribution layers are correspondingly disposed within the openings (e.g., the first opening 105 and the second opening 107) of the semiconductor substrate 100. For example, a first redistribution layer 126 is correspondingly disposed within the first opening 105 and extends to one or more corresponding signal / power pads 102 and is electrically connected thereto. Similarly, a second redistribution layer 128 is correspondingly disposed within the second opening 107 and extends to the ground pad region 104 of the patterned metal plate 120 and is electrically connected thereto.

[0036] In some embodiments, the first redistribution layer 126 and the second redistribution layer 128 extend onto an insulating liner 101 above the lower surface 100b of the semiconductor substrate 100, such that the insulating liner 101 is located between the first redistribution layer 126 and the second redistribution layer 128 and the semiconductor substrate 100. Furthermore, the first redistribution layer 126 and the second redistribution layer 128 conformally extend onto the sidewalls and the bottom of the corresponding openings (e.g., the first opening 105 and the second opening 107) and are directly or indirectly electrically connected to the exposed corresponding conductive pads 106a. Accordingly, the first redistribution layer 126 and the second redistribution layer 128 within the first opening 105 and the second opening 107 are also referred to as through substrate vias (TSVs). In some embodiments, the first redistribution layer 126 and the second redistribution layer 128 may each include aluminum, titanium, tungsten, copper, or a combination thereof.

[0037] In some embodiments, the wafer package 20 further includes a passivation layer 130, which is disposed above the lower surface 100b of the device substrate 100 and partially fills the first opening 105 and the second opening 107 to cover the first redistribution layer 126 and the second redistribution layer 128. In some embodiments, the passivation layer 130 has an uneven surface. For example, the surface of the passivation layer 130 has recesses corresponding to the first opening 105 and the second opening 107. In one embodiment, the passivation layer 130 may include epoxy resin, solder mask, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination of the foregoing), organic polymer materials (e.g., polyimide resin, benzocyclobutene (BCB), parylene, naphthalene polymer, fluorocarbon, or acrylate), or other suitable insulating materials.

[0038] Since the passivation layer 130 does not fill the second opening 107, a void 132 is formed between the first wiring layer 126 in the first opening 105 and the passivation layer 130, and another void 132 is formed between the second wiring layer 128 in the second opening 107 and the passivation layer 130. Therefore, during the heat treatment in the subsequent process, the void 132 can serve as a buffer between the passivation layer 130 and the first wiring layer 126 and the second wiring layer 128 to reduce unnecessary stress caused by the mismatch of the coefficient of thermal expansion between the passivation layer 130 and the first wiring layer 126 and the second wiring layer 128. In one embodiment, the interface between the void 132 and the passivation layer 130 has an arched profile.

[0039] The passivation layer 130 located on the lower surface 100b of the device substrate 100 has openings to expose the signal / power pads 102 and the ground pad region 104. Furthermore, conductive connectors (e.g., solder balls, bumps, or conductive pillars) are electrically connected to the exposed signal / power pads 102 and the ground pad region 104 through the openings of the passivation layer 130. For example, a first conductive connector 140 (also referred to as a signal / power connector) is disposed on the surface of a corresponding signal / power pad 102 and electrically connected thereto, and a second conductive connector 142 (also referred to as a ground connector) is disposed on the surface of the patterned metal plate 120 and electrically connected thereto. In some embodiments, the first conductive connector 140 and the second conductive connector 142 may include tin, lead, copper, gold, nickel, or a combination of the foregoing.

[0040] In some embodiments, the wafer package 20 further includes an optical component 111, which is disposed on the insulating layer 106 and corresponds to the sensing region 110. In one embodiment, the optical component 111 includes a microlens array, a filter layer, a combination thereof, or other suitable optical components.

[0041] In some embodiments, the wafer package 20 further includes a cover plate 122, which is disposed above the upper surface 100a of the device substrate 100 to protect the optical component 111. The cover plate 122 may include glass, quartz, a transparent polymer material, or other suitable transparent materials. Furthermore, a spacer layer (or called a dam) 108 is disposed between the device substrate 100 and the cover plate 122. The spacer layer 108 covers the conductive pads 106a and exposes the optical component 111. In some embodiments, the cover plate 122, the spacer layer 108, and the insulating layer 106 jointly surround a cavity 119 on the sensing region 110, such that the optical component 111 is located within the cavity 119. In other embodiments, the spacer layer 108 covers the optical component 111, such that there is no cavity between the cover plate 122 and the insulating layer 106.

[0042] In some embodiments, the spacer layer 108 may include epoxy resin, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination of the foregoing), organic polymer materials (e.g., polyimide resin, benzocyclobutene (BCB), parylene, naphthalene polymer, fluorocarbon, or acrylate), photoresist materials, or other suitable insulating materials.

[0043] Please refer to Figure 2 , which shows a plan view of the electrical shielding structure 10 according to some embodiments. In some embodiments, the electrical shielding structure 10 can be used in Figure 1 the wafer package 20. In this case, the electrical shielding structure 10 includes a device substrate 100 and a patterned metal plate 120. One or more signal / power pads 102 and the patterned metal plate 120 are disposed on a surface (e.g., the lower surface 100b (i.e., the backside surface)) of the device substrate 100.

[0044] In some embodiments, each signal / power pad 102 is connected to a redistribution layer (e.g., the first redistribution layer 126). Furthermore, the patterned metal plate 120 surrounds and separates the signal / power pads 102 and the first redistribution layer 126 connected thereto. That is, there is no physical contact between the inner edge 121I (or the inner sidewall) of the patterned metal plate 120 and the signal / power pads 102 and the first redistribution layer 126 connected thereto.

[0045] In some embodiments, the patterned metal plate 120 includes a plurality of first slit openings 121 that extend in a first direction (e.g., the Y direction) and are arranged parallel to each other. Each first slit opening 121 exposes the lower surface 100b of the device substrate 100. However, in other embodiments, the first slit openings 121 extend in a second direction (e.g., the X direction) different from the first direction and are arranged parallel to each other. For example, these first slit openings 121 can be elongated rectangles arranged parallel to each other in a top view angle and can be dispersed throughout the patterned metal plate 120. Furthermore, the width W1 of each of these first slit openings 121 is in the range of 20 to 40 micrometers (e.g., 30 micrometers). In addition, at least two of these first slit openings 121 have the same or different lengths.

[0046] In some embodiments, each first slit opening 121 is located between the outer edge 121O and the inner edge 121I of the patterned metal plate 120 and does not extend to the outer edge 121O and / or the inner edge 121I. For example, at least one of these first slit openings 121 has an end portion E1 adjacent to the inner edge 121I of the patterned metal plate 120, and the minimum distance D1 between the end portion E1 and the inner edge 121I is in the range of 20 to 40 micrometers (e.g., 30 micrometers). Furthermore, at least one of these first slit openings 121 has an end portion E2 adjacent to the outer edge 121O of the patterned metal plate 120, and the minimum distance D2 between the end portion E2 and the outer edge 121O is in the range of 20 to 40 micrometers (e.g., 30 micrometers). In some embodiments, the spacing S1 between two adjacent slit openings among these first slit openings 121 is in the range of 80 to 120 micrometers (e.g., 100 micrometers).

[0047] Please refer to Figure 3 , which shows a schematic plan view of the electrical shielding structure 10a according to some embodiments, where components identical to Figure 2 are denoted by the same reference numerals and their descriptions are omitted. The structure of the electrical shielding structure 10a is similar to Figure 2 the electrical shielding structure 10. However, different from the electrical shielding structure 10, in addition to the first slit openings 121 extending in a first direction (e.g., the Y direction) and arranged parallel to each other within the patterned metal plate 120 of the electrical shielding structure 10a, there are also second slit openings 123 extending in a second direction (e.g., the X direction) and arranged parallel to each other.

[0048] Similar to the first slit openings 121, these second slit openings 123 can be elongated rectangles arranged parallel to each other in a top view and can be dispersedly formed throughout the patterned metal plate 120. In some embodiments, at least one second slit opening 123 extends to a first slit opening 121 to form a T-shaped or L-shaped slit opening in a top view. Furthermore, at least one second slit opening 123 extends between two adjacent first slit openings 121 and contacts them, forming an H-shaped or I-shaped slit opening in a top view.

[0049] Similar to the first slit openings 121, the width W2 of each of these second slit openings 123 is in the range of 20 to 40 micrometers (e.g., 30 micrometers). Additionally, at least two of these second slit openings 123 have the same or different lengths. Furthermore, in some embodiments, the spacing S1 between two adjacent first slit openings 121 is in the range of 80 to 120 micrometers (e.g., 100 micrometers), and the spacing S2 between two adjacent second slit openings 123 is in the range of 80 to 120 micrometers (e.g., 100 micrometers).

[0050] Different from the electrical shielding structure 10, in the electrical shielding structure 10a, at least one first slit opening 121 and at least one second slit opening 123 extend to the outer edge 121O and / or the inner edge 121I.

[0051] Please refer to Figure 4A , which shows a cross-sectional schematic diagram of an exemplary wafer package 20' according to some embodiments, where components identical to Figure 1 are denoted by the same reference numerals and their descriptions are omitted. The structure of the wafer package 20' is similar to that of the wafer package 20 shown in Figure 1 . However, different from the wafer package 20, the first opening 105 and the second opening 107 formed in the semiconductor substrate 100 and the conductive pads 106a disposed in the insulating layer 106 are not located directly below the spacer layer 108. From a top view perspective, the first opening 105 and the second opening 107 and the corresponding conductive pads 106a are located directly below the cavity 119, such that the inner sidewalls of the spacer layer 108 are laterally spaced apart from the first opening 105 and the second opening 107, as shown in Figure 4A . In this case, the insulating layer 106 has a sufficient thickness to serve as a support layer during the formation of the first opening 105 and the second opening 107, thereby preventing damage or cracking of the insulating layer 106 and the conductive pads 106a. For example, the insulating layer 106 has a thickness of about 9 μm or more.

[0052] Since the first opening 105 and the second opening 107 are not formed directly below the spacer layer 108, the width of the spacer layer 108 is not limited by the positions of the first opening 105 and the second opening 107. In addition, since the first opening 105 and the second opening 107 are formed directly below the cavity 119, the design flexibility of the positions of the substrate vias (which are formed in the first opening 105 and the second opening 107) can be increased.

[0053] Please refer to Figure 4B , which shows a cross-sectional schematic diagram of an exemplary wafer package 30 according to some embodiments, where components identical to Figure 4A are denoted by the same reference numerals and their descriptions are omitted. The structure of the wafer package 30 is similar to that of Figure 4AThe wafer package 30 shown is similar to the wafer package 20'. However, different from the wafer package 20' having solid conductive pads 106a (e.g., solid metal layers), the wafer package 30 includes a conductive pad structure. Each conductive pad structure is a multi-layer pad structure, which includes a stack 206a of an insulating layer 106 and a conductive layer (e.g., metal layer) having vias formed therein. Therefore, the conductive pad structure can also be referred to as a mesh pad structure. The mesh pad structure helps to release the stress propagated from the conductive layer stack 206a to the insulating layer 106, thereby preventing delamination of the conductive layer stack 206a.

[0054] In some embodiments, the stack 206a of conductive layers includes two or more stacked conductive layers. For example, the stack 206a of conductive layers may include a first metal layer 208, a second metal layer 210 disposed above the first metal layer 208, and a third metal layer 212 disposed above the second metal layer 210. Furthermore, the vias in each conductive layer are arranged in an array.

[0055] Figure 5A Illustrates according to some embodiments Figure 4B A plan view of the first metal layer 208 in the wafer package 30 shown. Figure 5B Illustrates according to some embodiments Figure 4B A plan view of the second metal layer 210 in the wafer package 30 shown. Figure 5C-1 A plan view of the third metal layer 212 in the wafer package 30 is shown. Figure 5C-2 A plan view of the third metal layer 212 in the wafer package 30 is shown. In some embodiments, the first metal layer 208 has first vias 208a arranged in a first array. Similarly, the second metal layer 210 has second vias 210a arranged in a second array, and the third metal layer 212 has third vias 212a arranged in a third array.

[0056] In some embodiments, when viewed from a top-down perspective, the second array is laterally offset relative to the first array, as shown in Figure 5A and Figure 5B shown. In this way, when viewed from a top-down perspective, the second vias 210a do not overlap with any of the first vias 208a. In some embodiments, different from the second array, when viewed from a top-down perspective, the third array is longitudinally offset relative to the first array, as shown in Figure 5C-1 shown. In this way, when viewed from a top-down perspective, the third vias 212a do not overlap with the first vias 208a and the second vias 210a.

[0057] In some other embodiments, the via pattern in the third metal layer 212 is the same as the via pattern in the second metal layer 210, as shown in Figure 5C-2As shown. In other words, from a top-down perspective, the third array overlaps with the second array. In this way, from a top-down perspective, the third through-hole 212a overlaps with the second through-hole 210a, but does not overlap with the first through-hole 208a.

[0058] From a top-down perspective, the first through-hole 208a, the second through-hole 210a, and the third through-hole 212a have a square shape, as Figure 5A , Figure 5B , Figure 5C-1 and Figure 5C-2 shown. However, according to design requirements, the first through-hole 208a and the second through-hole 210a can have other shapes. For example, these through-holes can have a circular, triangular, rectangular, or polygonal shape. In addition, it can be understood that the number of the first through-hole 208a, the second through-hole 210a, and the third through-hole 212a can be changed and is not limited to Figure 5A , Figure 5B , Figure 5C-1 and Figure 5C-2 the embodiments shown.

[0059] Figure 6 Illustrates an enlarged cross-sectional schematic view of the Figure 4B shown area PS1 according to some embodiments, Figure 6 also illustrates a cross-sectional schematic view of the stacked structure of the first metal layer 208, the second metal layer 210, and the third metal layer 212 according to some embodiments along the Figure 5A , Figure 5B and Figure 5C-1 I-I' line in. The area PS1 shows a conductive pad structure, which includes an insulating layer 106 and a conductive layer stack 206a located within the insulating layer 106, and the second redistribution layer 104 is electrically connected to the conductive layer stack 206a. Each conductive layer in the conductive layer stack 206a formed within the insulating layer 106 corresponds to an opening (e.g., the first opening 105 or the second opening 107) within the device substrate 100. Furthermore, a redistribution layer (the first redistribution layer 126 or the second redistribution layer 128) is electrically connected to the corresponding conductive layer stack 206a via a corresponding opening within the device substrate 100.

[0060] For example, in the area PSl, the stack 206a of conductive layers corresponds to the second opening 107 (as Figure 4B shown), and includes the first metal layer 208, the second metal layer 210, and the third metal layer 212 (as Figure 5A , Figure 5B and Figure 5C-1are stacked in sequence from bottom to top. Furthermore, the first metal layer 208 is electrically connected to the second metal layer 210 through a via hole Vl formed in the insulating layer 106 located between the first metal layer 208 and the second metal layer 210. Similarly, the second metal layer 210 is electrically connected to the third metal layer 212 through a via hole V2 formed in the insulating layer 106 located between the second metal layer 210 and the third metal layer 212.

[0061] The first metal layer 208 having the first through hole 208a is exposed in the second opening 107 (not shown in Figure 6 ). Furthermore, the second rewiring layer 128 is disposed in the second opening 107 and extends into the insulating layer 106 to directly contact the first metal layer 208 and a portion of the insulating layer 106 filled in the first through hole 208a.

[0062] Similarly, another conductive layer stack 206a corresponds to the first opening 105 (as Figure 4B shown), wherein the first metal layer 208 having the first through hole 208a is exposed in the first opening 105 and extends into the insulating layer 106 to directly contact the corresponding first metal layer 208 and a portion of the insulating layer 106 filled in the corresponding first through hole 208a.

[0063] Figure 7 shows an enlarged cross-sectional schematic view of the region PS1 according to some embodiments Figure 4B shown. Figure 7 Also shown is the stacked structure of the first metal layer 208, the second metal layer 210, and the third metal layer 212 according to some embodiments along Figure 5A , Figure 5B and Figure 5C-1 the cross-sectional schematic view of the line I-I' in. The region PS1 shows a conductive pad structure, the conductive pad structure includes the insulating layer 106 and the conductive layer stack 206a located in the insulating layer 106, and the second rewiring layer 128 is electrically connected to the conductive layer stack 206a. Figure 7 The structure of the region PS1 shown is similar to the structure of the region PS1 shown in Figure 6 . Different from the structure in the region PS1 shown in Figure 6 , the second rewiring layer 128 extends into the insulating layer 106 so as to directly contact the first metal layer 208 and fills the first through hole 208a to directly contact the second metal layer 210. In this case, after the second opening 107 is formed, the insulating layer 106 covering the first metal layer 208 and filled in the first through hole 208a can be completely removed by one or more etching processes. In this way, the process tolerance for forming the second opening 107 can be increased, thereby ensuring that the subsequently formed first rewiring layer 102 directly contacts the first metal layer 208.

[0064] Similarly, another conductive layer stack 206a corresponds to the first opening 105 (as Figure 4B shown), in which a first metal layer 208 having a first through-hole 208a is exposed in the first opening 105. The first rewiring layer 126 is disposed in the first opening 105 and extends into the insulating layer 106 to directly contact the corresponding first metal layer 208, and fills the corresponding first through-hole 208a to directly contact the corresponding second metal layer 210.

[0065] Figure 8 Illustrates an enlarged cross-sectional schematic view of the Figure 4B shown area PS1 according to some embodiments, Figure 8 also illustrates a stacked structure of the first metal layer 208, the second metal layer 210, and the third metal layer 212 according to some embodiments along Figure 5A , Figure 5B and Figure 5C-2 the cross-sectional schematic view taken along the line I-I' in. The area PS1 shows a conductive pad structure, which includes an insulating layer 106 and a conductive layer stack 206a located in the insulating layer 106, and the second rewiring layer 128 is electrically connected to the conductive layer stack 206a. Figure 8 The structure of the shown area PS1 is similar to that of Figure 6 shown. Different from Figure 6 the shown area PS1, the through-hole pattern in the third metal layer 212 is the same as the through-hole pattern in the second metal layer 210. In this way, from a top view perspective, the third array overlaps with the second array, such that the third through-hole 212a overlaps with the second through-hole 210a, but does not overlap with the first through-hole 208a.

[0066] Figure 9 Illustrates an enlarged cross-sectional schematic view of the Figure 4B shown area PS1 according to some embodiments, Figure 9 also illustrates a stacked structure of the first metal layer 208, the second metal layer 210, and the third metal layer 212 according to some embodiments along Figure 5A , Figure 5B and Figure 5C-2 the cross-sectional schematic view taken along the line I-I' in. The area PS1 shows a conductive pad structure, which includes an insulating layer 106 and a conductive layer stack 206a located in the insulating layer 106, and the second rewiring layer 128 is electrically connected to the conductive layer stack 206a. Figure 9 The structure of the shown area PS1 is similar to that of Figure 7 shown. Different from Figure 7In the shown area PS1, the via hole pattern in the third metal layer 212 is the same as the via hole pattern in the second metal layer 210. In this way, from a top view perspective, the third array overlaps with the second array, such that the third via hole 212a overlaps with the second via hole 210a, but does not overlap with the first via hole 208a.

[0067] According to the above embodiments, the large-area patterned metal plate in the electrical shielding structure has slit openings formed therein in a dispersed manner and arranged in parallel along a single direction, or has slit openings arranged in parallel along a first direction and slit openings arranged in parallel along a second direction. Through the above slit openings, the stress between the large-area patterned metal plate and the device substrate can be reduced, thereby avoiding the peeling of the patterned metal plate from the lower surface of the device substrate. In this way, the reliability of the electrical shielding structure in the wafer package can be increased, and thus the electromagnetic interference during the operation of the wafer package can be effectively prevented. According to the above embodiments, corresponding to the opening for forming the through-substrate via (TSV) electrode, and having a single-layer conductive pad or a conductive pad structure including multiple layers of conductive pads, is disposed directly below the cavity (defined by the cover plate and the spacer layer formed on the device substrate). In this way, the width of the spacer layer can be changed or reduced according to design requirements. Furthermore, the design flexibility of the position of the through-substrate via (TSV) electrode can also be increased. According to the above embodiments, the wafer package includes a multi-layer pad structure having through holes. In this way, the mesh pad structure helps to release the stress propagated from the multi-layer pad structure to the adjacent insulating layer, thereby preventing the peeling of the multi-layer pad structure. Furthermore, the conductive pad structure having through holes can assist in completely removing the insulating layer covering the first metal layer and filling the through holes in the first metal layer. In this way, the subsequently formed redistribution layer can be in direct contact with the first and second metal layers, thereby increasing the contact area between the redistribution layer and the conductive pad structure. In addition, the process tolerance for forming the opening exposing the conductive pad structure can also be increased.

[0068] The above description is only for the preferred embodiments of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements and changes on the basis of not departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims of this application.

Claims

1. A chip package, comprising: A device substrate having an active surface and a backside surface, wherein the device substrate comprises a first opening and a second opening extending from the backside surface through the device substrate to the active surface; At least one signal / power pad is disposed on the back surface; as well as The patterned metal plate is disposed on the back surface and surrounds and separates the signal / power pad, wherein the patterned metal plate includes a plurality of first slit openings, exposing the back surface and extending along a first direction and arranged parallel to each other.

2. The chip package according to claim 1, further comprising: At least one grounding connector is disposed on the surface of the patterned metal plate and is electrically connected thereto.

3. The chip package according to claim 1, wherein: The patterned metal plate also includes: A plurality of second slit openings expose the back surface and extend along a second direction different from the first direction and are arranged parallel to each other.

4. The chip package according to claim 3, wherein: At least one of the plurality of second slit openings extends to one of the plurality of first slit openings to form a T-shaped or L-shaped slit opening in a top view.

5. The chip package according to claim 3, wherein: At least one of the plurality of second slit openings is located between two adjacent first slit openings of the plurality of first slit openings and extends to the two adjacent first slit openings, thereby forming an H-shaped or I-shaped slit opening in a top view.

6. The chip package according to claim 1, further comprising: a spacer layer disposed above the active surface of the device substrate; A cover plate, covering the spacer layer to form a cavity between the device substrate and the cover plate, wherein the cavity is surrounded by the spacer layer; as well as The first redistribution layer and the second redistribution layer are respectively disposed in the first opening and the second opening, wherein the first redistribution layer extends from the first opening to the signal / power pad, and the second redistribution layer extends from the second opening to the patterned metal plate.

7. The chip package according to claim 6, wherein: The first opening and the second opening are located directly below the cavity, so that from a top view, the inner sidewall of the spacing layer is laterally spaced from the first opening and the second opening.

8. The chip package according to claim 1, further comprising: The first conductive pad structure and the second conductive pad structure are adjacent to the active surface of the device substrate and correspond to the first opening and the second opening respectively, wherein the first conductive pad structure and the second conductive pad structure each include: an insulating layer having an upper surface defined by the active surface of the device substrate; A first metal layer is located in the insulating layer and has a plurality of first through holes arranged in a first array; and The second metal layer is located in the insulating layer, stacked above the first metal layer, and has a plurality of second through holes arranged in a second array, wherein from a top view, the second array is laterally offset relative to the first array so that the plurality of second through holes do not overlap with the plurality of first through holes.

9. The chip package according to claim 8, further comprising: The first redistribution layer and the second redistribution layer are respectively disposed in the first opening and the second opening and extend into the insulating layer to directly contact the first metal layer and the insulating layer portion located in the plurality of first through holes.

10. The chip package according to claim 8, further comprising: The first redistribution layer and the second redistribution layer are respectively disposed in the first opening and the second opening and extend into the insulating layer to directly contact the first metal layer and fill in the plurality of first through holes to directly contact the second metal layer.

11. A chip package, comprising: A device substrate having an active surface and a backside surface, wherein the device substrate includes an opening extending from the backside surface through the device substrate to the active surface; an insulating layer disposed on the device substrate and having an upper surface defined by the active surface of the device substrate; A first metal layer is located in the insulating layer and has a plurality of first through holes arranged in a first array; as well as The second metal layer is located in the insulating layer, stacked on the first metal layer, and has a plurality of second through holes arranged in a second array, wherein from a top view, the second array is laterally offset relative to the first array so that the plurality of second through holes do not overlap with the plurality of first through holes.

12. The chip package according to claim 11, further comprising: The redistribution layer is disposed in the opening and extends into the insulating layer to directly contact the first metal layer and the insulating layer portion located in the plurality of first through holes.

13. The chip package according to claim 11, further comprising: The redistribution layer is disposed in the opening and extends into the insulating layer to directly contact the first metal layer, and is filled into the plurality of first through holes to directly contact the second metal layer.

14. The chip package according to claim 11, further comprising: The third metal layer is located in the insulating layer, stacked on the second metal layer, and has a plurality of third through holes arranged in a third array.

15. The chip package according to claim 14, wherein: From a top view, the third array overlaps with the second array, so that the plurality of third through holes overlap with the plurality of second through holes.

16. The chip package according to claim 14, wherein: From a top view, the third array is longitudinally offset relative to the first array, so that the plurality of third through holes do not overlap with the plurality of first through holes.

17. The chip package according to claim 11, further comprising: A spacer layer is disposed above the insulating layer; as well as A cover plate, covering the spacer layer to form a cavity between the device substrate and the cover plate, wherein the cavity is surrounded by the spacer layer; The opening is located directly below the cavity, so that from a top view, the inner side wall of the spacing layer is laterally spaced from the opening.

18. A chip package, comprising: A device substrate having an active surface and a backside surface, wherein the device substrate includes an opening extending from the backside surface through the device substrate to the active surface; an insulating layer disposed on the device substrate and having an upper surface defined by the active surface of the device substrate; A spacer layer is disposed above the insulating layer; as well as A cover plate, covering the spacer layer to form a cavity between the device substrate and the cover plate, and the cavity is surrounded by the spacer layer; The opening is located directly below the cavity, so that from a top view, the inner side wall of the spacing layer is laterally spaced from the opening.

19. The chip package according to claim 18, further comprising: A metal pad is located in the insulating layer and has a plurality of first through holes arranged in a first array, wherein the opening extends into the insulating layer to expose the metal pad; as well as The redistribution layer is disposed in the opening and extends into the insulating layer to directly contact the metal pad.

20. The chip package according to claim 19, further comprising: A metal layer, located in the insulating layer above the metal pad, and having a plurality of second through holes arranged in a second array; Wherein, from a top view, the second array is offset relative to the first array, so that the plurality of second through holes do not overlap with the plurality of first through holes; as well as The redistribution layer extends into the plurality of first through holes to directly contact the metal layer.

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