Semiconductor device

Abstract

The purpose of the present disclosure is to suppress an increase in chip size and an increase in process cost in a semiconductor device having an insulated signal transmission element. A semiconductor device (1010) is divided, in plan view, into a low potential region (1) having a ground potential as a reference potential, a high potential region (2) having a floating potential as a reference potential, and a high withstand voltage separation region (3) that is provided between the low potential region and the high potential region and separates the low potential region and the high potential region. A semiconductor device is provided with a signal transmission element provided on an element structure (21) in a high withstand voltage separation region. The signal transmission element is provided with: a primary coil (18) provided on the low potential region side of the high withstand voltage separation region and connected to the low potential region; and a secondary coil (19) provided on the high potential region side of the high withstand voltage separation region and connected to the high potential region. The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the P-type substrate (4).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses a structure in a HVIC (High Voltage IC) structure that, instead of transistors driven by a high voltage, realizes a signal transmission function accompanied by insulation and level conversion through a magnetic coupling element.

[0003] Patent Document 1: Japanese Patent No. 6843799 Gazette

[0004] In the prior art, an insulating signal transmission element (a magnetic coupling element in Patent Document 1) is integrated on one chip of a HVIC. However, since the size of the signal transmission element is large and becomes an ineffective area, there is a problem that the chip size increases. In addition, in order to achieve high withstand voltage, it is necessary to thicken the interlayer film between wirings, and there is a problem of an increase in process cost. Summary of the Invention

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to suppress an increase in chip size and an increase in process cost in a semiconductor device having an insulating signal transmission element.

[0006] The semiconductor device of the present disclosure is a semiconductor device including a semiconductor substrate and an element structure formed on the semiconductor substrate. In the semiconductor device, when viewed from above, it is divided into: a low potential region having a ground potential as a reference potential, a high potential region having a floating potential as a reference potential, and a high withstand voltage separation region provided between the low potential region and the high potential region and separating the two. The semiconductor device includes a signal transmission element provided on the element structure in the high withstand voltage separation region. The signal transmission element includes: a primary side element provided on the low potential region side of the high withstand voltage separation region and connected to the low potential region; and a secondary side element provided on the high potential region side of the high withstand voltage separation region and connected to the high potential region. The primary side element and the secondary side element are magnetically coupled or capacitively coupled to each other through a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate.

[0007] Since the semiconductor device of the present disclosure has a signal transmission element in the ineffective area, that is, the high withstand voltage separation region, there is no further increase in the ineffective area due to the provision of the signal transmission element, and an increase in chip size can be suppressed. In addition, since the longitudinal potential difference between the signal transmission element and the element structure is small, it is possible to thin the interlayer film thickness between wirings, thereby reducing the process cost. Brief Description of the Drawings

[0008] Figure 1 It is a top view of the semiconductor device according to Embodiment 1.

[0009] Figure 2 is a cross-sectional view of a semiconductor device according to Embodiment 1 taken along the A-A' line Figure 1 shown in the figure.

[0010] Figure 3 is a top view of a semiconductor device according to the first modification of Embodiment 1.

[0011] Figure 4 is a cross-sectional view of a semiconductor device according to the first modification of Embodiment 1 taken along the A-A' line Figure 3 shown in the figure.

[0012] Figure 5 is a top view of a semiconductor device according to the second modification of Embodiment 1.

[0013] Figure 6 is a cross-sectional view of a semiconductor device taken along the A-A' line Figure 5 shown in the figure.

[0014] Figure 7 is a top view of a semiconductor device according to the third modification of Embodiment 1.

[0015] Figure 8 is a cross-sectional view of a semiconductor device taken along the A-A' line Figure 7 shown in the figure.

[0016] Figure 9 is a top view of a semiconductor device according to the fourth modification of Embodiment 1.

[0017] Figure 10 is a cross-sectional view of a semiconductor device taken along the A-A' line Figure 9 shown in the figure.

[0018] Figure 11 is a top view of a semiconductor device according to the fifth modification of Embodiment 1.

[0019] Figure 12 is a cross-sectional view of a semiconductor device taken along the A-A' line Figure 11 shown in the figure.

[0020] Figure 13 is a top view of a semiconductor device according to Embodiment 2.

[0021] Figure 14 is a top view of a semiconductor device according to the first modification of Embodiment 2.

[0022] Figure 15 is a top view of a semiconductor device according to Embodiment 3.

[0023] Figure 16 is a cross-sectional view of a semiconductor device taken along the A-A' line of Figure 15 .

[0024] Figure 17 is a top view of the semiconductor device according to Embodiment 4.

[0025] Figure 18 is a top view of the semiconductor device according to the first modification of Embodiment 4.

[0026] Figure 19 is a top view of the semiconductor device according to Embodiment 5.

[0027] Figure 20 is a top view of the semiconductor device according to Embodiment 6.

[0028] Description of Reference Numerals

[0029] 1... low potential region; 2... high potential region; 3... high breakdown voltage isolation region; 4... P-type substrate; 5... N+-type buried layer; 6... P-type well layer; 7... N-type well layer; 8... P-type anti-inversion layer; 9... N-type anti-inversion layer; 10... LOCOS oxide film for element isolation; 11... doped polysilicon electrode; 12... high-resistance polysilicon field plate; 13... P-type body region; 14... P-type contact region; 15... N-type contact region; 16, 17... aluminum wiring field plate; 18... primary coil; 19... secondary coil; 20... coil core; 21... element structure; 22... metal structure; 25... capacitive coupling type field plate; 26... trench; 27... buried oxide film layer; 31... primary flat electrode; 32... secondary flat electrode; 181, 182, 183, 184, 191, 192, 193, 194... metal wiring; 251... lower field plate; 252... upper field plate; 311... first surface; 321... second surface; 1010, 1011, 1012, 1013, 1014, 1015, 1020, 1021, 1030, 1040, 1041, 1050, 1060... semiconductor devices. Detailed Description of the Embodiments

[0030] In the following description, N-type and P-type indicate the conductivity type of the semiconductor. N+-type indicates that the N-type impurity concentration is higher than that of the N-type.

[0031] <A. Embodiment 1>

[0032] <A-1. Structure>

[0033] Figure 1 is a top view of the semiconductor device 1010 according to Embodiment 1. Figure 2 is along Figure 1Cross-sectional view of the semiconductor device 1010 taken along the line A-A'. Hereinafter, the structure of the semiconductor device 1010 will be described with reference to these figures.

[0034] The semiconductor device 1010 is an HVIC (High Voltage Integrated Circuit) chip that drives and controls power devices. Here, the power device is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (metal-oxide-semiconductor field-effect transistor), etc.

[0035] As Figure 1 shown, when viewed from above, the semiconductor device 1010 is divided into three regions: a low-potential region 1, a high-potential region 2, and a high-voltage withstand isolation region 3. The high-voltage withstand isolation region 3 is provided between the low-potential region 1 and the high-potential region 2, and electrically isolates the low-potential region 1 from the high-potential region 2. In Figure 1 the example, the high-voltage withstand isolation region 3 is formed to surround the high-potential region 2.

[0036] The low-potential region 1 has a ground potential (GND) as the reference potential. The high-potential region 2 has a floating voltage electrically isolated from the GND as the reference voltage.

[0037] As Figure 2 shown, the semiconductor device 1010 includes a P-type substrate 4 as a semiconductor substrate, an element structure 21 formed on the P-type substrate 4, and a metal structure 22 formed on the element structure 21 and composed of three-layer metal wirings.

[0038] The element structure 21 includes an N+-type buried layer 5, a P-type well layer 6, an N-type well layer 7, a P-type anti-inversion layer 8, an N-type anti-inversion layer 9, an element isolation LOCOS oxide film 10, a doped polysilicon electrode 11, a high-resistance polysilicon field plate 12, a P-type body region 13, a P-type contact region 14, and an N-type contact region 15.

[0039] The N+-type buried layer 5 is provided on the P-type substrate 4 in the high-potential region 2 by ion implantation.

[0040] The P-type well layer 6 and the N-type well layer 7 are formed by epitaxial growth on the P-type substrate 4 and the N+-type buried layer 5, followed by ion implantation. The P-type well layer 6 is formed on the P-type substrate 4 in the low-potential region 1. The N-type well layer 7 is formed on the P-type substrate 4 in the high-voltage isolation region 3 and on the N+-type buried layer 5 in the high-potential region 2. The N-type well layer 7 is a RESURF layer. That is, the high-voltage isolation region 3 has a RESURF isolation structure. In addition, either the P-type well layer 6 or the N-type well layer 7 can also be directly an epitaxial growth layer.

[0041] The P-type anti-inversion layer 8, the N-type anti-inversion layer 9, and the element isolation LOCOS oxide film 10 are formed by ion implantation into the epitaxial growth layer followed by thermal oxidation treatment. The P-type anti-inversion layer 8 is formed on the P-type well layer 6 in the low-potential region 1. The N-type anti-inversion layer 9 is formed on the N-type well layer 7 in the high-potential region 2. The element isolation LOCOS oxide film 10 is formed on the N-type well layer 7 in the high-voltage isolation region 3.

[0042] To stabilize the potential gradient of the N-type well layer 7, a doped polysilicon electrode 11 is formed on the N-type well layer 7, and a high-resistance polysilicon field plate 12 is formed on the element isolation LOCOS oxide film 10 above the N-type well layer 7. Thus, the element structure 21 in the high-voltage isolation region 3 has a resistive field plate.

[0043] To connect to the P-type substrate 4, a P-type body region 13, a P-type contact region 14, and an N-type contact region 15 are formed. The P-type body region 13 is formed on the P-type well layer 6, and the P-type contact region 14 is formed on the P-type body region 13. The N-type contact region 15 is formed on the N-type anti-inversion layer 9. The above is the structure of the element structure 21.

[0044] In this embodiment, the metal structure 22 is composed of three layers of metal wiring. The first layer of metal wiring forms aluminum wiring field plates 16, 17. The aluminum wiring field plate 16 is formed on the low-potential region 1 side of the high-voltage isolation region 3 and contacts the doped polysilicon electrode 11 and the P-type contact region 14. The aluminum wiring field plate 17 is formed on the high-potential region 2 side of the high-voltage isolation region 3 and contacts the doped polysilicon electrode 11 and the N-type contact region 15.

[0045] As Figure 1 shown, one end of the high-resistance polysilicon field plate 12 is connected to the low-potential region 1 via the aluminum wiring field plate 16. In addition, the high-resistance polysilicon field plate 12 spirally surrounds above the high-voltage isolation region 3, and the other end is connected to the high-potential region 2 via the aluminum wiring field plate 17.

[0046] The metal wiring of the second layer includes the second-layer metal wiring 182 disposed on the side of the low-potential region 1 of the high-voltage isolation region 3, and the second-layer metal wiring 192 disposed on the side of the high-potential region 2 of the high-voltage isolation region 3. The metal wiring of the third layer includes the third-layer metal wiring 183 disposed on the side of the low-potential region 1 of the high-voltage isolation region 3, and the third-layer metal wiring 193 disposed on the side of the high-potential region 2 of the high-voltage isolation region 3.

[0047] The horizontal primary coil 18 is formed by the second-layer metal wiring 182 and the third-layer metal wiring 183. The primary coil 18 is disposed on the side of the low-potential region 1 of the high-voltage isolation region 3. In addition, the horizontal secondary coil 19 is formed by the second-layer metal wiring 192 and the third-layer metal wiring 193. The secondary coil 19 is disposed on the side of the high-potential region 2 of the high-voltage isolation region 3. Here, the fact that the primary coil 18 and the secondary coil 19 are horizontal means that the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the plane direction of the P-type substrate 4. The primary coil 18 is connected to the low-potential region 1, and the secondary coil 19 is connected to the high-potential region 2.

[0048] As Figure 1 shown, the coil axis of the primary coil 18 is opposed to the coil axis of the secondary coil 19. That is, the coil axis of the secondary coil 19 exists on the extension line of the coil axis of the primary coil 18. Thus, the primary coil 18 and the secondary coil 19 are magnetically coupled by the magnetic field on the coil axis. That is, the primary coil 18 is a primary-side element, the secondary coil 19 is a secondary-side element, and the primary coil 18 and the secondary coil 19 are paired and function as signal transmission elements.

[0049] The semiconductor device 1010 described above includes a P-type substrate 4 as a semiconductor substrate and an element structure 21 formed on the P-type substrate 4. When the semiconductor device is viewed from above, it is divided into a low-potential region 1 having a GND as a reference potential, a high-potential region 2 having a floating potential as a reference potential, and a high-voltage isolation region 3 provided between the low-potential region 1 and the high-potential region 2 and insulating the two. The semiconductor device 1010 includes a signal transmission element provided on the element structure 21 of the high-voltage isolation region 3. The signal transmission element includes: a primary-side element disposed on the side of the low-potential region 1 of the high-voltage isolation region 3 and connected to the low-potential region 1; and a secondary-side element disposed on the side of the high-potential region 2 of the high-voltage isolation region 3 and connected to the high-potential region 2. The primary-side element and the secondary-side element are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the P-type substrate 4.

[0050] In addition, in the semiconductor device 1010, the primary-side element is a horizontal coil having a coil axis in a direction parallel to the main surface of the P-type substrate 4, that is, the primary coil 18. Further, the secondary-side coupling element is a horizontal coil having a coil axis in a direction parallel to the main surface of the P-type substrate 4, that is, the secondary coil 19. Moreover, the primary coil 18 and the secondary coil 19 are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the P-type substrate 4.

[0051] According to the semiconductor device 1010 described above, the following effects can be obtained. The maximum potential difference HV between the primary coil 18 and the secondary coil 19 is, for example, 600 V or 1200 V. However, since the primary coil 18 and the secondary coil 19 are horizontal coils, as long as the distance between the primary coil 18 and the secondary coil 19 is ensured by a layout pattern, the withstand voltage between the two can be relatively easily ensured.

[0052] In addition, since both the primary coil 18 and the secondary coil 19 are disposed above the high withstand voltage isolation region 3, the potential difference in the longitudinal direction, that is, the thickness direction of the P-type substrate 4, is reduced. For example, in the conventional structure in which both the primary coil 18 and the secondary coil 19 are provided in the low potential region 1, the maximum potential difference in the longitudinal direction between the lead wiring of the secondary coil and the high-resistance polysilicon field plate 12 is HV.

[0053] In contrast, in the semiconductor device 1010, the maximum potential difference in the longitudinal direction between the primary coil 18 and the high-resistance polysilicon field plate 12 is HV / 2, and the maximum potential difference in the longitudinal direction between the secondary coil 19 and the high-resistance polysilicon field plate 12 is also HV / 2. Thus, the potential difference in the longitudinal direction is halved compared to the conventional structure. As a result, the thickness of the interlayer film between the wirings can be thinned, thereby reducing the process cost.

[0054] In addition, in the semiconductor device 1010, since the primary coil 18 and the secondary coil 19 are provided in the ineffective region, that is, the high withstand voltage isolation region 3, an increase in the ineffective region due to the provision of the primary coil 18 and the secondary coil 19 does not occur. Therefore, the chip size can be reduced compared to the conventional structure.

[0055] <A-2. First Modified Example>

[0056] Figure 3 It is a top view of the semiconductor device 1011 according to the first modified example of the first embodiment. Figure 4 It is along Figure 3 A cross-sectional view of the semiconductor device 1011 taken along the line A-A′. Hereinafter, the structure of the semiconductor device 1011 will be described using these figures.

[0057] The semiconductor device 1011 differs from the semiconductor device 1010 only in the metal structure 22. The metal structure 22 of the semiconductor device 1011 is composed of N metal wirings. Here, N is a natural number of 4 or more.

[0058] In Figure 4 's example, the metal structure 22 is composed of 4 metal wirings. The fourth-layer metal wiring includes the fourth-layer metal wiring 184 provided on the low-potential region 1 side of the high-voltage withstand isolation region 3 and the fourth-layer metal wiring 194 provided on the high-potential region 2 side of the high-voltage withstand isolation region 3.

[0059] The horizontal primary coil 18 is composed of the second-layer metal wiring 182 and the fourth-layer metal wiring 184. In addition, the horizontal secondary coil 19 is composed of the second-layer metal wiring 192 and the fourth-layer metal wiring 194. The third-layer metal wiring 183 longitudinally connects the second-layer metal wiring 182 and the fourth-layer metal wiring 184 that constitute the primary coil 18. Similarly, the third-layer metal wiring 193 longitudinally connects the second-layer metal wiring 192 and the fourth-layer metal wiring 194 that constitute the secondary coil 19.

[0060] In Figure 4 's example, the metal structure 22 is composed of 4 metal wirings, and the horizontal coils are longitudinally connected through the third-layer metal wiring. In the case where the metal structure 22 is composed of 5 metal wirings, it is only necessary to longitudinally connect the horizontal coils through the third-layer and fourth-layer metal wirings.

[0061] That is, the semiconductor device 1011 includes N metal wirings formed on the element structure 21, where N is a natural number of 4 or more. The horizontal coils are composed of the second-layer and the Nth-layer metal wirings. The second-layer and the Nth-layer metal wirings that constitute one horizontal coil are longitudinally connected through the metal wirings from the third layer to the N-1th layer. Thereby, the effects of increasing the cross-sectional area of the primary coil 18 and the secondary coil 19 and improving the magnetic coupling strength between the primary coil 18 and the secondary coil 19 can be obtained.

[0062] However, for the structure of the semiconductor device 1011, since the number of wiring layers increases and the process cost increases, it is preferably applied to the case where multi-layer wiring is required in other circuit regions, or to the case where the magnetic coupling strength needs to be improved to ensure the operation margin of signal transmission, etc.

[0063] <A-3. Second Modified Example>

[0064] Figure 5 is a top view of the semiconductor device 1012 according to the second modified example of Embodiment 1. Figure 6 is along Figure 5Cross-sectional view of the semiconductor device 1012 taken along the line A-A'. Hereinafter, the structure of the semiconductor device 1012 will be described using these figures.

[0065] In the structure of the semiconductor device 1011, the semiconductor device 1012 is formed of a magnetic material for the metal wirings from the third layer to the (N-1)th layer, and they are inserted into the primary coil 18 and the secondary coil 19 formed by the metal wirings of the second layer and the Nth layer in a flat plate shape to form the coil core 20.

[0066] Figure 6 Shows the case where the metal structure 22 is composed of four metal wirings. In this example, the metal wiring of the third layer is inserted into the primary coil 18 and the secondary coil 19 to become the coil core 20.

[0067] That is, the semiconductor device 1012 includes N metal wirings formed on the element structure, where N is a natural number of 4 or more. The horizontal coil is formed by the metal wirings of the second layer and the Nth layer, and the metal wirings from the third layer to the (N-1)th layer are formed of a magnetic material to form the coil core 20 of the horizontal coil. With the above structure, the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is increased.

[0068] In addition, for the magnetic material used for the coil core 20, cobalt has been put into practical use as a semiconductor wiring material, so it is preferable. However, in addition to cobalt, nickel can also be used, or an alloy of cobalt or nickel can also be used.

[0069] However, for the structure of the semiconductor device 1012, since the number of wiring layers increases and the process cost increases, it is preferably applied to the case where multi-layer wiring is required in other circuit regions, or the case where the magnetic coupling strength needs to be increased to ensure the operation margin of signal transmission, etc.

[0070] <A-4. Third Modified Example>

[0071] Figure 7 Is a top view of the semiconductor device 1013 according to the third modified example of the first embodiment. Figure 8 Is along Figure 7 Cross-sectional view of the semiconductor device 1013 taken along the line A-A'. Hereinafter, the structure of the semiconductor device 1013 will be described using these figures.

[0072] The semiconductor device 1013 is different from the semiconductor device 1010 only in the metal structure 22. The metal structure 22 of the semiconductor device 1013 is composed of two metal wirings. The metal wiring of the first layer includes, in addition to the aluminum wiring field plates 16 and 17, the metal wiring 181 of the first layer that forms the primary coil 18 and the metal wiring 191 of the first layer that forms the secondary coil 19. That is, the metal wirings 181 and 191 of the first layer are aluminum wirings.

[0073] The primary coil 18 is composed of the metal wiring 181 of the first layer and the metal wiring 182 of the second layer. In addition, the secondary coil 19 is composed of the metal wiring 191 of the first layer and the metal wiring 192 of the second layer.

[0074] That is, the semiconductor device 1013 includes two-layer metal wiring formed on the element structure 21, and the horizontal coil is composed of the metal wiring of the first layer and the second layer. According to the semiconductor device 1013, the metal structure 22 is composed of two-layer metal wiring fewer than the other semiconductor devices 1010, 1011, and 1012 described above, so the process cost is reduced. However, the lower-layer wiring of the horizontal coil needs to be formed by the aluminum wiring on the same layer as the aluminum wiring field plates 16 and 17. Therefore, the area where the horizontal coil can be formed becomes narrow, the number of turns of the coil decreases, and the magnetic coupling strength weakens. In addition, since the longitudinal distance between the primary coil 18 and the secondary coil 19 and the high-resistance polysilicon field plate 12 becomes short, the electric field strength increases and the breakdown voltage decreases. However, when the required breakdown voltage and the operation margin for signal transmission can be ensured despite this, the semiconductor device 1013 is the cheapest and preferred method.

[0075] <A-5. Fourth Modified Example>

[0076] Figure 9 It is a top view of the semiconductor device 1014 according to the fourth modified example of the first embodiment. Figure 10 It is along Figure 9 The cross-sectional view of the semiconductor device 1014 taken along the A-A' line. Hereinafter, the structure of the semiconductor device 1014 will be described using these figures.

[0077] The difference between the semiconductor device 1014 and the semiconductor device 1013 is that the metal structure 22 is composed of N-layer metal wiring. Here, N is a natural number of 3 or more.

[0078] In Figure 10 In the example, the metal structure 22 is composed of three-layer metal wiring. The metal wiring 181 and 191 of the first layer have the same structure as the semiconductor device 1013. The horizontal primary coil 18 is composed of the metal wiring 181 of the first layer and the metal wiring 183 of the third layer. In addition, the horizontal secondary coil 19 is composed of the metal wiring 191 of the first layer and the metal wiring 193 of the third layer. The metal wiring 182 of the second layer connects the metal wiring 181 of the first layer and the metal wiring 183 of the third layer that constitute the primary coil 18 longitudinally. Similarly, the metal wiring 192 of the second layer connects the metal wiring 191 of the first layer and the metal wiring 193 of the third layer that constitute the secondary coil 19 longitudinally.

[0079] In Figure 10In the example, the metal structure 22 is composed of three layers of metal wirings. Through the metal wiring of the second layer, the horizontal coils are connected longitudinally. When the metal structure 22 is composed of four layers of metal wirings, the horizontal coils can be connected longitudinally through the metal wirings of the second and third layers. That is, when using N layers of metal wirings, the horizontal coils can be connected longitudinally through the metal wirings from the second layer to the (N - 1)th layer.

[0080] That is, the semiconductor device 1014 includes N layers of metal wirings formed on the element structure 21, where N is a natural number of 3 or more. The horizontal coils are composed of the metal wirings of the first layer and the Nth layer. The metal wirings of the second layer and the Nth layer constituting one horizontal coil are connected longitudinally through the metal wirings from the second layer to the (N - 1)th layer. Through the above structure, the cross-sectional areas of the primary coil 18 and the secondary coil 19 can be increased, and the magnetic coupling strength between the primary coil 18 and the secondary coil 19 can be improved. According to the number of wiring layers as a process or layout limitations, etc., the structure of the semiconductor device 1014 can be optimized.

[0081] <A-6. Fifth Modified Example>

[0082] Figure 11 It is a top view of the semiconductor device 1015 according to the fifth modified example of the first embodiment. Figure 12 is along Figure 11 The cross-sectional view of the semiconductor device 1015 taken along the A - A' line. Hereinafter, the structure of the semiconductor device 1015 will be described using these figures.

[0083] In the structure of the semiconductor device 1014, the semiconductor device 1015 is formed by forming the metal wirings from the second layer to the (N - 1)th layer with a magnetic material and inserting them into the primary coil 18 and the secondary coil 19 formed by the metal wirings of the first layer and the Nth layer in a flat plate shape to form the coil core 20.

[0084] Figure 12 It shows the case where the metal structure 22 is composed of three layers of metal wirings. In this example, the metal wiring of the second layer is inserted into the primary coil 18 and the secondary coil 19 to become the coil core 20.

[0085] That is, the semiconductor device 1015 includes N layers of metal wirings formed on the element structure, where N is a natural number of 3 or more. The horizontal coils are composed of the metal wirings of the first layer and the Nth layer. The metal wirings from the second layer to the (N - 1)th layer are formed with a magnetic material and constitute the coil core of the horizontal coil. Through the above structure, the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is improved. According to the number of wiring layers as a process or layout limitations, etc., the structure of the semiconductor device 1015 can be optimized.

[0086] <B. Embodiment 2>

[0087] <B-1. Structure>

[0088] Figure 13 It is a top view of the semiconductor device 1020 according to Embodiment 2. The difference between the semiconductor device 1020 and the semiconductor device 1010 according to Embodiment 1 is only that the primary coil 18 and the secondary coil 19 are arranged such that their coil axes are parallel to each other.

[0089] In the semiconductor device 1020, the primary coil 18 and the secondary coil 19 are magnetically coupled not through the magnetic flux on their coil axes but through the magnetic flux around their coils. The magnetic flux density around the coils is lower than that on the coil axes. However, since the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the circumferential direction of the high breakdown voltage isolation region 3, there is an advantage that the coil lengths of the primary coil 18 and the secondary coil 19 can be easily extended, and the number of turns can be increased.

[0090] <B-2. Modified Example>

[0091] Figure 14 It is a top view of the semiconductor device 1021 according to the modified example of Embodiment 2. In the semiconductor device 1021, the metal structure 22 is composed of 4 or more N-layer metal wirings, and the coil core 20 is formed by the metal wirings from the third layer to the N-1 layer. In other words, the semiconductor device 1021 is formed by applying the configuration in which the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the semiconductor device 1012 according to the second modified example of Embodiment 1.

[0092] According to the structure of the semiconductor device 1021, in addition to being able to increase the number of turns of the coil, since the primary coil 18 and the secondary coil 19 are magnetically coupled by the magnetic flux on the coil axes passing through the coil core 20, a high magnetic coupling strength can also be obtained.

[0093] <C. Embodiment 3>

[0094] <C-1. Structure>

[0095] Figure 15 It is a top view of the semiconductor device 1030 according to Embodiment 3. Figure 16 It is along Figure 15 The cross-sectional view of the semiconductor device 1030 taken along the A-A' line. Hereinafter, the structure of the semiconductor device 1030 will be described using these figures.

[0096] The metal structure 22 of the semiconductor device 1030 includes: a primary flat electrode 31 disposed on the low-potential region 1 side of the high-voltage isolation region 3 and connected to the low-potential region 1; and a secondary flat electrode 32 disposed on the high-potential region 2 side of the high-voltage isolation region 3 and connected to the high-potential region 2. The primary flat electrode 31 corresponds to the primary-side element, and the secondary flat electrode 32 corresponds to the secondary-side element.

[0097] The primary flat electrode 31 has a first surface 311 parallel to the thickness direction of the P-type substrate 4. The secondary flat electrode 32 has a second surface 321 parallel to the thickness direction of the P-type substrate 4 and opposed to the first surface 311. The primary flat electrode 31 and the secondary flat electrode 32 are capacitively coupled to each other through the electric field between the first surface 311 and the second surface 321, thereby performing signal transmission.

[0098] That is, in the semiconductor device 1030, the primary-side element is the primary flat electrode 31 having the first surface 311 parallel to the thickness direction of the P-type substrate 4. In addition, the secondary-side element is the secondary flat electrode 32 having the second surface 321 parallel to the thickness direction of the P-type substrate 4 and opposed to the first surface 311. The primary flat electrode 31 and the secondary flat electrode 32 are capacitively coupled to each other through the electric field in the direction parallel to the main surface of the P-type substrate 4 between the first surface 311 and the second surface 321.

[0099] According to the above structure, the longitudinal potential difference between the primary flat electrode 31 and the high-resistance polysilicon field plate 12 becomes HV / 2. In addition, the longitudinal potential difference between the secondary flat electrode 32 and the high-resistance polysilicon field plate 12 also becomes HV / 2. That is, similar to Embodiments 1 and 2 in which a horizontal coil is used for the capacitive coupling element, the longitudinal potential difference is halved compared to the conventional structure. Therefore, it is possible to reduce the film thickness of the interlayer insulating film between wirings, thereby reducing the process cost.

[0100] <C-2. Modified Example>

[0101] Although not shown in the drawings, the capacitance value can also be increased by making the capacitance-forming surface between the primary flat electrode 31 and the secondary flat electrode 32, that is, the first surface 311 and the second surface 321, zigzag to form a pattern meshing in a comb shape. However, in this case, since the longitudinal electric field strength increases at the convex portions of each comb tooth, it is necessary to determine the pattern while achieving a balance with ensuring the withstand voltage.

[0102] In Embodiments 1 to 3, the signal transmission element is provided only on one side of the four sides of the high-voltage isolation region 3. However, the signal transmission element can also be provided on two or more sides of the high-voltage isolation region 3, or can be provided on the entire surface of the high-voltage isolation region 3 including the arc portion. Thereby, the magnetic coupling strength or the capacitive coupling strength can be increased. Or, a plurality of signal transmission element pairs can be provided.

[0103] <D. Embodiment 4>

[0104] <D-1. Structure>

[0105] Figure 17 It is a top view of the semiconductor device 1040 according to Embodiment 4. In the semiconductor device 1012 according to the second modification of Embodiment 1, the primary coil 18 is disposed in the low potential region 1, and the secondary coil 19 is disposed in the high potential region 2.

[0106] The metal wirings from the third layer to the (N-1)th layer are made of a magnetic material and are inserted into the primary coil 18 and the secondary coil 19 in a flat plate shape from the low potential region 1 to the high potential region 2 to form the coil core 20. The magnetic coupling strength is ensured by the coil core 20.

[0107] That is, in the semiconductor device 1040, the signal transmission element includes: a primary coil 18 disposed in the low potential region 1; a secondary coil 19 disposed in the high potential region 2; and a coil core 20 that is inserted into both the primary coil 18 and the secondary coil 19 across the high breakdown voltage isolation region 3 and is made of a magnetic material. According to the above structure, since the primary coil 18 and the secondary coil 19 as the signal transmission element are disposed on the circuit region, the chip size increases. However, since the longitudinal potential difference between the horizontal coil and the high-resistance polysilicon field plate 12 disappears, it is possible to realize thinning of the interlayer oxide film thickness and reduction of the process cost.

[0108] <D-2. Modification>

[0109] Figure 18 It is a top view of the semiconductor device 1041 according to the modification of Embodiment 4. In the semiconductor device 1040, the primary coil 18 and the secondary coil 19 are arranged such that their coil axes are opposed to each other. In contrast, in the semiconductor device 1041, the primary coil 18 and the secondary coil 19 are arranged such that their coil axes are parallel to each other.

[0110] <E. Embodiment 5>

[0111] Figure 19 It is a cross-sectional view of the semiconductor device 1050 according to Embodiment 5. Figure 19 The shown cross-section corresponds to Figure 2 the cross-section of the semiconductor device 1010 shown.

[0112] In the semiconductor device 1050 according to Embodiment 1, the capacitive coupling type field plate 25 is used instead of the high-resistance polysilicon field plate 12.

[0113] The element structure 21 of the semiconductor device 1050 has a lower field plate 251 on the same layer as the doped polysilicon electrode 11 in the high breakdown voltage isolation region 3. In addition, the metal structure 22 of the semiconductor device 1050 is composed of three layers of metal wirings, and the first layer of metal wiring includes an upper field plate 252 in addition to the aluminum wiring field plates 16 and 17. That is, the upper field plate 252 is composed of aluminum wiring.

[0114] A capacitively coupled field plate 25 is composed of the lower field plate 251 and the upper field plate 252. According to the semiconductor device 1050, since aluminum wiring is used for the upper field plate 252, the longitudinal electric field intensity becomes high. However, when the RESURF separation distance is short and a high-resistance polysilicon field plate 12 is used, the leakage current and power consumption become large and it is not suitable, etc. In such cases, this structure is preferably applied.

[0115] In addition, the structure of the present embodiment using the capacitively coupled field plate 25 can also be applied to semiconductor devices among the above various semiconductor devices that do not use the first layer of metal wiring as a horizontal coil.

[0116] <F. Embodiment 6>

[0117] Figure 20 It is a cross-sectional view of the semiconductor device 1060 according to Embodiment 6. Figure 20 The shown cross-section corresponds to Figure 2 the cross-section of the shown semiconductor device 1010.

[0118] The semiconductor device 1060 has, in the semiconductor device 1010 according to Embodiment 1, a separation structure based on a trench 26 (hereinafter, trench separation structure) instead of the bonding separation structure. The trench 26 penetrates the N-type well layer 7 of the high breakdown voltage isolation region 3 in the thickness direction. That is, the element structure 21 of the high breakdown voltage isolation region 3 is dielectrically isolated by the trench 26. A buried oxide film layer 27 is provided between the P-type substrate 4, the P-type well layer 6, and the N-type well layer 7.

[0119] According to the semiconductor device 1060, since there is no field plate above the high breakdown voltage isolation region 3, the longitudinal electric field intensity becomes weak, but due to the trench separation structure, the process cost increases. Therefore, when a dielectric isolation structure is required in the low potential region 1 or the high potential region 2, this structure of the present embodiment is preferably applied.

[0120] As described above, the preferred embodiments and the like have been described in detail, but are not limited to the above embodiments and the like, and various modifications and substitutions can be made to the above embodiments and the like without departing from the scope described in the claims.

[0121] Hereinafter, each aspect of the present disclosure will be summarized and described as an appendix.

[0122] (Supplementary Note 1)

[0123] A semiconductor device includes a semiconductor substrate and an element structure formed on the semiconductor substrate. Among them,

[0124] When viewed from above, the semiconductor device is divided into: a low-potential region with a ground potential as the reference potential, a high-potential region with a floating potential as the reference potential, and a high-voltage isolation region provided between the low-potential region and the high-potential region to separate the two.

[0125] The semiconductor device includes a signal transmission element provided on the element structure in the high-voltage isolation region.

[0126] The signal transmission element includes:

[0127] A primary-side element provided on the low-potential region side of the high-voltage isolation region and connected to the low-potential region; and

[0128] A secondary-side element provided on the high-potential region side of the high-voltage isolation region and connected to the high-potential region.

[0129] The primary-side element and the secondary-side element are magnetically coupled or capacitively coupled to each other through a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate.

[0130] (Supplementary Note 2)

[0131] According to the semiconductor device described in Supplementary Note 1, among them,

[0132] The primary-side element is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, that is, a primary coil.

[0133] The secondary-side element is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, that is, a secondary coil.

[0134] The primary coil and the secondary coil are magnetically coupled to each other through a magnetic field in a direction parallel to the main surface of the semiconductor substrate.

[0135] (Supplementary Note 3)

[0136] According to the semiconductor device described in Supplementary Note 2, among them,

[0137] It includes N-layer metal wirings formed on the element structure, where N is a natural number of 4 or more.

[0138] The horizontal coil is composed of the second layer and the Nth layer of the metal wirings.

[0139] The second layer and the Nth layer of the above-mentioned horizontal coil are longitudinally connected through the above-mentioned metal wirings from the third layer to the (N-1)th layer.

[0140] (Supplementary Note 4)

[0141] According to the semiconductor device described in Supplementary Note 2, wherein,

[0142] it has N layers of metal wirings formed on the above-mentioned element structure, where N is a natural number of 4 or more,

[0143] the above-mentioned horizontal coil is composed of the second layer and the Nth layer of the above-mentioned metal wirings,

[0144] the above-mentioned metal wirings from the third layer to the (N-1)th layer are made of a magnetic material and form the coil core of the above-mentioned horizontal coil.

[0145] (Supplementary Note 5)

[0146] According to the semiconductor device described in Supplementary Note 2, wherein,

[0147] it has two layers of metal wirings formed on the above-mentioned element structure,

[0148] the above-mentioned horizontal coil is composed of the first layer and the second layer of the above-mentioned metal wirings.

[0149] (Supplementary Note 6)

[0150] According to the semiconductor device described in Supplementary Note 2, wherein,

[0151] it has N layers of metal wirings formed on the above-mentioned element structure, where N is a natural number of 3 or more,

[0152] the above-mentioned horizontal coil is composed of the first layer and the Nth layer of the above-mentioned metal wirings,

[0153] the first layer and the Nth layer of the above-mentioned metal wirings that form one of the above-mentioned horizontal coils are longitudinally connected through the above-mentioned metal wirings from the second layer to the (N-1)th layer.

[0154] (Supplementary Note 7)

[0155] According to the semiconductor device described in Supplementary Note 2, wherein,

[0156] it has N layers of metal wirings formed on the above-mentioned element structure, where N is a natural number of 3 or more,

[0157] the above-mentioned horizontal coil is composed of the first layer and the Nth layer of the above-mentioned metal wirings,

[0158] the above-mentioned metal wirings from the second layer to the (N-1)th layer are made of a magnetic material and form the coil core of the above-mentioned horizontal coil.

[0159] (Supplementary Note 8)

[0160] The semiconductor device according to Supplementary Note 2, wherein,

[0161] The primary coil and the secondary coil are arranged such that their coil axes are parallel to each other.

[0162] (Supplementary Note 9)

[0163] The semiconductor device according to Supplementary Note 1, wherein,

[0164] The primary-side element is a primary flat electrode having a first surface parallel to the thickness direction of the semiconductor substrate,

[0165] The secondary-side element is a secondary flat electrode having a second surface parallel to the thickness direction of the semiconductor substrate and facing the first surface,

[0166] The primary flat electrode and the secondary flat electrode are capacitively coupled to each other by an electric field in a direction parallel to the main surface of the semiconductor substrate between the first surface and the second surface.

[0167] (Supplementary Note 10)

[0168] The semiconductor device according to Supplementary Note 9, wherein,

[0169] The first surface and the second surface are zigzag and meshed in a comb shape when viewed from above.

[0170] (Supplementary Note 11)

[0171] The semiconductor device according to Supplementary Note 1, wherein,

[0172] The signal transmission element is provided on the entire surface of the high-voltage isolation region.

[0173] (Supplementary Note 12)

[0174] A semiconductor device includes a semiconductor substrate and an element structure formed on the semiconductor substrate, wherein,

[0175] When viewed from above, the semiconductor device is divided into: a low-potential region having a ground potential as a reference potential, a high-potential region having a floating potential as a reference potential, and a high-voltage isolation region provided between the low-potential region and the high-potential region and separating the two,

[0176] The semiconductor device includes a signal transmission element provided on the element structure over the low-potential region, the high-voltage isolation region, and the high-potential region,

[0177] The signal transmission element includes:

[0178] A primary coil, disposed in the above-mentioned low-potential region;

[0179] A secondary coil, disposed in the above-mentioned high-potential region; and

[0180] A coil core, inserted into both the above-mentioned primary coil and the above-mentioned secondary coil across the above-mentioned high-voltage isolation region and made of a magnetic material,

[0181] The above-mentioned primary coil and the above-mentioned secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the above-mentioned semiconductor substrate.

[0182] (Supplementary Note 13)

[0183] The semiconductor device according to any one of Supplementary Notes 4, 7, and 12, wherein

[0184] The above-mentioned magnetic material is cobalt.

[0185] (Supplementary Note 14)

[0186] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein

[0187] The above-mentioned element structure of the above-mentioned high-voltage isolation region has a resistive field plate.

[0188] (Supplementary Note 15)

[0189] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein

[0190] The above-mentioned element structure of the above-mentioned high-voltage isolation region has a capacitively coupled field plate.

[0191] (Supplementary Note 16)

[0192] The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein

[0193] The above-mentioned element structure of the above-mentioned high-voltage isolation region is dielectrically isolated by a trench.

Claims

1. A semiconductor device comprising a semiconductor substrate and an element structure formed on the semiconductor substrate, It is characterized in that The semiconductor device is divided into: a low potential region with a ground potential as a reference potential, a high potential region with a floating potential as a reference potential, and a high withstand voltage separation region provided between the low potential region and the high potential region to separate the two, when viewed from above. The semiconductor device includes a signal transmission element provided on the element structure of the high withstand voltage isolation region. The signal transmission element comprises: A primary-side element, disposed on the low-potential region side of the high-withstand voltage separation region and connected to the low-potential region; and A secondary-side element is provided on the high-potential region side of the high-withstand voltage separation region and is connected to the high-potential region. The primary-side element and the secondary-side element are magnetically coupled or capacitively coupled to each other by a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: The primary side element is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, namely, a primary coil. The secondary side element is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, that is, a secondary coil. The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein: There are N layers of metal wiring formed on the element structure, wherein N is a natural number greater than 4, The horizontal coil is composed of the metal wiring of the second layer and the Nth layer, The metal wirings of the second layer and the Nth layer constituting one of the horizontal coils are connected in the vertical direction through the metal wirings from the third layer to the N-1th layer.

4. The semiconductor device according to claim 2, wherein: There are N layers of metal wiring formed on the element structure, wherein N is a natural number greater than 4, The horizontal coil is composed of the metal wiring of the second layer and the Nth layer, The metal wiring from the third layer to the N-1th layer is made of a magnetic material and constitutes a coil core of the horizontal coil.

5. The semiconductor device according to claim 2, wherein: A two-layer metal wiring is formed on the element structure. The horizontal coil is composed of the first layer and the second layer of the metal wiring.

6. The semiconductor device according to claim 2, wherein: There are N layers of metal wiring formed on the element structure, wherein N is a natural number greater than 3, The horizontal coil is composed of the metal wiring of the first layer and the Nth layer, The metal wirings of the first layer and the Nth layer constituting one horizontal coil are connected in the vertical direction through the metal wirings from the second layer to the N-1th layer.

7. The semiconductor device according to claim 2, wherein: There are N layers of metal wiring formed on the element structure, wherein N is a natural number greater than 3, The horizontal coil is composed of the metal wiring of the first layer and the Nth layer, The metal wiring from the second layer to the N-1th layer is made of a magnetic material and constitutes a coil core of the horizontal coil.

8. The semiconductor device according to claim 2, wherein: The primary coil and the secondary coil are arranged so that coil axes thereof are parallel to each other.

9. The semiconductor device according to claim 1, wherein: The primary side element is a primary plate electrode having a first surface parallel to the thickness direction of the semiconductor substrate, The secondary side element is a secondary plate electrode having a second surface parallel to the thickness direction of the semiconductor substrate and facing the first surface, The primary plate electrode and the secondary plate electrode are capacitively coupled to each other by an electric field between the first surface and the second surface in a direction parallel to the main surface of the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein: The first surface and the second surface are bent and meshed in a comb-teeth shape when viewed from above.

11. The semiconductor device according to claim 1, wherein: The signal transmission element is provided on the entire surface of the high withstand voltage isolation region.

12. A semiconductor device comprising a semiconductor substrate and a device structure formed on the semiconductor substrate, It is characterized in that The semiconductor device is divided into: a low potential region with a ground potential as a reference potential, a high potential region with a floating potential as a reference potential, and a high withstand voltage separation region provided between the low potential region and the high potential region to separate the two, when viewed from above. The semiconductor device includes a signal transmission element provided on the element structure over the low potential region, the high withstand voltage isolation region, and the high potential region. The signal transmission element comprises: A primary coil is arranged in the low potential area; A secondary coil is arranged in the high potential region; and a coil core which is inserted into both the primary coil and the secondary coil across the high withstand voltage separation region and is made of a magnetic body; The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate.

13. The semiconductor device according to any one of claims 4, 7 and 12, characterized in that: The magnetic body is cobalt.

14. The semiconductor device according to any one of claims 1 to 12, wherein: The element structure of the high withstand voltage separation region has a resistive field plate.

15. The semiconductor device according to any one of claims 1 to 12, wherein: The element structure of the high withstand voltage isolation region has a capacitive coupling field plate.

16. The semiconductor device according to any one of claims 1 to 12, wherein: The element structures of the high withstand voltage isolation region are dielectrically isolated by trenches.

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