Semiconductor package

Abstract

A semiconductor package for a PCB is disclosed. The semiconductor package includes: a die pad; a die; a plurality of terminals and an enclosure. The die is coupled to the die pad. The plurality of terminals are electrically connected to the die. The plurality of terminals includes a first terminal array disposed along a first side of the semiconductor package, and a second terminal array disposed along a second side of the semiconductor package. The second side is opposite to the first side. Each terminal of the plurality of terminals includes a pad having a flank. The encapsulation at least partially surrounds the die. A recess is defined between each terminal of each of the first terminal array and the second terminal array.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, a method of manufacturing a batch of semiconductor packages, and a semiconductor package array. Background Art

[0002] Semiconductor packages, such as transistors, are manufactured as layered assemblies including components such as die pads (e.g., thermal pads), dies (e.g., chips), leads (e.g., traces), and encapsulants (e.g., housings).

[0003] The leads of a semiconductor package having a plurality of leads typically electrically connected to a die define pads (e.g., contacts) through which the semiconductor package can be electrically connected to a printed circuit board (PCB). In typical applications, the entire semiconductor package can be coupled to the PCB only by means of the pads. This is typically by way of a soldered connection. In many applications, such as in the automotive field, it is desirable to inspect the solder joints as part of a quality control process to confirm that the semiconductor package is securely connected to the PCB. One problem with current processes is that the thickness of the solder between the semiconductor package pads and the corresponding PCB pads is typically very thin (e.g., on the order of about 10 microns). Inspecting the solder joints at this scale from a top (e.g., planar) view using automated optical inspection (AOI) presents a real challenge.

[0004] There is a need to overcome the disadvantages associated with existing semiconductor packages, as well as the associated manufacturing methods, whether mentioned in this document or otherwise. Summary of the Invention

[0005] According to a first aspect of the present invention, there is provided a semiconductor package for a PCB, the semiconductor package comprising:

[0006] A die pad;

[0007] A die coupled to the die pad;

[0008] A plurality of terminals electrically connected to the die, the plurality of terminals including a first terminal array disposed along a first side of the semiconductor package and a second terminal array disposed along a second side of the semiconductor package, wherein the second side is opposite the first side, and each terminal of the plurality of terminals includes a pad having flanks; and

[0009] An encapsulant at least partially surrounding the die; wherein

[0010] A groove is defined between each terminal of each terminal array in the first terminal array and the second terminal array.

[0011] A semiconductor package may alternatively be described as a semiconductor component. The semiconductor package may be a diode, a transistor, a combination of diodes and / or transistors, or other semiconductor devices.

[0012] The die pad may alternatively be described as a plate of conductive material. The die pad may be made of a copper alloy or entirely of copper. The die pad may be described as a thermal pad. The die pad may consist of a single body or may include multiple parts (e.g., a multi-part or multi-piece die pad). The die pad may have a variable thickness (e.g., including one or more protruding features).

[0013] The die may be a single component or may include multiple constituent components. The die is preferably coupled to the die pad using solder. The die coupled to the die pad may alternatively be described as a die attached to the die pad. The die may be described as bonded to the die pad. The die may be a silicon chip.

[0014] The terminals may be described as IO terminals. Each terminal may be described as a lead. Each terminal may include pads for attachment to a PCB. Each terminal may be at least partially bounded by a block.

[0015] In some embodiments, a first plurality of leads may extend from a first side of the die and then only a second plurality of leads may extend from the opposite second side. In other words, the third and fourth sides of the die may have no leads. This may be described as a bilateral configuration.

[0016] The side suitable for applying solder thereto may refer to a side-wettable flank (SWF). The flank preferably has a thickness of about 100 microns. This is achievable when the thickness of the lead frame array and the die pad is about 102 microns.

[0017] The encapsulant may alternatively be described as a housing or a shroud. The encapsulant may be described as encapsulating the die. The encapsulant advantageously reduces the risk of contaminants such as moisture infiltrating the semiconductor package. The encapsulant preferably extends between a first major surface and a second major surface of the die pad. The encapsulant may be plastic. The encapsulant may alternatively be described as made of a polymer. The encapsulant is preferably manufactured using an injection molding method, wherein at least partially molten material is molded into the desired encapsulant shape. Additionally, a transfer molding or compression molding process may be used to manufacture the encapsulant. The encapsulant may be thermoplastic (e.g., a thermosetting polymer). The encapsulant may completely surround the die.

[0018] In some embodiments, the die pad may consist of multiple terminals. That is, in some embodiments, the die may be directly coupled to multiple terminals. In such embodiments, the electrical connection from the multiple terminals to the die may be provided by coupling the die (electrically) to the terminals. Another different way is described where, in some embodiments, the die pad is not a separate component of the terminal, but the terminal provides the die pad function.

[0019] Advantageously, the recess means that the terminal effectively protrudes from the encapsulation, making it easier to inspect the solder joints from a top-down perspective (e.g., using automated optical inspection [AOI]). Additionally, the joints can be inspected from multiple different orientations of the flank (e.g., from above, from the side, etc.).

[0020] Each pad and flank may be exposed through the encapsulation.

[0021] The pads and flanks being exposed may mean that the pads and flanks are flush (but visible) with the surrounding encapsulation. The pads and flanks being exposed may mean that the pads and flanks protrude through the surrounding encapsulation (i.e., protruding features).

[0022] Advantageously, the pads and flanks being exposed through the encapsulation means easier inspection.

[0023] Each recess may be a stepped recess.

[0024] Each recess preferably extends across the entire range of the height of the semiconductor package.

[0025] Each recess may extend from a first terminal of an adjacent pair of terminals to a second terminal of the adjacent pair of terminals.

[0026] In other words, the recess extends entirely between adjacent terminals.

[0027] One or more of the terminals may include a metal plating that at least partially extends through the pad and flank.

[0028] The metal plating may alternatively be described as a metal layer. The metal plating may include one or more of tin or silver. The metal plating that at least partially extends through the flank is intended to surround the metal plating that at least partially extends along the non-horizontal surface of the pad. For example, if the pad defines a bottom side and also has an associated height, that height may be described as defining the flank. The metal plating may extend through the entire range of one or more pads and flanks. The metal plating may extend through the entire range of each pad and flank in the pads and flanks.

[0029] Preferably, each terminal includes a metal-plated flank and a metal-plated pad.

[0030] Advantageously, at least a portion of the side wings including the metal plating means that the semiconductor package can be coupled to the PCB through both the lower side (i.e., the pads) of the terminals and the side wings. This means that a greater thickness of solder can be used, which means that a wider range of inspection processes can be used to confirm that the solder joints are strong and that the semiconductor package is firmly coupled to the PCB.

[0031] The plurality of terminals may also include a third terminal array disposed along a third side of the semiconductor package and a fourth terminal array disposed along a fourth side of the semiconductor package, wherein the fourth side is opposite to the third side.

[0032] The first side, the second side, the third side, and the fourth side of the die may define all sides of the quadrilateral die. In other words, the corresponding plurality of terminals may extend from each side of the semiconductor package (or die). This may refer to a quadrilateral configuration (e.g., QFN - quadrilateral, flat, leadless). Leadless may refer to the fact that the terminals are not provided on elongated conductive leads extending beyond the encapsulation.

[0033] The thickness of the side wings may be equal to the thickness of the terminals.

[0034] Advantageously, more material is available for electrical connection to the PCB. The thickness here is intended to represent the height of the terminals, which can be described as the smaller dimension of the terminals. The thickness of the side wings may be equal to the thickness of the terminals. The thickness of all side wings may be equal to the minimum thickness of the plurality of terminals. The thickness of the side wings may be equal to the minimum thickness (e.g., height) of the die pads. The thickness of the side wings may be equal to the minimum thickness (e.g., height) of the lead frame.

[0035] According to a second aspect of the present invention, there is provided a method of manufacturing a batch of semiconductor packages, the method comprising: coupling a plurality of dies to a plurality of die pads, the plurality of die pads being arranged in an array on a lead frame, wherein each die pad defines a corresponding semiconductor package, and coupling the plurality of dies to a plurality of terminals on the plurality of die pads, the terminals corresponding to each die pad at least including a first terminal array disposed along a first side of each semiconductor package and a second terminal array disposed along a second side of the semiconductor package, wherein the second side is opposite to the first side;

[0036] Providing a molten encapsulant on the plurality of semiconductor packages, the molten encapsulant at least partially surrounding the array;

[0037] Removing a first portion of the molten encapsulant and a first portion of the connecting bars of the lead frame extending between the terminals of the corresponding terminal arrays of each semiconductor package through a first removal operation to expose the side wings of the terminals while the terminals remain electrically connected to each other;

[0038] Using a plating process to plate at least a portion of the pads, the at least a portion of the pads including at least a portion of the exposed side wings;

[0039] Remove a second portion of the molten encapsulant and a second portion of the connecting rod through a second removal operation to isolate the terminals within each terminal array and define a groove between each isolated terminal of the first terminal array and each terminal array of the second terminal array; and

[0040] Cut the molten encapsulant at multiple locations to singulate the semiconductor packages from the array.

[0041] A batch of semiconductor packages can refer to multiple semiconductor packages.

[0042] The lead frame and / or the die pad can alternatively be described as a plate of conductive material. The die pad can be made of a copper alloy or entirely of copper. The die pad can have a variable thickness (e.g., including one or more protruding features).

[0043] Each die pad that defines a corresponding semiconductor package can alternatively be described as each separate die pad that continues to form an individual semiconductor package. The die pad can consist of a single body or can include multiple parts (e.g., a multi-part or multi-piece die pad).

[0044] The die can be a single component or can include multiple constituent components. The die is preferably coupled to the die pad using solder. The die coupled to the die pad can alternatively be described as the die attached to the die pad. The die can be a silicon chip. Multiple dies can be coupled to corresponding multiple die pads (e.g., one die per die pad).

[0045] The molten encapsulant is intended to represent a combined encapsulant molded in a single mold. For example, the molten encapsulant can be molded over multiple corresponding semiconductor packages. The encapsulant can be plastic. The encapsulant can alternatively be described as being made of a polymer. Preferably, an injection molding method is used to manufacture the encapsulant, wherein at least partially molten material is molded into the desired encapsulant shape. The plastic can be thermoplastic (e.g., a thermosetting polymer).

[0046] The connecting rod preferably extends directly between adjacent terminals. In other words, the connecting rod preferably takes the most direct path between the terminals (e.g., a straight-line path).

[0047] Singulating the semiconductor packages from the array can alternatively be described as separating or disassembling the semiconductor packages from the array. Alternatively, it can be described as cutting the semiconductor packages from the array.

[0048] In embodiments where the die is directly coupled to the terminals, the steps of coupling the die to the die pad and coupling the die to the terminals may be simultaneous (e.g., in the same step). That is, in some embodiments, coupling the die to the die pad may further include coupling the die to a plurality of terminals. In other embodiments, the die may be coupled to the die pad in a first step. In a subsequent step, the die may be coupled to the terminals, which are separate sub-components within the die pad.

[0049] Advantageously, when coupled to the PCB due to the recess, the semiconductor package can be easily inspected.

[0050] Removing the second portion of the connecting rod may include removing the remaining portion of the connecting rod.

[0051] One or more of the first removal operation and the second removal operation may include one or more of a laser cutting, water jetting, sawing, or chemical etching process.

[0052] Coupling a plurality of dies to a plurality of terminals may include using a wire bonding process.

[0053] Removing the first portion of the connecting rod may include cutting off a molten connecting rod that extends between a second terminal array of a first semiconductor package and a first terminal array of an adjacent second semiconductor package.

[0054] The first removal operation may include removing material from a plurality of discontinuous elongated regions.

[0055] The plurality of die pads may further include a third terminal array disposed along a third side of each semiconductor package and a fourth terminal array disposed along a fourth side of each semiconductor package, where the fourth side is opposite the third side.

[0056] According to a third aspect of the present invention, there is provided a lead frame for manufacturing a semiconductor package, the lead frame comprising:

[0057] An array of die pads, where each die pad defines a corresponding semiconductor package;

[0058] A plurality of terminals disposed around each die pad, each plurality of terminals including a first terminal array disposed along a first side of the die pad and a second terminal array disposed along a second side of the die pad, where the second side is opposite the first side, and each terminal of the plurality of terminals includes a pad having a flank;

[0059] Wherein the terminals within each first terminal array are electrically connected to each other by a first connecting rod that extends directly between the terminals;

[0060] Each terminal within each second terminal array is electrically connected to each other via a second connecting rod, and the second connecting rod extends directly between the terminals;

[0061] Adjacent die pads are electrically connected to each other via one or more of the first connecting rod and the second connecting rod.

[0062] In addition, a plane parallel to the first direction and the second direction can be described as a plane passing through the thickness of the lead frame (e.g., passing through the minimum dimension of the lead frame). A plane parallel to the first direction and the second direction can be described as a plane parallel to the plan view of the lead frame.

[0063] The first connecting rod and the second connecting rod that extend directly between the corresponding terminals are intended to mean that the first connecting rod and the second connecting rod extend in a straight line. At least a part of the thickness of the connecting rod is adjacent to the terminal. The connecting rod can be described as extending through the center points of the terminals of the array. The connecting rod can be described as extending between the terminals at the shortest possible distance.

[0064] The thickness of the first connecting rod and the second connecting rod is preferably greater than the corresponding thickness of the member extending between the first connecting rod and the second connecting rod.

[0065] Advantageously, the connecting rod having the above structure provides a more robust lead frame. The lead frame is more suitable for wire bonding operations. In addition, the thickness of the entire lead frame (e.g., perpendicular to the thickness of the connecting rod) can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Embodiments of the present invention will now be described by way of example only, with reference to the accompanying drawings, in which:

[0067] Figure 1 and Figure 2 is a perspective view of a semiconductor package according to an embodiment of the present invention;

[0068] Figure 3 is Figure 1 a plan view of the underside of the semiconductor package of

[0069] Figure 4 is Figures 1 to 3 a perspective view of the semiconductor package shown in

[0070] Figure 5 is a perspective view of a semiconductor package according to another embodiment of the present invention;

[0071] Figure 6 is Figure 5 a plan view of the underside of the semiconductor package of

[0072] Figure 7is a general plan view of a lead frame according to an embodiment of the present invention;

[0073] Figure 8 is Figure 7 a plan view of the first die pad of the lead frame;

[0074] Figure 9 is Figure 7 a plan view of the lower side of the lead frame;

[0075] Figure 10 is Figure 7 and Figure 9 a perspective view of the lead frame, wherein the die is coupled to the die pad;

[0076] Figure 11 is Figure 10 a perspective view of a partially assembled array, wherein the molten encapsulant is molded;

[0077] Figure 12 is Figure 11 a perspective view of the lower side of the partially assembled array after the first removal operation;

[0078] Figure 13 is Figure 12 a plan view of the lower side of the partially assembled array;

[0079] Figure 14 is Figure 12 and Figure 13 a plan view of the lower side of the partially assembled array, wherein the molten encapsulant is shown in a partially transparent view;

[0080] Figure 15 is

[0081] Figure 16 is Figure 15 a perspective view of the lower side of the partially assembled array after the second removal operation;

[0082] Figure 17 is Figure 16 a plan view of the lower side of the partially assembled array;

[0083] Figure 18 is Figure 16 and Figure 17 a plan view of the lower side of the partially assembled array, wherein the molten encapsulant is shown in a partially transparent view; and

[0084] Figure 19 is Figures 16 to 18 a perspective view of the lower side of the singulated semiconductor package after singulating the partially assembled array. Detailed Description

[0085] Go to Figure 1 , a perspective view of a semiconductor package 2 according to an embodiment of the present invention is provided.

[0086] The semiconductor package 2 includes a die pad 4, which is only partially visible in Figure 1 but is more clearly visible in Figure 2 (the first component part and the second component part are respectively labeled as 6 and 8). The semiconductor package 2 further includes a die coupled to the die pad 4 but not visible in Figure 1 . The semiconductor package 2 further includes a plurality of terminals. The terminals 2 can be described as IO (input / output) terminals.

[0087] The plurality of terminals respectively include a first terminal array 10 and a second terminal array 12. The first terminal array 10 includes a first terminal to a third terminal 14, 16, 18. The second terminal array, which is not visible in Figure 1 but is shown in Figure 2 , includes corresponding first to third terminals 20, 22, 24. The first terminal array 10 is disposed along a first side 26 of the semiconductor package 2 (and the die pad 4). The second terminal array 12 is disposed along a second side 28 of the semiconductor package 2 (and the die pad 4). The second side 28 is opposite to the first side 26.

[0088] Continuing to refer to Figure 2 , each terminal includes a pad having a flank. Taking the first terminal 20 of the second array 12 as an example, the terminal 20 includes a pad 20a and a flank 20b. In use, the pad 20a can be described as the lower side of the terminal 20. The flank 20b is a part of the terminal 20, which has a thickness and can be described as defining at least a part of the height of the terminal 20. The flank 20b can be described as the thickness of the pad 20a. In use, the flank provides another area through which the terminal can be connected to the PCB. Such flanks can refer to side-wettable flanks (SWF). As described in connection with the terminal 20, each of the other terminals also includes a corresponding pad and flank. The thickness of the flank 20b is labeled as 20c for reference. This thickness 20c can be described as being in a direction parallel to the height of the semiconductor package 2 (e.g., Figure 1 40 in

[0089] Return Figure 1 , the semiconductor package 2 further includes an encapsulant 28, which can be described as a housing. The encapsulant 28 at least partially surrounds the die (which is received by the encapsulant 28). The encapsulant 28 can be a polymer.

[0090] Continuing to refer to Figure 1, four grooves 32, 34, 36, 38 are defined as part of semiconductor package 2. Taking the first groove 32 and the second groove 34 as examples, the grooves 32, 34 are respectively defined between the first terminal 14 and the second terminal 16 and between the second terminal 16 and the third terminal 18. Although not visible in the figure, briefly referring to Figure 2 , the third groove 36 and the fourth groove 38 are respectively defined between the first terminal 20 and the second terminal 22 and between the second terminal 22 and the third terminal 24 of the second array 12. Thus, grooves are defined between each terminal of each terminal array of the first terminal array 10 and the second terminal array 12. Advantageously, by incorporating these grooves, the terminals effectively protrude from or are exposed from the encapsulant 28. Thus, using a top-down view (e.g., from the direction generally shown in Figure 1 ), it is easier to inspect the solder joints between the terminals and the PCB coupled to the semiconductor package 2. This inspection can be by means of automated optical inspection (AOI) of the assembled PCB. This inspection can include inspecting the spread of the solder.

[0091] Related to the above advantages, by comparing Figure 1 and Figure 2 , it can be understood that the pads and flanks of each terminal in the terminals include a metal plating. This is preferably a metal plating. The metal plating helps the adhesion of the solder to the pads and flanks to facilitate the coupling of the semiconductor package 2 to the PCB and the conductivity with the PCB. The incorporation of the flanks as part of the terminals also advantageously provides a larger surface area through which the solder can be attached to provide electrical communication with the PCB and the corresponding pads. In addition, as described above, the flanks are more easily inspected by AOI (which is necessary in some industries).

[0092] Also, each of the grooves 32, 34, 36, 38 is defined between the respective terminals of the first array 10 and the second array 12. In the illustrated embodiment, each of the grooves extends from the first terminal to the second terminal of an adjacent pair of terminals. In other words, each of the grooves 32, 34, 36, 38 extends entirely between adjacent terminals (i.e., from one terminal to another). In other embodiments, such as a four-sided configuration (see Figure 5 and Figure 6 ), this may not be the case. In addition, each of the grooves 32, 34, 36, 38 extends through the entire height 40 of the encapsulant 28 (and thus the semiconductor package 2). Each of the grooves is also a stepped groove.

[0093] The semiconductor package 2 also has a third side 42 and a fourth side 44. The semiconductor package 2 is a two-sided configuration, and thus the third side 42 and the fourth side 44 do not have any terminals. However, and again as will be combined with Figure 5 andFigure 6 As shown and described, for a four-sided configuration, the third and fourth sides may have terminals disposed on these sides. Return Figure 1 , taking the fourth side 44 as an example, although as Figure 1 shown, the die pad 4 has three exposed portions 46a-c, but these exposed portions themselves are not terminals, but are merely artifacts of the die pad 4 that began as part of a lead frame (see Figure 7 and Figure 8 ). The exposed portions 46a-c exist during the manufacturing process to facilitate electrical connection between the terminals of adjacent die pads, but the exposed portions are cut off at the point where the individual semiconductor package 2 is singulated (e.g., separated from the array). This will be described and shown in connection with the subsequent figures.

[0094] For completeness, Figure 1 a semiconductor view is shown generally from the top side. Figure 2 A semiconductor package 2 is shown generally from the bottom side (e.g., as indicated by the presence of the respective terminals).

[0095] Turning to Figure 3 , a plan view of the bottom side of the semiconductor package 2 is provided. Thus, Figure 3 the view of Figure 2 generally corresponds to the view shown in

[0096] Regarding the recess 36, the schematic marker 48 indicates that the extent of the third recess 36 generally corresponds to the distance between the first terminal 20 and the second terminal 22 of the second array 12. In other words, there is also a third recess 36 defined between the first terminal 20 and the second terminal 22, and the third recess 36 also extends from the first terminal 20 to the second terminal 22 (i.e., entirely between them).

[0097] Turning to Figure 4 , a perspective view of the semiconductor package 2 is provided, but the encapsulant 28 is shown in a translucent manner. Thus, Figure 4 the various internal components of the semiconductor package 2 are visible in

[0098] Figure 4 The first portion 6 and the second portion 8 of the entire die pad 4 are shown. As Figure 4 partially visible in Figure 8 , the first portion 6 and the second portion 8 are not actually electrically connected to each other. However, as will be understood by briefly referring to

[0099] Returning to Figure 4 , the first die portion 50 and the second die portion 52 are inFigure 4 is visible. The first die portion 50 and the second die portion 52 together define a die. The first die portion 50 is coupled to a first part 6 of the die pad. The second die portion 52 is coupled to a second part 8 of the die pad 4. The coupling can be by way of bonding, such as a solder layer. Taking the first die portion 50 as an example, two leads 56, 58 couple the first die portion 50 to a first terminal 14 and a second terminal 16 of the first terminal array 10. This coupling provides an electrical connection between the die portion and the terminals 14, 16. In the example shown, the coupling between the first die portion 50 and the terminals 14, 16 is by way of wire bonding. However, this is not necessary, and in other embodiments, alternative connections, such as using rigid connectors, can be employed.

[0100] Turning to the second die portion 52, as previously described, the second die portion 52 is coupled to the second part 8 of the die pad 4. The second die portion 52 is coupled to a second terminal 22 and a third terminal 24 of the second terminal array 12. This coupling provides an electrical connection between the second die portion 52 and the terminals 22, 24. Similar to the first die portion 50, electrical coupling is provided by leads 60, 62 that extend from the second die portion 52 to the second terminal 22 and the third terminal 24, respectively. The leads 60, 62 are again formed by a wire bonding process, but other connection methods can also be used.

[0101] Figure 4 Also shown is a third terminal 18 of the first terminal array 10 that is rigidly connected to the second part 8 of the die pad. This rigid connection is by way of a bridge 188 of the die pad 4. Thus, in some interpretations, the third terminal 18 can be considered to form part of the second part 8 of the die pad 4.

[0102] The same is true for a first terminal 20 of the second array 12 that forms part of a first part 6 of the die pad 4. This will also be understood by briefly referring to Figure 8 and Figure 14 (where the bridges are labeled 188, 184 in Figure 8 ).

[0103] Figure 4 It is also indicated how to effectively cut the exposed portions 46a - c of the die pad into the defined lines when removing the second part 8 of the die pad from the lead frame. By comparing Figure 1 , Figure 2 and Figure 4 , it can be understood that many of the components described in conjunction with Figure 4 are completely or partially encapsulated / shielded by the encapsulant 28.

[0104] Figure 4Also shown is how each of the first terminal 14, second terminal 16, and third terminal 18 of the first array 10 is electrically isolated from each other when the semiconductor package 2 is singulated. Described in another way, connecting rods such as Figure 8 shown (e.g., labeled 148) that previously extended between the terminals are removed as part of the manufacturing process. This also applies to the first through third terminals 20, 22, 24 of the second array 12.

[0105] In some embodiments, the die or die portion may be directly coupled to the terminals. That is, as in the illustrated embodiment, there may not be a first part and a second part of the die pad. Instead, the terminals may form part of the die pad to which the die or die portion is coupled (e.g., bonded).

[0106] Turning to Figure 5 , a perspective view is provided generally corresponding to the underside (e.g., similar to the underside of Figure 2 ) of a semiconductor package 70 according to another embodiment. The semiconductor package 70 shares many common features with the semiconductor package 2 already described and, thus, for the sake of brevity, the common features will not be described in detail. However, by comparing Figure 5 with Figure 2 , it will be apparent that the semiconductor package 70 involves a four-sided configuration (e.g., as opposed to the two-sided configuration of the semiconductor package 2). As such, terminals are provided along each of the first through fourth sides 74, 76, 78, 80 of the semiconductor package 70.

[0107] Like the previous embodiment, the semiconductor package 70 includes a plurality of terminal arrays. The semiconductor package 70 includes four terminal arrays 82, 84, 86, 88. Each of the first through fourth terminal arrays 82, 84, 86, 88 is provided along each of the first through fourth sides 74, 76, 78, 80 of the semiconductor package 70, respectively. The first terminal array 82 includes a first terminal 90 and a second terminal 92, respectively. The second terminal array 84 includes a first terminal 94 and a second terminal 96, respectively. The third terminal array 86 includes a first terminal 98, a second terminal 100, and a third terminal 102. The fourth terminal array 88 includes a first terminal 104, a second terminal 106, and a third terminal 108.

[0108] Turning to the grooves between the respective terminals, and starting from the first terminal array 82, a first groove 110 and a second groove 112 are defined between a first terminal 90 and a second terminal 92. Different from the first embodiment, due to the protrusion 114 provided between the first terminal 90 and the second terminal 92, the first groove 110 and the second groove 112 do not extend therebetween. The corresponding arrangement for the second array 84 is achieved through grooves 116, 118, which are again defined between a first terminal 94 and a second terminal 96, but do not extend between these terminals due to the protrusion 120. For each of the first array 82 and the second array 84, a plurality of grooves (110, 112, 116, 118) extend between adjacent pairs of terminals.

[0109] Turning respectively to the third terminal array 86 and the fourth terminal array 88, starting from the third array 86: a first groove 122 and a second groove 124 are respectively defined between a first terminal 98 and a second terminal 100 and between the second terminal 100 and a third terminal 102. Thus, a groove is defined between each adjacent pair of terminals. Turning to the fourth array 88, a first groove 126 and a second groove 128 are respectively defined between a first terminal 104 and a second terminal 106 and between the second terminal 106 and a third terminal 108. Thus, similar to the third array 86, although the grooves do not extend between each adjacent pair of terminals, the grooves are defined between each adjacent pair of terminals.

[0110] Briefly referring to the first terminal 94 of the second array 84, as described above, the terminal 94 includes a pad 94a and a flank 94b. However, it should be understood that the flank 94b extends along the corresponding second side 76 over a greater extent than the pad 94a. This also applies to each of the terminals in the four-sided configuration shown (although in other embodiments, this may not be the case). It is noted that the protrusions 114, 120 do not include the corresponding pads, so they refer to the protrusions rather than the terminals.

[0111] Turning to Figure 6 a plan view of the underside of the semiconductor package 70 is provided.

[0112] Turning to Figure 7 a perspective view of a lead frame 140 according to an embodiment of the present invention is provided. Generally set from the underside of the lead frame 140 Figure 7 .

[0113] The lead frame 140 is generally a planar plate, on which various protruding features are formed, preferably made of copper or a copper alloy. The lead frame 140 can be manufactured by chemical etching, stamping or other processes.

[0114] As Figure 7As shown, lead frame 140 defines a die pad array. Each die pad further defines and forms part of a corresponding semiconductor package. As Figure 7 shown, the first die pad is labeled 4, and the second, third, and fourth die pads are labeled 142, 144, and 146, respectively. In Figure 7 , a boundary is schematically indicated using a dashed line, which indicates the coverage area of the first die pad 4 and the second die pad 142. By comparing Figure 7 with Figure 2 , it can be understood that the upper terminal array shown for die pad 4 corresponds to the first terminal array 10 in Figure 2 . Similarly, the lower terminal array corresponds to the second terminal array 12. As described in connection with Figure 2 , the first terminal array 10 is disposed along the first side 26 of die pad 4, while the terminal array 12 is disposed along the second side 28 of die pad.

[0115] Corresponding connecting bars extend between the terminals of each terminal array (e.g., 10, 12). The first connecting bar 148 includes a first portion 148a and a second portion 148b. The first connecting bar 148 electrically connects each of the first terminal 14, the second terminal 16, and the third terminal 18 that form part of the first terminal array 10. It is noted that the connecting bar (e.g., the first connecting bar 148) is defined by the boundary of the die pad / semiconductor package (e.g., defined by the dashed line that defines die pad 4). The first portion 148a and the second portion 148b can be described as the extent of the first connecting bar 148 that extends directly between adjacent terminals. That is, the first portion 148a and the second portion 148b have the shortest possible length while still extending between adjacent terminals. For example, a U-shaped connecting bar or a portion thereof is not considered to extend directly between adjacent terminals.

[0116] In view of the above description of the first connecting bar 148 disposed on the first side 26 of die pad 4, a corresponding second connecting bar 150 is disposed on the opposite second side 28. The second connecting bar 150 extends between the first terminal 20, the second terminal 22, and the third terminal 24 of the second terminal array 12 and electrically couples the first terminal, the second terminal, and the third terminal of the second terminal array. The second connecting bar 150 includes a first portion 150a and a second portion 150b. The first portion 150a extends between the first terminal 20 and the second terminal 22. The second portion 150b extends between the second terminal 22 and the third terminal 24, respectively.

[0117] For the above reasons, the first connecting bar 148 and the second connecting bar 150 respectively couple and electrically connect each of the first terminal and the third terminal of each of the first array 10 and the second array 12. As will be described below in connection withFigure 8 Briefly described, each of the connecting rods 148, 150 also includes tabs extending from the ends of the connecting rods to effectively couple the connecting rods to adjacent connecting rods in a direction along the (longitudinal) extent of the connecting rods. Additionally, in the case where the die pads are provided with terminal arrays (e.g., the second array 12) and adjacent die pads (e.g., die pad 146) include adjacent terminal arrays, adjacent connecting rods (e.g., including 150) can be described as defining a fused connecting rod. In the example shown, the fused connecting rod extends between the second terminal array 12 on the first semiconductor package 4 and the (adjacent) first terminal array of the adjacent fourth semiconductor package 146.

[0118] By means of the connecting rods, each die pad is connected to a plurality of other adjacent die pads. Thus, the entire lead frame 140 is electrically connected. This is desirable because when the entire lead frame 140 is held at the same potential, metal plating of the pads and flanks of the terminals that occurs midway through the manufacturing process can take place. This makes it easier to perform the process compared to, for example, if each of the terminals were electrically isolated at this stage of the process (in which case each terminal would need to be independently connected to hold them at the same potential).

[0119] As will be described in detail in connection with the manufacturing process, the connecting rods are at least partially removed to electrically isolate the terminals from each other and singulate the adjacent die pads and thus the semiconductor packages from each other.

[0120] Turning to Figure 8 , an enlarged view of the isolated first die pad 4 is provided. It is noted that at the point where the semiconductor packages are singulated from the array during the manufacturing process, various other components (such as dies, leads, etc.) will be coupled to the die pad 4. Thus, during manufacturing, a singulated die pad (isolated) typically does not occur. However, it is included here Figure 8 to provide more description around the connecting rods.

[0121] First, it will be recalled that the first connecting rod 148 includes a first portion 148a and a second portion 148b. The first connecting rod 148 electrically connects the first terminal 14, the second terminal 16, and the third terminal 18 of the first array 10.

[0122] Similarly as described previously in connection with Figure 7 the Figure 8 shows the first tab 152 and the second tab 154 that form part of the first connecting rod 148. The first tab 152 and the second tab 154 do not extend between the terminals of the respective arrays, but rather between the terminals of adjacent but unfused terminal arrays. In other words, in Figure 7In this case, the tab of the first connecting rod 148 couples the first terminal 14 to an adjacent terminal of the second die pad 142, but these terminals are not melted or directly opposed in the same manner as, for example, the terminals of the second array 12 and the adjacent terminals of the fourth die pad 146. The tab may alternatively be described as a frame.

[0123] Return Figure 8 , as an example, also schematically indicates various portions of the connecting rod 148 for reference, and these portions will be removed during the manufacturing process. Labeled 156 is the first portion of the connecting rod 148, and this first portion is removed during a first removal operation (e.g., see Figures 12 to 14 ). By comparison Figure 8 and Figure 7 it can be understood that for a terminal array having adjacent opposing terminal arrays (e.g., such that the corresponding connecting rods define melted connecting rods), removing the portion 156 cuts off the melted connecting rods. Removing the first portion 156 also exposes the flanks of the connectors 14, 16, 18 (for metal plating).

[0124] In a subsequent step of the process, as Figures 16 to 18 shown, a second portion 158 of the connecting rod is removed by a second removal operation. Removing the second portion 158 (labeled in Figure 8 ) isolates the terminals 14, 16, 18 within each terminal array (e.g., 10), and also defines a groove between each isolated terminal (e.g., see the grooves 32, 34 shown in Figure 2 ). In some embodiments, the second removal operation may remove all of the connecting rods. However, in other embodiments, some connecting rods may remain even though they do not electrically couple adjacent terminals.

[0125] Figure 7 Another advantage of the design of the lead frame 140 in Figure 8 and the die pad 4 in

[0126] is that the thickened connecting rods (e.g., 148, 150) strengthen the lead frame structure, making the lead frame 140 and the component die pads more stable during the manufacturing process. For example, during the wire bonding step, the risk of damage is lower. Figure 8has a minimum thickness of 175 microns in the direction 160 schematically indicated. The range of the minimum thickness is marked as 162, and the minimum thickness is also defined between the connected terminals (in this case 20, 22). That is, in other embodiments, depending on the distance between adjacent terminals (e.g., for isolated terminals), the connecting rod can have a different thickness (e.g., less than 175 microns).

[0127] The dimension 162 can be described as determining the groove depth after the second removal operation occurs. The dimensions 164, 166 can be described as determining the groove width (e.g., between each isolated terminal). The minimum groove depth and minimum groove width are determined by the minimum distance required to isolate the terminals from each other after the second removal operation occurs.

[0128] Continuing to refer Figure 8 , as indicated along a portion of the connecting rod extending between the first terminal 20 and the second terminal 22 of the second array 12, the thickness 162 of the connecting rod 150 is marked as 164. It can be understood that a portion of the connecting rod 150 extends further beyond the range 162 in the direction of movement towards the second side 28 (e.g., between the terminal 20 and the second side 28). However, for ease of reference, only the range 164 is marked in connection with the first portion 158 of the second connecting rod 150 to provide a suggested dimension.

[0129] The inventors have advantageously found that a connecting rod 150 having a thickness (e.g., 162) of at least 175 microns (in the direction 160) between the connected terminals (e.g., between terminals 20, 22 as indicated by 164) is particularly advantageous for providing a lead frame 140 with improved rigidity and robustness. For the sake of clarity, the corresponding range of the second portion 150b of the second connecting rod 150 is marked as 166. According to the previous discussion, advantageously, the thickness 162 is at least 175 microns over the regions 164, 166 (for the second connecting rod 150), and it will be understood that given Figure 7 , this is repeated for all die pads in the lead frame array 140. Return Figure 8 , the range 164 also at least spans the range 168 of the groove 170, which is defined between the first portion 6 of the die pad 4 and the second connecting rod 150. Similarly, the second range 166 at least spans the range of the groove 174 extending between the second portion 8 of the die pad 4 and the second connecting rod 150. Nevertheless, in other embodiments, the connecting rod can have a thickness less than 175 microns. Briefly referring Figure 9 , the molten connecting rod, i.e., the combination of two adjacent connecting rods 150, 190, preferably has a minimum thickness 151 of 350 microns.

[0130] Although inFigure 8 There is no marking, but it should be understood that corresponding grooves and ranges exist between the first part 6 and the second part 8 and the first part 148a and the second part 148b of the first connecting rod 148. For example, the thickness of each part of the first part and the second part of the connecting rods 148a, 148b between the terminals is at least 175 micrometers, and this range at least covers the range where the grooves between the first die part 6 and the second die part 8 and the first connecting rod 150 extend.

[0131] Extending between the first connecting rod 148 and the second connecting rod 150 are a first member 176 and a second member 178. The first member 176 generally extends from the first connecting rod 148 at an end near the first terminal 14 to the second connecting rod 115 at an end near the first terminal 20. Described in another way, the first member 176 extends between the first connecting rod 148 and the first tabs 152, 180 of the second connecting rod 150. Similarly, the second member 178 extends between the second tabs 154, 182 of the first connecting rod 148 and the second connecting rod 150 respectively. The first member 178 defines a first side 42 of the die pad 4. The second member 178 defines a second side 44 of the die pad 4.

[0132] Brief reference Figure 1 , it will be recalled that after the semiconductor package 2 has been manufactured and singulated from the array, the first exposed portion to the third exposed portion 46a-c of the die pad are retained. Return Figure 8 , respectively indicating the same first exposed portion to the third exposed portion 46a-c with respect to the first tab 152, the first member 178, and the first tab 180. In other words, when the semiconductor package has been assembled and singulated, as part of the singulation process, a part of the tab 152, the first side member 178, and the first tab 180 are removed to leave the first exposed portion to the third exposed portion 46a-c. It should also be understood that the second exposed portion 46b forms a part of the bridge between the side member 178 and the first part 6 of the die pad 4, and the first part 6 is supported by this bridge. For completeness, a second bridge generally marked as 184 extends between the first part 6 and the second connecting rod 150 at the first terminal 20. A corresponding rotational arrangement is provided for the second part 8 of the die pad 4. When the semiconductor package is singulated, the first exposed portion, the second exposed portion, and the third exposed portion 186a-c will continue to be exposed on the fourth side 44 of the die pad 4. The first part 186a and the third part 186c are defined in the second tabs 154, 182, and the second exposed portion 186b is defined in the bridge extending between the second part 8 and the second member 178. Another bridge extending between the terminal 18 and the first part 8 is marked as 188.

[0133] Go toFigure 9 shows a top view of the top side of the lead frame 140. The first through fourth die pads 4, 142, 144, 146 that make up the lead frame 140 are marked again. As will be understood from Figure 7 it, the portions and terminals (e.g., Figure 7 the first array 10 and the second array 12 of 6, 8) that define the first and second portions of the die pad (e.g., Figure 7 are not visible in Figure 9 because these features generally protrude from the effective top side of the die pad / lead frame.

[0134] Since the first die pad 4 in the array is defined at the upper left side of the lead frame 140, as Figure 9 shown, it can be understood that for the first die pad 4, there are no adjacent die pads above (e.g., adjacent to the first connecting bar 148) and to the left (e.g., adjacent to the second member 178). However, there are two adjacent die pads on the lower side and the right side (e.g., adjacent to the second connecting bar 150 and the first member 176 respectively). They are the fourth die pad 146 and the second die pad 142 respectively.

[0135] Starting from the fourth die pad 146, as described above, the fourth die pad 146 is adjacent to the first die pad 4 and adjacent to the second connecting bar 150. The fourth die pad 146 is identical in geometry to the first die pad 4. Accordingly, although not described in detail here, the fourth die pad 146 includes the first connecting bar 190. Given that the second connecting bar 150 of the first die pad 4 and the first connecting bar 190 of the fourth die pad 146 are connected as Figure 9 shown, this combination can be described as a fused connecting bar. In other words, this combination can be described as a pair of fused connecting bars. As will be described in connection with Figures 12 to 14 in the first removal operation of the manufacturing process, the first part of the fused encapsulant and the first part of the connecting bars 150, 190 (among the other connecting bars in the array) are removed. This exposes the flanks of the corresponding terminals. This cuts off the fused connecting bars.

[0136] Turning to describe the second die pad 142, as described above, the second die pad 142 surrounds the first member 176 and is adjacent to the first die pad 4. The second die pad 142 includes the corresponding second member 192. Similar to the connecting bars 150, 190, the second member 176 of the first die pad 4 and the first member 192 of the second die pad 142 are joined as Figure 9 shown. As will be described in connection with the following figures, in the singulation step of this process, in order to separate the semiconductor package from the array, the first member 176 and the second member 192 (among the other die pads on the array) are removed respectively.

[0137] Figure 9 Figure 9 also shows cavities defined between groups of four die pads. The cavities are labeled 194, 196, 198, 200. Taking cavity 194 as an example, the cavity is defined between the first die pad 144, the second die pad 142, the fourth die pad 146, and the fifth die pad 193. Advantageously, the incorporation of the cavities reduces the amount of material required to manufacture the lead frame 140 without adversely affecting the robustness in these areas.

[0138]

[0138] In addition to cavities 194, 196, 198, 200, a solid perimeter of material extends around each die pad that forms part of the array 140. Taking the first die pad 4 as an example, the solid perimeter is defined by the first connecting rod 148 and the second connecting rod 150, as well as the first member 176 and the second member 178.

[0139] Turning to Figure 10 , a perspective view of subsequent steps of the manufacturing process is provided. Figure 10 Figure 10 Corresponds to steps in a method of manufacturing a batch of semiconductor packages, where multiple dies are coupled to multiple die pads, and each die pad defines a corresponding semiconductor package.

[0140] Taking the first die pad 4 as an example, Figure 10 Figure 10 shows steps of the manufacturing process in which a first die portion 50 and a second die portion 52 are respectively coupled to a first portion 6 and a second portion 8 of the die pad 4. As previously described, the first portion 50 and the second portion 52 of the die can be considered to constitute the die itself. In other embodiments, the die can consist of a single piece. Similarly, different from the first portion 6 and the second portion 8 in this embodiment, the die pad can include only a single portion.

[0141] Die portions 50, 52 are attached to corresponding portions 6, 8 of die pad 4 via a bonding process, such as via a solder layer. Other processes may be employed. After attachment of die portions 50, 52, die portions 50, 52 are coupled to corresponding terminals. This coupling may alternatively be described as an electrical connection. Taking the first die portion 50 as an example, the first die portion 50 is coupled to the first terminal 14 via wire 56 and to the second terminal 16 via wire 58 (terminals 14, 16 form part of a first terminal array). The electrical connections between the first die portion 50 and terminals 14, 16 are formed via a wire bonding process. However, in other embodiments, rigid connectors may alternatively be used to couple the die portions to the terminals. A corresponding arrangement is provided for the second die portion 52, but for brevity it is not described herein. Given that the first die portion 50 and the second die portion 52 are described as a set of dies, the entire die (e.g., die portions 50 and 52) may be considered to be coupled to the terminals on each of the first terminal array and the second terminal array (e.g., on either side of die pad 4). Although in fact the first die portion 50 is taken as an example, the first die portion 50 is only electrically connected to the terminals forming part of the first array.

[0142] Although corresponding descriptions will not be provided for each of the other individual die pads (e.g., the second to fourth die pads 142, 144, 146), the above description equally applies to each of these die pads, and in fact all of the other die pads form part of an array (a 3×3 array in the illustrated embodiment). For the avoidance of doubt, as Figure 9 shown, the die is coupled to the top side of the lead frame 114. Figure 10 The underside of the lead frame 140 array is visible, which shows some of the blocks defining the terminals.

[0143] As previously described, in some embodiments, the die or die portion may be directly coupled to the terminal. That is, the terminal may form part of the die pad to which the die or die portion is coupled. In such embodiments, the coupling of the die or die portion to the terminal may constitute the die pad coupling and terminal connection steps. In other words, coupling the die or die portion to the terminal may both: i) couple the die or die portion to the die pad; and ii) attach (e.g., electrically couple) the die or die portion to the terminal.

[0144] Turning to Figure 11 , a perspective view of a partially assembled batch of semiconductor packages in a subsequent step of the manufacturing process is shown. Relative to Figure 10 , in Figure 11 , a molten encapsulant 202 is disposed over the plurality of partially assembled semiconductor packages. The molten encapsulant 202 partially surrounds the array 140.

[0145] As will be understood by comparing Figure 11 with Figure 19 it will be understood that what is referred to as the fused encapsulant 202 is so called because during the singulation step of the manufacturing process, a portion of the fused encapsulant 202 is removed along with a portion of the lead frame array 140 to singulate the semiconductor packages. In so doing, an encapsulant is defined for each individual semiconductor package (e.g., Figure 1 28 as shown). Thus, the fused encapsulant as used herein refers to a solid block of encapsulant that will subsequently be divided into individual component encapsulants. In short, in Figure 11 such as using an injection molding process, an encapsulant block, such as a polymer, is molded over and around the partially assembled array. In Figure 11 a partially transparent view of the fused encapsulant 202 is shown because if it were not a partially transparent view, most of the components forming part of the partially assembled array would be obscured.

[0146] Turning to Figure 12 a perspective view of the partially assembled array of semiconductor packages is provided in a subsequent manufacturing step. Compared with Figure 11 wherein the fused encapsulant 202 is provided as a solid block, in Figure 12 a first portion of the fused encapsulant 202 and a first portion of the connecting bar are removed by a first removal operation. This operation exposes the flanks of the terminals while the terminals still remain electrically connected to each other to facilitate a plating process.

[0147] It is also worth noting that Figure 12 the orientation of the array in Figure 11 is flipped relative to the orientation shown in Figure 11 That is to say, while Figure 11 generally shows the top side of the array 140, Figure 12 generally shows the bottom side (e.g., the terminals are visible). Thus, Figure 12 the orientation of the array 140 shown in Figure 7 corresponds to the orientation shown in

[0148] Referring to Figure 12 as previously described, Figure 12 shows the partially assembled array after the first portion of the fused encapsulant 202 and the first portion of the connecting bar have been removed. Taking the first die pad / semiconductor package 4 as an example, the first portion of the fused encapsulant 202 and the connecting bar are generally labeled 204, 206 respectively. This is also shown in Figure 13 and Figure 14 and will be described in conjunction with these figures.

[0149] Briefly returning to Figure 12, removing the first portions 204, 206 of the molten encapsulant 202 and the connecting rods (the first connecting rod is not visible in Figure 12 but the second connecting rod is labeled 150) exposes the flanks of the respective terminals while still leaving each of the terminals in the terminal electrically connected to each other. Taking the first through third terminals 20, 22, 24 as an example, it will be recalled that these terminals form part of a second terminal array. Even after removing the first portion 206, the first through third terminals 20, 22, 24 remain electrically connected to each other through the second connecting rod 150. However, similarly, for example, by comparing Figure 12 with Figure 9 , Figure 10 or Figure 11 , it can be understood that a portion of the connecting rod 150 is also removed. Although shown together with the first connecting rod 148, the first portion removed from the connecting rod is labeled 156 in Figure 8 . Thus, the first removal operation can be described as including removing material in a plurality of discontinuous elongated regions. For example, generally in a dashed line manner.

[0150] Briefly, each of the terminals in the terminal defines a pad and a flank. Taking the first terminal 20 as an example, the pad is labeled 20a and the flank 20b. The flank 20b defines the thickness of the terminal 20, and the flank 20b is exposed in the first removal operation already performed in Figure 12 . In Figure 7 , a portion of the second connecting rod 150 extends beyond the flank (e.g., toward the fourth die pad 146). Thus, in the step shown in Figure 11 (if not for the subsequent first removal operation), the flank of the terminal 20a will not be exposed after the molten encapsulant 202 is molded.

[0151] It is noted that after the first removal operation has occurred, the molten encapsulant 202 still extends between all of the die pads / semiconductor packages of the die pads / semiconductor packages forming part of the array 140 because the first portions removed are actually discontinuous. In other words, the array 140 can still operate as a single coupled component. The material removal operation can be performed by one or more laser cutting, water jetting, sawing, or chemical etching processes. Given the combination of the encapsulant material (e.g., polymer) and at least a portion of the lead frame 140 to be removed, these are desirable removable processes for the material mixture present in the partially assembled array. Laser cutting is particularly advantageous due to the reduced risk of encapsulant delamination.

[0152] It is noted that although the removal of the first portions of the materials 204, 206 has been described only in connection with the first die pad 4, but from Figure 12It can be understood that a first portion of corresponding material is removed from each die pad / semiconductor package of the die pads / semiconductor packages forming part of the array 140, and terminals are disposed along the first opposite side and the second opposite side.

[0153] Go to Figure 13 , there is provided Figure 12 a plan view of the underside of the partially assembled array shown. It should be noted that the orientation has been rotated with respect to Figure 12 the orientation shown such that the first die pad 4 corresponds to Figure 13 the lower left corner in

[0154] Figure 13 Schematically indicated are first portions 204, 206 of the molten encapsulant and connecting rods associated with the first die pad 4 removed in the first removal operation. Thus, removing these first portions 204, 206 leaves grooves adjacent to the first terminal array and the second terminal array (the first array includes terminals 14, 16, 18 and the second array includes terminals 20, 22, 24). For ease of understanding, another first portion 208 associated with the fourth die pad / semiconductor package 146 is also schematically indicated. Thus, it should be understood that the combination of the first portions 206, 208 defines a single cavity and the removal of the first portions 206, 208 occurs in a single removal step.

[0155] Go to the brief description Figure 14 , again showing Figure 13 the partially assembled array shown, but showing the molten encapsulant 202 in a partially transparent manner. Although the first portions 204, 206, 208 of the material removed in the first removal step are again annotated, different markings are used for ease of visibility. As Figure 14 shown, although not marked, the flanks and pads of each terminal are exposed. This is ready for a plating process in which a metal layer is provided to improve the solderability of these features. For the avoidance of doubt, in Figure 14 , cavities 210, 212, 214, 216 and 218 are also defined in the first material removal step. The cavities extending around the outer die pads in the array (e.g., the cavity defined by the first portion 204 connected to the die pad 4) are not marked. It can be understood from Figure 14 that the first removal operation may include a series of removal steps. For example, material may first be removed from the area adjacent to the first die pad 4 and then from the area adjacent to the second die pad etc.

[0156] In direction 160 (eg, in a plane parallel to the first and second directions), the extent of material removed by the first removal operation (ie, first portion 204, among others) is labeled 161. Dimension 161 is preferably about 75 microns.

[0157] Go to Figure 15 , provides Figures 12 to 14 A perspective view of a partially assembled array in a manufacturing step subsequent to the step shown. Figure 14 In the process, a coating process is performed. The coating process can be, for example, a metal coating process, such as tin plating. A chemical cleaning step also preferably occurs in the same step.

[0158] By comparison Figure 12 and Figure 15 , it will be appreciated that the exposed portions of the die pads (e.g., the terminals, the first portion 6 and the second portion 8, the connecting rods) have been plated. The plating process applies a metal layer to these portions of the lead frame, which greatly improves the adhesion of the solder to these features. It is noteworthy that the exposed portions of the connecting rods (e.g., the second connecting rod 150 for the first die pad 4, where the corresponding first connecting rod is not visible) are also plated as part of the process. It will be recalled that while the plating process is occurring, all of the die pads forming part of the array 140 remain electrically connected to each other. That is, all of the terminals in the terminals are also electrically connected to each other. Therefore, the entire array 140 can be easily maintained at the same potential to facilitate the plating process. Described in another way, it is not necessary to electrically connect each independent exposed portion of the lead frame 140 to plate the features separately. Instead, the entire array of partially assembled semiconductor packages can be uniformly provided at the necessary potential, and then the entire combined batch of partially assembled semiconductor packages can be plated simultaneously. It should be understood that any exposed edges / features (e.g., Figure 8 Portions of the first component 176 and the second component 178 shown are plated as part of the plating process.

[0159] Go to Figure 16 ,exist Figure 15 A partially assembled semiconductor package array 140 is shown in the subsequent manufacturing steps shown.

[0160] By comparison Figure 15 and Figure 16 Understandably, Figure 16 , the second portion of the molten encapsulant and the second portion of the tie bar have been removed by a second removal operation. This removal step isolates the terminals within each terminal array and also defines a groove between each isolated terminal of each terminal array. Referring to the first die pad / semiconductor package 4, in particular the first to third terminals 20, 22, 24, by comparison Figure 15 andFigure 16 , it can be understood that the exposed portion of the (second) connecting rod 150 has been removed in Figure 16 . Figure 15 In this way, in the case where the exposed portion of the connecting rod 150 is the only direct electrical coupling between adjacent terminals, each of the terminals 20, 22, 24 forming part of the second terminal array is electrically isolated from each other in Figure 16 .

[0161] Although not marked in conjunction with Figure 16 , the second portion of the removed material corresponds to the second portion marked as 158 in Figure 8 (although Figure 8 only shows the second portion in conjunction with the second connecting rod 150). In this way, given that the first portion 156 was removed in the previous step, the mesh geometries 156, 158 have now been effectively removed from the die pad 4 (and in fact, the rest of the semiconductor package, e.g., also including the fused encapsulation in these areas). Similarly, although described only in conjunction with the first die pad 4, this description equally applies to all die pads / partially assembled semiconductor packages forming part of the array 140. It is worth noting that although the second portion was removed in the second removal operation step, the fused encapsulation 208 still extends between all the semiconductor packages such that they also remain coupled to each other as part of the array 140.

[0162] Moving on to Figure 17 , a plan view of the underside of the partially assembled semiconductor package array shown in Figure 16 is provided. In Figure 17 , the second portions 220, 222 are generally marked, which are adjacent to the first and second terminal arrays of the first semiconductor package 4, respectively. The corresponding second portion is marked as 224, corresponding to the fourth semiconductor package 146, adjacent to the first set of terminals. Although not marked in Figure 17 for ease of reference, it should be understood that the removal of the second portions 220, 222 defines the first to fourth grooves 32, 34, 36, 38 (e.g., as shown in Figure 1 and Figure 2 ). Therefore, it can be considered that the cavities defined between adjacent semiconductor packages increase in size in this step (e.g., the cavities 210, 212 shown in Figure 14 increase the coverage area of the grooves 32, 34, etc. shown in Figure 1 and Figure 2 ).

[0163] Moving on to Figure 18 , a plan view of the underside corresponding to the partially assembled array 140 shown in Figure 17 is provided again. However, inFigure 18 In [the figure], the molten encapsulant 202 is shown in a partially transparent view.

[0164] Figure 18 It is included to show the electrical connection or lack of electrical connection between the respective terminals. Referring to the first semiconductor package 4, the first terminal 14 and the second terminal 16 are now electrically isolated from each other. For completeness, note that the wires 56, 58 extend between the first terminal 14 and the second terminal 16 to the corresponding die portions and thus to the first portion 6 of the die pad 4. However, the electrical isolation here is intended to mean the lack of a direct electrical connection through a connecting rod between the terminals. Similarly, the first terminal 16 and the second terminal 18 are electrically isolated from each other.

[0165] Turning to the second array of terminals 20, 22, 24, the first terminal 20 and the second terminal 22 are electrically isolated from each other. Due to the lack of a connecting rod, the second terminal 22 and the third terminal 24 are also electrically isolated from each other. That is, again note that the wires 60, 62 connect the terminals to the die pad portion 8 via the die portion 8. It is also worth noting that due to the lack of electrical connection between the second terminal 16 and the third terminal 18 of the first array and the first terminal 20 and the second terminal 22 of the second array, each of the first and second portions of the die pads 6, 8 is electrically isolated from each other at this point. Advantageously, this means that separate die portions can effectively house multiple semiconductor devices in a single package.

[0166] The first terminals 14, 20 of the first and second arrays are still electrically connected to each other by means of a first member 176 respectively. Similarly, the third terminal 18 of the first array and the third terminal 24 of the second array are still electrically connected to each other by means of a second member 178. From Figure 19 it can be understood that in subsequent manufacturing steps, the first and second members are removed to electrically isolate these terminals from each other.

[0167] Although not described in connection with all the die pads and semiconductor packages in the array and other die pads and semiconductor packages not forming part of the array, the above description equally applies to all the die pads / semiconductor packages in the other die pads / semiconductor packages in the array 140. As Figure 18 shown, in a subsequent singulation step, in which the semiconductor package is separated from the array 140, the molten encapsulant 202 and more generally the array are cut at a plurality of locations labeled 226, 228, 230, 232. These cut locations separate the semiconductor package from the array and can be described as removing a third portion of the material (e.g., the die pads and the molten encapsulant) in a third removal operation. In this step, the members 176, 178 (among other things) are removed while the remaining molten encapsulant couples adjacent semiconductor packages that were previously coupled by molten connecting rods. From Figure 18The arrayed diced semiconductor packages shown result in Figure 19 the singulated (i.e., “completed”) semiconductor packages shown.

[0168] The singulation steps corresponding to the dicing lines 226, 228, 230, 232 can be performed by combining the same dicing methods described in the first part and the second part. That is, one or more of laser dicing, water jetting, sawing, or chemical etching processes can be used. When performing this singulation step, and with reference to this first package: also the first component 176 and the second component 178 are removed, the joint pieces that previously electrically connected adjacent connecting rods, even at Figure 18 the stage shown (between the first semiconductor package 4 and the second semiconductor package 142 - see Figure 8 152, 180 in) are also diced. Thus, as desired, the singulation step dices the molten encapsulant 220 and a part of the die pads to separate and electrically isolate the different semiconductor packages from each other.

[0169] For completeness, the thickness or extent of the material removed in the second removal operation along the direction 160 (e.g., to form a groove) is labeled 225. The thickness 225 is preferably about 100 microns. This can alternatively be described as removing material in a plane parallel to the first direction and the second direction.

[0170] Briefly turning to Figure 19 , a perspective view of the singulated semiconductor packages after the singulation step is schematically indicated in Figure 18 . For ease of reference, the first semiconductor package through the fourth semiconductor package retain their reference numerals 4, 142, 144, 146. However, reference numerals are added for the fifth semiconductor package 234, the sixth semiconductor package 236, the seventh semiconductor package 238, the eighth semiconductor package 240, and the ninth semiconductor package 22. It should be understood that although nine semiconductor packages in a three - by - three array have been described, any different number of semiconductor packages can be assembled in a batch using this process.

[0171] In addition, although two - side - configured semiconductor packages (e.g., two arrays having three terminals) are shown throughout the illustrated embodiments, in other embodiments, a different number of terminals can alternatively be used. Similarly, although the method has been described in detail for a two - side configuration, the same method can also be used to manufacture a four - side configuration similar to Figure 5 and Figure 6 shown. Briefly referring to Figure 8 , for the die pads of the four - side configuration, the members 176, 178 are more similar to the geometry of the die pad 4 at the first side 26 and the second side 28. In other words, an array of terminals and associated connecting rods are provided in place of the relatively thin first member 176 and second member 178. AsFigure 12 As shown forwardly herein, the modification to the process will include removing the molten encapsulant and the first portion of the connecting rod, and will also include removing material in the Figure 12 substantially vertical direction shown (e.g., between the first semiconductor package 4 and the second semiconductor package 142, between the second semiconductor package 142 and the third semiconductor package 144, etc.). However, the semiconductor packages will remain electrically connected to each other, and the molten encapsulant couples the semiconductor packages in a manner similar to that shown between the first semiconductor package 4 and the second semiconductor package 146.

[0172] The connecting rod described herein can be described as part of a terminal lead array. The connecting rod can be thicker (e.g., deeper) than the terminals.

[0173] Advantageously, the present invention described herein can be applied to any package having three or more terminals on each (occupied) side. The present invention can be applied to any leadless package (e.g., a package in which the terminals do not form part of an elongated lead protruding from the encapsulant). Advantageously, the present invention can be used in conjunction with terminals having a micro-pitch of approximately 0.3 mm (e.g., the spacing therebetween).

Claims

1. A semiconductor package for a printed circuit board (PCB), the semiconductor package comprising: Die pad; a die coupled to the die pad; a plurality of terminals electrically connected to the die, the plurality of terminals comprising a first array of terminals disposed along a first side of the semiconductor package and a second array of terminals disposed along a second side of the semiconductor package, wherein the second side is opposite the first side, each of the plurality of terminals comprising a pad having flanks; as well as an encapsulant at least partially surrounding the die; in A groove is defined between each terminal of each of the first array of terminals and the second array of terminals. 2 . The semiconductor package of claim 1 , wherein each pad and wing are exposed through the encapsulant. 3 . The semiconductor package according to claim 1 , wherein each groove is a stepped groove.

4. A semiconductor package according to any preceding claim, wherein each recess extends from a first terminal of the adjacent pair of terminals to a second terminal of the adjacent pair of terminals.

5. A semiconductor package according to any preceding claim, wherein one or more of the terminals comprises a metallization extending at least partially through the pad and the flank.

6. The semiconductor package of any preceding claim, wherein the plurality of terminals further comprises a third terminal array disposed along a third side of the semiconductor package, and a fourth terminal array disposed along a fourth side of the semiconductor package, wherein the fourth side is opposite to the third side.

7. A semiconductor package according to any preceding claim, wherein the thickness of the flanks is equal to the thickness of the terminal.

8. A method for manufacturing a batch of semiconductor packages, the method comprising: coupling a plurality of dies to a plurality of die pads, the plurality of die pads being arranged in an array on a lead frame, wherein each die pad defines a corresponding semiconductor package, and coupling the plurality of dies to a plurality of terminals on the plurality of die pads, the terminals corresponding to each die pad comprising at least a first terminal array arranged along a first side of each semiconductor package, and a second terminal array arranged along a second side of the semiconductor package, wherein the second side is opposite to the first side; disposing a fused encapsulant on the plurality of semiconductor packages, the fused encapsulant at least partially surrounding the array; removing, by a first removal operation, a first portion of the molten encapsulant and a first portion of a tie bar of the lead frame extending between terminals of a corresponding terminal array of each semiconductor package to expose flanks of the terminals while the terminals remain electrically connected to each other; Plating at least a portion of the pad using a plating process, the at least a portion of the pad including at least a portion of the exposed flank; removing a second portion of the molten envelope and a second portion of the tie bar by a second removal operation to isolate the terminals within each terminal array and define a groove between each isolated terminal of each terminal array of the first terminal array and the second terminal array; as well as The molten encapsulant is cut at a plurality of locations to singulate the semiconductor packages from the array.

9. The method of claim 8, wherein removing the second portion of the connecting rod comprises removing a remaining portion of the connecting rod.

10. The method of claim 8 or 9, wherein one or more of the first removal operation and the second removal operation comprises one or more of a laser cutting, water jetting, sawing or chemical etching process.

11. The method of any one of claims 8 to 10, wherein coupling the plurality of dies to the plurality of terminals comprises using a wire bonding process.

12. The method of any one of claims 8 to 11, wherein removing the first portion of the tie bar comprises severing a fused tie bar extending between the second terminal array of a first semiconductor package and the first terminal array of an adjacent second semiconductor package.

13. A method according to any one of claims 8 to 12, wherein the first removal operation comprises removing material in a plurality of discontinuous elongated regions.

14. The method according to any one of claims 8 to 13, wherein the plurality of die pads further comprises a third terminal array disposed along a third side of each semiconductor package, and a fourth terminal array disposed along a fourth side of each semiconductor package, wherein the fourth side is opposite to the third side.

15. A lead frame for manufacturing a semiconductor package, the lead frame comprising: a die pad array, wherein each die pad defines a corresponding semiconductor package; a plurality of terminals disposed around each die pad, each plurality of terminals comprising a first array of terminals disposed along a first side of the die pad and a second array of terminals disposed along a second side of the die pad, wherein the second side is opposite to the first side, each of the plurality of terminals comprising a pad having flanks; wherein the terminals in each first terminal array are electrically connected to each other via a first connecting rod, the first connecting rod extending directly between the terminals; wherein the terminals in each second terminal array are electrically connected to each other via a second connecting rod, the second connecting rod extending directly between the terminals; Adjacent die pads are electrically connected to each other through one or more of the first connecting bar and the second connecting bar.

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