Method and apparatus for sensing a stamper motor load variation

Abstract

The invention relates to a method and an apparatus for sensing a stepping motor load change. An example apparatus includes current driver circuitry (150) configured to supply power to a stepping motor (125); and controller circuitry (155) coupled to the current driver circuitry (150), the controller circuitry (155) configured to: determine a first duty cycle (945) of power delivered to the stepping motor by the current driver circuitry during a first operation of the stepping motor, the first operation supplies power using a current of a target amplitude; determining a previous duty cycle of power delivered to the stepping motor by the current driver circuitry during a second operation of the stepping motor (965), the second operation of the stepping motor using a current supply power of the target amplitude; and determining a change in a mechanical load applied to the stepping motor in response to a comparison of the first duty cycle and the previous duty cycle.

Description

Technical Field

[0001] This specification generally relates to motor control, and more particularly, to methods and apparatus for sensing changes in the load of a stepper motor. Background Art

[0002] Electric motors are becoming increasingly common and complex. An electric motor converts electrical energy into mechanical energy for driving various operations. In an electric vehicle (EV), the mechanical energy from one or more electric motors causes the EV to accelerate. In manufacturing, the mechanical energy from one or more electric motors drives manufacturing operations. A common type of electric motor is a stepper motor. Some systems utilize stepper motors to achieve precise position control. For example, medical systems require precise sequencing of the position of a motor to control the supply of mechanical energy. Summary of the Invention

[0003] For a method and apparatus for sensing changes in the load of a stepper motor, an example apparatus includes: a current driver circuitry configured to supply power to a stepper motor; and a controller circuitry coupled to the current driver circuitry, the controller circuitry being configured to: determine a first duty cycle of power transmitted by the current driver circuitry to the stepper motor during a first operation of the stepper motor, the first operation supplying power using a current of a target magnitude; determine a previous duty cycle of power transmitted by the current driver circuitry to the stepper motor during a second operation of the stepper motor, the second operation of the stepper motor supplying power using the current of the target magnitude; and in response to a comparison of the first duty cycle and the previous duty cycle, determine a change in a mechanical load applied to the stepper motor. Brief Description of the Drawings

[0004] Figure 1 is a block diagram of an example motor system including a driver circuitry that supplies power to a stepper motor using a current driver circuitry and a controller circuitry.

[0005] Figure 2 is Figure 1 a block diagram of an example motor system.

[0006] Figure 3 is Figure 1 and 2 a schematic diagram of an example of the current driver circuitry of.

[0007] Figure 4 is Figure 1 and 2 a timing diagram of an example operation of the driver circuitry of.

[0008] Figure 5 is Figure 1 and2 Timing diagram of an example operation of a driver circuit system.

[0009] Figure 6 is Figure 1 and 2 Block diagram of an example of a controller circuit system of Figure 1 and 2 where an example step duty cycle monitor circuit system is used to detect

[0010] Figure 7 is Figure 6 Timing diagram of an example windowing operation of a step duty cycle monitor circuit system of

[0011] Figure 8 is Figure 6 Timing diagram of an example operation of a step duty cycle monitor circuit system of

[0012] Figure 9A and 9B form a flowchart representing example machine-readable instructions and / or example operations that can be implemented, instantiated, and / or executed using Figure 6 an example programmable circuit system implementation of a duty cycle monitor circuit system of Figure 1 , 2 and the controller circuit system 155 of 6 to implement, instantiate, and / or execute.

[0013] Figure 10 is a block diagram of an example processing platform that includes a programmable circuit system configured to implement, instantiate, and / or execute example machine-readable instructions and / or perform Figure 9A and 9B example operations of Figure 6 to implement the controller circuit system of

[0014] Figure 11 is Figure 10 Block diagram of an example implementation of a programmable circuit system of

[0015] Figure 12 is Figure 10 Block diagram of another example implementation of a programmable circuit system of

[0016] The same reference numerals or other reference indicators are used in the drawings to indicate features that are (functionally and / or structurally) the same or similar. Detailed Description

[0017] The figures are not necessarily drawn to scale. In general, like reference numerals in the figures and this specification refer to like or similar parts. Although the figures show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular.

[0018] Electric motors are becoming increasingly common and complex. An electric motor converts electrical energy into mechanical energy, such as rotation. One type of electric motor is a stepper motor. A stepper motor includes a shaft, a magnet, and multiple inductors (e.g., coils, windings, etc.). A drive circuit system supplies current to the stepper motor. When current is supplied, the inductors of the stepper motor cause the shaft to rotate by making the magnet change from a first position to a second position in response to the current from the drive circuit system. This change in the position of the magnet is due to the current flowing through the inductor creating a magnetic field that attracts and / or repels the magnet's polarity. The magnet is coupled to the shaft to cause the shaft to rotate in response to the rotation of the magnet. To rotate the magnet precisely, the drive circuit system sequences the power supplied to each inductor.

[0019] In some devices, the drive circuit system uses sine waves to sequence the power supplied to the inductors of the stepper motor. In such an application, the drive circuit system uses a first sine wave to supply power to a first inductor and a second sine wave to supply power to a second inductor. To sequence the rotation of the magnet, the drive circuit system generates the second sine wave as a phase-shifted version of the first sine wave. Ideally, the drive circuit system supplies a continuous-time sine wave to the inductor. However, a drive circuit system operating in discrete time cannot generate a continuous-time sine wave. Instead, the drive circuit system changes the current amplitude supplied to the inductor in a series of discrete steps. As the drive circuit system progresses through the series of steps, the change in the current amplitude resembles a sine wave. Although using a series of steps is an effective alternative to supplying power as a continuous-time sine wave, it is relatively complex to get the current through the inductor to reach a fixed value within a set step duration.

[0020] The drive circuit system includes a current drive circuit system and a controller circuit system. In some devices, the drive circuit system supplies current to one of the inductors of the stepper motor by setting the operating mode of the current drive circuit system. In such an application, the controller circuit system controls the operating mode of the current drive circuit system to achieve a target current. The current drive circuit system is capable of a drive operating mode, a fast decay operating mode, and a slow decay operating mode.

[0021] The controller circuit system adjusts the current driver circuit system to a drive operation mode to increase the current flowing through the inductor. In such instances, the current driver circuit system supplies current from a voltage source through the inductor. Thus, when in the drive operation mode, the current driver circuit system supplies power to the inductor. The controller circuit system maintains the current driver circuit system in the drive operation mode until the current through the inductor is approximately equal to the target current of a given step.

[0022] Once the current through the inductor is approximately equal to the target current, the controller circuit system adjusts the current driver circuit system to a slow decay operation mode or a fast decay operation mode. In the slow decay operation mode, the current driver circuit system allows the inductor to slowly release current. When in the slow decay operation mode, the current driver circuit system does not use current to supply power to the inductor.

[0023] In some operations such as when the target amplitude of a current is stepped down, the controller circuit system adjusts the current driver circuit system to achieve the fast decay mode. In the fast decay operation mode, the current driver circuit system supplies current in a direction opposite to the direction in which current was supplied during the drive operation mode. Thus, when in the fast decay mode, the current driver circuit system supplies power to the inductor. The fast decay operation mode allows the controller circuit system to decrease the current through the inductor at a decreasing rate greater than the slow decay mode.

[0024] The current driver circuit system includes a current sensing circuit system for determining the current flowing through the inductor of a stepper motor. The controller circuit system determines whether to modify the operation mode of the current driver circuit system in response to the current determined by the current sensing circuit system. In some applications, the controller circuit system adjusts the current driver circuit system to the fast decay operation mode to account for a decrease in current from the target current. In such an application, the controller circuit system switches the operation mode of the current driver circuit system to achieve the target current of a given step. The amplitude of the target current of any given step is determined in response to the constants of the stepper motor, the supply voltage of the current driver circuit system, the number of steps in a sine wave, and the peak current to be supplied.

[0025] Changes in the mechanical load applied to the stepper motor shaft change the power required to rotate the shaft. The controller circuitry can account for relatively small changes in the mechanical load by increasing the duration for which the current driver circuitry supplies power to the inductor. For example, the controller circuitry increases the duration in the drive operating mode. However, the controller circuitry may not account for relatively large changes in the mechanical load resulting from drive times that require a duration greater than each step. In such instances, the stepper motor may stall in response to an inability to supply sufficient power to create a magnetic field capable of causing motion. The stall condition also reduces the accuracy of the positioning information because any given step of the motor cannot be positioned. In embodiments such as medical and low speed applications where the positioning of the stepper motor is critical, changes in the mechanical load can substantially affect the operation of the device.

[0026] The examples described herein include methods and apparatus for sensing changes in a stepper motor load in response to a duty cycle of power delivered to the stepper motor for any given step. In some of the described examples, the driver circuitry includes a current driver circuitry and a controller circuitry. The current driver circuitry supplies power to the inductor of the stepper motor. The controller circuitry controls an operating mode of the current driver circuitry to cause a target current to pass through the inductor of the motor. The current driver circuitry provides a value representing the current supplied to the inductor by the current sensing circuitry to the controller circuitry. The controller circuitry determines an indexer coefficient using a total number of steps and a current step in a quarter cycle of a sine wave. The controller circuitry determines the target current using the indexer coefficient and a peak current.

[0027] The controller circuit system includes a duty cycle monitor circuit system for sensing changes in the mechanical load of a stepper motor using the power supplied to the current driver circuit system. The duty cycle monitor circuit system determines the duty cycle of the power delivered to a given inductance. The duty cycle is the duration, relative to the total time of a step, that the controller circuit system sets the current driver circuit system to be in either a drive mode or a fast decay mode. In some instances, the duty cycle monitor circuit system determines the duty cycle of one or more steps. The duty cycle monitor circuit system compares the duty cycle to a previous duty cycle under similar operating conditions. For example, the duty cycle monitor circuit system compares the duty cycle of the current one or more steps of the stepper motor to at least one previous duty cycle of a similar one or more steps. In response to the difference between the previously determined duty cycle and the current duty cycle, the duty cycle senses a change in the mechanical load applied to the stepper motor. The step duty cycle monitor circuit system increases the peak current of the sine wave to modify the supplied power to prevent stalling and maintain precise positioning of the shaft. Advantageously, the duty cycle monitor circuit system detects changes in the mechanical load within one or more steps of a given duty cycle. Advantageously, the controller circuit system can increase the power supplied to the stepper motor in response to detecting a change in the mechanical load.

[0028] Figure 1 FIG. 4 is a block diagram of an example motor system 100 that includes an example stepper motor 110 and an example driver circuit system 120. The stepper motor 110 is coupled to the driver circuit system 120. The stepper motor 110 converts electrical energy into mechanical energy. The driver circuit system 120 supplies power to the stepper motor 110.

[0029] In Figure 1 an example, the stepper motor 110 includes an example housing 125, a first example inductance (L A ) 130, a second example inductance (L B ) 135, an example magnet 140, and an example shaft 145. The stepper motor 110 receives power from the driver circuit system 120 through the inductances 130, 135. The stepper motor 110 converts electrical energy into mechanical energy by rotating the shaft 145 using the magnet 140. Herein, the term inductance is synonymous with an inductive element or inductor or conductor (such as a coil, winding, etc.) characterized by inductance. In some instances, the stepper motor 110 may include one or more additional inductances.

[0030] The driver circuit system 120 is coupled to the stepper motor 110. In Figure 1 an example, the driver circuit system 120 includes a first example current driver circuit system 150, an example controller circuit system 155, a second example current driver circuit system 160, and an example duty cycle monitor circuit system 165. The driver circuit system 120 provides a first current (IA ) and a second current (I B ).

[0031] The housing 125 encloses a portion of the inductors 130, 135, the magnet 140, and the shaft 145. The housing 125 is mechanically coupled to the inductors 130, 135. The housing 125 includes an opening for the shaft 145.

[0032] The inductors 130, 135 are electrically coupled to the driver circuitry 120. In operation, the inductors 130, 135 are magnetically coupled to the magnet 140. The inductors 130, 135 generate a magnetic field in response to a current from the driver circuitry 120. The magnetic field can be adjusted by the amplitude and the direction of the current supplied by the driver circuitry 120. For example, the first inductor 130 generates a first amplitude of magnetic field in response to a first amplitude of current from the driver circuitry 120. In such an instance, the first inductor 130 generates a second amplitude of magnetic field in response to a second amplitude of current from the driver circuitry 120. Advantageously, the driver circuitry 120 controls the magnetic fields of the inductors 130, 135.

[0033] The magnet 140 is coupled to the shaft 145. The magnet 140 is rotatable about the shaft 145. The magnet 140 has a north pole and a south pole (as Figure 2 shown). The inductors 130, 135 can attract and / or repel the magnetic poles of the magnet 140. In an example operation, the magnetic fields of the inductors 130, 135 cause rotation of the magnet 140 and the shaft 145 by attracting and repelling the magnetic poles of the magnet 140. The shaft 145 can be coupled to an external system (not shown). For example, the shaft 145 can be coupled to a wheel to accelerate a vehicle.

[0034] The first current driver circuitry 150 is coupled to the first inductor 130 and the controller circuitry 155. The first current driver circuitry 150 supplies a first current to the first inductor 130. The controller circuitry 155 controls the first current driver circuitry 150. The first current driver circuitry 150 can be adjusted to be in one of a drive operation mode, a slow decay operation mode, or a fast decay operation mode. When in the drive operation mode, the first current driver circuitry 150 supplies power to the first inductor 130 by increasing the first current. When in the slow decay operation mode, the first current driver circuitry 150 allows the first inductor 130 to release the magnetic field induced by the first current. When in the fast decay operation mode, the first current driver circuitry 150 supplies power to the first inductor 130 by driving the first current in a direction opposite to the current in the drive operation mode. An example of the first current driver circuitry 150 is shown and described in more detail below in Figure 3 .

[0035] The controller circuit system 155 is coupled to the current driver circuit systems 150 and 160. In Figure 1 an example, the controller circuit system 155 includes a duty cycle monitor circuit system 165. The controller circuit system 155 receives current measurements from the current driver circuit systems 150, 160. The controller circuit system 155 determines first and second currents supplied to the stepper motor 110 in response to the current measurements from the current driver circuit systems 150, 160. The controller circuit system 155 determines an indexer coefficient (K n ) using the number of identified steps (n) and the total number of steps in a portion of a sine wave (M) (e.g., a quadrant, a half cycle, etc.).

[0036] The controller circuit system 155 determines target currents (I 峰值 ) for the first and second currents in steps in response to a peak current (I n ) and the indexer coefficient. The controller circuit system 155 determines the operating modes of the current driver circuit systems 150, 160 by comparing the target currents with the determined first and second currents. In an example operation, the controller circuit system 155 modifies the operating modes of the current driver circuit systems 150 and 160 such that the determined first and second currents are approximately equal to the target currents. An example of the controller circuit system 155 is shown and described in more detail below in conjunction with Figure 6 .

[0037] The duty cycle monitor circuit system 165 determines a duty cycle for supplying power to the stepper motor 110. The duty cycle monitor circuit system 165 determines a drive duration (∑T on ), a fast decay duration (∑T fd ), and a total duration (∑T step ). The drive duration is an interval during which the controller circuit system 155 adjusts the total duration of the first current driver circuit system 150 for a drive operating mode. The fast decay duration is an interval during which the controller circuit system 155 adjusts the total duration of the first current driver circuit system 150 for a fast decay operating mode. The total duration is the total interval of one or more steps, including the drive duration, the fast decay duration, and a slow decay duration. The slow decay duration is an interval during which the controller circuit system 155 adjusts the total duration of the first current driver circuit system 150 for a slow decay operating mode. In some examples, the total duration is approximately equal to the interval of a single step. In other examples, the total duration is a multiple of the single step interval. The duty cycle monitor circuit system 165 determines that the duty cycle is approximately equal to the difference between the drive duration and the fast decay duration divided by the total duration. Advantageously, the duty cycle represents the duration of each step during which the first current driver circuit system 150 supplies power to the first inductor 130.

[0038] The duty cycle monitor circuitry 165 determines the duty cycle of each operation step and / or multiple operation steps. The duty cycle monitor circuitry 165 compares the determined duty cycle with a previous duty cycle of a similar operation. For example, the duty cycle monitor circuitry 165 can determine that the previous duty cycle is similar to the determined duty cycle in response to a similar magnitude of the target current. In such an instance, the duty cycle monitor circuitry 165 can compare the determined duty cycle with the previous duty cycle of a step of the target current having approximately the same magnitude. In some instances, the duty cycle monitor circuitry 165 uses a moving average of comparable previous duty cycles. In such an instance, the duty cycle monitor circuitry 165 averages the determined duty cycle with the previous average of the comparable previous duty cycles to update the average duty cycle.

[0039] The duty cycle monitor circuitry 165 determines a change in the mechanical load applied to the stepper motor 110 in response to a difference between the determined duty cycle and a comparable previous duty cycle. When the determined duty cycle is less than the comparable previous duty cycle, the duty cycle monitor circuitry 165 determines that the mechanical load of the stepper motor 110 has decreased. In such an instance, the decrease in the duty cycle is in response to a decrease in the load applied to the stepper motor 110. When the determined duty cycle is greater than the comparable previous duty cycle, the duty cycle monitor circuitry 165 determines that the mechanical load of the stepper motor 110 has increased. In such an instance, the increase in the duty cycle is in response to an increase in the load applied to the stepper motor 110. Examples of the duty cycle monitor circuitry 165 are further shown and described below in connection with Figure 6 Further shown and described is an example of the duty cycle monitor circuitry 165.

[0040] The second current driver circuitry 160 is coupled to the second inductor 135 and the controller circuitry 155. The second current driver circuitry 160 supplies a second current to the second inductor 135. The controller circuitry 155 controls the second current driver circuitry 160. The second current driver circuitry 160 can be adjusted to one of a drive operation mode, a slow decay operation mode, or a fast decay operation mode. The drive operation mode corresponds to adjusting the second current driver circuitry 160 to increase the second current (I B ). The slow decay operation mode corresponds to adjusting the second current driver circuitry 160 to allow the second inductor 135 to discharge the second current (I B ). The fast decay operation mode corresponds to adjusting the second current driver circuitry 160 to decrease the second current (I B ).

[0041] Figure 2 is Figure 1 a block diagram of an example motor system 100. InFigure 2 In an example of Figure 1 the magnet 140 has an exemplary south pole 210 and an exemplary north pole 220. In an exemplary operation, Figure 1 the drive circuit system 120 of Figure 1 causes the stepper motor 110 of Figure 1 to rotate by supplying power to the inductors 130, 135 of

[0042] In an exemplary operation, when the drive circuit system 120 supplies a current flowing in a first exemplary direction 230, the first inductor 130 generates a first magnetic field that attracts the north pole 220 and repels the south pole 210. In such an exemplary operation, when the drive circuit system 120 supplies a current flowing in a second exemplary direction 240, the first inductor 130 generates a second magnetic field that repels the north pole 220 and attracts the south pole 210. The drive circuit system 120 modifies the strength of the magnetic attraction and repulsion of the magnetic poles 210, 220 by modifying the magnitudes of the first and second currents from Figure 1 the current drive circuit systems 150, 160 of

[0043] In an exemplary operation, the drive circuit system 120 supplies the first and second currents as out-of-phase sinusoidal signals with a peak current (I 峰值 ) as the amplitude. Examples of the first and second currents are shown and described below in Figure 4 . In such an exemplary operation, the first and second currents cause the magnet 140 to rotate by attracting and repelling the magnetic poles 210, 220. However, a power loss due to the generation of a back electromotive force is in response to the rotation of the magnetic poles 210, 220. In some examples, the back electromotive force is a sinusoidal waveform similar to the supplied current, such as a phase-shifted sinusoidal waveform. The phase difference between the first current and the back electromotive force is called the load angle. The load angle characterizes the magnitude of the back electromotive force. Examples of the back electromotive force generated by the rotation of the magnet 140 are shown and described below in Figure 4 .

[0044] In an exemplary operation, when the stepper motor 110 rotates with a minimum mechanical load, the back electromotive force is maximum. Such an operation of the stepper motor 110 is called a no-load condition. Under such conditions, the magnetic poles 210, 220 rotate freely through the magnetic fields of the inductors 130, 135. In such an exemplary operation, the load angle is approximately 90°. In another exemplary operation, when the stepper motor 110 does not rotate due to an immovable mechanical load, the back electromotive force is minimum. Such an operation of the stepper motor 110 is called a stall condition. Under such conditions, the magnetic poles 210, 220 cannot rotate through the magnetic fields of the inductors 130, 135. In such an exemplary operation, the load angle is approximately 0°.

[0045] Figure 3 is Figure 1 and 2 schematic diagrams of examples of current driver circuit systems 150, 160. In Figure 3 example, the first current driver circuit system 150 includes a reference voltage terminal 305 that receives a reference voltage (V M ), a first example transistor 310, a first example current sensing circuit system 315, a second example transistor 320, a second example current sensing circuit system 325, a third example transistor 330, a third example current sensing circuit system 335, a fourth example transistor 340, a fourth example current sensing circuit system 345, and an example resistor 350. The reference voltage V M can be provided by a voltage source (not shown) of the system. In Figure 3 example, the first current driver circuit system 150 can be referred to as the current driver circuit system 150. The current driver circuit system 150 can be coupled to Figure 1 controller circuit system 155. The current driver circuit system 150 generates a current (I A ).

[0046] The first transistor 310 has a drain terminal (drain), a source terminal (source), and a gate terminal (gate). The drain terminal of the first transistor 310 is coupled to the reference voltage terminal 305 and the first current sensing circuit system 315. The source terminal of the first transistor 310 is coupled to the first current sensing circuit system 315, the second transistor 320, and can be coupled to Figure 1 and 2 first inductor 130. The gate terminal of the first transistor 310 is coupled to the first current sensing circuit system 315 and can be coupled to the controller circuit system 155. The first transistor 310 has a first example body diode 355. The first body diode 355 is coupled to the drain and source terminals of the first transistor 310. The first body diode 355 is a characteristic of the first transistor 310. In some examples, the first body diode 355 may not be shown.

[0047] The first current sensing circuit system 315 has a first input coupled to a reference voltage terminal 305. The first current sensing circuit system 315 has a second input coupled to the drain terminal of the first transistor 310. The first current sensing circuit system 315 has a third input coupled to the source terminal of the first transistor 310. The first current sensing circuit system 315 has a fourth input coupled to the gate terminal of the first transistor 310. The first current sensing circuit system 315 has an output that can be coupled to the controller circuit system 155. The first current sensing circuit system 315 determines a first current value indicative of the magnitude of the current flowing through the first transistor 310. The first current sensing circuit system 315 supplies the first current value at the output of the first current sensing circuit system 315. In some examples, the current sensing circuit systems 315, 325, 335, 345 are implemented using current sensing resistors, current sensing integrated circuits, Hall effect sensors, or any other suitable circuit system that can measure current.

[0048] In an example operation, the controller circuit system 155 controls the first transistor 310 by controlling the gate voltage at the gate terminal of the first transistor 310. The controller circuit system 155 turns on (e.g., conducts) and turns off (e.g., does not conduct) the first transistor 310 through the gate terminal of the first transistor 310. In such example operations, the first current sensing circuit system 315 determines the first current value (and / or determines a first current value indicative of the amount of current flowing through the first transistor) in response to the amount of current flowing through the first transistor 310. The first current sensing circuit system 315 supplies the first current value to the controller circuit system 155.

[0049] The second transistor 320 has a drain terminal, a source terminal, and a gate terminal. The drain terminal of the second transistor 320 is coupled to the first transistor 310, the second current sensing circuit system 325, and can be coupled to the first inductor 130. The source terminal of the second transistor 320 is coupled to the resistor 350. The gate terminal of the second transistor 320 is coupled to the second current sensing circuit system 325 and can be coupled to the controller circuit system 155. The second transistor 320 has a second example body diode 360. The second body diode 360 is coupled to the drain and source terminals of the second transistor 320. The second body diode 360 is a characteristic of the second transistor 320. In some examples, the second body diode 360 may not be shown.

[0050] The second current sensing circuit system 325 has a first input coupled to the reference voltage terminal 305. The second current sensing circuit system 325 has a second input coupled to the drain terminal of the second transistor 320. The second current sensing circuit system 325 has a third input coupled to the source terminal of the second transistor 320. The second current sensing circuit system 325 has a fourth input coupled to the gate terminal of the second transistor 320. The second current sensing circuit system 325 has an output that can be coupled to the controller circuit system 155. The second current sensing circuit system 325 determines a second current value representative of the magnitude of the current flowing through the second transistor 320. The second current sensing circuit system 325 supplies the second current value at the output of the second current sensing circuit system 325.

[0051] In an example operation, the controller circuit system 155 controls the second transistor 320 by controlling the gate voltage at the gate terminal of the second transistor 320. The controller circuit system 155 turns on (e.g., conducts) and turns off (e.g., does not conduct) the second transistor 320 via the gate terminal of the second transistor 320. In such example operations, the second current sensing circuit system 325 determines the second current value (and / or determines a second current value representative of the amount of current flowing through the second transistor) in response to the amount of current flowing through the second transistor 320. The second current sensing circuit system 325 supplies the second current value to the controller circuit system 155.

[0052] The third transistor 330 has a drain terminal, a source terminal, and a gate terminal. The drain terminal of the third transistor 330 is coupled to the reference voltage terminal 305 and the third current sensing circuit system 335. The source terminal of the third transistor 330 is coupled to the third current sensing circuit system 335, the fourth transistor 340, and can be coupled to the first inductor 130. The gate terminal of the third transistor 330 is coupled to the third current sensing circuit system 335 and can be coupled to the controller circuit system 155. The third transistor 330 has a third example body diode 365. The third body diode 365 is coupled to the drain and source terminals of the third transistor 330. The third body diode 365 is a characteristic of the third transistor 330. In some instances, the third body diode 365 may not be shown.

[0053] The third current sensing circuit system 335 has a first input coupled to a reference voltage terminal 305 that supplies a reference voltage. The third current sensing circuit system 335 has a second input coupled to the drain terminal of the third transistor 330. The third current sensing circuit system 335 has a third input coupled to the source terminal of the third transistor 330. The third current sensing circuit system 335 has a fourth input coupled to the gate terminal of the third transistor 330. The third current sensing circuit system 335 has an output that can be coupled to the controller circuit system 155. The third current sensing circuit system 335 determines a third current value representative of the magnitude of the current flowing through the third transistor 330. The third current sensing circuit system 335 provides the third current value at the output of the third current sensing circuit system 335.

[0054] In an example operation, the controller circuit system 155 controls the third transistor 330 by controlling the gate voltage at the gate terminal of the third transistor 330. The controller circuit system 155 turns on (e.g., conducts) and turns off (e.g., does not conduct) the third transistor 330 via the gate terminal of the third transistor 330. In such example operations, the third current sensing circuit system 335 uses the amount of current flowing through the third transistor 330 to determine the third current value (and / or determine a third current value representative of the amount of current flowing through the third transistor). The third current sensing circuit system 335 supplies the third current value to the controller circuit system 155.

[0055] The fourth transistor 340 has a drain terminal, a source terminal, and a gate terminal. The drain terminal of the fourth transistor 340 is coupled to the third transistor 330, the fourth current sensing circuit system 345, and can be coupled to the first inductor 130. The source terminal of the fourth transistor 340 is coupled to the resistor 350. The gate terminal of the fourth transistor 340 is coupled to the fourth current sensing circuit system 345 and can be coupled to the controller circuit system 155. The fourth transistor 340 has a fourth example body diode 370. The fourth body diode 370 is coupled to the drain and source terminals of the fourth transistor 340. The fourth body diode 370 is a characteristic of the fourth transistor 340. In some instances, the fourth body diode 370 may not be shown.

[0056] In Figure 3In an example, transistors 310, 320, 330, and 340 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 310, 320, 330, and 340 can be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), and / or slightly modified p-type equivalent devices. Transistors 310, 320, 330, and 340 can be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors. Additionally, transistors 310, 320, 330, and 340 can be implemented in / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0057] The fourth current sensing circuit system 345 has a first input coupled to a reference voltage terminal 305. The fourth current sensing circuit system 345 has a second input coupled to the drain terminal of the fourth transistor 340. The fourth current sensing circuit system 345 has a third input coupled to the source terminal of the fourth transistor 340. The fourth current sensing circuit system 345 has a fourth input coupled to the gate terminal of the fourth transistor 340. The fourth current sensing circuit system 345 has an output that can be coupled to the controller circuit system 155. The fourth current sensing circuit system 345 determines a fourth current value representative of the magnitude of the current flowing through the fourth transistor 340. The fourth current sensing circuit system 345 supplies the fourth current value at the output of the fourth current sensing circuit system 345.

[0058] In an example operation, the controller circuit system 155 controls the fourth transistor 340 by controlling the gate voltage at the gate terminal of the fourth transistor 340. The controller circuit system 155 turns on (e.g., conducts) and turns off (e.g., does not conduct) the fourth transistor 340 via the gate terminal of the fourth transistor 340. In such example operations, the fourth current sensing circuit system 345 uses the amount of current flowing through the fourth transistor 340 to determine the fourth current value (and / or determines a fourth current value representative of the amount of current flowing through the fourth transistor). The fourth current sensing circuit system 345 supplies the fourth current value to the controller circuit system 155.

[0059] Resistor 350 has a first terminal coupled to transistors 320 and 340. Resistor 350 has a second terminal coupled to a common terminal providing a common electrical potential (e.g., ground). In some examples, resistor 350 is referred to as a pull-down resistor. In such examples, resistor 350 provides a current path to the common electrical potential.

[0060] In an example operation, the controller circuitry 155 may adjust the current driver circuitry 150 to one of a drive operation mode, a fast decay operation mode, and a slow decay operation mode. When in the drive operation mode, the current driver circuitry 150 supplies a first current to the first inductor 130 using a first example current path 375. The first current path 375 allows current to flow from the reference voltage terminal 305 through the first transistor 310, the first inductor 130, the fourth transistor 340, and the resistor 350. When the current driver circuitry 150 is in the drive operation mode, the transistors 310, 340 are turned on, and the transistors 320, 330 are turned off. When in the drive operation mode, the current driver circuitry 150 supplies power to the first inductor 130 using current.

[0061] When in the fast decay operation mode, the current driver circuitry 150 supplies a first current to the first inductor 130 using a second example current path 380. The second current path 380 allows current to flow from the reference voltage terminal 305 through the third transistor 330, the first inductor 130, the second transistor 320, and the resistor 350. When the current driver circuitry 150 is in the fast decay operation mode, the transistors 320, 330 are turned on, and the transistors 310, 340 are turned off. When in the fast decay operation mode, the current driver circuitry 150 supplies power to the first inductor 130 using current.

[0062] When in the slow decay operation mode, the current driver circuitry 150 releases the first current using a third example current path 385. The third current path 385 allows current to flow through the second transistor 320, the first inductor 130, and the fourth transistor 340. When the current driver circuitry 150 is in the slow decay operation mode, the transistors 320, 340 are turned on, and the transistors 310, 330 are turned off. When in the slow decay operation mode, the current driver circuitry 150 cannot supply power to the first inductor 130 using current.

[0063] In an example operation, the controller circuitry 155 modifies the operation mode of the current driver circuitry 150 to supply a first current approximately equal to a target current. An example sequence of the operation modes of the current driver circuitry 150 is shown and described below in Figure 5 An example sequence of the operation modes of the current driver circuitry 150 is shown and described below in

[0064] Figure 4 is Figure 1 and 2 is a timing diagram 400 of an example operation of the driver circuitry 120 of Figure 4In the example, timing diagram 400 shows a first example current step 405, a first example current 410, an example back electromotive force 415, a second example current step 420, a second example current 425, and an example step pulse train 430 (shown as a series of pulses or a pulse sequence). Driver circuitry 120 supplies current steps 405, 420 to the Figure 1 and 2 inductors 130, 135 of Figure 1 and 2 Magnets 140 of Figure 1 cause the shaft 145 of

[0065] to rotate in response to current steps 405, 420. Figure 1 , 2 and 3. The first current step 405 is an approximate representation of the current from the first current driver circuitry 150 of

[0066] The back electromotive force 415 represents the Figure 1 and 2 The phase difference between the first current 410 and the back electromotive force 415 is an example load angle 435. The no-load condition of the stepper motor 110 corresponds to the load angle 435 being approximately equal to 90°. The stall condition of the stepper motor 110 corresponds to the load angle being approximately equal to 0°.

[0067] The second current step 420 is an approximate representation of the current from the second current driver circuitry 160 of Figure 1 and 2 The second current step 420 represents a continuous-time sinusoidal waveform using discrete time. The second current step 420 has multiple steps approximating the sinusoidal waveform represented by the second current 425. The second current driver circuitry 160 generates the second current step 420 as an approximate representation of the sinusoidal waveform of the second current 425. The second current 425 has a frequency approximately equal to 1 divided by 2 times pi (π) omega (ω). The second current 425 represents the ideal second current from the second current driver circuitry 160.

[0068] At Figure 4In the example, currents 410, 425 are out of phase. The phase difference between currents 410, 425 responds to and / or represents the orientation of inductors 130, 135. The phase difference allows Figure 2 magnetic poles 210, 220 of Figure 2 to transition from a first magnetic field of a first one of inductors 130, 135 to a second magnetic field of a second one of inductors 130, 135.

[0069] Step pulse train 430 represents the timing of the transition between steps of current steps 405, 420. The pulse frequency of step pulse train 430 determines the rotational speed of stepper motor 110. In some examples, controller circuitry 155 can increase the speed of stepper motor 110 by reducing the time between pulses of step pulse train 430. In such examples, controller circuitry 155 increases the pulse frequency of step pulse train 430. Controller circuitry 155 generates step pulse train 430 to increment current steps 405, 420, thereby increasing and / or decreasing the number of steps of subsequent steps.

[0070] Figure 5 is Figure 1 and 2 Timing diagram 500 of an example operation of driver circuitry 120 of 2 . In Figure 5 the example, timing diagram 500 includes Figure 4 an example portion of first current step 405 of Figure 4 and example driver output current 510. Figure 5 The portion of first current step 405 shown in Figure 5 includes first example step (step N ) 515 and second example step (step N+1 ) 520.

[0071] Driver output current 510 represents Figure 1 , 2 and the current at the output of first current driver circuitry 150 of 3. During first step 515, Figure 1 and 2The controller circuitry 155 determines an operating mode of the first current driver circuitry 150 in response to a first magnitude of a first current step 405 of a first step 515. In some instances, the first step 515 may be identified by an indexer value. In such instances, the indexer value identifies which step within the first current step 405 corresponds to the first step 515. In such instances, the indexer value may determine a target current for the first step 515. During a second step 520, the controller circuitry 155 determines an operating mode of the first current driver circuitry 150 in response to a second magnitude of the first current step 405 at the second step 520. In some instances, a transition between steps 515, 520 occurs by adjusting the indexer value to identify the second step 520. In such instances, the controller circuitry 155 may adjust the indexer value in response to pulses of a step pulse train 430.

[0072] At a first time 525, the controller circuitry 155 adjusts the first current driver circuitry 150 to a slow decay operating mode in response to the driver output current 510 being approximately equal to a target current of the first current step 405 for the first step 515. In some instances, the slow decay operating mode corresponds to Figure 3 a third current path 385. When in the slow decay operating mode, the driver output current 510 decreases relatively slowly.

[0073] At a second time 530, the controller circuitry 155 determines that the driver output current 510 has decreased by a threshold. At the second time 530, the controller circuitry 155 adjusts the first current driver circuitry 150 to a drive operating mode. In some instances, the drive operating mode corresponds to Figure 3 a first current path 375. When in the drive operating mode, the driver output current 510 increases relatively quickly in response to a current supplied by a reference terminal that supplies a reference voltage.

[0074] At a third time 535, the controller circuitry 155 detects that the driver output current 510 is approximately equal to a target current of the first current step 405 for the first step 515. At the third time 535, the controller circuitry 155 adjusts the first current driver circuitry 150 to a slow decay operating mode. After the third time 535, the driver output current 510 decreases relatively slowly.

[0075] At a fourth time 540, the controller circuitry 155 detects that the driver output current 510 has decreased by a threshold amount. At the fourth time 540, the controller circuitry 155 adjusts the first current driver circuitry 150 to a drive operation mode. When in the drive operation mode, the driver output current 510 increases relatively rapidly with the power supplied to the system.

[0076] At a fifth time 545, the controller circuitry 155 detects a transition from the first step 515 to the second step 520. In some instances, the controller circuitry 155 detects the transition in response to a pulse of the step pulse train 430. At the fifth time 545, the controller circuitry 155 adjusts the first current driver circuitry 150 to a fast decay operation mode. In some instances, the fast decay operation mode corresponds to Figure 3 the second current path 380. When in the fast decay operation mode, the driver output current 510 decreases relatively rapidly. Advantageously, the fast decay operation mode enables the first current driver circuitry 150 to decrease the driver output current 510 relatively faster than in the slow decay operation mode. In some example operations, such as when the amplitude of the first current step 405 is negative, the controller circuitry 155 uses the fast decay mode to achieve the target current of the first current step 405. In such example operations, the controller circuitry 155 can use the drive operation mode to transition the driver output current 510 between steps.

[0077] At a sixth time 550, the controller circuitry 155 detects that the driver output current 510 is approximately equal to the target current of the first current step 405 for the second step 520 minus a threshold. At the sixth time 550, the controller circuitry 155 adjusts the first current driver circuitry 150 to a drive operation mode. When in the drive operation mode, the driver output current 510 increases relatively rapidly.

[0078] At a seventh time 555, the controller circuitry 155 detects that the driver output current 510 is approximately equal to the first current step 405 during the second step 520. At the seventh time 555, the controller circuitry 155 adjusts the first current driver circuitry 150 to a slow decay operation mode. After the seventh time 555, the driver output current 510 decreases relatively slowly. Advantageously, the controller circuitry 155 can use Figure 1 、 2 and the different operation modes of the current driver circuitries 150, 160 of 3 to generate Figure 4 the current steps 405, 420.

[0079] Figure 6 is Figure 1 and 2The controller circuitry 155 is used to change Figure 1 And 2 Block diagram of an example implementation of the load of the stepper motor 110. Figure 6 The controller circuitry 155 can be instantiated (e.g., created, implemented over any length of time, embodied, implemented, etc.) by a programmable circuitry (such as a central processing unit (CPU)) that executes a first instruction. Additionally or alternatively, Figure 6 The controller circuitry 155 can be instantiated (e.g., created, implemented over any length of time, embodied, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) that is constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of a second instruction. Thus, Figure 6 All of the controller circuitries 155 can be instantiated at the same or different times. For example, Figure 6 Some or all of the controller circuitries 155 can be instantiated in one or more threads that execute in parallel on hardware and / or serially on hardware. Additionally, in some instances, Figure 6 Some or all of the controller circuitries 155 are implemented by a microprocessor circuitry that executes instructions and / or an FPGA circuitry that performs operations to implement one or more virtual machines and / or containers.

[0080] In Figure 6 the instance, the controller circuitry 155 includes Figure 1 And 2The duty cycle monitor circuit system 165, example clock circuit system 604, example step incrementer 608, example motor control characteristics 612, example step value in a quadrant 616, example peak current value 620, first example current driver control circuit system 624, example step indexer circuit system 628, example step current determination circuit system 632, example inductor current determination circuit system 636, example proportional integral derivative (PID) control circuit system 640, example operation mode determination circuit system 644, first example drive operation control circuit system 648, second example current driver control circuit system 652, second example drive operation control circuit system 656, example step time counter 660, example drive time counter 664, example fast decay time counter 668, example duty cycle determination circuit system per step 672, example duty cycle averaging circuit system 676, example storage device 678, first example average value 680, second example average value 682, third example average value 684, example error amplifier circuit system 686, example low pass filter 688, example threshold circuit system 690, and example peak current control circuit system 694. The controller circuit system 155 controls in response to the drive operation control circuit systems 648, 656 Figure 1 , 2 and the operation modes of the current driver circuit systems 150, 160 of 3. The duty cycle monitor circuit system 165 senses Figure 1 and 2 the change in the load of the stepper motor 110.

[0081] The clock circuit system 604 is coupled to the duty cycle monitor circuit system 165 and the step incrementer 608. The clock circuit system 604 generates a reference clock. The clock circuit system 604 supplies the reference clock to the duty cycle monitor circuit system 165, the step incrementer 608, and the counters 660, 664, 668. In some instances, the controller circuit system 155 may receive the reference clock from an external clock source such as a crystal oscillator, a resistor-capacitor oscillator, etc.

[0082] The step incrementer 608 has a first input coupled to the clock circuit system 604. The step incrementer 608 has a second input coupled to the current driver control circuit systems 624, 652. The step incrementer 608 generates a step pulse train (e.g., Figure 4 the step pulse train 430) in response to the reference clock from the clock circuit system 604. The step incrementer 608 supplies the step pulse train to the current driver control circuit systems 624, 652. In some instances, the step incrementer 608 is composed of a programmable circuit system that executes step incrementer instructions and / or executes, for example, Figure 9A and 9BOther circuit system instantiations of the operations shown in the flowcharts.

[0083] The motor control feature 612 is coupled to the duty cycle monitor circuitry 165 and the current driver control circuitry 624, 652. Figure 6 In the example of , the motor control characteristic 612 includes a mid-quadrant step value 616 and a peak current value 620. In some examples, the motor control characteristic 612 can be implemented as a memory, such as one or more registers, volatile memory, non-volatile memory, etc. In other examples, the motor control characteristic 612 can receive the values ​​616, 620 from an external data source, such as a main memory, a processor circuit system, etc.

[0084] The step value 616 in the quadrant indicates Figure 4 The number of steps within the quadrant of the sinusoidal waveform of the first current 410 (eg, Figure 5 For example, the step value 616 in the quadrant is approximately 1 divided by 8 times the number of steps of pi (π) omega (ω) of the sinusoidal waveform of the first current 410. The peak current value 620 represents the amplitude of the first current 410. In addition, during the example operation, the peak current value 620 is from Figure 1 and 2 The maximum current among the currents of the driver circuit system 120. The motor control characteristic 612 supplies the values ​​616 and 620 to the current driver control circuit systems 624 and 652.

[0085] The first current driver control circuitry 624 may be coupled to Figure 1 , 2 and 3 of the first current driver circuit system 150 Figure 3 The current sensing circuit systems 315, 325, 335, 345 of the first current driver control circuit system 624 are coupled to the duty cycle monitor circuit system 165, the step incrementer 608, the motor control characteristics 612 and the first drive operation control circuit system 648. Figure 6 In the example of , the first current driver control circuit system 624 includes a step indexer circuit system 628, a step current determination circuit system 632, an inductor current determination circuit system 636, a PID control circuit system 640, and an operation mode determination circuit system 644.

[0086] The first current driver control circuit system 624 uses a step indexer circuit system 628 and a step current determination circuit system 632 to determine the current for a given step. The first current driver control circuit system 624 determines a first current in response to an inductor current determination circuit system 636. The first current driver control circuit system 624 uses an operating mode determination circuit system 644 to determine the operating mode of the first current driver circuit system 150. In some instances, the first current driver control circuit system 644 is instantiated by a programmable circuit system that executes current driver control instructions and / or other circuit system examples that perform operations such as shown in the flowcharts of Figure 9A and 9B .

[0087] The step indexer circuit system 628 has an input coupled to a step incrementer 608. The step indexer circuit system 628 has an output coupled to a duty cycle monitor circuit system 165 and a step current determination circuit system 632. The step indexer circuit system 628 generates an indexer value (n) that identifies Figure 4 the step in the first current step 405 of Figure 9A and 9B . The step indexer circuit system 628 adjusts the indexer value in response to pulses of a step pulse train 430 from the step incrementer 608. In some instances, the step indexer circuit system 628 increments the indexer value by one in response to each pulse of the step pulse train 430. The step indexer circuit system 628 supplies the indexer value to the duty cycle monitor circuit system 165 and the step current determination circuit system 632. In some instances, the step indexer circuit system 628 is instantiated by a programmable circuit system that executes step tracking instructions and / or other circuit system examples that perform operations such as shown in the flowcharts of

[0088] The step current determination circuit system 632 has a first input coupled to a step value in quadrant 616 of a motor control characteristic 612. The step current determination circuit system 632 has a second input coupled to a peak current value 620 of the motor control characteristic 612. The step current determination circuit system 632 has a third input coupled to the step indexer circuit system 628. The step current determination circuit system 632 receives an indexer value representing a current step (n), a step value in quadrant (M) 616, and a peak current value (I 峰值 ).

[0089] The step current determination circuit system 632 determines an indexer coefficient (K n ) for the current step of the indexer value. The indexer coefficient represents a current (e.g., Figure 4The portion of the sine wave of the currents 410, 425) corresponding to the indexer value. The step current determination circuitry 632 uses the indexer value and the step value (M) 616 in the quadrant to determine the indexer coefficient. In some examples, the step current determination circuitry 632 determines the indexer coefficient by taking the sine of 90 divided by the step value 632 in the quadrant times the indexer value. In such examples, the step current determination circuitry 632 uses the following equation (1) to determine the indexer coefficient.

[0090] K n = sin((90° / M)*n); Equation (1)

[0091] The step current determination circuitry 632 determines the target step current (I n ) in proportion to the peak current value 620 and the indexer coefficient. The target step current is the target current during the current step (e.g., one of the steps in current steps 405, 420). In some examples, the step current determination circuitry 632 determines the target step current by multiplying the peak current value 620 by the indexer coefficient. In such examples, the step current determination circuitry 632 uses the following equation (2) to determine the target step current.

[0092] I n = I 峰值 *K n Equation (2)

[0093] The step current determination circuitry 632 has an output coupled to the PID control circuitry 640. The step current determination circuitry 632 supplies the target step current to the PID control circuitry 640. In some examples, the step current determination circuitry 632 is instantiated by a programmable circuitry that executes step current determination instructions and / or other circuitry examples that perform operations shown in the flowcharts such as Figure 9A and 9B shown.

[0094] The inductor current determination circuitry 636 has an input that can be coupled to the first current driver circuitry 150. The inductor current determination circuitry 636 receives current values from Figure 3 the current sensing circuitry 315, 325, 335, 345. The inductor current determination circuitry 636 determines the sensed current value (I SENSE_n)。For example, when in the drive operation mode, the inductor current determination circuitry 636 determines a first current in response to the current values of the current sensing circuitries 315, 345. The inductor current determination circuitry 636 has an output coupled to the PID control circuitry 640. The inductor current determination circuitry 636 supplies the determined sensed current value to the PID control circuitry 640. In some instances, the inductor current determination circuitry 636 is instantiated by a programmable circuitry that executes inductor current determination instructions and / or other circuitry instances that perform operations as shown in the flowcharts of Figure 9A and 9B .

[0095] The PID control circuitry 640 has a first input coupled to the step current determination circuitry 632 and a second input coupled to the inductor current determination circuitry 636. The PID control circuitry 640 receives a target step current and a sensed current value. The PID control circuitry 640 is a control loop that generates a control variable (u(t)) using an error value (e(t)). In Figure 6 instances, the PID control circuitry 640 determines that the error value is approximately equal to the target step current minus the sensed current value. The PID control circuitry 640 combines proportional (P), integral (I), and derivative (D) elements to generate the control variable. The proportional element is approximately the error value multiplied by the proportional gain (K p ). The integral element is approximately the integral of the error value multiplied by the integral gain (K i ). The derivative element is approximately equal to the derivative of the error value multiplied by the derivative gain (K d ). The proportional, integral, and derivative gains of the PID control circuitry 640 allow the PID control circuitry 640 to adjust the weights of the proportional, integral, and derivative elements in the calculation of the control variable.

[0096] The PID control circuitry 640 has an output coupled to the operation mode determination circuitry 644. The PID control circuitry 640 supplies the control variable to the operation mode determination circuitry 644. In some instances, the PID control circuitry 640 is instantiated by a programmable circuitry that executes PID control instructions and / or other circuitry instances that perform operations as shown in the flowcharts of Figure 9A and 9B .

[0097] The operation mode determination circuitry 644 has an input coupled to the PID control circuitry 640. The operation mode determination circuitry 644 receives the control variable. The operation mode determination circuitry 644 selects one of a drive operation mode, a fast decay operation mode, or a slow decay operation mode in response to the control variable.

[0098] When the control variable represents a condition where the sensed current value is approximately less than a threshold of the target step current, the operation mode determination circuitry 644 selects the drive operation mode. For example, the operation mode determination circuitry 644 selects the drive operation mode at Figure 5 times 530, 540, 550. In some instances, the operation mode determination circuitry 644 selects the drive operation mode in response to the control value being greater than a reference value. The reference value represents an acceptable error value.

[0099] When the control variable represents a condition where the sensed current value is approximately equal to the target step current, the operation mode determination circuitry 644 selects the slow decay operation mode. For example, the operation mode determination circuitry 644 selects the slow decay operation mode at Figure 5 times 525, 535, 555. In some instances, when the target step current is approximately equal to the target step voltage, the operation mode determination circuitry 644 may select the slow decay operation mode.

[0100] When the control variable represents a condition where the sensed current value is greater than a threshold and less than the target step current, the operation mode determination circuitry 644 selects the fast decay operation mode. In some instances, in response to a step increment, the target step current rapidly decreases. In such an instance, the step current determination circuitry 632 adjusts the target step current, and the sensed current value remains constant through the step until the operation mode determination circuitry 644 compensates. For example, the operation mode determination circuitry 644 selects the fast decay operation mode at Figure 5 the fifth time 545. In some instances, the PID control circuitry 640 considers a sudden change in the target step current in response to a differential element of the control variable. For example, the sudden change in the target step current has a relatively large differential compared to a time when the indexer value remains fixed. Advantageously, the operation mode determination circuitry 644 selects an operation mode in response to the control variable of the PID control circuitry 640.

[0101] The operation mode determination circuitry 644 has an output coupled to the duty cycle monitor circuitry 165 and the first drive operation control circuitry 648. The operation mode determination circuitry 644 supplies the selected operation mode to the duty cycle monitor circuitry 165 and the first drive operation control circuitry 648. In some instances, the operation mode determination circuitry 644 is instantiated by a programmable circuitry that executes operation mode determination instructions and / or other circuitry instances that perform operations as shown in the flowcharts of Figure 9A and 9B for example.

[0102] The first drive operation control circuit system 648 has an input coupled to the first current driver control circuit system 624. The first drive operation control circuit system 648 has an output that can be coupled to the first current driver circuit system 150. The first drive operation control circuit system 648 receives a selected operation mode from the operation mode determination circuit system 644. The first drive operation control circuit system 648 adjusts the first current driver circuit system 150 in response to the selected operation mode. In some instances, the first drive operation control circuit system 648 turns on and / or off Figure 3 transistors 310, 320, 330, 340 to adjust the first current driver circuit system 150 to the selected operation mode. In some instances, the first drive operation control circuit system 648 is instantiated by a programmable circuit system that executes drive operation control instructions and / or other circuit systems that perform operations such as those shown in the flowcharts of Figure 9A and 9B .

[0103] The second current driver control circuit system 652 can be coupled to the second current driver circuit system 160 of Figure 1 and 2 . The second current driver control circuit system 652 is coupled to the step incrementer 608, the motor control characteristics 612, and the second drive operation control circuit system 656. The second current driver control circuit system 652 determines the target current for a given step of the second current step 420 of Figure 4 . The second current driver control circuit system 652 determines the second current of the second current driver circuit system 160. The second current driver control circuit system 652 determines the operation mode of the second current driver circuit system 160. Similar to the first current driver control circuit system 624, the second current driver control circuit system 652 selects the operation mode of the second drive operation control circuit system 656. In some instances, the second current driver control circuit system 652 is instantiated by a programmable circuit system that executes current driver control instructions and / or other circuit systems that perform operations such as those shown in the flowcharts of Figure 9A and 9B .

[0104] The second drive operation control circuit system 656 has an input coupled to the second current driver control circuit system 652. The second drive operation control circuit system 656 has an output that can be coupled to the second current driver circuit system 160. The second drive operation control circuit system 656 receives a selected operation mode from the second current driver control circuit system 652. The second drive operation control circuit system 656 adjusts the second current driver circuit system 160 in response to the selected operation mode. In some instances, the second drive operation control circuit system 656 adjusts the second current driver circuit system 160 to the selected operation mode. In some instances, the second drive operation control circuit system 656 is instantiated by a programmable circuit system that executes drive operation control instructions and / or other circuit systems that perform operations such as Figure 9A and 9B as shown in the flowchart of.

[0105] The duty cycle monitor circuit system 165 is coupled to the clock circuit system 604, the step incrementer 608, the motor control characteristic 612, and the first current driver control circuit system 624. In Figure 6 an instance, the duty cycle monitor circuit system 165 includes a step time counter 660, a drive time counter 664, a fast decay time counter 668, a per-step duty cycle determination circuit system 672, a duty cycle averaging circuit system 676, a storage device 678 further having average duty cycle values 680, 682, 684, an error amplifier circuit system 686, a low-pass filter 688, and a threshold circuit system 690. The duty cycle monitor circuit system 165 senses load changes of the stepper motor 110. The duty cycle monitor circuit system 165 determines the duty cycle of one or more steps in response to the duration of the operation mode. The duty cycle monitor circuit system 165 determines the load change of the stepper motor 110 by comparing the determined period with the previous duty cycle of a similar operation.

[0106] The step time counter 660 has a first input coupled to the clock circuit system 604 and a second input coupled to the step incrementer 608. The step time counter 660 receives a reference clock and a step pulse train. The step time counter 660 uses the reference clock and the step pulse train to determine the total duration of a step (∑T 阶跃)。In some instances, the step time counter 660 counts the number of reference clock cycles between the rising edges of the step pulse train. In such instances, the number of reference clock cycles represents the total duration of any given step. In other instances, the step time counter 660 counts the number of reference clock cycles over multiple pulses of the step pulse train. In such instances, the number of cycles represents the total duration of multiple operational steps. The step time counter 660 has an output coupled to the per-step duty cycle determination circuitry 672. The step time counter 660 supplies the total duration of the step to the per-step duty cycle determination circuitry 672.

[0107] The drive time counter 664 has a first input coupled to the clock circuitry 604, a second input coupled to the step incrementer 608, and a third input coupled to the first current driver control circuitry 624. The drive time counter 664 receives the reference clock, the step pulse train from the step incrementer 608, and the selected operation mode. The drive time counter 664 determines the drive duration (∑T when the first current driver circuitry 150 is in the drive operation mode during one or more steps. on )。In some instances, the drive time counter 664 determines the drive duration as the time interval during which the operation mode is the drive operation mode between the rising edges of the step pulse train. In such instances, when the selected operation mode is the drive operation mode, the drive time counter 664 counts the number of reference clock cycles between the rising edges of the step pulse train. The number of reference clock cycles represents the duration that the first current driver circuitry 150 is in the drive operation mode. The drive time counter 664 has an output coupled to the per-step duty cycle determination circuitry 672. The drive time counter 664 supplies the drive duration of the drive operation mode for one or more steps to the duty cycle determination circuitry 672.

[0108] The fast decay time counter 668 has a first input coupled to the clock circuitry 604, a second input coupled to the step incrementer 608, and a third input coupled to the first current driver control circuitry 624. The fast decay time counter 668 receives the reference clock, the step pulse train, and the selected operation mode. The fast decay time counter 668 determines the fast decay duration (∑T when the first current driver circuitry 150 is in the fast decay operation mode during one or more steps. fd)。The fast decay time counter 668 determines the duration of the fast decay operation mode between one or more rising edges of the step pulse train. In some instances, when the selected operation mode is the fast decay operation mode, the fast decay time counter 668 counts the number of cycles of the reference clock between the rising edges of the step pulse train. In such instances, the number of cycles of the reference clock represents the fast decay duration. The fast decay time counter 668 has an output coupled to the per-step duty cycle determination circuitry 672. The fast decay time counter 668 supplies the fast decay duration to the per-step duty cycle determination circuitry 672.

[0109] The per-step duty cycle determination circuitry 672 has inputs coupled to the counters 660, 664, 668. The per-step duty cycle determination circuitry 672 receives the total duration (T 阶跃 ), the drive duration (ΣT on ), and the fast decay duration (ΣT fd ). The per-step duty cycle determination circuitry 672 determines the duty cycle (D n_k ) of one or more steps in response to the total duration, the drive duration, and the fast decay duration. In some instances, the per-step duty cycle determination circuitry 672 determines that the duty cycle is approximately equal to the difference between the drive duration and the fast decay duration divided by the total duration. In such instances, the per-step duty cycle determination circuitry 672 uses the following equation (3) to determine the power delivered to the stepper motor 110 during one or more steps.

[0110] D n_k =(ΣT on -ΣT fd ) / T 阶跃 ; Equation (3)

[0111] The per-step duty cycle determination circuitry 672 has outputs coupled to the duty cycle averaging circuitry 676 and the error amplifier circuitry 686. The per-step duty cycle determination circuitry 672 supplies the determined duty cycle to the duty cycle averaging circuitry 676 and the error amplifier circuitry 686. In some instances, the per-step duty cycle determination circuitry 672 is instantiated by a programmable circuitry that executes per-step duty cycle determination instructions and / or other circuitry instances that perform operations shown in the flowcharts such as Figure 9A and 9B .

[0112] The duty cycle averaging circuit system 676 has a first input coupled to the step indexer circuit system 628, a second input coupled to the per-step duty cycle determination circuit system 672, and a third input coupled to the storage device 678. The duty cycle averaging circuit system 676 receives an indexer value, the determined duty cycle, and access to the average duty cycle values 680, 682, 684. The duty cycle averaging circuit system 676 selects one of the average duty cycle values 680, 682, 684 in response to the indexer value. The average duty cycle values 680, 682, 684 represent the previously determined duty cycles of one or more indexer values as an average. The average duty cycle values 680, 682, 684 correspond to the operation of the controller circuit system 155. In some instances, each of the average duty cycle values 680, 682, 684 represents the duty cycle of one or more target currents. In such instances, the duty cycle averaging circuit system 676 selects one of the average duty cycle values 680, 682, 684 corresponding to the operation at the indexer value.

[0113] The duty cycle averaging circuit system 676 has an output coupled to the error amplifier circuit system 686. The duty cycle averaging circuit system 676 supplies the selected one of the average duty cycle values 680, 682, 684 to the error amplifier circuit system 686. In response to supplying one of the average duty cycle values 680, 682, 684 to the error amplifier circuit system 686, the duty cycle averaging circuit system 676 combines the determined duty cycle with the selected one of the average duty cycle values 680, 682, and 684. In some instances, the duty cycle averaging circuit system 676 averages the determined duty cycle with the selected one of the average duty cycle values 680, 682, 684 to generate a moving average. The duty cycle averaging circuit system 676 updates the selected one of the average duty cycle values 680, 682, 684 in response to the combination. In some instances, the duty cycle averaging circuit system 676 is instantiated by a programmable circuit system executing a duty cycle averaging instruction and / or other circuit systems performing operations such as Figure 9A and 9B shown in the flowchart of.

[0114] The error amplifier circuit system 686 has a first input coupled to the per-step duty cycle determination circuit system 672 and a second input coupled to the duty cycle averaging circuit system 676. The error amplifier circuit system 686 receives the determined duty cycle and the average duty cycle. The error amplifier circuit system 686 compares the determined duty cycle with the average duty cycle. The error amplifier circuit system 686 calculates the duty cycle difference (D DIFF) is determined as the difference between the determined duty cycle and the average duty cycle. The error amplifier circuit system 686 has an output coupled to the low-pass filter 688. The error amplifier circuit system 686 supplies the duty cycle difference to the low-pass filter 688. In some instances, the error amplifier circuit system 686 is instantiated by a programmable circuit system that executes error amplifier instructions and / or other circuit system examples that perform operations such as Figure 9A and 9B shown in the flowchart of.

[0115] The low-pass filter 688 has an input coupled to the error amplifier circuit system 686. The low-pass filter 688 receives the duty cycle difference. The low-pass filter 688 has a cut-off frequency that determines the frequencies that are allowed to pass through the low-pass filter 688. The low-pass filter 688 reduces the variations in the duty cycle difference that occur at frequencies greater than the cut-off frequency. The low-pass filter 688 reduces the effect of relatively high-speed variations (such as noise) on the total error. The low-pass filter 688 has an output coupled to the threshold circuit system 690. The low-pass filter 688 supplies the filtered duty cycle difference to the threshold circuit system 690.

[0116] The threshold circuit system 690 has an input coupled to the low-pass filter 688. The threshold circuit system 690 receives the filtered duty cycle difference. The threshold circuit system 690 determines whether the filtered duty cycle difference has a positive or negative amplitude. When the filtered duty cycle difference has a negative amplitude, the threshold circuit system 690 determines that the determined duty cycle is less than the average duty cycle. In such instances, the threshold circuit system 690 determines that the load applied to the stepper motor 110 remains constant and / or decreases. In some instances, the threshold circuit system 690 determines a feed-forward error that is approximately zero in response to the filtered duty cycle difference having a negative amplitude.

[0117] When the filtered duty cycle difference has a positive amplitude, the threshold circuit system 690 determines that the determined duty cycle is greater than the average duty cycle. In such instances, the threshold circuit system 690 determines that the load applied to the stepper motor 110 has increased. The threshold circuit system 690 compares the filtered duty cycle difference with a threshold difference. The threshold difference represents the minimum change in the load of the stepper motor 110 that ensures a change in the peak current value 620. For example, the power supplied by the current driver circuit systems 150, 160 may be sufficient to allow relatively small changes in the load of the stepper motor 110. In such instances, an excessive increase in the load of the stepper motor 110 requires additional power to compensate, prevent position loss, and / or prevent stalling. The threshold circuit system 690 generates a feed-forward error in response to the filtered duty cycle difference being greater than the threshold difference. However, when the filtered duty cycle is less than the threshold difference, the threshold circuit system 690 sets the feed-forward error to approximately zero.

[0118] The threshold circuit system 690 has an output coupled to the peak current control circuit system 694. The threshold circuit system 690 supplies a feedforward error to the peak current control circuit system 694. In some instances, the threshold circuit system 690 is instantiated by a programmable circuit system that executes threshold instructions and / or other circuit system examples that perform operations as shown in the flowchart such as Figure 9A and 9B .

[0119] The peak current control circuit system 694 has an input coupled to the threshold circuit system 690. The peak current control circuit system 694 receives the feedforward error. The peak current control circuit system 694 determines a modified peak current value in response to a non-zero feedforward error. In some instances, the peak current control circuit system 694 uses the peak current value 620 and the feedforward error to determine the modified peak current value. The peak current control circuit system 694 has an output coupled to the peak current value 620. The peak current control circuit system 694 adjusts the peak current value 620 in response to the determined modified peak current value. In some instances, the peak current control circuit system 694 is instantiated by a programmable circuit system that executes peak current control instructions and / or other circuit system examples that perform operations as shown in the flowchart such as Figure 9A and 9B .

[0120] Advantageously, updating the peak current value 620 adjusts the current driver control circuit systems 624, 652. Advantageously, the controller circuit system 155 adjusts the power supplied to the stepper motor 110 in response to a change in the duty cycle of one or more steps. Advantageously, the duty cycle monitor circuit system 165 can determine a change in the load of the stepper motor 110 with as little as a single step of the stepper motor 110.

[0121] Figure 7 is Figure 1 , 2 and 6 of the timing diagram 700 of the example windowing operation of the duty cycle monitor circuit system 165. In Figure 7 instances, the timing diagram 700 includes an example ideal current 710, a first example operation 720, a second example operation 730, a third example operation 740, a fourth example operation 750, a fifth example operation 760, a sixth example operation 770, and a seventh example operation 780.

[0122] The ideal current 710 represents the ideal current from Figure 1 , 2 and 3 of the current driver circuit systems 150, 160. The ideal current 710 is a sine wave, and its frequency is approximately equal to 1 divided by 2 times pi (π) omega (ω). Advantageously, the ideal current 710 is a periodic sine wave.

[0123] Operations 720, 730, 740, 750, 760, 770, 780 represent Figure 1 , 2 one or more steps of the controller circuitry 155 for 5

[0124] Figure 8 and 6. Operations 720, 730, 740, 750, 760, 770, 780 produce the desired current 710. In response to the desired current being a sine wave form, each of operations 720, 730, 740, 750, 760, 770, 780 is periodically repeated. In an example operation, the duty cycle monitor circuitry 165 can compare the duty cycle of any instance of any one of operations 720, 730, 740, 750, 760, 770, 780 with the repetition of the same one of operations 720, 730, 740, 750, 760, 770, 780 at a later time. For example, the duty cycle determined at any occurrence of the first operation 720 can be compared to determine a load change of the stepper motor 110. Advantageously, after the first occurrence of any one of operations 720, 730, 740, 750, 760, 770, 780, the duty cycle monitor circuitry 165 can begin sensing a load change of the stepper motor 110. In some instances, operations within a half cycle of the desired current 710 can be compared to operations with a similar current. For example, when the target currents of operations 720, 780 are approximately equal, operations 720, 780 can be used to sense a load change of the stepper motor 110. Figure 1 、 2 and 6 is a timing diagram 800 of an example operation of the duty cycle monitor circuitry 165. In Figure 8 an instance, the timing diagram 800 includes an example indexer diagram 805, an example phase diagram 810, an example sensed current diagram 815, an example load diagram 820, an example torque diagram 825, and an example duty cycle difference diagram 830.

[0125] The indexer diagram 805 represents Figure 6 the indexer value of the step indexer circuitry 628 for 5 Figure 6 . The step indexer circuitry 628 adjusts the indexer value in response to pulses of the step pulse train 430 from Figure 4 the step incrementer 608 for 5

[0126] The sensed current diagram 815 represents the current sensed by Figure 1 ,2 The current driver circuit system 150 of 1 and 3 supplies current in response to Figure 1 , 2 the operation of the controller circuit system 155 of 5 and 6. In an example operation, Figure 6 the inductor current determination circuit system 636 determines the magnitude of the sensed current graph 815 at a given time. In such an instance, the first current driver control circuit system 624 may adjust the current driver circuit system 150 in response to changes in the sensed current graph 815.

[0127] The load graph 820 represents the mechanical load applied to Figure 1 and 2 the stepper motor 110. In some instances, an increase in the magnitude of the load graph 820 corresponds to an increase in the applied mechanical load. In such an instance, the controller circuit system 155 may need to adjust the power supplied to the stepper motor to compensate for some of the increase in the load graph 820.

[0128] The torque graph 825 represents the mechanical energy supplied by the stepper motor 110. When the mechanical load applied to the stepper motor 110 increases, the controller circuit system 155 needs to increase the power supply of the current driver circuit system 150 to prevent stalling and / or keep the positioning accurate.

[0129] The duty cycle difference graph 830 represents the duty cycle difference determined by Figure 6 the error amplifier circuit system 686. When the magnitude of the duty cycle difference graph 830 is negative, the duty cycle monitor circuit system 165 determines that the mechanical load applied to the stepper motor 110 has decreased. When the magnitude of the duty cycle difference graph 830 is positive, the duty cycle monitor circuit system 165 determines that the mechanical load applied to the stepper motor 110 has increased. Figure 6 The threshold circuit system 690 of determines that, in response to the magnitude of the duty cycle difference graph 830 being greater than the threshold, an increase in the magnitude of the duty cycle difference graph 830 requires an adjustment of Figure 6 the peak current value 620.

[0130] At the first time 835, the indexer graph 805 starts to step with the peak current value. At the first time 835, the sensed current graph 815 represents the peak current value 620 as the first peak. At the second time 840, the indexer graph 805 starts to step with the peak current value. However, at the second time 840, the magnitude of the sensed current graph 815 is a negative value in response to the value of the phase graph 810.

[0131] At the third time 845, the load graph 820 increases. Starting from the third time 845, the power supplied to the stepper motor 110 by the sinusoidal waveform of the peak current value 620 may no longer be able to continue to make Figure 1The shaft 145 rotates. After the third time 845, the drive duration of the drive time counter 664 increases in response to the back electromotive force generated by increasing the mechanical load.

[0132] Between the third time 845 and the fourth time 850, the duty cycle monitor circuit system 165 senses a change in the load graph 820 at the third time 845 in response to a change in the duty cycle caused by the increase in the drive duration. For example, Figure 6 the error amplifier circuit system 686 of compares the duty cycle at the fourth time 850 with a previous duty cycle of a similar target current. In such an instance, the error amplifier circuit system 686 generates an increase in the magnitude of the duty cycle difference graph 830. At the fourth time 850, the duty cycle monitor circuit system 165 generates a feedforward error in response to the magnitude of the duty cycle difference graph 830 being greater than a threshold. At approximately the fourth time 850, the peak current control circuit system 694 increases the peak current value 620 to a second peak. At approximately the fourth time 850, the torque graph 825 increases in response to the increase in the peak current value 620 from the first peak to the second peak.

[0133] At the fifth time 855, the indexer graph 805 starts to step with the peak current value. At the fifth time 855, the sense current graph 815 represents the peak current value 620 as the second peak from the fourth time 850. Advantageously, the duty cycle monitor circuit system 165 can use a single step to sense a change in the mechanical load applied to the stepper motor 110.

[0134] Figure 9A and 9B Form a flowchart representing example machine-readable instructions and / or example operations 900 that can be used Figure 1 、 2 and example programmable circuit system implementations of the duty cycle monitor circuit system 165 of 6 and / or more generally using Figure 1 、 2 in and the controller circuit system 155 of 6 to implement, instantiate, and / or execute. The example operation 900 starts at block 905, where Figure 6 the step current determination circuit system 632 of determines the indexer coefficient of the motor step. In some instances, the step current determination circuit system 632 determines the indexer coefficient using Equation (1) above.

[0135] The step current determination circuit system 632 uses the indexer coefficient to determine the target current of the motor step. (Block 910). In some instances, the step current determination circuit system 632 determines the target current of the motor step using Equation (2) above.

[0136] Figure 6The inductor current determination circuit system 636 determines the current supplied to the inductor by the current driver circuit system. (Block 915). In some instances, the inductor current determination circuit system 636 determines the current supplied to Figure 3 in response to the output of one or more of the current sensing circuit systems 315, 325, 335, 345, the current supplied to Figure 1 and 2 the first inductor 130. In such instances, the inductor current determination circuit system 636 can determine the current by combining and / or comparing the currents flowing through Figure 3 the transistors 310, 320, 330, 340. For example, when Figure 3 the first current path 375 is active (e.g., Figure 1 , 2 and the current driver circuit system 150 of 3 is in drive mode), the inductor current determination circuit system 636 determines the current through the first inductor 130 in response to the current through one or both of the transistors 310, 340.

[0137] Figure 6 The PID control circuit system 640 of Figure 6 uses the target current and the supplied current to determine a control variable. (Block 920). In some instances, the PID control circuit system 640 determines that the error value is approximately equal to the difference between the target current and the supplied current. In such instances, the PID control circuit system 640 determines the control variable in response to implementing the error value with proportional, integral, and derivative elements. Advantageously,

[0138] Figure 6 the change in the peak current value 620 of Figure 6 is reflected in the target current that adjusts the control variable.

[0139] Figure 6The drive time counter 664 determines a first duration that the current driver circuitry is in the drive mode during a motor step. (Block 930). In some instances, the drive time counter 664 determines the drive duration as the time interval that the first current driver circuitry 150 is in the drive mode in one or more steps. For example, the drive time counter 664 counts the number of cycles of the reference clock from Figure 6 the clock circuitry 604 during the drive duration.

[0140] Figure 6 The fast decay time counter 668 determines a second duration that the current driver circuitry is in the fast decay mode during a motor step. (Block 935). In some instances, the fast decay time counter 668 determines the fast decay duration as the time interval that the first current driver circuitry 150 is in the fast decay mode in one or more steps. For example, the fast decay time counter 668 counts the number of cycles of the reference clock from the clock circuitry 604 during the fast decay duration.

[0141] Figure 6 The step time counter 660 determines the total duration of a motor step. (Block 940). In some instances, the step time counter 660 determines the total duration as the time interval between the pulse edges of the step pulse train 430 from the step incrementer 608. In such instances, the step time counter 660 can determine the total duration as the interval of multiple steps. For example, the step time counter 660 can determine the total duration as the interval between two pulses of the step pulse train 430. In such instances, in response to the frequency of the reference clock from the clock circuitry 604 being approximately one thousand times the frequency of the step pulse train 430, the total duration can be one thousand.

[0142] Figure 6 The per-step duty cycle determination circuitry 672 determines the duty cycle of a motor step. (Block 945). In some instances, the per-step duty cycle determination circuitry 672 determines the duty cycle of a motor step using Equation (3) above.

[0143] The per-step duty cycle determination circuitry 672 determines whether the duty cycle of a motor step window has been determined. (Block 950). In some instances, the per-step duty cycle determination circuitry 672 determines the duty cycle of multiple steps of the step pulse train 430. In such instances, the per-step duty cycle determination circuitry 672 determines the total duty cycle of multiple steps.

[0144] If the per-step duty cycle determination circuit system 672 determines that the duty cycle has not been determined for all steps of the motor step window (e.g., the result of block 950 is "No"), then the step incrementer 608 increments the motor step to the next motor step. (Block 955). In some instances, the step incrementer 608 generates a pulse on the step pulse train 430. In such instances, in response to the pulse, Figure 6 the step indexer circuit system 628 of

[0145] increments the indexer value. Control returns to block 905 for the next motor step. Figure 9B Now turning to

[0146] Figure 6 if the per-step duty cycle determination circuit system 672 determines that the duty cycle has been determined for all steps of the motor step window (e.g., the result of block 950 is "Yes"), then the per-step duty cycle determination circuit system 672 determines the total duty cycle of the motor step window. (Block 960). In some instances, the per-step duty cycle determination circuit system 672 uses Equation (3) above to determine the duty cycle of each step of the step window. In such instances, the per-step duty cycle determination circuit system 672 combines the duty cycles of each step. Figure 4 the duty cycle averaging circuit system 676 of Figure 7 determines the average duty cycle of the previous duty cycles of the comparable previous motor step window. (Block 965). In some instances, the duty cycle averaging circuit system 676 uses the indexer value from the step indexer circuit system 628 to select

[0147] Figure 6 one of the average duty cycle values 680, 682, 684. In such instances, the selected one of the average duty cycle values 680, 682, 684 corresponds to the operation of the controller circuit system 155, similar to the operation during the step window. For example, the magnitude of the target current during the selected one of the average duty cycle values 680, 682, 684 is approximately the same as the magnitude of the target current during the step window. In such instances, the duty cycle averaging circuit system 676 can compare Figure 6A low-pass filter 688, which can apply a truncation factor. The truncation factor can simplify the duty cycle difference before comparison.

[0148] Figure 6 The threshold circuit system 690 determines whether the duty cycle difference is greater than zero. (Block 975). In some instances, the threshold circuit system 690 determines that the duty cycle difference represents a reduced load on the stepper motor 110 in response to a negative magnitude of the duty cycle difference. In such instances, the threshold circuit system 690 determines that the controller circuit system 155 accurately controls the stepper motor 110 for such a load.

[0149] If the threshold circuit system 690 determines that the duty cycle difference is greater than zero (e.g., the result of block 975 is "yes"), then the threshold circuit system 690 determines whether the duty cycle difference is greater than a threshold. (Block 980). In some instances, the threshold circuit system 690 determines that the duty cycle difference represents an increased load on the stepper motor 110 in response to a positive magnitude of the duty cycle difference. In such instances, the threshold circuit system 690 can determine that the controller circuit system 155 needs to increase the power supply to compensate for the increased load on the stepper motor 110.

[0150] If the threshold circuit system 690 determines that the duty cycle difference is greater than the threshold (e.g., the result of block 980 is "yes"), then Figure 6 The peak current control circuit system 694 uses the duty cycle difference to adjust the peak current. (Block 985). In some instances, the threshold circuit system 690 determines to increase the power supply to the stepper motor 110 in response to the duty cycle difference being greater than the threshold. In such instances, the peak current control circuit system 694 increases the peak current value 620 to modify the current supplied by Figure 1 , 2 and the current driver circuit systems 150, 160 of 3. In an example operation, the step current determination circuit system 632 adjusts the target current to compensate for the change in the peak current value 620. Advantageously, the controller circuit system 155 can adjust the power supply to the stepper motor 110 to compensate for the load change of the stepper motor 110. Advantageously, adjusting the power supply reduces the likelihood of the stepper motor 110 stalling and / or losing position.

[0151] If the threshold circuit system 690 determines that the duty cycle difference is not greater than zero (e.g., the result of block 975 is "No"), then if the threshold circuit system 690 determines that the duty cycle difference value is not greater than the threshold (e.g., the result of block 980 is "No"), or the operation of block 985 occurs, the duty cycle averaging circuit system 676 updates the average duty cycle using the total duty cycle (block 990). In some instances, the duty cycle averaging circuit system 676 averages a selected one of the average duty cycle values 680, 682, 684 with the determined duty cycle to generate an updated average duty cycle. In such instances, the duty cycle averaging circuit system 676 sets the selected one of the average duty cycle values 680, 682, 684 to reflect the updated average duty cycle.

[0152] The step incrementer 608 steps the motor to the next motor step (block 995). In some instances, the step incrementer 608 generates a pulse on the step pulse train 430. In such instances, in response to the pulse, Figure 6 the step indexer circuit system 628 of increments the indexer value. Control returns to block 905 for the next motor step.

[0153] Although the flowcharts shown in Figure 9A and 9B describe example methods, many other methods for implementing the duty cycle monitor circuit system 165 may alternatively be used in accordance with this specification. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated examples during the manufacturing process.

[0154] Although Figure 6 shows an example implementation of the Figure 1 controller circuit system 155, Figure 6One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Additionally, example clock circuit system 604, example step incrementer 608, example motor control characteristics 612, example step value in a quadrant 616, example peak current value 620, first example current driver control circuit system 624, example step indexer circuit system 628, example step current determination circuit system 632, example inductor current determination circuit system 636, example PID control circuit system 640, example operating mode determination circuit system 644, first example drive operation control circuit system 648, second example current driver control circuit system 652, second example drive operation control circuit system 656, example step time counter 660, example drive time counter 664, example fast decay time counter 668, example per-step duty cycle determination circuit system 672, example duty cycle averaging circuit system 676, example storage device 678, first example average 680, second example average 682, third example average 684, example error amplifier circuit system 686, example low-pass filter 688, example threshold circuit system 690, and example peak current control circuit system 694 and / or more generally Figure 6The example controller circuitry 155 can be implemented alone by hardware or by a combination of hardware with software and / or firmware. Thus, for example, the example clock circuitry 604, the example step incrementer 608, the example motor control characteristics 612, the example in-quadrant step values 616, the example peak current values 620, the first example current driver control circuitry 624, the example step indexer circuitry 628, the example step current determination circuitry 632, the example inductor current determination circuitry 636, the example PID control circuitry 640, the example operating mode determination circuitry 644, the first example drive operation control circuitry 648, the second example current driver control circuitry 652, the second example drive operation control circuitry 656, the example step time counter 660, the example drive time counter 664, the example fast decay time counter 668, the example per-step duty cycle determination circuitry 672, the example duty cycle averaging circuitry 676, the example storage device 678, the first example average 680, the second example average 682, the third example average 684, the example error amplifier circuitry 686, the example low-pass filter 688, the example threshold circuitry 690, and the example peak current control circuitry 694 and / or more generally the example controller circuitry 155, can be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs) (e.g., FPGAs). Further, in addition to or instead of Figure 6 those elements shown, Figure 6 the example controller circuitry 155 can also include one or more elements, processes, and / or devices, and / or can include more than one of any or all of the shown elements, processes, and devices.

[0155] Figure 9A and 9B FIGS. show flowcharts representative of example machine-readable instructions that can cause programmable circuitry to implement and / or instantiate Figure 6 the controller circuitry 155, and / or representative of example operations that can be performed by programmable circuitry to implement and / or instantiate Figure 6 the controller circuitry 155 of FIGS.. The machine-readable instructions can be one or more executable programs or a portion of one or more executable programs for execution by programmable circuitry, such as the programmable circuitry 1012 shown in the example processor platform 1000 discussed below in connection with Figure 10 and / or can be the Figure 11One or more functions or portions of functions to be performed by an example programmable circuit system (e.g., FPGA) discussed in and / or with 12. In some instances, machine-readable instructions cause operations, tasks, etc. to be carried out and / or executed in an automated manner in the real world. As used herein, "automated" means without human intervention.

[0156] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or discs (e.g., Blu-ray discs, compact discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.) and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by a programmable circuit system located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware other than the programmable circuit system. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between the server and the endpoint client hardware device. Similarly, the non-transitory computer-readable storage media may comprise one or more media. Additionally, while reference Figure 9A and 9BThe flowchart shown describes an example program, but many other methods may alternatively be used to implement the example controller circuitry 155. For example, the order of execution of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuitry, etc.) structured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed at different network locations and / or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, the programmable circuitry may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate enclosures), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple sub-processors distributed across one or more server racks, etc., and / or any combination thereof.

[0157] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.)) or a data structure (e.g., a portion of an instruction, code, a representation of code, etc.), the data being usable to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations of a network or network collection (e.g., in the cloud, at an edge device, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpackaged, distributed, reassigned, compiled, etc. in order to be directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts, the parts being individually compressed, encrypted, and / or stored on separate computing devices, where the parts form a set of machine-executable and / or machine-executable instructions when decrypted, decompressed, and / or combined, the instructions performing one or more functions and / or operations that may together form, for example, a program as described herein.

[0158] In another example, the machine-readable instructions may be stored in a state in which they are readable by a programmable circuitry, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc. may need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, it may be necessary to configure the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions and / or one or more corresponding programs can be executed in whole or in part. Thus, the machine-readable, computer-readable, and / or machine-readable media used herein may include instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs.

[0159] The machine-readable instructions described herein may be represented in any past, current, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any one of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0160] As mentioned above, Figure 9A and 9BExample operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagated signals and to exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., an extended period of time, permanently, briefly, temporarily buffered, and / or cached). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for retaining information for a period of time, but to exclude propagated signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or which is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0161] Figure 10 is a block diagram of an example programmable circuit system platform 1000, the example programmable circuit system platform being configured to implement and / or instantiate example machine-readable instructions and / or execute Figure 9A and 9B example operations of Figure 6 to implement the LED driver circuitry 155 of TM The programmable circuit system platform 1000 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smartphone, a tablet computer such as an iPad TM ), a personal digital assistant (PDA), an Internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a head-mounted device (e.g., an augmented reality (AR) head-mounted device, a virtual reality (VR) head-mounted device, etc.), or any other wearable device, or any other type of computing and / or electronic device.

[0162] The programmable circuit system platform 1000 of the illustrated example includes a programmable circuit system 1012. The programmable circuit system 1012 of the illustrated example is hardware. For example, the programmable circuit system 1012 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 1012 can be implemented by one or more semiconductor (e.g., silicon-based) devices. In this example, the programmable circuit system 1012 implements an example clock circuit system 604, an example step incrementer 608, a first example current driver control circuit system 624, an example step indexer circuit system 628, an example step current determination circuit system 632, an example inductor current determination circuit system 636, an example PID control circuit system 640, an example operation mode determination circuit system 644, a first example drive operation control circuit system 648, a second example current driver control circuit system 652, a second example drive operation control circuit system 656, an example step time counter 660, an example drive time counter 664, an example fast decay time counter 668, an example per-step duty cycle determination circuit system 672, an example duty cycle averaging circuit system 676, an example storage device 678, a first example average value 680, a second example average value 682, a third example average value 684, an example error amplifier circuit system 686, an example low pass filter 688, an example threshold circuit system 690, and an example peak current control circuit system 694.

[0163] The programmable circuit system 1012 of the illustrated example includes local memory 1013 (e.g., cache, registers, etc.). The programmable circuit system 1012 of the illustrated example communicates with a main memory 1014, 1016 that includes volatile memory 1014 and non-volatile memory 1016 via a bus 1018. The volatile memory 1014 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic random access memory ( ), and / or any other type of RAM device. The non-volatile memory 1016 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 of the illustrated example is controlled by a memory controller 1017. In some examples, the memory controller 1017 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer for managing data flow to and from the main memory 1014, 1016.

[0164] The programmable circuit system platform 1000 of the illustrated example also includes an interface circuit system 1020. The interface circuit system 1020 can be implemented by hardware that conforms to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0165] In the illustrated example, one or more input devices 1022 are connected to the interface circuit system 1020. The input devices 1022 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit system 1012. The input devices 1022 can be implemented by, for example, audio sensors, microphones, cameras (static or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, and / or voice recognition systems.

[0166] One or more output devices 1024 are also connected to the interface circuit system 1020 of the illustrated example. The output devices 1024 can be implemented by, for example, display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-plane switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. Thus, the interface circuit system 1020 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processing circuit system such as a GPU.

[0167] The interface circuit system 1020 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) via a network 1026. The communication can be performed via, for example, an Ethernet connection, a Digital Subscriber Line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular phone system, an optical connection, etc.

[0168] The programmable circuit system platform 1000 of the illustrated example also includes one or more mass storage disks or devices 1028 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1028 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0169] Can be by Figure 9A and 9BThe machine-readable instructions 1032 implemented by the machine-readable instructions can be stored in the mass storage device 1028, the volatile memory 1014, the non-volatile memory 1016, and / or at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0170] Figure 11 is Figure 10 A block diagram of an example implementation of the programmable circuitry 1012. In this example, Figure 10 the programmable circuitry 1012 is implemented by the microprocessor 1100. For example, the microprocessor 1100 can be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuitry). The microprocessor 1100 executes Figure 9A and 9B some or all of the machine-readable instructions of the flowchart to effectively instantiate Figure 6 the circuitry as a logic circuit for performing operations corresponding to those machine-readable instructions. In some such examples, Figure 6 the circuitry is instantiated by the hardware circuitry of the microprocessor 1100 in combination with the machine-readable instructions. For example, the microprocessor 1100 can be implemented by a multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it can include any number of example cores 1102 (e.g., 1 core), the microprocessor 1100 of this example is a multi-core semiconductor device including N cores. The cores 1102 of the microprocessor 1100 can operate independently or can cooperate to execute the machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 1102, or can be executed by multiple ones of the cores 1102 at the same or different times. In some examples, the machine code corresponding to a firmware program, an embedded software program, or a software program is split into threads and executed in parallel by two or more of the cores 1102. The software program can correspond to part or all of the machine-readable instructions and / or operations represented by Figure 9A and 9B the flowchart.

[0171] The core 1102 can communicate via the first example bus 1104. In some instances, the first bus 1104 can be implemented by a communication bus to enable communication associated with one or more of the cores 1102. For example, the first bus 1104 can be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1104 can be implemented by any other type of computing or electrical bus. The core 1102 can obtain data, instructions, and / or signals from one or more external devices via the example interface circuitry 1106. The core 1102 can output data, instructions, and / or signals to one or more external devices via the interface circuitry 1106. Although the core 1102 of this example includes an example local memory 1120 (e.g., a level 1 (L1) cache, which can be split into an L1 data cache and an L1 instruction cache), the microprocessor 1100 also includes an example shared memory 1110 (e.g., a level 2 (L2) cache) that can be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from the shared memory 1110. The local memory 1120 and the shared memory 1110 of each core 1102 can be part of a storage device hierarchy that includes multiple levels of cache memory and main memory (e.g., Figure 10 main memories 1014, 1016). Generally, higher-level memories in the hierarchy exhibit shorter access times and have smaller storage capacities compared to lower-level memories. Changes to the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0172] Each core 1102 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1102 includes control unit circuitry 1114, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 1116, multiple registers 1118, local memory 1120, and a second example bus 1122. Other structures may exist. For example, each core 1102 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / jump unit circuitry, floating point unit (FPU) circuitry, etc. The control unit circuit 1114 includes semiconductor-based circuitry configured to control (e.g., coordinate) data movement within the corresponding core 1102. The AL circuitry 1116 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1102. Some examples of the AL circuitry 1116 perform integer-based operations. In other examples, the AL circuitry 1116 also performs floating point operations. In still other examples, the AL circuitry 1116 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating point operations. In some examples, the AL circuitry 1116 may be referred to as an arithmetic logic unit (ALU).

[0173] The registers 1118 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more operations performed by the AL circuitry 1116 of the corresponding core 1102. For example, the registers 1118 may include vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1118 may be arranged in groups, as Figure 11 shown. Alternatively, the registers 1118 may be organized in any other arrangement, format, or structure, such as in a manner that is distributed within the core 1102 to reduce access time. The second bus 1122 may be implemented by at least one of an I2C bus, an API bus, a PCI bus, or a PCIe bus.

[0174] Each core 1102 and / or more generally the microprocessor 1100 may include additional and / or alternative structures of those shown and described above. For example, there may be one or more clock circuit systems, one or more power supplies, one or more power gates, one or more cache coherence agents (CHA), one or more convergence / common mesh stoppers (CMS), one or more shifters (e.g., barrel shifters), and / or other circuit systems. The microprocessor 1100 is a semiconductor device manufactured to include many transistors interconnected to implement the structures described above in one or more integrated circuit systems (ICs) included in one or more packages.

[0175] The microprocessor 1100 may include one or more accelerators (e.g., acceleration circuit systems, hardware accelerators, etc.) and / or cooperate therewith. In some instances, the accelerator is implemented by logic circuit systems to perform certain tasks more quickly and / or efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on-board the microprocessor 1100, in the same chip package as the microprocessor 1100, and / or in one or more separate packages from the microprocessor 1100.

[0176] Figure 12 is Figure 10 A block diagram of another example implementation of the programmable circuit system 1012. In this example, the programmable circuit system 1012 is implemented by the FPGA circuit system 1200. For example, the FPGA circuit system 1200 may be implemented by an FPGA. For example, the FPGA circuit system 1200 may be used to perform operations that may be otherwise implemented by the example microprocessor 1100 of Figure 11 by executing corresponding machine-readable instructions. However, once configured, the FPGA circuit system 1200 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware and can thus generally perform the operations / functions more quickly compared to when the operations / functions may be performed by a general-purpose microprocessor executing corresponding software.

[0177] More specifically, compared to the microprocessor 1100 described above Figure 11 which is a general-purpose device that can be programmed to execute some or all of the machine-readable instructions represented by the flowcharts of Figure 9A and 9B but whose interconnects and logic circuits are fixed once manufactured, Figure 12 the example FPGA circuit system 1200 of Figure 9A and 9BSome or all of the operations / functions corresponding to the machine-readable instructions represented by the flowchart. Specifically, the FPGA circuitry 1200 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected via the interconnects, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuitry 1200 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuitry. Those operations can correspond to some or all of the instructions (e.g., software and / or firmware) represented by Figure 9A and 9B the flowchart. Thus, the FPGA circuitry 1200 can be configured and / or constructed to effectively instantiate some or all of the operations / functions corresponding to the machine-readable instructions of Figure 9A and 9B the flowchart as dedicated logic circuits to perform the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, the FPGA circuitry 1200 can perform the operations / functions faster compared to a general-purpose microprocessor executing some or all of the operations / functions corresponding to the machine-readable instructions of Figure 9A and 9B .

[0178] In an Figure 12 instance, the FPGA circuitry 1200 is configured and / or constructed in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some instances, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in the HDL; the code / program can be transformed into a low-level language as needed; and the code / program (e.g., the code / program in the low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some instances, Figure 12 the FPGA circuitry 1200 can access and / or load the binary file to cause Figure 12 the FPGA circuitry 1200 to be configured and / or constructed to implement one or more operations / functions. For example, the binary file can be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible by Figure 12 the FPGA circuitry 1200 to cause the configuration and / or construction of Figure 12 the FPGA circuitry 1200 or a portion thereof.

[0179] In some instances, binary files are compiled, generated, transformed, and / or otherwise output from a unified software platform for programming an FPGA. For example, the unified software platform can transform first instructions (e.g., code or programs) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in HDL. In some such instances, the binary files are compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some instances, Figure 12 the FPGA circuitry 1200 can access and / or load the binary file(s) such that Figure 12 the FPGA circuitry 1200 is configured and / or constructed to implement one or more operations / functions. For example, the binary file(s) can be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to Figure 12 the FPGA circuitry 1200 to effect the configuration and / or construction of Figure 12 the FPGA circuitry 1200 or portions thereof.

[0180] Figure 12 The FPGA 1200 includes an example input / output (I / O) circuitry 1202 to obtain data from and / or output data to an example configuration circuitry 1204 and / or external hardware 1206. For example, the configuration circuitry 1204 can be implemented by an interface circuitry that can obtain a binary file that can be implemented by a bitstream, data, and / or machine-readable instructions to configure the FPGA circuitry 1200 or portions thereof. In some such instances, the configuration circuitry 1204 can obtain the binary file from a user, a machine (e.g., a hardware circuitry that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file (e.g., a programmable or dedicated circuitry)), etc. and / or any combination thereof. In some instances, the external hardware 1206 can be implemented by an external hardware circuitry. For example, the external hardware 1206 can be implemented by Figure 11 the microprocessor 1100.

[0181] The FPGA circuitry 1200 also includes an example logic gate circuitry 1208, an array of multiple example configurable interconnects 1210, and an example storage circuitry 1212. The logic gate circuitry 1208 and the configurable interconnects 1210 can be configured to instantiate that can be associated with Figure 9A and 9Bat least some of the corresponding one or more operations / functions in the machine-readable instructions, and / or other desired operations. Figure 12 The illustrated logic gate circuit system 1208 is fabricated in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into a logic circuit. In some instances, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide the basic building blocks for the logic circuit. Electrically controlled switches (e.g., transistors) are present within each logic gate circuit system 1208 to implement the configuration of the electrical structures and / or logic gates, thereby forming a circuit system for performing the desired operations / functions. The logic gate circuit system 1208 may include other electrical structures, such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0182] The configurable interconnect 1210 of the illustrated example is a conductive path, trace, via, etc. that can include electrically controlled switches (e.g., transistors), and the state of the switches can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 1208 to program the desired logic circuit.

[0183] The illustrated example's storage circuit system 1212 is configured to store the results of one or more operations performed by the corresponding logic gates. The storage circuit system 1212 can be implemented by registers, etc. In the illustrated example, the storage circuit system 1212 is distributed among the logic gate circuit systems 1208 to facilitate access and improve execution speed.

[0184] Figure 12 The example FPGA circuit system 1200 also includes an example dedicated operation circuit system 1214. In this example, the dedicated operation circuit system 1214 includes a dedicated circuit system 1216 that can be called to implement common functions, thus eliminating the need to program those functions in the field. Examples of such dedicated circuit systems 1216 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiply-accumulate circuit systems. Other types of dedicated circuit systems may exist. In some instances, the FPGA circuit system 1200 may also include an example general-purpose programmable circuit system 1218, such as an example CPU 1220 and / or an example DSP 1222. Additionally or alternatively, there may be other general-purpose programmable circuit systems 1218 that can be programmed to perform other operations, such as GPUs, XPU, etc.

[0185] Although Figure 11 and 12 illustrate Figure 10Two example implementations of the programmable circuit system 1012 are shown, but many other approaches are conceivable. For example, an FPGA circuit system may include an on-board CPU, such as one or more of the example CPUs 1220 shown in Figure 12 . Thus, Figure 10 the programmable circuit system 1012 may alternatively be implemented by at least combining Figure 11 the example microprocessor 1100 shown in Figure 12 with the example FPGA circuit system 1200 shown in Figure 11 . In some such hybrid instances, Figure 9A one or more cores 1102 of 9B may execute a first portion of machine-readable instructions represented by the flowcharts of Figure 12 and Figure 9A to perform a first operation / function, 9B the FPGA circuit system 1200 of Figure 9A and 9B may be configured and / or constructed to perform a second operation / function corresponding to a second portion of machine-readable instructions represented by the flowcharts of

[0186] , and / or an ASIC may be configured and / or constructed to perform a third operation / function corresponding to a third portion of machine-readable instructions represented by the flowcharts of Figure 6 and Figure 11 . It should be understood, therefore, that Figure 12 some or all of the circuit systems of

[0187] may be instantiated at the same or different time instances. For example, Figure 6 the same and / or different portions of the microprocessor 1100 of Figure 11 may be programmed to execute portions of machine-readable instructions at the same and / or different times. In some instances, Figure 12 the same and / or different portions of the FPGA circuit system 1200 of Figure 6 may be configured and / or constructed to perform operations / functions corresponding to portions of machine-readable instructions at the same and / or different times. Figure 11 In some instances,

[0188] some or all of the circuit systems of Figure 10The programmable circuit system 1012 can be in one or more packages. For example, Figure 11 the microprocessor 1100 and / or Figure 12 the FPGA circuit system 1200 can be in one or more packages. In some instances, the XPU can be implemented by Figure 10 the programmable circuit system 1012, which can be in one or more packages. For example, the XPU can include a CPU in one package (e.g., Figure 11 the microprocessor 1100, Figure 12 the CPU 1220, etc.), a DSP in another package (e.g., Figure 12 the DSP 1222), a GPU in yet another package, and an FPGA in still another package (e.g., Figure 12 the FPGA circuit system 1200).

[0189] "Comprising" and "including" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "comprising" or "including" (e.g., comprises, comprising, includes, including, having, etc.) as a lead-in or in any type of claim recitation, it should be understood that additional elements, terms, etc. may exist without falling outside the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transitional term in, for example, the lead-in of a claim, it is open-ended in the same manner as the terms "comprising" and "including". The term "and / or" when used in the form of, for example, A, B, and / or C means any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" is intended to mean an embodiment that includes any one of the following: (1) at least one A; (2) at least one B; or (3) at least one A and at least one B. Similarly, the phrase "at least one of A or B" as used herein in the context of describing a structure, component, item, object, and / or thing means an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. The phrase "at least one of A and B" as used herein in the context of describing the conduct or performance of a process, instruction, action, activity, etc. means an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the phrase "at least one of A or B" as used herein in the context of describing the conduct or performance of a process, instruction, action, activity, etc. means an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0190] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object means one or more of the objects. The terms "a (or an)", "one or more", and "at least one" may be used interchangeably herein. Further, although listed separately, a plurality of components, elements, or acts may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different instances or claims, these features may be combined, and inclusion in different instances or claims does not imply that the combination of features is not feasible and / or advantageous.

[0191] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. If there is at least one part of the second part between the earth and the first part, the first part is above the second part. Similarly, as used herein, when the first part is closer to the earth than the second part, the first part is "below" the second part. As mentioned above, the first part can be above or below the second part, with one or more of the following cases: there are other parts therebetween, there are no other parts therebetween, the first and second parts are in contact, or the first and second parts do not directly contact each other.

[0192] As used herein, in this patent, stating that any part (such as a layer, film, region, zone or plate) is located on another part in any manner (such as on it, positioned on it, disposed on it or formed on it, etc.) indicates that the part being referred to is in contact with the other part, or the part being referred to is above the other part, with one or more intermediate parts positioned therebetween.

[0193] As used herein, unless otherwise specified, connection references (such as attach, couple, connect and join) can include intermediate components between the elements referred to by the connection reference and / or relative movement between those elements. Thus, a connection reference does not necessarily infer that two elements are directly connected and / or in a fixed relationship with each other. As used herein, stating that any part "contacts" another part is defined to mean that there are no intermediate parts between the two parts.

[0194] Unless otherwise specifically stated, descriptive terms such as "first", "second", "third", etc. used herein do not imply or otherwise indicate a priority, physical order, meaning of arrangement, and / or any way of sorting in a list, but are only used as labels and / or arbitrary names to distinguish elements, for the convenience of understanding the described examples. In some examples, the descriptive term "first" can be used to refer to an element in a specific embodiment, while the same element can be referred to by different descriptive terms such as "second" or "third" in a technical solution. In such cases, it should be understood that these descriptors are only used to clearly identify those elements within the context of the discussion (such as within a claim), where the elements may, for example, otherwise share the same name.

[0195] As used herein, "substantially" and "about" modify their subject / value to identify the potential existence of variations that occur in real-world applications. For example, as would be understood by one of ordinary skill in the art, "approximate" and "about" can modify dimensions and / or empirical values that may be imprecise due to manufacturing tolerances and / or other real-world defects. For example, unless otherwise specified herein, "approximate" and "about" can indicate that such dimensions can be within a tolerance range of + / - 10%.

[0196] As used herein, "substantially real-time" means occurring in a near-instantaneous manner, recognizing that there may be delays in computing time, transmission, etc. in the real world. Thus, unless otherwise specified, "substantially real-time" means real-time + 1 second.

[0197] As used herein, the phrase "communicate" and its variants encompass direct communication and / or indirect communication through one or more intermediate components, and do not require direct physical (e.g., wired) communication and / or continuous communication, but rather additionally encompass selective communication at periodic intervals, predetermined intervals, aperiodic intervals, and / or one-time events.

[0198] As used herein, "programmable circuitry" is defined to include the following: (i) one or more dedicated circuits (e.g., application-specific integrated circuits (ASICs)) that are configured to perform one or more specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions and / or one or more operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as: a central processing unit (CPU) that can execute a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to configure and / or structure the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technique (e.g., an application programming interface (API)) that can allocate computing tasks to any one of the multiple types of programmable circuitry that is suitable and available to execute the computing task.

[0199] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-chip (SoC), etc.

[0200] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0201] In this specification, the term "coupled" may encompass a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0202] Numeric identifiers such as "first", "second", "third", etc. are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description do not necessarily conform to those used in the claims.

[0203] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnects of the device, or a combination thereof.

[0204] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their ends.

[0205] A circuit or apparatus described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuitry or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0206] The circuits described herein may be reconfigured to include replacement components to provide at least partially similar functionality to that available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may in fact be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0207] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise indicated, "about", "substantially", or "essentially" in front of a parameter means within a range of + / - 10% of the stated parameter.

[0208] Within the scope of the claims, the described examples may be modified, and other examples are possible.

Claims

1. A device comprising: current driver circuitry configured to supply power to the stepper motor; as well as a controller circuit system coupled to the current driver circuit system, the controller circuit system being configured to: determining a first duty cycle of power delivered by the current driver circuitry to the stepper motor during a first operation of the stepper motor, the first operation supplying power using a current of a target magnitude; determining a previous duty cycle of power delivered by the current driver circuitry to the stepper motor during a second operation of the stepper motor, the second operation of the stepper motor supplying power using a current of the target magnitude; as well as A change in a mechanical load applied to the stepper motor is determined in response to a comparison of the first duty cycle to the previous duty cycle.

2. The apparatus of claim 1 , wherein the controller circuit system is further configured to determine the first duty cycle using a first duration, a second duration, and a third duration, wherein the first duration represents a time during which current is supplied to the stepper motor in a first direction, the second duration represents a time during which current is supplied to the stepper motor in a second direction, and the third duration represents a total duration of the first operation, the first direction being opposite to the second direction.

3. An apparatus according to claim 1, wherein the first operation uses a current supply power of multiple target currents, the previous duty cycle of the power delivered to the stepper motor during operation is configured to supply currents of the multiple target currents, and the second operation uses a current supply power of the multiple target currents.

4. The apparatus of claim 1 , wherein the controller circuitry is further configured to determine the target amplitude using a peak current representing the amplitude, a step number corresponding to a portion of a sinusoidal waveform supplying power to the stepper motor, and a step number in an operating quadrant of the stepper motor representing the number of portions in a quarter cycle of the sinusoidal waveform. 5 . The apparatus of claim 4 , wherein the controller circuitry is further configured to modify the peak current in response to a difference between the first duty cycle and the previous duty cycle being greater than a threshold.

6. The apparatus of claim 1, wherein the controller circuitry is further configured to determine an increase in the mechanical load applied to the stepper motor in response to the first duty cycle being greater than the previous duty cycle.

7. The apparatus of claim 1, wherein the controller circuitry is further configured to determine a decrease in the mechanical load applied to the stepper motor in response to the first duty cycle being less than the previous duty cycle.

8. At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a programmable circuit system to at least: determining a first duty cycle of power delivered to the stepper motor during a first operation of the stepper motor, the first operation supplying power using a current of a target magnitude; determining a previous duty cycle of power delivered to the stepper motor during a second operation of the stepper motor, The second operation of the stepper motor uses a current supply power of the target magnitude; as well as A change in a mechanical load applied to the stepper motor is determined in response to a comparison of the first duty cycle to the previous duty cycle.

9. At least one non-transitory computer-readable storage medium according to claim 8, wherein the instructions cause the programmable circuit system to determine the first duty cycle in response to determining a first duration, a second duration, and a third duration, wherein the first duration represents a time during which current is supplied to the stepper motor in a first direction, the second duration represents a time during which current is supplied to the stepper motor in a second direction, and the third duration represents a total interval of the first operation, the first direction being opposite to the second direction.

10. At least one non-transitory computer-readable storage medium according to claim 8, wherein the first operation uses current supply power of multiple target currents, the previous duty cycle of power delivered to the stepper motor during operation is configured to supply current of the multiple target currents, and the second operation uses current supply power of the multiple target currents.

11. At least one non-transitory computer-readable storage medium according to claim 8, wherein the instructions cause the programmable circuit system to determine the target amplitude using a peak current, a step number, and a step number in an operating quadrant of the stepper motor, wherein the peak current represents the amplitude, the step number corresponds to a portion of a sinusoidal waveform supplying power to the stepper motor, and the step number in an operating quadrant of the stepper motor represents the number of the portions in a quarter cycle of the sinusoidal waveform.

12. The at least one non-transitory computer-readable storage medium of claim 8, wherein the instructions cause the programmable circuitry to determine an increase in the mechanical load applied to the stepper motor in response to a difference between the first duty cycle and the previous duty cycle being positive.

13. The at least one non-transitory computer-readable storage medium of claim 8, wherein the instructions cause the programmable circuitry to determine a reduction in the mechanical load applied to the stepper motor in response to a difference between the first duty cycle and the previous duty cycle being negative.

14. An apparatus comprising: A duty cycle determination circuit system is configured to: determining a first duty cycle of power delivered to the stepper motor during a first operation of the stepper motor, the first operation supplying power using a current of a target magnitude; as well as determining a second duty cycle for a second operation of the stepper motor, the second operation of the stepper motor being powered by a current supply of the target magnitude; an error amplifier configured to compare the first duty cycle with the second duty cycle; as well as Peak current control circuitry is configured to adjust a peak current of the power supply in response to a comparison of the first duty cycle and the second duty cycle.

15. The apparatus of claim 14, wherein the duty cycle determination circuit system is further configured to determine the first duty cycle in response to determining a first duration, a second duration, and a third duration, wherein the first duration represents a time during which current is supplied to the stepper motor in a first direction, the second duration represents a time during which current is supplied to the stepper motor in a second direction, and the third duration represents a total interval of the first operation, the first direction being opposite to the second direction.

16. The apparatus of claim 14, wherein the first operation supplies power using a plurality of target currents, the second duty cycle of the power delivered to the stepper motor during operation is configured to supply currents of the plurality of target currents, and the second operation supplies power using the plurality of target currents.

17. The apparatus of claim 14, further comprising a current driver control circuit system configured to determine the target amplitude using the peak current, a step number, and a step number in an operating quadrant of the stepper motor, wherein the peak current represents the amplitude, the step number corresponds to a portion of a sinusoidal waveform supplying power to the stepper motor, and the step number in an operating quadrant of the stepper motor represents the number of portions in a quarter cycle of the sinusoidal waveform.

18. The apparatus of claim 14, wherein the second duty cycle is an average duty cycle of power delivered to the stepper motor during operation configured to supply the current of the target magnitude using the first duty cycle and the second duty cycle.

19. The apparatus of claim 14, further comprising threshold circuitry configured to determine an increase in a mechanical load applied to the stepper motor in response to a difference between the first duty cycle and the second duty cycle being positive.

20. The apparatus of claim 14, further comprising threshold circuitry configured to determine a decrease in a mechanical load applied to the stepper motor in response to a difference between the first duty cycle and the second duty cycle being negative.

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