Doherty amplifier circuit and semiconductor device

Abstract

The invention provides a Doherty amplifier circuit and a semiconductor device. A Doherty amplifier circuit is provided with: a distributor that distributes an input signal that is input into a first signal and a second signal; a circuit board; a first amplifier which is provided on the circuit board, amplifies the first signal, and outputs the amplified signal as a fourth signal; a second amplifier which is provided on the circuit board, amplifies the second signal, and outputs the amplified signal as a fifth signal; a combining node combining the fourth signal and the fifth signal, and outputting the combined signal as an output signal to an output terminal; an open stub, an end of which is electrically connected to a path between the distributor and the first amplifier; the first end of the first impedance transformer is electrically connected to the second amplifier, and the second end of the first impedance transformer is electrically connected to the synthesis node.

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device. Background Art

[0002] There is known an N-way (N ≥ 3) Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Document 1 and Patent Document 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent No. 8,022,760 Specification

[0006] Patent Document 2: U.S. Patent No. 10,601,375 Specification

[0007] However, in a Doherty amplifier circuit, an impedance transformer is provided at the subsequent stage of either the main amplifier or the peak amplifier. In order to adjust the phase lag caused by the impedance transformer, a phase adjuster is provided at the preceding stage of either the main amplifier or the peak amplifier. Therefore, it becomes large-sized. Summary of the Invention

[0008] An object of the present disclosure is to achieve miniaturization.

[0009] One embodiment of the present disclosure is a Doherty amplifier circuit including: a splitter that splits an input signal input thereto into a first signal and a second signal; a circuit board; a first amplifier provided on the circuit board that amplifies the first signal and outputs the amplified signal as a fourth signal; a second amplifier provided on the circuit board that amplifies the second signal and outputs the amplified signal as a fifth signal; a combining node that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal; an open stub provided on the circuit board, an end of the open stub being electrically connected to a path between the splitter and the first amplifier; and a first impedance transformer provided on the circuit board, a first end of the first impedance transformer being electrically connected to the second amplifier and a second end of the first impedance transformer being electrically connected to the combining node.

[0010] One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit, comprising: a first input terminal for inputting a first signal obtained by distributing an input signal to be input; a second input terminal for inputting a second signal obtained by distributing the input signal; a first amplifier for amplifying the first signal and outputting the amplified signal as a fourth signal; a second amplifier for amplifying the second signal and outputting the amplified signal as a fifth signal; a first output terminal for outputting the fourth signal; a second output terminal for outputting the fifth signal; and a terminal connected to a line between the first input terminal and the first amplifier, to which an open stub for adjusting the phase of the first signal can be connected.

[0011] Advantages of the Invention

[0012] According to the present disclosure, the Doherty amplifier circuit or the semiconductor device for the Doherty amplifier circuit can be miniaturized. Description of the Drawings

[0013] Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0014] Figure 2 It is a top view of the semiconductor device of Embodiment 1.

[0015] Figure 3 It is a top view of the circuit board of Embodiment 1.

[0016] Figure 4 It is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Embodiment 1.

[0017] Figure 5 It is a block diagram of the Doherty amplifier circuit of Comparative Example 1.

[0018] Figure 6 It is a top view of the semiconductor device of Comparative Example 1.

[0019] Description of Reference Numerals:

[0020] 10 (first amplifier): main amplifier;

[0021] 12 (second amplifier), 14 (third amplifier): peak amplifiers;

[0022] 16: distributor;

[0023] 18: combiner;

[0024] 20a, 20b, 20c: semiconductor chips;

[0025] 21a, 21b, 21c: Substrate;

[0026] 22a, 22b, 22c, 23a, 23b, 23c: Pad;

[0027] 24a, 24b, 24c: Capacitive component;

[0028] 25: Dielectric substrate;

[0029] 26: Electrode;

[0030] 27a (First input terminal), 27b (Second input terminal), 27c (Third input terminal), 28a (First output terminal), 28b (Second output terminal), 28c (Third output terminal), 29 (Terminal): Lead;

[0031] 30, 31, 32, 33, 34, 35: Matching circuit;

[0032] 36, 37, 38, 39: Bias circuit;

[0033] 46, 47, 48, 49: Bonding wire;

[0034] 50: Package;

[0035] 51: Substrate;

[0036] 52 (First impedance transformer), 53 (Second impedance transformer): Impedance transformer;

[0037] 54: Open - circuited stub;

[0038] 55: Circuit board;

[0039] 56a, 56b, 56c, 57a, 57b, 57c: Line;

[0040] 58: Phase adjuster;

[0041] 59a (First side), 59b (Second side), 59c (Third side), 59d: Side;

[0042] 100, 110: Doherty amplifier circuit;

[0043] 102: Semiconductor device;

[0044] S1 (First signal), S2 (Second signal), S3 (Third signal), S4 (Fourth signal), S5 (Fifth signal), S6 (Sixth signal): Signal;

[0045] N1: Combining node;

[0046] Sin: Input signal;

[0047] Sout: Output signal;

[0048] Tin: Input terminal;

[0049] Tout: Output terminal. Detailed implementation manners

[0050] [Description of the embodiments of the present disclosure]

[0051] First, the content of the embodiments of the present disclosure will be listed for description.

[0052] (1) One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a distributor that distributes an input signal into a first signal and a second signal; a circuit board; a first amplifier disposed on the circuit board, which amplifies the first signal and outputs the amplified signal as a fourth signal; a second amplifier disposed on the circuit board, which amplifies the second signal and outputs the amplified signal as a fifth signal; a combining node that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal; an open stub disposed on the circuit board, the end of the open stub being electrically connected to the path between the distributor and the first amplifier; and a first impedance transformer disposed on the circuit board, a first end of the first impedance transformer being electrically connected to the second amplifier, and a second end of the first impedance transformer being electrically connected to the combining node. Thus, the open stub can be shortened, and thus miniaturization can be achieved.

[0053] (2) In the above (1), it may also be that the Doherty amplifier circuit comprises: a third amplifier disposed on the circuit board, which amplifies a third signal and outputs the amplified signal as a sixth signal; and a second impedance transformer disposed on the circuit board, a first end of the second impedance transformer being electrically connected to the third amplifier, and a second end of the second impedance transformer being electrically connected to the combining node, the distributor distributes the input signal into the first signal, the second signal, and the third signal, and the combining node combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as the output signal to the output terminal. Thus, miniaturization can be achieved.

[0054] (3) In the above (1) or (2), it may also be that no impedance transformer is provided between the first amplifier and the combining node. Thus, the phases at the combining node can be made consistent.

[0055] (4) In any one of the above (1) to (3), it is also possible that the first amplifier is a main amplifier and the second amplifier is a peak amplifier. Thus, broadband can be achieved.

[0056] (5) In any one of the above (1) to (4), it is also possible that the first amplifier and the second amplifier are arranged in a first direction, the first impedance transformer is disposed adjacent to the second amplifier in a second direction intersecting the first direction, and the open stub is disposed adjacent to the first amplifier in the first direction. Thus, the width of the circuit board in the second direction can be reduced.

[0057] (6) In any one of the above (1) to (5), it is also possible that the Doherty amplifier circuit includes: a package on which the first amplifier and the second amplifier are mounted and installed on the circuit board, and the open stub and the first impedance transformer are not mounted on the package. Thus, the first amplifier, the second amplifier, the open stub, and the first impedance transformer can be disposed on the circuit board.

[0058] (7) In any one of the above (1) to (6), it is also possible that the first impedance transformer is a 1 / 4 wavelength line of the center frequency of the operating band, and the open stub is a 1 / 8 wavelength line of the center frequency of the operating band. Thus, the phases of the fourth signal and the fifth signal at the combining node can be made consistent.

[0059] (8) An embodiment of the present disclosure is a semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, and includes: a first input terminal for inputting a first signal obtained by distributing an input signal to be input; a second input terminal for inputting a second signal obtained by distributing the input signal; a first amplifier for amplifying the first signal and outputting the amplified signal as a fourth signal; a second amplifier for amplifying the second signal and outputting the amplified signal as a fifth signal; a first output terminal for outputting the fourth signal; a second output terminal for outputting the fifth signal; and a terminal connected to the line between the first input terminal and the first amplifier, and an open stub for adjusting the phase of the first signal can be connected thereto. Thus, miniaturization can be achieved.

[0060] (9) In the above (8), it is also possible that the semiconductor device includes: a third input terminal for inputting a third signal obtained by distributing the input signal; a third amplifier for amplifying the third signal and outputting the amplified signal as a sixth signal; and a third output terminal for outputting the sixth signal. Thus, miniaturization can be achieved.

[0061] (10) In the above (8) or (9), it may also be that the semiconductor device includes: a package on which the first amplifier and the second amplifier arranged in the first direction are mounted, the first input terminal and the second input terminal are provided on the first side of the package that faces the second side in the second direction intersecting the first direction, the first output terminal and the second output terminal are provided on the second side of the package, the terminal is provided on the third side connecting the first side and the second side, and the first amplifier is closer to the third side than the second amplifier. Thus, the electrical length between the path between the first input terminal and the first amplifier and the open stub can be shortened.

[0062] [Details of Embodiments of the Present Disclosure]

[0063] Hereinafter, with reference to the drawings, specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0064] [Example 1]

[0065] As a Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 It is a block diagram of the Doherty amplifier circuit of Example 1.

[0066] As shown in Figure 1 , in the Doherty amplifier circuit 100, a main amplifier 10 (first amplifier), a peak amplifier 12 (second amplifier), and a peak amplifier 14 (third amplifier) are connected in parallel between a distributor 16 and a combiner 18. Thus, the Doherty amplifier circuit 100 is a three-way (3-way) amplifier circuit. The Doherty amplifier circuit may also be an N-way (N-way) Doherty amplifier circuit having one or three or more peak amplifiers.

[0067] The high-frequency signal is input as an input signal Sin to the input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). The distributor 16 is, for example, a Wilkinson-type distributor.

[0068] The path of the input signal S1 includes an open stub 54, a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path of the input signal S2 includes a matching circuit 31, a bias circuit 37, a peak amplifier 12, and a matching circuit 34. The path of the input signal S3 includes a matching circuit 32, a bias circuit 38, a peak amplifier 14, and a matching circuit 35.

[0069] The matching circuits 30 to 32 match the impedances when looking at the matching circuits 30 to 32 from the distributor 16 respectively with the impedances when looking at the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 from the matching circuits 30 to 32 respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively.

[0070] The open stub 54 adjusts the phase of the signal S1 to adjust the phases of the signals S5, S6, and S4 that are changed by the impedance transformers 52 and 53. The open stub 54 is a transmission line such as a microstrip line or a coplanar line with an open end, and is, for example, a 1 / 8 wavelength line at the center frequency of the operating frequency band.

[0071] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 amplify the signals S1, S2, and S3 respectively, and output the amplified signals S4 (the fourth signal), S5 (the fifth signal), and S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. The matching circuits 33 to 35 match the impedances when looking at the matching circuits 33 to 35 from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively with the impedances when looking at the synthesizer 18 from the matching circuits 33 to 35 respectively.

[0072] The synthesizer 18 includes a synthesis node N1, an impedance transformer 52, and an impedance transformer 53. The first end of the impedance transformer 52 is electrically connected to the peak amplifier 12 via the matching circuit 34, and the second end of the impedance transformer 52 is electrically connected to the synthesis node N1. The first end of the impedance transformer 53 is electrically connected to the peak amplifier 14 via the matching circuit 35, and the second end of the impedance transformer 53 is electrically connected to the synthesis node N1. The synthesis node N1 synthesizes the signals S4 to S6, and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0073] The impedance transformers 52 and 53 transform the impedance on the real axis of the Smith chart when looking from the matching circuits 34 and 35 to the impedance transformers 52 and 53 into: the impedance at different positions on the real axis of the Smith chart when looking from the impedance transformers 52 and 53 to the synthesis node N1. Further, when the peak amplifier 12 is not operating, the impedance transformer 52 sets the impedance when looking from the synthesis node N1 to the peak amplifier 12 to infinity. When the peak amplifier 14 is not operating, the impedance transformer 53 sets the impedance when looking from the synthesis node N1 to the peak amplifier 14 to infinity.

[0074] The impedance transformers 52 and 53 are, for example, transmission lines such as microstrip lines or coplanar lines, and are 1 / 4 wavelength lines at the center frequency of the operating frequency band. The electrical length of the 1 / 4 wavelength line may not be strictly 1 / 4 wavelength. The 1 / 4 wavelength line only needs to have an electrical length that functions as the impedance transformers 52 and 53. For example, the electrical length of the 1 / 4 wavelength line may be 3 / 16 wavelength or more and 5 / 16 wavelength or less, or may be 7 / 32 wavelength or more and 9 / 32 wavelength or less. The impedance on the real axis in the Smith chart may not be strictly on the real axis (the reactance component is 0). The absolute value of the reactance component of the impedance may be 0.2 times or less of the resistance component, or may be 0.1 times or less.

[0075] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, the signals S1 to S3 are respectively input to the gates G, and the signals S4 to S6 are respectively output from the drains D.

[0076] Figure 2 is a top view of the semiconductor device of Embodiment 1. In Figure 2 the lid of the package 50 is not shown. The thickness direction of the substrate 51 of the package 50 is set as the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is set as the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is set as the Y direction (the first direction).

[0077] AsFigure 2 As shown, in the semiconductor device 102, the package 50 has a conductive substrate 51 at least on the upper surface. The substrate 51 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the substrate 51. A semiconductor chip 20a to a semiconductor chip 20c and a capacitive component 24a to a capacitive component 24c are mounted on the substrate 51.

[0078] Leads 27a to 27c are provided on the - side in the X direction of the substrate 51 with an insulating layer (not shown) interposed therebetween. Leads 28a to 28c are provided on the + side in the X direction of the substrate 51. A lead 29 is provided on the + side in the Y direction of the substrate 51 with an insulating layer (not shown) interposed therebetween. The leads 27a to 27c and the leads 28a to 28c are, for example, metal layers or metal plates such as copper. Signals S1 to S3 are respectively input to the leads 27a to 27c, and signals S4 to S6 are respectively output from the leads 28a to 28c.

[0079] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and an electrode (not shown) provided on the lower surface of the substrate 21a. The pads 22a, 23a, and the lower - surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and an electrode provided on the lower surface of the substrate 21b. The pads 22b, 23b, and the lower - surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and an electrode provided on the lower surface of the substrate 21c. The pads 22c, 23c, and the lower - surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q3, respectively.

[0080] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates, or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOSs, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, the pads 23a to 23c, and the electrodes on the lower surface are, for example, metal layers such as gold layers. Although the transistor Q1 is shown to be smaller than the transistors Q2 and Q3 (for example, the gate width is smaller, and the saturation power is smaller when the gate bias voltage and the drain bias voltage are the same), the transistor Q1 may also be the same as the transistors Q2 and Q3 (for example, the gate width is the same, and the saturation power is the same when the gate bias voltage and the drain bias voltage are the same).

[0081] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. A capacitor is formed by the electrode 26 and the electrode on the lower surface with the dielectric substrate 25 interposed therebetween. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is, for example, a metal layer such as a gold layer.

[0082] The bonding wires 46 electrically connect the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c, respectively. The bonding wires 47 electrically connect the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c, respectively. The bonding wires 48 electrically connect the pads 23a to 23c and the leads 28a to 28c, respectively. The bonding wire 49 connects the lead 27a and the lead 29. The bonding wires 46 to 49 are, for example, metal wires such as gold wires or aluminum wires.

[0083] The bonding wires 46 and the bonding wires 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bonding wires 46, the bonding wires 47, and the capacitive components 24a to 24c correspond to the matching circuits 30 to 32 of the T-type LCL circuit.

[0084] Figure 3 is a top view of the circuit board of the first embodiment. As Figure 3 shown, a package 50 is mounted on the circuit board 55. On the upper surface of the circuit board 55, there are provided lines 56a to 56c, lines 57a to 57c, an impedance transformer 52, an impedance transformer 53, and an open stub 54. The circuit board 55 is, for example, a resin board such as glass epoxy. The lines 56a to 56c, the lines 57a to 57c, the impedance transformer 52, the impedance transformer 53, and the open stub 54 are metal layers such as copper layers.

[0085] Lines 56a to 56c are electrically connected to leads 27a to 27c respectively. Lines 57a to 57c are electrically connected to leads 28a to 28c respectively. Lines 56a to 56c and lines 57a to 57c extend in the X direction. Impedance transformers 52 and 53 are provided midway between lines 57b and 57c. The impedance transformers 52 and 53 have a desired characteristic impedance and are lines with an electrical length of 1 / 4 wavelength. If the 1 / 4 wavelength line is arranged linearly, it will be long. Therefore, the 1 / 4 wavelength line is formed by folding it in a meandering shape. In Figure 3 it, the appearance of the folded 1 / 4 wavelength line is shown in a rectangular diagram.

[0086] The end of the open stub 54 is electrically connected to the lead 29. The open stub 54 extends in the X direction.

[0087] Figure 4 It is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in the first embodiment.

[0088] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. Each gain is the power gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. It should be noted that Pin and Pout are expressed in dB. The gain of the main amplifier 10 below the power P1 of each gain is greater than the gain of the peak amplifier 12 above the power P1 and below the power P2. That is, the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is greater than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin. However, Figure 4 It is a schematic diagram, and the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is shown as less than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin.

[0089] As Figure 4As shown, when the output power Pout is the power P0, the probability of the modulation wave is the highest. That is, in the case of outputting a modulation wave signal, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A or AB amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin for turning on the peak amplifier 12 is greater than the input power Pin for turning on the main amplifier 10, and the input power Pin for turning on the peak amplifier 14 is greater than the input power Pin for turning on the peak amplifier 12. To operate in this way, it can be achieved by making the gate bias voltage VG2 of the transistor Q2 greater than the gate bias voltage VG1 of the transistor Q1 in the negative direction, and making the gate bias voltage VG3 of the transistor Q3 greater than the gate bias voltage VG2 of the transistor Q2 in the negative direction.

[0090] As the input power Pin of the input signal Sin increases, the input power Pin exceeds the power P0 and reaches up to the power P1. The main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, if the input power Pin increases, the output power Pout of the main amplifier 10 will increase linearly. Therefore, when the input power Pin is below the power P1, each gain and the overall gain are approximately fixed.

[0091] When the input power Pin is above the power P1 and below the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. The main amplifier 10 saturates within this range. Therefore, the gain of the main amplifier 10 decreases. The overall gain also decreases accordingly. The peak amplifier 12 operates in class C, so the gain of the peak amplifier 12 between the power P1 and the power P2 is lower than the gain of the main amplifier 10 below the power P1. In addition, the saturation power of the peak amplifier 12 is less than the saturation power of the main amplifier 10.

[0092] When the input power Pin is above the power P2 and below the power P3, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate. Within this range, in addition to the main amplifier 10, the peak amplifier 12 also saturates. Therefore, the gain of the peak amplifier 12 decreases. The overall gain also decreases accordingly. The operating point of the peak amplifier 14 is greater than that of the peak amplifier 12 in the negative direction, so the gain of the peak amplifier 14 between the power P2 and the power P3 is lower than the gain of the peak amplifier 12 between the power P1 and the power P2. In addition, the saturation power of the peak amplifier 14 is less than the saturation power of the peak amplifier 12.

[0093] When the input power Pin is above the power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 also saturates. Therefore, the gain of the peak amplifier 14 decreases. The overall gain also decreases accordingly.

[0094] The product of the probability and the overall gain corresponds to the gain of the modulation wave. To increase the gain of the modulation wave, the overall gain at Pout with a high probability is increased.

[0095] [Comparative Example 1]

[0096] Figure 5 is a block diagram of the Doherty amplifier circuit of Comparative Example 1. As Figure 5 shown, in the Doherty amplifier circuit 110 of Comparative Example 1, a phase adjuster 58 is provided instead of the open stub 54. The phase adjuster 58 is, for example, a 1 / 4 wavelength line. The phases of the signal S5 and the signal S6 are rotated by 90° by the impedance transformer 52 and the impedance transformer 53. Therefore, the phase adjuster 58 is, for example, a 1 / 4 wavelength line.

[0097] Figure 6 is a top view of the semiconductor device of Comparative Example 1. As Figure 6 shown, in Comparative Example 1, a phase adjuster 58 is provided in the middle of the line 56a instead of the open stub 54.

[0098] In the Doherty amplifier circuit, in the synthesizer 18, the impedance is appropriately changed according to the operating states of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. Therefore, the impedance transformers 52 and 53 are used in any one of the paths between the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 and the synthesis node N1. The impedance transformers 52 and 53 are, for example, 1 / 4 wavelength lines, which rotate the phase by 90°. When the phases of the signals S4 to S6 are inconsistent at the synthesis node N1, when Figure 4 the input power Pin is equal to or higher than the power P1, the overall gain decreases.

[0099] Therefore, a phase adjuster 58 is provided in the path where the impedance transformers 52 and 53 are not provided. As a result, the phases of the signals S4 to S6 are made consistent at the synthesis node N1, and the signals S4 to S6 are synthesized. Thereby, the overall gain can be increased.

[0100] However, for the phase adjuster 58, in order to adjust the phase rotated by 90° in the impedance transformers 52 and 53, it is required to rotate the phase by 90°. Therefore, when a 1 / 4 wavelength line is used as the phase adjuster 58, the Doherty amplifier circuit becomes large-sized.

[0101] [Description of Embodiment 1]

[0102] In the Doherty amplifier circuit 100, the impedance when looking from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 to the combining node N1 is appropriately transformed, and when the peak amplifier 12 and the peak amplifier 14 are not operating, the impedance when looking from the combining node N1 to the peak amplifier 12 and the peak amplifier 14 is set to infinity. Therefore, an impedance converter 52 (first impedance converter) is provided, and a first end of the impedance converter 52 is electrically connected to one of the peak amplifier 12 and the peak amplifier 14, a second amplifier (for example, the peak amplifier 12), and a second end of the impedance converter 52 is electrically connected to the combining node N1. In such a case, as Figure 1 shown, as a phase adjuster, an open stub 54 is provided, and an end of the open stub 54 is electrically connected to a path between one of the main amplifier 10, the peak amplifier 12, and a first amplifier (for example, the main amplifier 10) and the distributor 16. For example, in order to rotate the phase of the signal S1 by 90°, the electrical length of the center frequency of the operating band of the open stub 54 is 1 / 8 wavelength. Thus, as Figure 3 shown, the open stub 54 can be shortened, and therefore, the circuit board 55 can be miniaturized. The peak amplifier 14 and the impedance converter 53 may not be provided.

[0103] The electrical length of the 1 / 8 wavelength line serving as the open stub 54 may not be strictly 1 / 8 wavelength of the center frequency of the operating band, as long as the phases of the signals S4 to S6 can be made consistent. The electrical length of the 1 / 8 wavelength line can be, for example, 3 / 32 wavelength or more and 5 / 32 wavelength or less, or can be 7 / 64 wavelength or more and 9 / 64 wavelength or less.

[0104] When there are two or more peak amplifiers 12 and 14, an impedance converter 53 (second impedance converter) is provided, and a first end of the impedance converter 53 is electrically connected to one of the peak amplifier 12 and the peak amplifier 14, a third amplifier (for example, the peak amplifier 14), and a second end of the impedance converter 53 is electrically connected to the combining node N1. In this case, the phases of both the signal S5 and the signal S6 are rotated by 90°. Thus, the phases of the signals S4 to S6 at the combining node N1 can be made consistent by providing the open stub 54.

[0105] An impedance converter is not provided between the main amplifier 10 and the combining node N1. In this case, the phases of the signals S4 to S6 at the combining node N1 can be made consistent by providing the open stub 54.

[0106] If a 1 / 4 wavelength line is provided as the impedance converter 52 and the impedance converter 53, it is difficult to achieve broadband operation. Therefore, as Figure 4As shown, in order to widen the bandwidth of the main amplifier 10 operating at all input powers Pin, sometimes, as Figure 1 shown, no impedance transformer is provided between the main amplifier 10 and the combining node N1. In such a case, an open stub 54 is connected between the distributor 16 and the main amplifier 10. Thus, the first amplifier is the main amplifier 10, and the second and third amplifiers are the peak amplifiers 12 and 14.

[0107] In Comparative Example 1, as Figure 6 shown, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are arranged in the Y direction (the first direction). The impedance transformers 52 and 53 are provided in the + direction of the X direction (the second direction intersecting the first direction) of the peak amplifiers 12 and 14. The phase adjuster 58 is provided in the - direction of the X direction of the main amplifier 10. Therefore, the width of the circuit board 55 in the X direction becomes larger.

[0108] In Embodiment 1, the open stub 54 is provided in the Y direction of the main amplifier 10. Thus, the width of the circuit board 55 in the X direction can be made smaller. Thus, the circuit board 55 can be miniaturized. The open stub 54 extends in the X direction. Thus, the width of the circuit board 55 in the Y direction can be made smaller.

[0109] As Figure 2 and Figure 3 shown, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are mounted on the package 50. The open stub 54, the impedance transformers 52, and the impedance transformer 53 are not mounted on the package 50 but are provided on the circuit board 55. Thus, by mounting the package 50 on the circuit board 55, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 can be provided on the circuit board 55, and the impedance transformers 52 and 53 can be provided on the circuit board 55.

[0110] The impedance transformers 52 and 53 are quarter-wavelength lines at the center frequency of the operating frequency band. Thus, the impedance transformers 52 and 53 can transform the impedance on the real axis of the Smith chart when looking from the matching circuits 34 and 35 to the impedance transformers 52 and 53 into: the impedance at a different position on the real axis of the Smith chart when looking from the impedance transformers 52 and 53 to the combining node N1. The open stub 54 is an eighth-wavelength line at the center frequency of the operating frequency band. Thus, the phases of the signals S5 and S6 rotated by 90° in the impedance transformers 52 and 53 can be made to coincide with the phase of the signal S4.

[0111] Figure 2The semiconductor device 102 includes leads 27a (first input terminal), 27b (second input terminal), 27c (third input terminal), leads 28a (first output terminal), 28b (second output terminal), and lead 28c (third output terminal). A lead 29 (terminal) is connected to the line between the lead 27a and the main amplifier 10, and an open stub 54 for adjusting the phase of the signal S1 can be connected thereto. Thus, by providing the lead 29 for the open stub 54 in the package 50, as Figure 3 shown, the circuit board 55 can be miniaturized.

[0112] The package 50 has sides 59a and 59b opposed in the X direction and sides 59c and 59d opposed in the Y direction. The leads 27a to 27c are provided on the side 59a (first side), and the leads 28a to 28c are provided on the side 59b (second side). Among the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, the main amplifier 10 is closest to the side 59c (third side) connecting the side 59a and the side 59b. The lead 29 is provided on the side 59c. Thereby, the bonding wire 49 connected to the lead 29 can be shortened. Thereby, the electrical length between the path between the lead 27a and the main amplifier 10 and the open stub 54 can be shortened. The accuracy of the substantial electrical length of the open stub 54 can be improved.

[0113] Although a three-way Doherty amplifier circuit has been described as an example, it may also be a two-way Doherty amplifier circuit without the peak amplifier 14 and the impedance converter 53. Further, it may be an N-way Doherty amplifier circuit where N is 4 or more. In this case, only N - 1 peak amplifiers need to be provided.

[0114] The embodiments disclosed herein should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown by the claims, rather than by the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A Doherty amplifier circuit, comprising: a distributor for distributing an input signal inputted into a first signal and a second signal; Circuit board; a first amplifier, disposed on the circuit substrate, amplifying the first signal and outputting the amplified signal as a fourth signal; a second amplifier, disposed on the circuit substrate, amplifying the second signal and outputting the amplified signal as a fifth signal; a synthesis node, synthesizing the fourth signal and the fifth signal, and outputting the synthesized signal as an output signal to an output terminal; an open-circuit stub, provided on the circuit substrate, the end of the open-circuit stub being electrically connected to a path between the distributor and the first amplifier; as well as The first impedance converter is disposed on the circuit substrate. The first end of the first impedance converter is electrically connected to the second amplifier, and the second end of the first impedance converter is electrically connected to the synthesis node.

2. The Doherty amplifier circuit according to claim 1, comprising: a third amplifier, disposed on the circuit substrate, amplifying the third signal and outputting the amplified signal as a sixth signal; and A second impedance converter is provided on the circuit substrate, a first end of the second impedance converter is electrically connected to the third amplifier, and a second end of the second impedance converter is electrically connected to the synthesis node. The distributor distributes the input signal into the first signal, the second signal, and the third signal, The synthesis node synthesizes the fourth signal, the fifth signal, and the sixth signal, and outputs the synthesized signal to the output terminal as the output signal.

3. The Doherty amplifier circuit according to claim 1 or 2, wherein: No impedance transformer is provided between the first amplifier and the synthesis node.

4. The Doherty amplifier circuit according to claim 1 or 2, wherein: The first amplifier is a main amplifier, and the second amplifier is a peak amplifier.

5. The Doherty amplifier circuit according to claim 1 or 2, wherein: The first amplifier and the second amplifier are arranged in a first direction, The first impedance converter and the second amplifier are disposed adjacent to each other in a second direction intersecting the first direction. The open stub is disposed adjacent to the first amplifier in the first direction.

6. The Doherty amplifier circuit according to claim 1 or 2, comprising: a package, the package carrying the first amplifier and the second amplifier, mounted on the circuit substrate, The open stub and the first impedance converter are not mounted on the package.

7. The Doherty amplifier circuit according to claim 1 or 2, wherein: The first impedance converter is a 1 / 4 wavelength line of the center frequency of the operating frequency band, and the open-circuit stub is a 1 / 8 wavelength line of the center frequency of the operating frequency band.

8. A semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, comprising: A first input terminal for inputting a first signal obtained by dividing the input signal; A second input terminal for inputting a second signal obtained by dividing the input signal; a first amplifier, amplifying the first signal and outputting the amplified signal as a fourth signal; a second amplifier, amplifying the second signal and outputting the amplified signal as a fifth signal; A first output terminal, for outputting the fourth signal; A second output terminal, for outputting the fifth signal; as well as The terminal is connected to a line between the first input terminal and the first amplifier, and an open-circuit stub for adjusting the phase of the first signal can be connected.

9. The semiconductor device according to claim 8, comprising: A third input terminal for inputting a third signal obtained by dividing the input signal; a third amplifier, amplifying the third signal and outputting the amplified signal as a sixth signal; and The third output terminal is used for outputting the sixth signal.

10. The semiconductor device according to claim 8 or 9, comprising: a package having the first amplifier and the second amplifier arranged in a first direction, The first input terminal and the second input terminal are provided on the first side of a first side and a second side of the package that are opposite to each other in a second direction intersecting the first direction. The first output terminal and the second output terminal are provided on the second side of the package. The terminal is provided on a third side connecting the first side and the second side, and the first amplifier is closer to the third side than the second amplifier.

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