Amplifier circuit, chip and packaging chip module

Abstract

The invention provides an amplifier circuit, a chip and a packaging chip module, and the amplifier circuit comprises an input network which comprises a first input tube core and a second input tube core which are connected in sequence, and a first stage matching network which is arranged between the first input tube core and the second input tube core; the output network comprises output tube cores which are sequentially connected with the second input tube cores; wherein the gate end of the first input tube core is a signal input end, and the first inter-stage matching network comprises a first inter-stage inductor which is connected between the first input tube core and the second input tube core to form a direct current path; the first inter-stage inductor is connected between the drain end of the first input tube core and the source end of the second input tube core; the gate end of the output tube core is connected with the drain end of the second input tube core, and the gate end of the output tube core is grounded through a gate end grounding capacitor.

Description

Technical Field

[0001] This application relates to the technical field of amplifiers. Background Art

[0002] Amplifiers are widely used in technical fields such as communication systems, audio and video, etc. For example, at the receiving end of a communication system, the low-noise amplifier plays a crucial role. It is the first-stage amplifier located behind the receiving antenna, and its function is to amplify the weak signal received by the communication antenna to reduce the noise sensitivity of the subsequent devices. According to the noise cascade formula, it can be found that the performance of the low-noise amplifier at the front end will affect the noise and linearity of the entire communication receiving system. In addition, as the integration level of communication systems becomes higher and higher, the communication receiving system has more stringent performance requirements for the low-power consumption and other performance of the low-noise amplifier chip. How to achieve low noise and high linear output power while maintaining low power consumption is an urgent problem to be solved in the circuit design of low-noise amplifiers. Summary of the Invention

[0003] To solve the existing technical problems, this application provides an amplifier circuit with low power consumption and high linear output power, a chip including the amplifier circuit, and a packaged chip module, especially suitable for the low-noise amplifier at the front end of a communication system.

[0004] In the first aspect of the embodiments of this application, an amplifier circuit is provided, including:

[0005] An input network, including a first input die and a second input die connected in sequence, and a first inter-stage matching network disposed between the first input die and the second input die;

[0006] An output network, including an output die connected in sequence with the second input die;

[0007] Wherein, the gate terminal of the first input die is the signal input terminal, the first inter-stage matching network includes a first inter-stage inductor connected between the first input die and the second input die to form a direct current path, and the first inter-stage inductor is connected between the drain terminal of the first input die and the source terminal of the second input die; the gate terminal of the output die is connected to the drain terminal of the second input die, and the gate terminal of the output die is grounded through a gate-grounding capacitor.

[0008] In the second aspect, a chip is provided, including the amplifier circuit according to any embodiment of this application.

[0009] In the third aspect, a packaged chip module is provided, including the chip according to any embodiment of this application and a packaging structure for packaging the chip therein.

[0010] Fourthly, a packaged chip module is provided, which includes a plurality of chips, the amplifier circuit according to any embodiment of the present application, and a packaging structure that packages the plurality of chips therein;

[0011] In the amplifier circuit, the first input die, the second input die, the first inter-stage matching network in the input network, and the output die are located on the same chip or different chips.

[0012] In the amplifier circuit provided in the above embodiment, the input network includes a first input die and a second input die connected in sequence, and a first inter-stage matching network is provided between the first input die and the second input die. The first inter-stage matching network includes a first inter-stage inductor connected between the first input die and the second input die to form a direct current path. The first inter-stage inductor is connected between the drain of the first input die and the source of the second input die, so that the static currents of the two-stage dies in the input network can be multiplexed from the drain to the source. In this way, the low static current of the input stage can be ensured, while reducing the input stage noise, reducing the overall power consumption and achieving small signal gain; secondly, the gate of the output die is connected to the drain of the second input die, and the gate of the output die in the output network is connected to the electrode ground through a gate-grounding capacitor. The gain can be adjusted within a large range through this gate-grounding capacitor, and the linear output power can be improved.

[0013] Among them, the amplifier circuit provided in the embodiment of the present application is particularly suitable for the application of a low-noise amplifier at the receiving end of a communication system, so as to effectively solve the problem that the receiving end of the communication system requires the low-noise amplifier to meet the requirements of low noise and high linear output power while maintaining low power consumption.

[0014] The chips and packaged chip modules provided in the above embodiments belong to the same concept as the corresponding amplifier circuit embodiments, and thus have the same technical effects as the corresponding amplifier circuit embodiments, which will not be elaborated here. Description of the Drawings

[0015] Figure 1 It is a schematic diagram of the principle of the amplifier circuit in an embodiment.

[0016] Figure 2 It is a circuit topology diagram of the two-stage static current multiplexing of the input network of the amplifier circuit in an embodiment.

[0017] Figure 3 It is a circuit topology diagram of the amplifier circuit in an embodiment.

[0018] Figure 4 It is a schematic diagram of the principle of the amplifier circuit in an embodiment.

[0019] Figure 5It is a circuit topology diagram of two-stage static current reuse for the input network of the amplifier circuit in another embodiment.

[0020] Figure 6 It is a schematic diagram of the small-signal gain of the simulation result of the amplifier circuit in one embodiment.

[0021] Figure 7 It is a schematic diagram of the input-output standing wave of the simulation result of the amplifier circuit in one embodiment.

[0022] Figure 8 It is a schematic diagram of the noise figure of the simulation result of the amplifier circuit in one embodiment.

[0023] Figure 9 It is a schematic diagram of the input-output power of the simulation result of the amplifier circuit in one embodiment. Detailed implementation manners

[0024] The technical solution of the present invention will be further elaborated in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0025] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the drawings. The described embodiments should not be regarded as limitations on the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0026] In the following description, the expression "some embodiments" is involved, which describes a subset of all possible embodiments. It should be noted that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "inner", "outer", "left", "right" and similar expressions used herein are only for the purpose of illustration in combination with the embodiments of the drawings and do not represent the only implementation manners.

[0028] In the research on the design of a low-noise amplifier, the inventors of the present application proposed the following design ideas in achieving low noise and high linear output power while maintaining low power consumption: First, the input network is designed with two diode chips. A direct current path can be formed by connecting an inter-stage inductor between the front-stage chip and the rear-stage chip, so that the static currents of the two diode chips are reused at two levels. By reusing the static currents at two levels, a lower static current of the input stage is achieved to reduce the chip power consumption of the amplifier. Second, in the output network, a gate terminal grounding capacitor is set at the gate terminal of the output chip, and the gain of the output terminal is adjusted by using the gate terminal grounding capacitor to achieve high gain and high linear output power.

[0029] To reduce the chip power consumption, the inventors of the present application further studied the power influencing factors between the input stage and the output stage and proposed the following design ideas: Assume that the total chip voltage of the amplifier is VD, the sizes of the two diode chips in the input network are the same, the gate voltage of the front-stage chip is VG1, and the gate voltage of the rear-stage chip is VG2. Then, the drain-source voltage VDS2 of the rear-stage chip with the two-level reuse of the static current will not exceed VD - (VG2 - VG1). According to the power formula P out =U o 2 / Z 0 ,where Z 0 is the system characteristic impedance, and U o is the output stage voltage swing. Limited by the drain-source voltage VDS2 of the rear-stage chip, the linear power of the low-noise amplifier will decrease, resulting in premature compression of the large-signal output power. Thus, the input network and the output network are newly designed from multiple performance aspects such as input-output standing wave, noise performance, gain adjustment, and linear output power. A larger working current is allocated to the input stage to achieve low noise and higher gain, while a smaller working current is allocated to the output stage, but the gain is adjustable within a large range and the output power has good linearity.

[0030] An implementation example of the amplifier circuit obtained based on the above design ideas will be described in detail in the subsequent embodiments.

[0031] Please refer to Figure 1 for an amplifier circuit provided in an embodiment, including: an input network 10, including a first input chip Q1 and a second input chip Q2 connected in sequence, and a first inter-stage matching network 11 provided between the first input chip Q1 and the second input chip Q2; an output network 20, including an output chip connected in sequence with the second input chip Q2; wherein, please refer to Figure 2, which is the circuit topology diagram of the input network 10. The gate terminal of the first input die Q1 is the signal input terminal in. The first inter-stage matching network 11 includes a first inter-stage inductor L5 connected between the first input die Q1 and the second input die Q2 to form a direct current path. The first inter-stage inductor L5 is connected between the drain terminal of the first input die Q1 and the source terminal of the second input die Q2. The drain terminal of the second input die Q2 serves as the output terminal OUT of the input network 10 to be connected to the subsequent output network 20. Specifically, it is connected to the gate terminal of the output die; please refer to Figure 3 , which is the circuit topology diagram of the overall amplifier circuit. The gate terminal of the output die is connected to the drain terminal of the second input die Q2, and the gate terminal of the output die is grounded through a gate-grounding capacitor C9.

[0032] The drain terminal of the first input die Q1 is connected to the gate terminal of the second input die Q2, and the first inter-stage inductor L5 is connected between the drain terminal of the first input die Q1 and the source terminal of the second input die Q2, so that the static current of the two-stage die in the input network 10 can be multiplexed from the drain to the source. In the output network 20, the gate terminal of the output die is connected to the drain terminal of the second input die Q2, and the gate terminal of the output die is connected to the electrode ground through a gate-grounding capacitor C9. By changing the value of the gate-grounding capacitor C9, the power gain of the output stage can be adjusted within a large range, improving the gain performance and enabling the output stage to maintain a high linear output power at a low operating current.

[0033] In the above embodiment, through the settings of the first input die Q1, the second input die Q2, and the first inter-stage matching network 11 in the input network 10, the multiplexing of the static current of the two-stage die in the input stage from the drain to the source and the isolation of the DC radio frequency signal are achieved. In this way, the low static current of the input stage can be ensured, the input stage noise can be reduced, the overall power consumption of the amplifier chip can be reduced, and small-signal gain can be achieved; secondly, the gate terminal of the output die in the output network 20 is connected to the electrode ground through a gate-grounding capacitor C9, and the gain can be adjusted within a large range through this gate-grounding capacitor C9, improving the linear output power.

[0034] Please refer to Figure 3 and Figure 4, the input network 10 further includes a negative feedback capacitor C4 that grounds the source terminal of the second input die Q2 to form a radio frequency path, and the first inter-stage matching network 11 further includes a first inter-stage capacitor C3 connected between the drain terminal of the first input die Q1 and the gate terminal of the second input die Q2; one end of the first inter-stage inductor L5 is connected to the node between the first inter-stage capacitor C3 and the drain terminal of the first input die Q1, and the other end is connected to the node between the negative feedback capacitor C4 and the source terminal of the second input die Q2. The negative feedback capacitor C4 is connected between the source terminal of the second input die Q2 and the electrode ground. Thus, in the design of the two-stage die for the input network 10, the negative feedback capacitor C4 serves as the biasing ground capacitor for the drain terminal of the second input die Q2, and also provides frequency selection for the source terminal of the second input die Q2 to ensure its operation in the expected frequency band. In addition, the first inter-stage capacitor C3 and the first inter-stage inductor L5 together constitute an inter-stage matching network between the first input die Q1 and the second input die Q2 to ensure the conjugate matching between the output impedance of the previous-stage first input die Q1 and the second input die Q2 of the subsequent stage, maximizing the power transfer and minimizing the loss between the two-stage dies.

[0035] In some embodiments, the input network 10 includes a first RLC negative feedback network 12 connected between the gate terminal and the drain terminal of the second input die Q2. The first RLC negative feedback network 12 includes a first resonant capacitor C5, a first resonant resistor R2, and a first resonant inductor L8 connected in series. Among them, the first RLC negative feedback network 12 is disposed between the gate and drain of the second input die Q2. No RLC negative feedback is used between the two-stage dies in the input stage to avoid introducing excessive noise. For the gain adjustment of the input stage, the first resonant capacitor C5 is used to select the operating frequency band of the circuit, the first resonant resistor R2 is used to adjust the low-frequency gain, the first resonant inductor L8 is used to adjust the high-frequency gain, and the negative feedback capacitor C4 at the source terminal of the second input die Q2 is also used to adjust the shape of the in-band gain curve. Thus, by setting the first RLC negative feedback network 12 between the drain and gate of the second input die Q2 and the negative feedback capacitor C4 grounded at the source terminal, the gain adjustment of the input stage is jointly achieved.

[0036] In some embodiments, a second inter-stage matching network 13 is provided between the second input die Q2 and the output die; the second inter-stage matching network 13 includes a second inter-stage inductor L9 and a second inter-stage capacitor C7 connected in series between the chip voltage VD and the gate terminal of the output die; one end of the first RLC negative feedback network 12 is connected to the gate terminal of the second input die Q2, and the other end is connected to the node between the second inter-stage inductor L9 and the second inter-stage capacitor C7. In this embodiment, the second inter-stage capacitor C7 and the second inter-stage inductor L9 together form an inter-stage matching network between the input die and the output die to ensure conjugate matching between the output impedance of the second input die Q2 of the previous stage and the output die of the subsequent stage, maximizing power transfer and minimizing losses between the two-stage dies; secondly, one end of the first RLC negative feedback network 12 connected to the drain terminal of the second input die Q2 is also connected to the node between the second inter-stage inductor L9 and the second inter-stage capacitor C7 provided at the gate terminal of the output die, so as to set the RLC negative feedback regulation for the input stage between the input die and the output die of the last stage, so as not to introduce noise to the input stage.

[0037] In some embodiments, a first bandwidth extension inductor L7 is connected to the drain terminal of the second input die Q2, and a first source inductor L6 is also connected between the source terminal of the second input die Q2 and the negative feedback capacitor C4. One end of the first bandwidth extension inductor L7 is connected to the drain terminal of the second input die Q2, and the other end is connected to the node between the second inter-stage inductor L9 and the second inter-stage capacitor C7. Among them, the first bandwidth extension inductor L7 and the first source inductor L6 provide a basis for forming a DC path between the drain and source terminals of the second input die Q2. The setting of the first bandwidth extension inductor L7 can reduce the overall signal attenuation and distortion of the chip of the amplifier circuit, increase the circuit resonance frequency, and reduce noise, thereby improving the bandwidth and signal transmission quality.

[0038] Optionally, the input network 10 further includes a first bias branch 14 connected between the node where the drain terminal of the second input die Q2 is connected to the chip voltage VD and the electrode ground. The first bias branch 14 includes a first bias RF capacitor C6 and a first bias de-resonant resistor R3 connected in series. In this embodiment, through the filtering of the first bias RF capacitor C6 and the de-resonance of the first bias de-resonant resistor R3 in the first bias branch 14, a stable bias current can be provided for the drain terminal of the second input die Q2 to ensure the operating point of the second input die Q2.

[0039] In some embodiments, a second bandwidth extension inductor L4 is connected to the drain terminal of the first input die Q1. One end of the second bandwidth extension inductor L4 is connected to the first inter-stage inductor L5, and the other end is connected to the drain terminal of the first input die Q1. The source terminal of the first input die Q1 is connected to the electrode ground through the second source terminal inductor L3. The setting of the second bandwidth extension inductor L4 can reduce the overall signal attenuation and distortion of the amplifier circuit chip, increase the circuit resonance frequency, and reduce noise, thereby improving the bandwidth and signal transmission quality. The setting that the drain terminal of the first input die Q1 is connected to the second bandwidth extension inductor L4 and the source terminal is grounded through the second source terminal inductor L3 provides a basis for forming a DC path between the drain and source terminals of the first input die Q1. Thus, the DC path between the first input die Q1 and the second input die Q2 can be specifically formed by the second inter-stage inductor L9, the first bandwidth extension inductor L7, the first source terminal inductor L6, the first inter-stage inductor L5, the second bandwidth extension inductor L4, and the second source terminal inductor L3. In this state, the static currents of the first input die Q1 and the second input die Q2 are exactly equal.

[0040] In some embodiments, an input matching network 15 is connected to the gate terminal of the first input die Q1. The input matching network 15 includes a first capacitor C1 and a first inductor L1 connected in series between the RF signal input terminal RFin and the gate terminal of the first input die Q1, and a gate bias inductor L2 connected between the node between the first capacitor C1 and the first inductor L1 and the first gate power supply VG1. The first input matching network 15 can match the RF input signal received by the RF signal input terminal RFin with the first input die Q1, adjust the input impedance of the first input die Q1 to match the output impedance of the RF input signal source, reduce the reflection and loss of signal transmission, and ensure that the RF input signal can effectively enter the input die of the amplifier circuit. Among them, the setting that the gate terminal of the first input die Q1 is connected to the first inductor L1 and the source terminal is connected to the second source terminal inductor L3 can improve the input standing wave and noise performance of the input stage.

[0041] In some embodiments, a second bias branch 16 is connected to the gate terminal of the first input die Q1. The second bias branch 16 includes a first gate power supply VG1, a gate bias inductor L2 connected between the first gate power supply VG1 and the gate terminal of the first input die Q1, and a second bias RF capacitor C2 connected between the node between the gate bias inductor L2 and the second gate power supply VG2 and the electrode ground. The second bias branch 16 and the first input matching network 15 share the gate bias inductor L2, which is beneficial to reducing the size of the chip layout. Through the filtering of the second bias RF capacitor and the de-resonance of the gate bias inductor L2, a stable bias current can be provided for the gate terminal of the first input die Q1 to ensure the operating point of the first input die Q1.

[0042] In some embodiments, the output die includes a cascode third output die Q3 and a fourth output die Q4. Among them, the output die adopts a cascode structure, which can increase the voltage swing of the output stage and thus improve the linear output power. Optionally, the gate-grounded capacitor C9 can adopt an open-circuit microstrip line, which can further reduce the output stage gain.

[0043] Optionally, a third bandwidth extension inductor L11 is provided between the drain end of the third output die Q3 and the source end of the fourth output die Q4, and the source end of the third output die Q3 is grounded through a third source inductor L10. By setting the output die with a cascode structure and using the third bandwidth extension inductor L11 between the source and drain, the overall signal attenuation and distortion of the amplifier circuit chip can be reduced, the circuit resonance frequency can be increased, and the noise can be reduced, thereby improving the bandwidth and signal transmission quality. Secondly, the addition of the third bandwidth extension inductor L11 is beneficial to improving the output standing wave performance of the output stage. Thirdly, the values of the third bandwidth extension inductor L11 and the gate-grounded capacitor C9 can be jointly used to select the operating frequency band of the output stage die, which is further beneficial to improving the linear output power of the output stage.

[0044] In some embodiments, among the die of each stage of the amplifier circuit, except that the gate end of the first input die Q1 is connected to the first gate power supply VG1 through a first bias branch 14 composed of an RC circuit, the gate ends of other die can be set to be connected to the corresponding gates by using gate resistors with large resistance values. In an optional specific example, the gate end of the second input die Q2 is connected to the second gate power supply VG2 through a first gate resistor R1; and / or, the gate end of the third output die Q3 is connected to the third gate power supply VG3 through a second gate resistor R5; and / or, the gate end of the fourth output die Q4 is connected to the fourth gate power supply VG4 through a third gate resistor R6. In order to provide gate voltage for each stage of die and improve stability, except for the first input die Q1, the biasing method for setting the gate voltage of other stages of die can be selected as the large resistance adjustment method according to the die impedance state, which is beneficial to saving the chip layout size. However, it should be noted that when the chip layout size permits, other stages of die can also select the biasing branch composed of an RC circuit according to the die impedance state to achieve gate voltage biasing. In addition, the gate power supply of each stage of die can be directly powered by using the system of the amplifier circuit, such as the corresponding power supply module in the design of a communication system, or can be obtained by voltage division of the chip voltage VD through a resistor voltage division circuit formed by a gate resistor or through a biasing branch composed of an RC circuit.

[0045] In some embodiments, a fourth bandwidth extension inductor L12 is connected to the drain terminal of the fourth output die Q4; the drain terminal of the fourth output die Q4 is also connected to an output matching network 23, and the output matching network 23 includes a matching inductor L14 and a matching capacitor C11. The matching inductor L14 is connected between the chip voltage VD and the fourth bandwidth extension inductor L12, and the matching capacitor C11 is connected between the node between the fourth bandwidth extension inductor L12 and the matching inductor L14 and the RF signal output terminal. The matching inductor L14 also serves as the drain terminal bias inductor of the fourth output die Q4 to provide a stable DC path for the drain terminal of the fourth output die Q4. The setting of the output matching network 23 can make the output impedance of the amplifier circuit match the load impedance, ensuring that power can be efficiently transmitted to the load to the greatest extent and reducing power loss and reflection.

[0046] In some embodiments, the output network 20 includes a second RLC negative feedback network 21 connected between the gate terminal of the third output die Q3 and the drain terminal of the fourth output die Q4. The second RLC negative feedback network 21 includes a second resonant capacitor C8, a second resonant resistor R7, and a second resonant inductor L13 connected in series. In this embodiment, the second resonant capacitor C8 is used to select the operating frequency band of the circuit, the second resonant resistor R7 is used to adjust the low-frequency gain, and the second resonant inductor L13 is used to adjust the high-frequency gain. Thus, by setting the second RLC negative feedback network 21 between the drain and gate terminals of the fourth output die Q4, the gain adjustment of the output stage can be reliably achieved.

[0047] In some embodiments, the output network 20 further includes a third bias branch 22 connected between the node where the drain terminal of the fourth output die Q4 is connected to the chip voltage VD and the electrode ground. The third bias branch 22 includes a third bias RF capacitor C10 and a second bias de-resonant resistor R8 connected in series. In this embodiment, through the filtering of the third bias RF capacitor C10 and the de-resonance of the second bias de-resonant resistor R8 in the third bias branch 22, a stable bias current can be provided for the drain terminal of the output die of the cascode structure to ensure the operating point of the output die.

[0048] In some embodiments, the chip static current allocated to the first input die Q1 and the second input die Q2 is greater than that allocated to the output die; the die sizes of the first input die Q1 and the second input die Q2 are smaller than that of the output die. In this embodiment, to ensure the low noise and low static current of the input stage, both the first input die Q1 and the second input die Q2 are selected to use dies with a relatively small total gate width size and adopt a static current reuse topology. For example, in a 0.15um GaAspHEMT process, a 40um×4 die is selected as the first input die Q1 and the second input die Q2. Different sizes can also be selected and they do not have to be exactly the same. Regarding the selection of the gate voltage, for the first input die Q1 and the second input die Q2, 50% or even more of the chip static current can be allocated. The magnitude of the static current is adjusted by the gate terminal power supply VG1 of the first input die Q1, and the gate terminal power supply VG2 of the second input die Q2 is generally fixed at one-half of the chip power supply. To ensure the high linear output power of the output stage, the third output die Q3 and the fourth output die Q4 are selected to use dies with a relatively large total gate width size and adopt a cascode topology. The die selection in the output stage needs to consider the die power consumption and gain level in the input stage. For example, in a 0.15um GaAspHEMT process, a 50um×4 die is selected as the third output die Q3 and the fourth output die Q4. Regarding the selection of the gate voltage, if the static current in the output stage is too low, it will cause the output signal to be compressed in advance. Generally, 40% to 50% of the chip static current is allocated. The magnitude of the static current is adjusted by the gate terminal power supply VG3 of the third output die Q3, and the gate terminal power supply VG4 of the fourth output die Q4 is generally fixed at one-half of the chip power supply.

[0049] It should be noted that in the actual layout of the amplifier circuit provided in the above embodiments, the first input die Q1 and the second input die Q2 in the input network 10, and the third output die Q3 and the fourth output die Q4 in the output network 20 can all be disposed on the same semiconductor chip (die), such as a MMIC (monolithic microwave integrated circuit) chip; they can also be separately disposed on different semiconductor chips and then multiple semiconductor chips are packaged together; it is also possible to only dispose some of the dies in the input network 10 and the output network 20 on the semiconductor chip, while some dies or circuit devices are disposed outside the semiconductor chip. These can be determined according to the dies, substrate materials, and the selected process in actual applications; the amplifier circuit can be integrally disposed on the same bare chip and then packaged to form a packaged chip module, or it can be disposed on multiple bare chips and then multiple chips are packaged to form a packaged chip module.

[0050] On the other hand, an aspect of the embodiments of the present application provides a chip, including the amplifier circuit described in any embodiment of the present application, and the amplifier circuit is disposed on the same chip.

[0051] On the other hand, an embodiment of the present application provides a chip packaging module, including the chip described in the above embodiment and a packaging structure that packages the chip therein.

[0052] In yet another aspect, an embodiment of the present application provides a chip packaging module, including multiple chips, an amplifier circuit described in any embodiment of the present application, and a packaging structure that packages the multiple chips therein; in the amplifier circuit, the first input die Q1, the second input die Q2, the first inter-stage matching network 11 in the input network 10, and the output die are located on the same chip or different chips. In one example, the input network 10 is entirely disposed on the same chip, the output network 20 is disposed on the same chip, and then packaged through the packaging structure to form a chip packaging module; in another example, the first input die Q1 and the second input die Q2 in the input network 10 are disposed on different chips, the first inter-stage matching network 11 and the second inter-stage matching network 13 are disposed outside the chip, the third output die Q3 and the fourth output die Q4 are disposed on the same chip, and then the multiple chips and the external-chip circuit are packaged through the packaging structure to form a chip packaging module; in yet another example, all the dies in the amplifier circuit are respectively disposed on different chips, the inter-stage matching network is disposed outside the chip, and then the multiple chips and the external-chip circuit are packaged through the packaging structure to form a chip packaging module. It should be noted that the product form of the amplifier circuit provided by the embodiments of the present application is not limited to a single chip or multiple chips, nor is it limited to a single chip being packaged to form a packaged chip module or multiple chips being packaged to form a packaged chip module, and the present application does not limit this.

[0053] In some embodiments, please refer to Figure 5 , the input network 10 further includes a fourth bias branch 17 connected in parallel with the negative feedback capacitor C4. The fourth bias branch 17 includes a fourth bias radio-frequency grounding capacitor C12 and a third bias de-resonant resistor R9 connected in series. One end of the fourth bias branch 17 is connected to the node between the negative feedback capacitor C4 and the first inter-stage inductor L5, and the other end is connected to the electrode ground. By setting the negative feedback capacitor C4 between the source terminal of the second input die Q2 and the electrode ground, direct current can be isolated to prevent short circuits, and at the same time, the source terminal of the second input die Q2 can be grounded to form a radio-frequency path. At the same time, by utilizing the frequency selection characteristic of the negative feedback capacitor C4, the amplification power of the current generated by the migration of the source terminal of the second input die Q2 to the drain terminal can be controlled, thereby controlling the passing rate of different frequency signals between the source and drain terminals of the second input die Q2 and adjusting the amplification degree of power at different signal frequencies, that is, the gain form. In this way, in the design of the two-stage dies in the input stage, the negative feedback capacitor C4 serves as both the drain terminal bias grounding capacitor of the first input die Q1 and provides frequency selection for the source terminal of the second input die Q2 to ensure that it operates in the expected frequency band. In this embodiment, the fourth bias branch 17 further connected in parallel with the negative feedback capacitor C4 at the source terminal of the second input die Q2 can actually be equivalent to disassembling the original negative feedback capacitor C4 intoFigure 5 The fourth bias radio frequency grounding capacitor C12, source terminal feedback capacitor C13, and third bias de-resonant resistor R9 shown in the figure.

[0054] The amplifier circuit provided by the embodiment of the present application has at least the following characteristics:

[0055] First, the static current of the two die in the input stage is multiplexed at two levels. The setting of the cascode structure in the output stage combined with the gate terminal grounding capacitor C9 of the output die is beneficial to simultaneously meet the requirements of low power consumption and high linear output power of the amplifier circuit; specifically including: by adjusting the value of the gate terminal grounding capacitor C9, the power gain of the output stage can be adjusted within a large range, and the lowest can provide a 2dB gain, and maintain a high linear output power at a lower operating current; the setting of the first inter-stage inductor L5 between the two die in the input stage enables the input stage to multiplex the static chip current of the first two die, reducing the overall power consumption of the chip and ensuring small-signal gain.

[0056] Second, the selection that the die size in the input stage is smaller than the die size in the output stage, and the design that the current distribution ratio in the input stage is greater than the current distribution ratio in the output stage. By allocating a larger operating current in the input stage, it is beneficial to achieve low noise and higher gain; by allocating a smaller operating current in the output stage, the gain can be adjusted within a large range, and the output power linearity is good.

[0057] Third, in the first input die Q1 and the second input die Q2, by forming a direct current path through the second inter-stage inductor L9, the first bandwidth extension inductor L7, the first source terminal inductor L6, the first inter-stage inductor L5, the first bandwidth extension inductor L4, and the second source terminal inductor L3, it is possible to ensure that the static currents of the first input die Q1 and the second input die Q2 are equal, realizing the multiplexing of the static currents of the two die.

[0058] Fourth, the design of the first inductor L1 at the gate terminal of the first input die Q1 and the second source terminal inductor L3 at the source terminal can improve the input standing wave and noise performance; the design of the first RLC negative feedback network 12 and the second RLC negative feedback network 21, as well as the bias de-resonant resistors in each bias branch, can improve the overall gain adjustment.

[0059] Fifth, between the two output die in the output stage, the addition of the third bandwidth extension inductor L11 and the addition of the matching capacitor C11 at the output terminal of the last output die can improve the output standing wave performance; further, a grounding capacitor can be connected in parallel or an inductor can be connected in series after the matching capacitor C11 to further improve the output standing wave and reduce the probability of performance deterioration after bare chip assembly.

[0060] Generally speaking, compared with the prior art, the three-stage circuit topology structure of the amplifier circuit provided by the embodiments of the present application takes into account performance such as low noise, low power consumption, and high linear output power, and can better meet the requirements of modern communication systems for low-noise amplifiers.

[0061] In order to effectively verify the performance of the amplifier circuit provided by the embodiments of the present application, the feasibility of this amplifier circuit topology was verified in the frequency band of 7 to 13 GHz based on the 0.15um GaAs process.

[0062] Please refer to Figures 6 to 9 , the layout simulation results based on the 0.15um GaAs pHEMT process: the small-signal gain is shown in Figure 6 , S21 > 25dB, and the gain flatness < 1dB. The input and output standing waves are shown in Figure 7 , both are less than -12dB. The in-band noise is shown in Figure 8 , which is lower than 0.93dB. The input and output powers are shown in Figure 9 , when the input power Pin = -16dBm, it reaches the 1dB compression point, and the output 1dB compression power is greater than 8.2dBm.

[0063] Based on the comprehensive simulation results, the total static current of the entire circuit does not exceed 20mA. The design goals of low power consumption, low noise, and high linear output power are achieved.

[0064] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0065] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An amplifier circuit, characterized in that: include: An input network, comprising a first input die and a second input die connected in sequence, and a first inter-stage matching network provided between the first input die and the second input die; an output network, comprising output dies sequentially connected to the second input dies; Among them, the gate terminal of the first input tube core is the signal input terminal, the first inter-stage matching network includes a first inter-stage inductor connected between the first input tube core and the second input tube core to form a DC path, and the first inter-stage inductor is connected between the drain terminal of the first input tube core and the source terminal of the second input tube core; the gate terminal of the output tube core is connected to the drain terminal of the second input tube core, and the gate terminal of the output tube core is grounded through a gate terminal grounding capacitor.

2. The amplifier circuit according to claim 1, characterized in that The input network further includes a negative feedback capacitor that grounds the source terminal of the second input die to form a radio frequency path, and a first inter-stage capacitor connected between the drain terminal of the first input die and the gate terminal of the second input die; One end of the first inter-stage inductor is connected to a node between the first inter-stage capacitor and the drain terminal of the first input tube core, and the other end is connected to a node between the negative feedback capacitor and the source terminal of the second input tube core.

3. The amplifier circuit according to claim 1, characterized in that The input network includes a first RLC negative feedback network connected between the gate terminal and the drain terminal of the second input tube core, and the first RLC negative feedback network includes a first resonant capacitor, a first resonant resistor and a first resonant inductor connected in series.

4. The amplifier circuit according to claim 3, characterized in that A second inter-stage matching network is provided between the second input tube core and the output tube core; The second inter-stage network includes a second inter-stage inductor and a second inter-stage capacitor connected in series between the chip voltage and the gate terminal of the output die; One end of the first RLC negative feedback network is connected to the gate terminal of the second input tube core, and the other end is connected to the node between the second inter-stage inductor and the second inter-stage capacitor.

5. The amplifier circuit according to claim 4, characterized in that The input network further comprises a first bias branch connected between the drain terminal of the second input die and the node connected to the chip voltage and the electrode ground, wherein the first bias branch comprises a first bias RF capacitor and a first bias de-resonance resistor connected in series; and / or, The drain end of the second input tube core is also connected to a first bandwidth extension inductor, and a first source end inductor is also connected between the source end and the negative feedback capacitor. One end of the first bandwidth extension inductor is connected to the drain end of the second input tube core, and the other end is connected to the node between the second inter-stage inductor and the second inter-stage capacitor.

6. The amplifier circuit according to claim 1, characterized in that The output dies include a third output die and a fourth output die in a cascode manner.

7. The amplifier circuit according to claim 6, characterized in that A third bandwidth extension inductor is provided between the drain end of the third output tube core and the source end of the fourth output tube core, and the source end of the third output tube core is grounded through the third source end inductor; and / or, The gate terminal of the second input tube core is connected to the second gate terminal power supply through the first gate terminal resistor; and / or, The gate terminal of the third output tube core is connected to the third gate terminal power supply through the second gate terminal resistor; and / or, The gate terminal of the fourth output tube core is connected to the fourth gate terminal power supply through the third gate terminal resistor.

8. The amplifier circuit according to claim 6, characterized in that The output network includes a second RLC negative feedback network connected between the gate terminal of the third input tube core and the drain terminal of the fourth output tube core, and the second RLC negative feedback network includes a second resonant capacitor, a second resonant resistor and a second resonant inductor connected in series; and / or, The output network also includes a third bias branch connected between the drain terminal of the fourth output tube core and the node connected to the chip voltage and the electrode ground, and the third bias branch includes a third bias RF capacitor and a second bias de-resonance resistor connected in series.

9. The amplifier circuit according to any one of claims 1 to 8, characterized in that The chip static current allocated to the first input die and the second input die is greater than the chip static current allocated to the output die; The die sizes of the first input die and the second input die are smaller than the die size of the output die.

10. The amplifier circuit according to claim 9, characterized in that The input stage static current of the first input die and the second input die is greater than 50% of the chip static current, and the output stage static current of the output die is 40% to 50% of the chip static current; and / or, The first input tube die and the second input tube die are 40um×4 tube die, and the output tube die is 50um×4 tube die.

11. A chip, characterized in that: Comprising the amplifier circuit as claimed in any one of claims 1 to 10.

12. A packaged chip module, characterized in that: A chip as claimed in claim 11 and a packaging structure encapsulating the chip.

13. A packaged chip module, characterized in that: A package structure comprising a plurality of chips, an amplifier circuit as claimed in any one of claims 1 to 10, and packaging the plurality of chips; In the amplifier circuit, the first input die, the second input die, the first inter-stage matching network, and the output die in the input network are located on the same chip or on different chips.

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