Rail-to-rail input stage circuit for constant transconductance operational amplifier and working method of rail-to-rail input stage circuit

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a rail-to-rail input stage circuit for a constant transconductance operational amplifier and a working method of the rail-to-rail input stage circuit. The rail-to-rail input stage circuit for the constant transconductance operational amplifier comprises a double-source follower circuit, a complementary differential pair circuit and a tail current source, wherein the double-source follower circuit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes M5, M6, M9 and M10 and NMOS (N-channel Metal Oxide Semiconductor) tubes M7, M8, M11 and M12, and the PMOS tubes M5 and M6 and the NMOS tubes M7 and M8 are used as double-source followers; the complementary differential pair circuit comprises an NMOS differential pair composed of NMOS tubes M1 and M2 and a PMOS differential pair composed of PMOS tubes M3 and M4, and the grid electrodes of the NMOS differential pair and the PMOS differential pair are connected to the output end of the double-source follower. The technical scheme disclosed by the invention has the advantages of relatively simple structure, relatively good transconductance stability and relatively high efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a rail-to-rail input stage circuit for a constant transconductance operational amplifier and a working method thereof. Background Art

[0002] In modern electronic systems, operational amplifiers are widely used in fields such as signal processing, data conversion, and amplification. In application scenarios such as wide-input single-ended to differential conversion and analog input drivers, it is required that the input stage of the operational amplifier can maintain a constant transconductance within the rail-to-rail common-mode input range to ensure signal stability and gain consistency. However, there are still many problems in the existing rail-to-rail operational amplifier input stage technology, which limit its performance in practical applications.

[0003] Currently, the traditional rail-to-rail operational amplifier input stage usually adopts a parallel NMOS and PMOS differential pair structure. Although this structure can achieve a large common-mode input range, its transconductance will fluctuate significantly with the change of the common-mode voltage, resulting in signal distortion and affecting the performance of the overall circuit. Further, although the existing transconductance stability optimization technologies can alleviate this problem to a certain extent, they still have defects such as complex structure, high process requirements, and low transconductance efficiency. Specifically, for example, the circuit structure using the triple current mirror technology can compensate the transconductance near the power supply rail, but its circuit design is complex and has extremely high requirements for the accuracy of the compensation current, increasing the difficulty of design and manufacturing; the level shifting technology using a single source follower can adjust the input level, but the input stage differential pair needs to work alternately, which not only reduces the transconductance efficiency but also increases the chip area requirement. Explanatorily, NMOS is an N-channel metal oxide semiconductor field effect transistor, and its full English name is N-channel metal oxide semiconductor FET; PMOS is a P-channel metal oxide semiconductor field effect transistor, and its full English name is P-channel metal oxide semiconductor FET.

[0004] In summary, there are still some defects in the existing technology, and it is urgent to develop an operational amplifier input stage structure that can achieve a constant transconductance within the rail-to-rail input range without increasing the circuit complexity and chip area to solve the technical problems such as large transconductance fluctuation, complex design, and low transconductance efficiency in the existing technical solutions. Summary of the Invention

[0005] The object of the present invention is to provide a rail-to-rail input stage circuit for a constant transconductance operational amplifier and its working method to solve one or more of the above-mentioned technical problems. The technical solution disclosed by the present invention is specifically a rail-to-rail input stage circuit with a simple structure, good transconductance stability and high efficiency, and has broad application prospects.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A rail-to-rail input stage circuit for a constant transconductance operational amplifier provided by the present invention includes: a dual source follower circuit, a complementary differential pair circuit, and a tail current source; wherein, The dual source follower circuit includes PMOS transistors M5, M6, M9, M10 and NMOS transistors M7, M8, M11, M12; wherein, PMOS transistors M5, M6 and NMOS transistors M7, M8 are used as a dual source follower; PMOS transistors M9, M10 and NMOS transistors M11, M12 are constantly conducting, and are used to provide bias as the current source load of the dual source follower and to adjust the common mode voltage of the input complementary differential pair circuit; The complementary differential pair circuit includes an NMOS differential pair composed of NMOS transistors M1, M2 and a PMOS differential pair composed of PMOS transistors M3, M4; wherein, the gates of the NMOS differential pair and the PMOS differential pair are respectively connected to the output terminals of the dual source follower; The tail current source includes tail current sources M13, M14; wherein, the sources of NMOS transistors M1, M2 are commonly connected to the drain of tail current source M14, the sources of PMOS transistors M3, M4 are commonly connected to the drain of tail current source M13, the gates of tail current sources M13, M14 are both used to connect to a bias circuit, the source of tail current source M13 is used to connect to a power supply terminal, and the source of tail current source M14 is used to connect to a ground terminal.

[0007] A further improvement of the present invention lies in that, In the dual source follower circuit, the gates of PMOS transistors M5, M6 and NMOS transistors M7, M8 are used to access a common mode voltage input signal, the source of PMOS transistor M5 is connected to output node b, the source of PMOS transistor M6 is connected to output node d, the source of NMOS transistor M7 is connected to output node a, and the source of NMOS transistor M8 is connected to output node c.

[0008] A further improvement of the present invention lies in that, In the dual source follower circuit, the drain of PMOS transistor M9 is connected to output node b, the drain of PMOS transistor M10 is connected to output node d, the drain of NMOS transistor M11 is connected to output node a, and the drain of NMOS transistor M12 is connected to output node c; the gates of PMOS transistors M9, M10 and NMOS transistors M11, M12 are all used to connect to the bias circuit; the sources of PMOS transistors M9, M10 are used to connect to the power supply terminal, and the sources of NMOS transistors M11, M12 are used to connect to the ground terminal.

[0009] A further improvement of the present invention lies in that In the complementary differential pair circuit, the gate of NMOS transistor M1 is connected to output node b, the gate of NMOS transistor M2 is connected to output node d, the gate of PMOS transistor M3 is connected to output node a, and the gate of PMOS transistor M4 is connected to output node c; the drain of NMOS transistor M1 is connected to output node N1, the drain of NMOS transistor M2 is connected to output node N2, the drain of PMOS transistor M3 is connected to output node P1, and the drain of PMOS transistor M4 is connected to output node P2.

[0010] A further improvement of the present invention lies in that It further includes: a bias circuit; the bias circuit is connected to the gates of tail current sources M13, M14 and is used to maintain a constant tail current of the NMOS differential pair and the PMOS differential pair by adopting a certain bias.

[0011] A working method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier provided by the present invention includes the following steps: Input common-mode voltage data to the dual source follower circuit, perform level shift processing, and output the processed common-mode voltage data; Connect the processed common-mode voltage data to the complementary differential pair circuit to ensure that the complementary differential pair operates in the saturation region within a voltage range close to the power supply rails.

[0012] A further improvement of the present invention lies in that the NMOS differential pair and the PMOS differential pair are constantly conducting.

[0013] A further improvement of the present invention lies in that during the process of the NMOS differential pair and the PMOS differential pair being constantly conducting, When V DD -(| V GS3,4 |+| V ov13 |)< V in < V DD , V in close to VDD When, PMOS transistors M5 and M6 are turned off, control PMOS transistors M9 and M10 to be in the on state, and turn on NMOS transistors M1 and M2; NMOS transistors M7 and M8 are normally on, control the gate-source voltage of NMOS transistors M7 and M8 to shift the potential of the input common-mode voltage, and turn on PMOS transistors M3 and M4, finally achieving the simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V DD represents the power supply voltage, V in represents the common-mode voltage input signal, V GS3,4 represents the gate-source voltage of PMOS transistors M3 and M4, V ov13 represents the overdrive voltage of the tail current source M13.

[0014] A further improvement of the present invention lies in that during the process of the constant conduction of the NMOS differential pair and the PMOS differential pair, When V SS < V in < V GS1,2 + V ov14 , V in close to V SS When, PMOS transistors M5 and M6 are normally on, control the gate-source voltage of PMOS transistors M5 and M6 to shift the potential of the input common-mode voltage, and turn on NMOS transistors M1 and M2; NMOS transistors M7 and M8 are turned off, control NMOS transistors M11 and M12 to be in the on state, and turn on PMOS transistors M3 and M4, finally achieving the simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V SS represents the ground terminal voltage, V GS1,2 represents the gate-source voltage of NMOS transistors M1 and M2, V ov14 represents the overdrive voltage of the tail current source M14.

[0015] A further improvement of the present invention lies in that during the operation of the rail-to-rail input stage circuit, the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

[0016] Compared with the prior art, the present invention has the following beneficial effects: In the rail-to-rail input stage circuit for a constant transconductance operational amplifier disclosed by the present invention, a complementary differential pair is formed by using a PMOS differential pair and an NMOS differential pair, aiming to expand the common-mode input range of the circuit. A dual source follower circuit is adopted to adjust the common-mode input level, and then adjust the transconductance of the input stage. It has the advantages of relatively simple structure, good transconductance stability and high efficiency, and has broad application prospects. Specifically, the circuit structure adopting the triple current mirror technology involves current matching control and the circuit structure is relatively complex. The present invention adopts a dual source follower circuit, reducing the structural complexity; although the level shift technology using a single source follower can adjust the input level, the input stage differential pair needs to work alternately, which not only reduces the transconductance efficiency but also increases the chip area. The present invention adopts a dual source follower circuit, enabling the complementary differential pair to work simultaneously, improving the transconductance efficiency and reducing the chip area.

[0017] In the present invention, a dual source follower is introduced to control the input common-mode voltage of the complementary differential pair. The dual source follower consists of PMOS transistors M5, M6 and NMOS transistors M7, M8, and they work together to achieve the level shift operation of the input common-mode voltage. Exemplarily, when the input common-mode voltage of the NMOS differential pair is relatively low, the dual source follower will raise it to ensure that the NMOS differential pair can work in the saturation region. On the contrary, when the input common-mode voltage of the PMOS differential pair is relatively high, the dual source follower will lower it, also ensuring that the PMOS differential pair can work stably.

[0018] In the present invention, the voltage processed by the dual source follower is transmitted to the gates (points a, b, c, d) of the complementary differential pair. In this way, regardless of how the input common-mode voltage changes, the complementary differential pair can always work stably in the saturation region, thus ensuring the performance of the circuit.

[0019] In the present invention, a stable bias circuit is adopted to maintain the constancy of the differential pair tail current. Through the precise control of the bias circuit, it can be ensured that the differential pair tail current remains constant within the rail-to-rail input range, and then the input stage transconductance of the circuit (i.e., the sum of the transconductances of the complementary differential pair) can also remain constant throughout the input range.

[0020] In summary, the improved technical means adopted in the technical solution of the present invention can effectively eliminate the transconductance fluctuation and significantly reduce the signal distortion. Compared with the traditional solution, the present invention does not require precise matching of the currents of the NMOS differential pair and the PMOS differential pair, which simplifies the circuit design. The collaborative work of the complementary differential pair avoids the efficiency loss caused by alternate work and improves the transconductance efficiency. At the same time, this design also reduces the chip area and significantly improves the transconductance efficiency and overall performance of the circuit. Summarily, the present invention realizes the constant transconductance within the rail-to-rail input range of the circuit, eliminates the transconductance fluctuation, reduces the signal distortion, and improves the transconductance efficiency and overall performance of the circuit by introducing technical means such as complementary differential pair, dual source-follower, and stable bias circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art; obviously, the drawings in the following description are some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 is a schematic diagram of a rail-to-rail input stage circuit for a constant transconductance operational amplifier in an embodiment of the present invention; Figure 2 is a schematic diagram of the simulation verification result of the input stage transconductance of the rail-to-rail input stage circuit for a constant transconductance operational amplifier in an embodiment of the present invention; Figure 3 is a schematic diagram of the comparison result of the input stage transconductance curves between the method of the present invention and the existing method in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0024] Based on the technical solutions disclosed in the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product, or device.

[0025] Please refer toFigure 1 , a rail-to-rail input stage circuit for a constant transconductance operational amplifier provided by an embodiment of the present invention, the implementation circuit thereof includes: a dual source follower circuit, a complementary differential pair circuit, and a tail current source; wherein, The dual source follower circuit includes PMOS transistors M5, M6, M9, M10 and NMOS transistors M7, M8, M11, M12; wherein, PMOS transistors M5, M6 and NMOS transistors M7, M8 are used as a dual source follower, the gates of PMOS transistors M5, M6 and NMOS transistors M7, M8 are used to access a common-mode voltage input signal, the sources of PMOS transistors M5, M6 are respectively output to nodes b, d, the sources of NMOS transistors M7 and M8 are respectively output to nodes a, c, and the output terminals (a, b, c, d) of the dual source follower are respectively connected to the gates of the complementary differential pair; at the same time, PMOS transistors M9, M10 and NMOS transistors M11, M12 are always conducting, serving both as a current source load of the dual source follower to provide bias and for adjusting the input common-mode voltage of the complementary differential pair transistors to ensure that the complementary differential pair can operate in the saturation region within a voltage range close to the power supply rails; in addition, a stable bias circuit is used to maintain the operating points of transistors M13, M14, further stabilizing the tail current of the complementary differential pair transistors, thereby keeping the transconductance constant. Further explanatorily, the common-mode voltage is input from the gates of PMOS transistors M5, M6 and NMOS transistors M7, M8 and output from the sources, and the output points of the dual source follower are points a, b, c, d. The drain of PMOS transistor M9 is connected to the source of PMOS transistor M5 (node b), the drain of PMOS transistor M10 is connected to the source of PMOS transistor M6 (node d); the drain of NMOS transistor M11 is connected to the source of NMOS transistor M7 (node a), and the drain of NMOS transistor M12 is connected to the source of NMOS transistor M8 (node c).

[0026] The complementary differential pair circuit includes an NMOS differential pair composed of NMOS transistors M1 and M2, and a PMOS differential pair composed of PMOS transistors M3 and M4. Among them, the sources of the NMOS differential pair are commonly connected to the drain of the tail current source M14, and the gates are respectively connected to the shifted common-mode levels of nodes b and d. The sources of the PMOS differential pair are commonly connected to the drain of the tail current source M13, and the gates are respectively connected to the shifted common-mode levels of nodes a and c. Further explanatorily, the sources of NMOS transistor M1 and NMOS transistor M2 are commonly connected to the drain of the tail current source M14, the sources of PMOS transistors M3 and M4 are commonly connected to the drain of the tail current source M13, the gates of NMOS transistors M1 and M2 are connected to points b and d, and the gates of PMOS transistors M3 and M4 are connected to points a and c. The drains of NMOS transistors M1 and M2 are respectively connected to output nodes N1 and N2. The drains of PMOS transistors M3 and M4 are respectively connected to output nodes P1 and P2, serving as the outputs of the complementary differential pair. M13 and M14 are tail current sources, and their gates are both connected to the bias circuit. The source of M13 is connected to the power supply, and the source of M14 is grounded. By using an appropriate bias to maintain the differential pair tail current constant, the total transconductance of the input stage can be ensured to be basically constant.

[0027] In the technical solution disclosed in the embodiment of the present invention, the PMOS differential pair and the NMOS differential pair together constitute a complementary differential pair to achieve an extended common-mode input range. The present invention adopts a dual-source follower (explanatorily, composed of PMOS transistors M5 and M6 and NMOS transistors M7 and M8) to control the input common-mode voltage of the complementary differential pair. The input common-mode voltage undergoes a level shift operation through the dual-source follower, that is, when the input common-mode voltage of the NMOS differential pair is low, it is raised through level shift; when the input common-mode voltage of the PMOS differential pair is high, it is lowered through level shift. Subsequently, the processed voltage is transmitted to the gates (points a, b, c, and d) of the complementary differential pair to ensure that the complementary differential pair always operates stably in the saturation region within a voltage range close to the power supply rails. In this operating state, the input-stage transconductance is the sum of the transconductances of the complementary differential pair. By using a stable bias circuit to maintain the differential pair tail current constant, the transconductance of the circuit can be made constant within the rail-to-rail input range. The technical means adopted in the embodiment of the present invention can effectively eliminate transconductance fluctuations, significantly reduce signal distortion, and there is no need to precisely match the currents of the NMOS differential pair and the PMOS differential pair. In addition, the complementary differential pair works together, avoiding the efficiency loss caused by alternate operation, having a high transconductance efficiency, reducing the chip area, and significantly improving the transconductance efficiency and overall performance of the circuit.

[0028] In an embodiment of the present invention, the specific working principle of the technical solution is as follows: When V DD -(| V GS3,4 |+|V ov13 |)< V in < V DD , i.e., V in close to V DD When it is close to, M5 and M6 are cut off. It is necessary to control the gate voltages of M9 and M10 to make M9 and M10 in the conducting state, raise the potentials of points b and d, and make M1 and M2 conduct. In addition, M7 and M8 are conducting normally, and control their V GS to perform a potential translation on the input common-mode voltage, pull down the potentials of points a and c, and make M3 and M4 conduct. Thus, the NMOS differential pair and the PMOS differential pair conduct simultaneously. Explanatorily, V DD represents the power supply voltage, V in represents the input signal of the common-mode voltage, V GS3,4 represents the gate-source voltage of M3 and M4, V ov13 represents the overdrive voltage of M13.

[0029] When V SS < V in < V GS1,2 + V ov14 , i.e., V in close to V SS When it is close to, M5 and M6 conduct normally, and control their V GS to perform a potential translation on the input common-mode voltage, raise the potentials of points b and d, and make M1 and M2 conduct. In addition, M7 and M8 are cut off, control the gate voltages of M11 and M12 to make M11 and M12 in the conducting state, raise the potentials of points a and c, and make M3 and M4 conduct. Thus, the NMOS differential pair and the PMOS differential pair conduct simultaneously. Explanatorily, V SS represents the ground terminal voltage; V GS1,2 represents the gate-source voltage of M1 and M2; V ov14 represents the overdrive voltage of M14.

[0030] When V GS1,2 + V ov14 < Vin < V DD -(| V GS3,4 |+| V ov13 |), V in In the intermediate range, the NMOS differential pair and the PMOS differential pair are turned on simultaneously.

[0031] Therefore, V in In any range, the input differential pair transistors are constantly turned on, and the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

[0032] The dual-source follower level-shifting technology proposed by the present invention does not require precise matching of the currents of the NMOS differential pair and the PMOS differential pair, and the NMOS and PMOS differential pairs work simultaneously within the entire power supply voltage range, improving the transconductance efficiency and avoiding the error of alternate operation. It not only has a simple working principle and a small number of devices, but also can achieve a smaller input-stage transconductance change rate with lower power consumption and occupied area compared with the traditional input-stage transconductance optimization technology.

[0033] The working method of the circuit of the present invention includes the following steps: Step 1: Use the gates of PMOS transistors M5, M6 and NMOS transistors M7, M8 to input the common-mode voltage data. This common-mode voltage will serve as the basic input signal for subsequent circuit processing to control the input common-mode voltage of the complementary differential pair.

[0034] Step 2: After the common-mode voltage is input from the gates of M5~M8, it is subjected to level-shifting processing through a dual-source follower (formed by PMOS transistors M5, M6 and NMOS transistors M7, M8). The common-mode voltage is output from the sources of M5~M8, and the output points of the dual-source follower are points a, b, c, d.

[0035] Step 3: The common-mode level after being shifted by the dual-source follower is connected to the complementary differential pair circuit. Ensure that the complementary differential pair can operate in the saturation region within the voltage range close to the power supply rails, expanding the common-mode input range. The complementary differential pair circuit is composed of an NMOS differential pair composed of NMOS transistors M1, M2 and a PMOS differential pair composed of PMOS transistors M3, M4. Among them, the gates of NMOS transistors M1, M2 are connected to points b, d, and the gates of PMOS transistors M3, M4 are connected to points a, c. The complementary differential pair works together, and the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair. Using a stable bias circuit to maintain the constant tail current of the differential pair can achieve a constant total transconductance within the rail-to-rail input range of the circuit.

[0036] Step 4: The processed signal is output from the drains (N1, N2, P1, P2) of NMOS transistors M1, M2 and PMOS transistors M3, M4 for subsequent signal processing or applications in other circuit modules.

[0037] The input-stage area, power consumption, and transconductance change rate of the present invention and the existing implementation structure are compared. As shown in Table 1, Table 1 is the simulation verification result obtained by circuit design under a 0.18 µm CMOS (Complementary Metal Oxide Semiconductor) process and a 1.8 V power supply voltage: Table 1. Parameter comparison between the present invention and the prior art structure

[0038] Table 1 compares the performance indicators of static power consumption, input-stage area, and transconductance change rate between the present invention and the traditional structure. For the three parameters of area, power consumption, and transconductance change rate, a figure of merit (FOM) is set to comprehensively evaluate the performance of the circuit. The FOM value is equal to the product of the input-stage area, power consumption, and transconductance change rate. The lower the FOM value, the better the comprehensive performance of the circuit.

[0039] Compared with the existing structure using triple current mirror technology and level shifting technology, the circuit structure provided by the present invention is simple, can achieve a small input-stage transconductance change rate with low power consumption and occupied area, only 0.95%, and its FOM value is also much lower than that of similar designs. The present invention simplifies the circuit structure, reduces the chip area, and lowers the production cost, and can meet the application scenarios with strict requirements for stability and anti-interference performance.

[0040] Please refer to Figure 2 , all transistors of the above constant transconductance rail-to-rail input stage circuit of the present invention adopt the same manufacturing process. Based on the 0.18 µm CMOS process, circuit simulation is carried out under a 1.8 V power supply voltage. The total input-stage transconductance curve of the constant transconductance rail-to-rail input stage circuit of the present invention is as Figure 2 shown, and the total input-stage transconductance remains basically stable with the change of the common-mode input voltage in the range of 0~1.8V.

[0041] Please refer to Figure 3 , based on the 0.18 μm CMOS process, the input-stage transconductance of the operational amplifier is designed and optimized by using triple current mirror technology, level shifting technology, and the dual-source follower level shifting technology of this article respectively. As Figure 3As shown, the total transconductance of the input stage of the operational amplifier in the traditional rail-to-rail implementation method will be halved when the common-mode input level is close to the power supply voltage and ground, and the triple current mirror technology will affect the current compensation effect due to non-ideal factors in the actual circuit. The level shift technology of the single source follower will have a certain deviation due to the alternating operation of the PMOS differential pair and the NMOS differential pair. The novel rail-to-rail input stage circuit for a constant transconductance operational amplifier disclosed in the present invention solves the drawback of poor transconductance stability in the existing transconductance optimization method for the input stage of an operational amplifier. Through the input voltage shift technology based on a dual source follower, not only the circuit complexity is reduced, but also a small input stage transconductance change rate is achieved with low power consumption and small area.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: still modifications or equivalent replacements can be made to the specific embodiments of the present invention, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A rail-to-rail input stage circuit for a constant transconductance operational amplifier, characterized in that: include: A dual source follower circuit, a complementary differential pair circuit and a tail current source; wherein, The dual source follower circuit includes PMOS tubes M5, M6, M9, M10 and NMOS tubes M7, M8, M11, M12; wherein the PMOS tubes M5, M6 and the NMOS tubes M7, M8 are used as dual source followers; the PMOS tubes M9, M10 and the NMOS tubes M11, M12 are constantly turned on, and are used to provide bias for the current source load of the dual source follower and to adjust the common mode voltage of the input complementary differential pair circuit; The complementary differential pair circuit includes an NMOS differential pair consisting of NMOS tubes M1 and M2 and a PMOS differential pair consisting of PMOS tubes M3 and M4; wherein the gates of the NMOS differential pair and the PMOS differential pair are respectively connected to the output ends of the dual source follower; The tail current source includes tail current sources M13 and M14; wherein the sources of the NMOS tubes M1 and M2 are commonly connected to the drain of the tail current source M14, the sources of the PMOS tubes M3 and M4 are commonly connected to the drain of the tail current source M13, the gates of the tail current sources M13 and M14 are both used to connect to the bias circuit, the source of the tail current source M13 is used to connect to the power supply end, and the source of the tail current source M14 is used to connect to the ground end.

2. A rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 1, characterized in that: In the dual source follower circuit, the gates of the PMOS tubes M5 and M6 and the NMOS tubes M7 and M8 are used to access the common mode voltage input signal, the source of the PMOS tube M5 is connected to the output node b, the source of the PMOS tube M6 is connected to the output node d, the source of the NMOS tube M7 is connected to the output node a, and the source of the NMOS tube M8 is connected to the output node c.

3. A rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 2, characterized in that: In the dual source follower circuit, the drain of the PMOS tube M9 is connected to the output node b, the drain of the PMOS tube M10 is connected to the output node d, the drain of the NMOS tube M11 is connected to the output node a, and the drain of the NMOS tube M12 is connected to the output node c; the gates of the PMOS tubes M9, M10 and the NMOS tubes M11, M12 are all used to connect to the bias circuit; the sources of the PMOS tubes M9, M10 are used to connect to the power supply end, and the sources of the NMOS tubes M11, M12 are used to connect to the ground end.

4. A rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 2, characterized in that: In the complementary differential pair circuit, the gate of the NMOS tube M1 is connected to the output node b, the gate of the NMOS tube M2 is connected to the output node d, the gate of the PMOS tube M3 is connected to the output node a, and the gate of the PMOS tube M4 is connected to the output node c; the drain of the NMOS tube M1 is connected to the output node N1, the drain of the NMOS tube M2 is connected to the output node N2, the drain of the PMOS tube M3 is connected to the output node P1, and the drain of the PMOS tube M4 is connected to the output node P2.

5. The rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 1, characterized in that: It also includes: a bias circuit; the bias circuit is connected to the gates of the tail current sources M13 and M14, and is used to use a certain bias to maintain the tail current of the NMOS differential pair and the PMOS differential pair constant.

6. A method for operating a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 1, characterized in that: The following steps are involved: Inputting common mode voltage data to the dual source follower circuit, performing level shift processing, and outputting processed common mode voltage data; The processed common mode voltage data is connected to the complementary differential pair circuit to ensure that the complementary differential pair operates in a saturation region within a voltage range close to the power rail.

7. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 6, characterized in that: The NMOS differential pair and the PMOS differential pair are always turned on.

8. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 7, characterized in that: During the process of constant conduction of the NMOS differential pair and the PMOS differential pair, when V DD -(| V GS3,4 |+| V ov13 |)< V in < V DD , V in near V DD When , PMOS tubes M5 and M6 are turned off, PMOS tubes M9 and M10 are controlled to be in the on state, and NMOS tubes M1 and M2 are turned on; NMOS tubes M7 and M8 are turned on normally, and the gate-source voltage of NMOS tubes M7 and M8 is controlled to shift the input common-mode voltage, and PMOS tubes M3 and M4 are turned on, and finally the NMOS differential pair and the PMOS differential pair are turned on at the same time; where, V DD Indicates the power supply voltage, V in represents the common mode voltage input signal, V GS3,4 Represents the gate-source voltage of PMOS tubes M3 and M4, V ov13 Represents the over-drive voltage of the tail current source M13.

9. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 7, characterized in that: During the process of constant conduction of the NMOS differential pair and the PMOS differential pair, when V SS < V in < V GS1,2 + V ov14 , V in near V SS When , PMOS tubes M5 and M6 are normally turned on, and the gate-source voltage of PMOS tubes M5 and M6 is controlled to shift the potential of the input common-mode voltage, and NMOS tubes M1 and M2 are turned on; NMOS tubes M7 and M8 are turned off, and NMOS tubes M11 and M12 are controlled to be in the on state, and PMOS tubes M3 and M4 are turned on, and finally the NMOS differential pair and the PMOS differential pair are turned on at the same time; where, V SS Indicates the ground terminal voltage, V GS1,2 Represents the gate-source voltage of NMOS tubes M1 and M2, V ov14 Represents the over-drive voltage of the tail current source M14.

10. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 6, characterized in that: During the operation of the rail-to-rail input stage circuit, the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

Images