Picosecond-level jitter continuous timestamp generation device and generation method

Abstract

The invention relates to time synchronization, in particular to a picosecond-level jitter continuous timestamp generation device and method, and the method comprises the steps: a microwave RF timing signal receiving link carries out the conditioning of a microwave RF timing signal, and forms a timing triggering RF signal; the constant proportion timing circuit carries out constant proportion timing processing on the timing trigger RF signal so as to weaken the influence of signal amplitude and noise fluctuation on timing precision, and a timing analog signal is formed. The ADC performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing overall envelope information of the timing analog signal; the FPGA obtains finer digital envelope information based on the timing digital signal, carries out matching pulse compression processing on the digital envelope information and prior envelope information to obtain an extremely narrow peak signal, and obtains a picosecond-level jitter continuous timestamp based on the peak signal; according to the technical scheme provided by the invention, the defect that the timing precision is difficult to control at a picosecond level in the prior art can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to time synchronization, and more particularly to a picosecond-level jitter continuous timestamp generation device and a generation method thereof. Background Art

[0002] For the collaborative time difference positioning of passive detection targets in a multi-station phased array system, or further applications such as multi-station beam-level synthesis, it is necessary to embed an accurate time flow signal in the continuously received data stream among multiple stations. The multi-station devices need to fuse the information of the baseband data stream according to the time flow signal. Therefore, continuous timestamps are a necessary condition and a technical difficulty for related applications.

[0003] Currently, the time synchronization accuracy of mainstream single devices is at the millisecond level, the time synchronization accuracy of differential schemes is at the microsecond level, and the time synchronization accuracy of carrier phases is at the nanosecond level, which simply cannot meet the time synchronization accuracy requirements of multi-station beam-level synthesis. Even the costly carrier phase time synchronization scheme has an accuracy only at the nanosecond level.

[0004] Under general conditions, the existing mainstream time synchronization schemes can meet the time synchronization accuracy requirements for the information fusion of multi-station device intelligence level. However, for multi-station beam-level collaborative data fusion, the nanosecond-level time synchronization accuracy cannot meet the usage requirements either. Especially for devices with a higher frequency band, subtle timing jitter will also bring very large phase errors. Therefore, it is necessary to design a picosecond-level jitter continuous timestamp generation device and a generation method thereof to break through the technical bottlenecks encountered by the existing technology. Summary of the Invention

[0005] Aiming at the above-mentioned drawbacks of the existing technology, the present invention provides a picosecond-level jitter continuous timestamp generation device and a generation method thereof, which can effectively overcome the defect that it is difficult to control the timing accuracy at the picosecond level in the existing technology.

[0006] To achieve the above object, the present invention is realized through the following technical solutions: A picosecond-level jitter continuous timestamp generation device includes a microwave RF timing signal receiving link, a constant fraction timing circuit, an ADC, and an FPGA; The microwave RF timing signal receiving link receives a microwave RF timing signal and conditions the microwave RF timing signal to form a timing trigger RF signal; The constant fraction timing circuit receives the timing trigger RF signal sent by the microwave RF timing signal receiving link and performs constant fraction timing processing on the timing trigger RF signal to weaken the influence of the signal amplitude and noise fluctuations on the timing accuracy, and forms a timing analog signal; The ADC receives the timing analog signal sent by the constant fraction timing circuit, and performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; The FPGA receives the timing digital signal sent by the ADC, obtains more refined digital envelope information based on the timing digital signal, performs matched pulse compression processing with the prior envelope information to obtain a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on the spike signal.

[0007] Preferably, the microwave RF timing signal receiving link includes an antenna, a low-noise amplifier LNA, and an automatic gain control AGC; The antenna receives the microwave RF timing signal; The low-noise amplifier LNA filters and amplifies the microwave RF timing signal to form a microwave RF timing amplified signal; The automatic gain control AGC receives the microwave RF timing amplified signal sent by the low-noise amplifier LNA, and performs AGC amplitude stabilization processing on the microwave RF timing amplified signal to form a timing trigger RF signal; Among them, the amplitude of the timing trigger RF signal has a certain fluctuation due to the influence of the propagation path environment.

[0008] Preferably, the constant fraction timing circuit uses a low-noise circuit to perform constant fraction timing processing on the timing trigger RF signal to weaken the influence of the signal amplitude and noise fluctuation on the timing accuracy, and forms a timing analog signal; Among them, the timing analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10 ps.

[0009] Preferably, the ADC performs ultra-low jitter high-speed sampling on the timing analog signal based on an ultra-low jitter high-quality clock to obtain a timing digital signal containing the overall envelope information of the timing analog signal; Among them, the ultra-low jitter high-speed sampling rate of the timing analog signal has an integer multiple relationship with the data rate of the beam signal.

[0010] Preferably, the ultra-low jitter high-quality clock is generated by a frequency source with ultra-low phase noise to weaken the influence of aperture jitter.

[0011] Preferably, the FPGA obtains more refined digital envelope information based on the timing digital signal, performs matched pulse compression processing with the prior envelope information to obtain a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on the spike signal, including: Receive the timing digital signal sent by the ADC, and perform interpolation and filtering processing on the timing digital signal to improve the time resolution of the timing digital signal and obtain more refined digital envelope information; Use the prior envelope information as the matching signal, perform pulse compression on the digital envelope information and the prior envelope information, and perform matching correlation processing to further improve the time resolution and obtain a spike signal with a width of one sampling point not exceeding the data rate; Use the spike signal as the generated driving signal to obtain a continuous timestamp with picosecond-level jitter; Among them, the processing clock for FPGA timing acquisition is consistent with the processing clock of the beam signal.

[0012] A method for generating a continuous timestamp with picosecond-level jitter includes the following steps: S1. The microwave RF timing signal receiving link receives the microwave RF timing signal and conditions the microwave RF timing signal to form a timing trigger RF signal; S2. The constant fraction timing circuit performs constant fraction timing processing on the timing trigger RF signal to weaken the influence of the signal amplitude and noise fluctuations on the timing accuracy and form a timing analog signal; S3. The ADC performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; S4. The FPGA obtains more refined digital envelope information based on the timing digital signal, performs matching pulse compression processing with the prior envelope information, obtains a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on the spike signal.

[0013] Preferably, the constant fraction timing circuit uses a low-noise circuit to perform constant fraction timing processing on the timing trigger RF signal to weaken the influence of the signal amplitude and noise fluctuations on the timing accuracy and form a timing analog signal; Among them, the timing analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10 ps.

[0014] Preferably, the ADC performs ultra-low jitter high-speed sampling on the timing analog signal based on an ultra-low jitter high-quality clock to obtain a timing digital signal containing the overall envelope information of the timing analog signal; Among them, the ultra-low jitter high-speed sampling rate of the timing analog signal has an integer multiple relationship with the data rate of the beam signal.

[0015] Preferably, in S4, the FPGA obtains more refined digital envelope information based on the timing digital signal, performs matching pulse compression processing with the prior envelope information, obtains a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on the spike signal, including: S41. Receive the timing digital signal sent by the ADC, and perform interpolation and filtering processing on the timing digital signal to improve the time resolution of the timing digital signal and obtain more refined digital envelope information; S42. Use the prior envelope information as a matching signal, perform pulse compression on the digital envelope information and the prior envelope information, and perform matching correlation processing to further improve the time resolution and obtain a spike signal with a sampling point width not exceeding the data rate; S43. Use the spike signal as a generated driving signal to obtain a continuous timestamp with picosecond-level jitter; Wherein, the processing clock for FPGA timing acquisition is consistent with the processing clock of the beam signal.

[0016] Compared with the prior art, the picosecond-level jitter continuous timestamp generating device and generating method provided by the present invention propose a solution with excellent performance and high universality for the timing accuracy requirements of existing multi-station beam-level collaborative data fusion. The present invention does not require a large amount of equipment, and fully utilizes the constant ratio timing circuit, ultra-low jitter high-quality clock and matching pulse compression processing method to realize the generation of picosecond-level continuous timestamp. The present invention has high application potential and low system hardware cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings without creative efforts based on these drawings.

[0018] Figure 1 is a system schematic diagram of the present invention; Figure 2 is a schematic diagram of the working principle of the constant ratio timing circuit in the present invention; Figure 3 is a schematic diagram of the working principle of the ADC in the present invention; Figure 4 is a schematic diagram of the working principle of the FPGA in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] A picosecond-level jitter continuous timestamp generation device, as Figure 1 shown, includes a microwave RF timing signal receiving link, a constant fraction timing circuit, an ADC, and an FPGA; The microwave RF timing signal receiving link receives a microwave RF timing signal and conditions the microwave RF timing signal to form a timing trigger RF signal; The constant fraction timing circuit receives the timing trigger RF signal sent by the microwave RF timing signal receiving link and performs constant fraction timing processing on the timing trigger RF signal to weaken the influence of the amplitude and noise fluctuations of the signal on the timing accuracy, thereby forming a timing analog signal; The ADC receives the timing analog signal sent by the constant fraction timing circuit and performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; The FPGA receives the timing digital signal sent by the ADC, obtains more refined digital envelope information based on the timing digital signal, performs matched pulse compression processing with the prior envelope information to obtain a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on the spike signal.

[0021] ① The microwave RF timing signal receiving link includes an antenna, a low-noise amplifier LNA, and an automatic gain control AGC; The antenna receives the microwave RF timing signal; The low-noise amplifier LNA filters and amplifies the microwave RF timing signal to form a microwave RF timing amplified signal; The automatic gain control AGC receives the microwave RF timing amplified signal sent by the low-noise amplifier LNA and performs AGC amplitude stabilization processing on the microwave RF timing amplified signal to form a timing trigger RF signal; Among them, the amplitude of the timing trigger RF signal has a certain fluctuation due to the influence of the propagation path environment.

[0022] ② As Figure 2 shown, the constant fraction timing circuit uses a low-noise circuit to perform constant fraction timing processing on the timing trigger RF signal to weaken the influence of the amplitude and noise fluctuations of the signal on the timing accuracy, thereby forming a timing analog signal; Among them, the timing analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10 ps.

[0023] ③ As Figure 3 shown, the ADC performs ultra-low-jitter high-speed sampling on the timing analog signal based on an ultra-low-jitter high-quality clock to obtain a timing digital signal containing the overall envelope information of the timing analog signal; Among them, the ultra-low-jitter high-speed sampling rate of the timing analog signal has an integer multiple relationship with the data rate of the beam signal.

[0024] In the technical solution of this application, the ultra-low-jitter high-quality clock is generated by a frequency source with ultra-low phase noise to weaken the influence of aperture jitter.

[0025] ④ As Figure 4 shown, the FPGA obtains more refined digital envelope information based on the timing digital signal, and performs matched pulse compression processing with the prior envelope information to obtain a spike signal with a width of one sampling point not exceeding the data rate, and obtains continuous timestamps with picosecond-level jitter based on this spike signal, including: Receiving the timing digital signal sent by the ADC, and performing interpolation and filtering processing on the timing digital signal to improve the time resolution of the timing digital signal and obtain more refined digital envelope information; Using the prior envelope information as a matching signal, performing pulse compression on the digital envelope information and the prior envelope information, and performing matching correlation processing to further improve the time resolution and obtain a spike signal with a width of one sampling point not exceeding the data rate; Using this spike signal as a generated driving signal to obtain continuous timestamps with picosecond-level jitter; Among them, the processing clock periodically collected by the FPGA is consistent with the processing clock of the beam signal.

[0026] In the technical solution of this application, on the basis of the above-mentioned disclosed device for generating continuous timestamps with picosecond-level jitter, a method for generating continuous timestamps with picosecond-level jitter is also disclosed, including the following steps: S1. The microwave RF timing signal receiving link receives the microwave RF timing signal and conditions the microwave RF timing signal to form a timing trigger RF signal; S2. The constant fraction timing circuit performs constant fraction timing processing on the timing trigger RF signal to weaken the influence of the amplitude and noise fluctuations of the signal on the timing accuracy and form a timing analog signal; S3. The ADC performs ultra-low-jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; S4. The FPGA obtains more refined digital envelope information based on the timed digital signal, performs matched pulse compression processing with the prior envelope information, obtains a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on this spike signal.

[0027] ① The constant fraction timing circuit uses a low-noise circuit to perform constant fraction timing processing on the timed trigger RF signal to weaken the influence of the signal amplitude and noise fluctuations on the timing accuracy, and forms a timed analog signal. Among them, the timed analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10 ps.

[0028] ② The ADC performs ultra-low jitter high-speed sampling on the timed analog signal based on an ultra-low jitter high-quality clock, and obtains a timed digital signal containing the overall envelope information of the timed analog signal. Among them, the ultra-low jitter high-speed sampling rate of the timed analog signal has an integer multiple relationship with the data rate of the beam signal.

[0029] ③ In S4, the FPGA obtains more refined digital envelope information based on the timed digital signal, performs matched pulse compression processing with the prior envelope information, obtains a spike signal with a width of one sampling point not exceeding the data rate, and obtains a continuous timestamp with picosecond-level jitter based on this spike signal, including: S41. Receive the timed digital signal sent by the ADC, and perform interpolation and filtering processing on the timed digital signal to improve the time resolution of the timed digital signal and obtain more refined digital envelope information. S42. Use the prior envelope information as the matching signal, perform pulse compression on the digital envelope information and the prior envelope information, and perform matching correlation processing to further improve the time resolution and obtain a spike signal with a width of one sampling point not exceeding the data rate. S43. Use this spike signal as the generated driving signal to obtain a continuous timestamp with picosecond-level jitter. Among them, the processing clock for the FPGA's timed acquisition is consistent with the processing clock of the beam signal.

[0030] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements will not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A picosecond-level jitter continuous timestamp generation device, characterized in that: It includes microwave RF timing signal receiving link, constant ratio timing circuit, ADC and FPGA; A microwave RF timing signal receiving link receives the microwave RF timing signal and conditions the microwave RF timing signal to form a timing trigger RF signal; A constant ratio timing circuit receives a timing trigger RF signal sent by a microwave RF timing signal receiving link, and performs constant ratio timing processing on the timing trigger RF signal to reduce the influence of the amplitude and noise fluctuation of the signal on the timing accuracy, thereby forming a timing analog signal; The ADC receives the timing analog signal sent by the constant ratio timing circuit, and performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; FPGA receives the timing digital signal sent by ADC, obtains more precise digital envelope information based on the timing digital signal, and performs pulse compression processing matching with the prior envelope information to obtain a spike signal with a sampling point width not exceeding the data rate, and obtains a continuous time stamp with picosecond jitter based on the spike signal.

2. The device for generating a picosecond-level jitter continuous timestamp according to claim 1, characterized in that: The microwave RF timing signal receiving link includes an antenna, a low noise amplifier LNA and an automatic gain control AGC; an antenna, receiving a microwave RF timing signal; A low noise amplifier LNA filters and amplifies the microwave RF timing signal to form a microwave RF timing amplified signal; The automatic gain control AGC receives the microwave RF timing amplification signal sent by the low noise amplifier LNA, and performs AGC amplitude stabilization processing on the microwave RF timing amplification signal to form a timing trigger RF signal; The amplitude of the timing triggered RF signal fluctuates due to the influence of the propagation path environment.

3. The device for generating picosecond-level jitter continuous timestamps according to claim 1, characterized in that: The constant ratio timing circuit uses a low noise circuit to perform constant ratio timing processing on the timing trigger RF signal to reduce the influence of the signal amplitude and noise fluctuation on the timing accuracy, and form a timing analog signal; The timing analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10ps.

4. The device for generating picosecond-level jitter continuous timestamps according to claim 1, characterized in that: The ADC performs ultra-low jitter high-speed sampling on the timing analog signal based on the ultra-low jitter high-quality clock to obtain a timing digital signal containing the overall envelope information of the timing analog signal; The ultra-low jitter high-speed sampling rate of the timing analog signal is an integer multiple of the data rate of the beam signal.

5. The device for generating picosecond-level jitter continuous timestamps according to claim 4, characterized in that: The ultra-low jitter high-quality clock is generated by a frequency source with ultra-low phase noise to reduce the influence of aperture jitter.

6. The device for generating picosecond-level jitter continuous timestamps according to claim 1, characterized in that: The FPGA obtains more refined digital envelope information based on the timing digital signal, and performs matching pulse compression processing with the prior envelope information to obtain a spike signal with a sampling point width not exceeding the data rate, and obtains a continuous time stamp of picosecond-level jitter based on the spike signal, including: Receive the timing digital signal sent by the ADC, and perform interpolation and filtering on the timing digital signal to improve the time resolution of the timing digital signal and obtain more precise digital envelope information; The prior envelope information is used as a matching signal, pulse compression is performed on the digital envelope information and the prior envelope information, and matching correlation processing is performed to further improve the time resolution and obtain a peak signal with a sampling point width not exceeding the data rate; The spike signal is used as a driving signal to obtain a continuous time stamp of picosecond-level jitter; The processing clock of the FPGA timing acquisition is consistent with the processing clock of the beam signal.

7. A method for generating a picosecond-level jitter continuous time stamp, applied to the picosecond-level jitter continuous time stamp generating device according to claim 1, characterized in that: The following steps are involved: S1, the microwave RF timing signal receiving link receives the microwave RF timing signal, and conditions the microwave RF timing signal to form a timing trigger RF signal; S2, the constant ratio timing circuit performs constant ratio timing processing on the timing trigger RF signal to reduce the influence of the signal amplitude and noise fluctuation on the timing accuracy, and form a timing analog signal; S3, ADC performs ultra-low jitter high-speed sampling on the timing analog signal to obtain a timing digital signal containing the overall envelope information of the timing analog signal; S4, FPGA obtains more precise digital envelope information based on the timing digital signal, and performs pulse compression processing matching the prior envelope information to obtain a spike signal with a sampling point width not exceeding the data rate, and obtains a continuous time stamp with picosecond jitter based on the spike signal.

8. The method for generating picosecond-level jitter continuous timestamps according to claim 7, characterized in that: The constant ratio timing circuit uses a low noise circuit to perform constant ratio timing processing on the timing trigger RF signal to reduce the influence of the signal amplitude and noise fluctuation on the timing accuracy, and form a timing analog signal; The timing analog signal is a pulse signal with a determined amplitude and shape and a rising edge within 10ps.

9. The method for generating picosecond-level jitter continuous timestamps according to claim 7, characterized in that: The ADC performs ultra-low jitter high-speed sampling on the timing analog signal based on the ultra-low jitter high-quality clock to obtain a timing digital signal containing the overall envelope information of the timing analog signal; The ultra-low jitter high-speed sampling rate of the timing analog signal is an integer multiple of the data rate of the beam signal.

10. The method for generating picosecond-level jitter continuous timestamp according to claim 7, characterized in that: The FPGA in S4 obtains more precise digital envelope information based on the timing digital signal, and performs pulse compression processing on the matching envelope information to obtain a spike signal with a sampling point width not exceeding the data rate. Based on the spike signal, a continuous time stamp with picosecond jitter is obtained, including: S41, receiving the timing digital signal sent by the ADC, and performing interpolation and filtering processing on the timing digital signal to improve the time resolution of the timing digital signal and obtain more precise digital envelope information; S42, using the prior envelope information as a matching signal, performing pulse compression on the digital envelope information and the prior envelope information, and performing matching correlation processing to further improve the time resolution and obtain a peak signal with a width of one sampling point not exceeding the data rate; S43, using the peak signal as a driving signal to obtain a continuous time stamp of picosecond-level jitter; The processing clock of the FPGA timing acquisition is consistent with the processing clock of the beam signal.

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