Multi-level di / di control of power semiconductor devices

Abstract

A power semiconductor device includes: a power semiconductor die forming a power switch including an input pad, an output pad, and a control pad; a collector power terminal coupled to an input pad of the power switch; an auxiliary gate terminal coupled to a control pad of the power switch; an emitter power terminal; two or more inductor / resistor pairs, wherein each inductor / resistor pair comprises a common stray inductor and a resistor arranged in series between the output pad of the power switch and the emitter power terminal; and a plurality of auxiliary emitter terminals coupled to both sides of the inductor / resistor pair such that one auxiliary emitter terminal is coupled to one side of one inductor / resistor pair. Furthermore, a control circuit for di / dt control of such a power semiconductor device and an electronic device comprising such a power semiconductor device are proposed.

Description

Technical Field

[0001] The present disclosure relates to power semiconductor devices, control circuits for di / dt control of power semiconductor devices, electronic devices including such power semiconductor devices and such control circuits, and methods for multi-level di / dt control of power semiconductor devices. Background Art

[0002] Power semiconductor-based switches such as insulated gate bipolar transistors (IGBTs), silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), gallium nitride (GaN) semiconductor devices, etc. are typically designed to switch as fast as possible to achieve minimal on and off power losses. However, when a freewheeling diode (also known as a flyback diode) is used in conjunction with the switch, during the turn-on transient, the freewheeling diode typically requires a slow transition to reduce reverse recovery current and diode transition power losses. During turn-off, the power semiconductor device typically requires a low overshoot voltage to avoid avalanche breakdown, which requires slowing down the turn-off transient. Power semiconductor devices typically include one or more such semiconductor-based switches.

[0003] Known power semiconductor devices use fixed-value gate resistors to achieve the above engineering goals. However, such a fixed-value gate resistor-based solution requires a trade-off in switching performance between low switching current and high switching current. Alternative solutions using closed-loop gate drive control methods are known, which can achieve good control of switching transients. However, such closed-loop control circuits typically require a very high design bandwidth, resulting in stability, complexity, and reliability challenges in designing and applying such circuits. Summary of the Invention

[0004] An overview of aspects of certain examples disclosed herein is set forth below. It should be understood that presenting these aspects is merely to provide a brief overview of these certain embodiments to the reader, and these aspects are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may cover various aspects and / or combinations of aspects that may not be set forth.

[0005] According to one aspect of the present disclosure, a power semiconductor device is provided. The power semiconductor device may include a power semiconductor die that forms a power switch. The power switch may include an input pad, an output pad, and a control pad. The power semiconductor device may further include a collector power terminal coupled to the input pad of the power switch. The power semiconductor device may further include an auxiliary gate terminal coupled to the control pad of the power switch. The power semiconductor device may further include an emitter power terminal. The power semiconductor device may further include two or more inductor / resistor pairs, where each inductor / resistor pair includes a common stray inductance and a resistor, and the common stray inductance and the resistor are arranged in series between the output pad of the power switch and the emitter power terminal. The power semiconductor device may further include a plurality of auxiliary emitter terminals. The auxiliary emitter terminals may be coupled to both sides of the inductor / resistor pair such that one auxiliary emitter terminal is coupled to one side of one inductor / resistor pair.

[0006] In one embodiment, the common stray inductance and the resistor may be formed by wire bonding and / or substrate copper traces.

[0007] In one embodiment, the first inductance value of the common stray inductance and / or the first resistance value of the resistor are the same in different inductor / resistor pairs.

[0008] In one embodiment, the second inductance value of the common stray inductance and / or the second resistance value of the resistor are different in different inductor / resistor pairs.

[0009] In one embodiment, a plurality of power semiconductor dies may form a plurality of power switches.

[0010] In one embodiment, the power semiconductor device may further include a device package. The collector power terminal, the auxiliary gate terminal, the emitter power terminal, and the plurality of auxiliary emitter terminals may extend through the device package.

[0011] According to one aspect of the present disclosure, a control circuit for di / dt control of a power semiconductor device is provided. The power semiconductor device may include one or more of the above features. The control circuit may be arranged to be coupled to the plurality of inductor / resistor pairs of the power semiconductor device. The control circuit may be arranged to form a gate drive current return loop through the inductor / resistor pairs. The control circuit may be arranged to select the inductor / resistor pairs. Thus, multi-level di / dt control can be achieved.

[0012] In one embodiment, the control circuit may include a plurality of electronic switches. Each electronic switch may be arranged to be coupled to one side of one inductor / resistor pair.

[0013] In one embodiment, the control circuit may further include an input arranged to receive a di / dt selection input signal. The control circuit may further include a demultiplexer circuit arranged to receive the di / dt selection input signal via the input and coupled to a plurality of electronic switches. The control circuit may further include one or more oscillation damping resistors coupled between the electronic switches and the gate drive power supply ground.

[0014] The control circuit may further include an input arranged to receive a di / dt selection input signal. The control circuit may further include a demultiplexer circuit arranged to receive the di / dt selection input signal via the input and coupled to a plurality of electronic switches. The control circuit may further include one or more oscillation damping resistors coupled between the electronic switches and the gate drive power supply ground. The control circuit may further include a diode. One side of the diode may be arranged to be coupled to one side of a first inductance / resistance pair in the inductance / resistance pair. One side of the first inductance / resistance pair in the inductance / resistance pair may be coupled to the output pad of the power switch of the power semiconductor device. The other side of the diode may be coupled to the gate drive power supply ground.

[0015] In one embodiment, one side of the diode may be the anode of the diode.

[0016] In another embodiment, one side of the diode may be the cathode of the diode.

[0017] The control circuit may further include a first input arranged to receive a di / dt reference input signal. The control circuit may further include a second input arranged to receive a di / dt feedback signal. The control circuit may further include di / dt processing logic circuitry arranged to receive the di / dt reference input signal via the first input. The control circuit may further include a demultiplexer circuit coupled to the di / dt processing logic circuitry and coupled to a plurality of electronic switches. The control circuit may further include one or more oscillation damping resistors coupled between the electronic switches and the gate drive power ground. The control circuit may further include a di / dt detection circuit arranged to receive the di / dt feedback signal via the second input and arranged to be coupled to one side of a first inductance / resistance pair in an inductance / resistance pair. One side of the first inductance / resistance pair in the inductance / resistance pair may be coupled to an output pad of a power switch of a power semiconductor device. The control circuit may further include an error amplification circuit arranged to receive the di / dt reference input signal via the first input and arranged to receive the di / dt feedback signal via the second input. The error amplification circuit may be coupled to a gate drive circuit for closed-loop di / dt control of the gate drive level.

[0018] According to one aspect of the present disclosure, an electronic device is provided. The electronic device may include a power semiconductor device having one or more of the above features. The electronic device may further include a control circuit having one or more of the above features.

[0019] In one embodiment, the electronic device may further include a gate drive circuit arranged to be coupled to an input pad and a control pad of a power switch of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Embodiments of the present disclosure will now be described, by way of example only, with reference to the schematic drawings, in which corresponding reference numerals indicate corresponding parts, wherein:

[0021] Figure 1 An example circuit diagram of a power semiconductor device is shown;

[0022] Figure 2 A three-dimensional (3D) model of an example power semiconductor device is shown;

[0023] Figures 3A to 3C An example embodiment of a circuit diagram for di / dt control of a semiconductor device is shown; and

[0024] Figures 4A to 4B As shown in Figure 3A A graph showing verification results of the configuration shown.

[0025] The accompanying drawings are intended for illustrative purposes only and are not to be construed as limiting the scope of protection defined by the claims. Detailed Description

[0026] It should be readily understood that the components of the embodiments generally described herein and shown in the drawings can be arranged and designed in a variety of different configurations. Accordingly, as represented in the figures, the more detailed description of the various embodiments below is not intended to limit the scope of the present disclosure, but merely represents the various embodiments. Although aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically noted.

[0027] The described embodiments are to be considered in all respects only as illustrative and not restrictive. Accordingly, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the meaning and range of equivalence of the claims are to be embraced within the scope of the claims.

[0028] The features, advantages, or similar language used throughout this specification do not imply that all features and advantages that can be realized by the present disclosure should be present or exist in any single example of the present disclosure. Rather, the language referring to the features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the discussion of the features, advantages, and similar language throughout this specification may, but does not necessarily, refer to the same example.

[0029] Furthermore, the features, advantages, and characteristics of the present disclosure can be combined in any suitable manner in one or more embodiments. Based on the description herein, those skilled in the art will recognize that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not exist in all embodiments of the present disclosure. The phrase "in one embodiment," "in an embodiment," or similar language used throughout this specification means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0030] di / dt control, often referred to as di / dt protection or current slew rate control, is a technique used in power electronic devices and power semiconductor devices to limit the rate of change of current (di / dt) during a switching transition. It can be used to manage and reduce electromagnetic interference (EMI), minimize voltage spikes and ringing, and / or prevent excessive stress on components, especially in high-frequency applications. Di / dt control is typically used in devices such as MOSFETs, IGBTs, and other power switches.

[0031] Di / dt control is particularly important in applications that require high-frequency switching, such as in switched-mode power supplies (SMPS), motor drives, and radio frequency (RF) systems. By managing the rate of change of current, it helps ensure that the system operates efficiently and reliably, reduces EMI, and also extends the lifespan of components.

[0032] Stray inductance in the context of MOSFETs, IGBTs, and other power semiconductor devices refers to parasitic inductance. This parasitic inductance can exist in various parts of the circuit and interconnects and can affect the performance and switching characteristics of the power semiconductor device. Stray inductance can impact the switching speed and efficiency of semiconductor devices in high-frequency applications. When a power semiconductor device turns on or off, voltage spikes can be generated due to the rapid change in current. These voltage spikes can cause ringing and may induce unwanted oscillations in the circuit. Stray inductance exacerbates these problems because it stores energy in the form of a magnetic field and can cause voltage spikes and ringing when the current changes rapidly.

[0033] The present disclosure presents a semiconductor device that includes a plurality of gate drive auxiliary emitter terminals and a di / dt control circuit to utilize these auxiliary emitter terminals to achieve substantially real-time multi-level di / dt control.

[0034] The solution of the present disclosure can utilize the negative feedback effect of the common stray inductance on the gate drive loop to achieve multi-level di / dt control. Here, the common stray inductance is the parasitic inductance coupled between the gate drive loop and the power emitter path. This parasitic inductance can be generated by wire bonding and / or copper traces on the substrate.

[0035] Compared with the conventional fixed-value gate resistor method, the proposed solution advantageously reduces switching losses and turn-on / turn-off time delays. In addition, compared with, for example, known closed-loop gate drive control solutions, the proposed solution is less complex and can achieve substantially real-time multi-level di / dt control with improved circuit stability and reliability.

[0036] Figure 1FIG. 0 shows an example circuit diagram of a power semiconductor device 1000 according to one aspect of the present disclosure. The power semiconductor device 1000 may include a device package 1, one or more power semiconductor dies 2, and one or more freewheeling diode dies 3. The power semiconductor device 1000 of the present disclosure further includes two or more pairs of common stray inductors 4 and resistors 5, which may be generated by wire bonding and / or substrate copper traces. Between these pairs, the values of the inductor 4 and / or the resistor 5 may be different. The power semiconductor device 1000 may further include a collector (C0) power terminal 6, an auxiliary gate (G0) terminal 7, an emitter power (E0) terminal 12, and a plurality of auxiliary emitter (E10 - E1x) terminals 8 - 11. In Figure 1 the example of, a first auxiliary emitter terminal 8, a second auxiliary emitter terminal 9, a third auxiliary emitter terminal 10, and an x-th auxiliary emitter terminal 11 are shown, where x indicates that any number of auxiliary emitter terminals may be present.

[0037] The power switch may be formed by any semiconductor die 2 such as an IGBT, SiC MOSFET, GaN, etc. The power switch generally includes an input pad such as the collector in an IGBT or the drain in a MOSFET, an output pad such as the emitter in an IGBT or the source in a MOSFET, and a control pad such as the gate in an IGBT or a MOSFET. Hereinafter, both the power semiconductor die and the power switch formed by the semiconductor die may be referred to by the reference numeral "2". There may be a single power semiconductor die 2 integrated into the package 1. Alternatively, there may be multiple power semiconductor dies 2 integrated into the package 1, for example, multiple semiconductor dies 2 in parallel or in series to form a half-bridge or multilevel topology.

[0038] The freewheeling diode die 3 forms a freewheeling diode. Hereinafter, both the freewheeling diode die and the freewheeling diode formed by the freewheeling diode die may be referred to by the reference numeral "3".

[0039] The power switch 2 of the power semiconductor device 1000 generally includes a freewheeling diode 3, but the power switch 2 may not use the freewheeling diode 3. In the latter example, the power semiconductor device 1000 may include a power semiconductor die 2 without a freewheeling diode die 3.

[0040] The auxiliary emitter terminals 8 - 11 provide a pin interface for di / dt control. Contrary to conventional semiconductor devices that generally include a single auxiliary emitter terminal, the power semiconductor device 1000 of the present disclosure includes a plurality of auxiliary emitter terminals 8 - 11. Between the auxiliary emitter terminals 8 - 11, the parasitic inductors 4 and resistors 5 are pair-coupled with the emitter current path from the power semiconductor die 2 and the freewheeling diode die 3 to the power terminal 12, such as Figure 1As shown. The number of auxiliary emitter terminals 8 - 11 is preferably three or more.

[0041] Figure 2 A 3D model of an exemplary power semiconductor device 1100 is shown, which may be similar to Figure 1 the power semiconductor device 1000. In Figure 2 the example, the power semiconductor device 1100 is an IGBT device with a D2PAK - 7 package. Figure 2 The power semiconductor device 1100 includes a D2PAK - 7 package body 1, a collector power (C0) terminal 6, an auxiliary gate (G0) terminal 7, an emitter power (E0) terminal 12, and a plurality of auxiliary emitter (E10 - E12) terminals 8 - 10. In Figure 2 the example, there are three auxiliary emitter terminals, namely the first auxiliary emitter terminal 8, the second auxiliary emitter terminal 9, and the third auxiliary emitter terminal 10. The emitter power terminal 12 may include one or more leads. In Figure 2 the example, the emitter power terminal 12 includes two leads to allow multiple connections to the same emitter power terminal 12. The power semiconductor die 2, the freewheeling diode die 3, the common stray inductance 4, and the resistor 5 may be integrated in the package 1 but are not visible in Figure 2 the appearance.

[0042] Figures 3A to 3C An example embodiment of a circuit diagram for di / dt control of semiconductor devices such as Figure 1 the power semiconductor device 1000 or Figure 2 the power semiconductor device 1100 is shown.

[0043] In Figures 3A to 3C it, the power semiconductor device components 1 - 12 form a semiconductor device, such as Figure 1 the power semiconductor device 1000 or Figure 2 the power semiconductor device 1100. In Figure 3A the example, the auxiliary emitter terminals 8 - 11 can be used to implement 4 - level di / dt control. More generally, with x auxiliary emitter terminals, x - level di / dt control can be achieved.

[0044] Figure 3AThe circuit diagram 2000 may include a gate drive circuit section 2002, which may be referred to as a gate drive circuit. The gate drive circuit section 2002 may include: a gate drive protection signal feedback 26; a pulse width modulation (PWM) control signal input 27; a temperature sensor input 29; a gate drive circuit block 14, which consists of a protection logic circuit 15, a PWM input and protection logic AND 16, a push-pull output 17, a power supply 19, and a power ground 20; a high-voltage pull-down diode 13; a power semiconductor collector voltage feedback 25, and a gate resistor 18. The gate drive circuit section 2002 may be based on a conventional gate drive circuit.

[0045] Figure 3A The circuit diagram may further include a di / dt control circuit section 2004, which may be referred to as a control circuit. The di / dt control circuit section 2004 may include: a di / dt selection input signal 28; a demultiplexer circuit 21, an electronic switch 23, and a plurality of connection lines 22 between the demultiplexer circuit 21 and the electronic switch 23; and an oscillation damping resistor 24.

[0046] The gate drive circuit section 2002 drives the power switch 2 according to the PWM input signal 27 through the gate drive circuit block 14 and the gate resistor 18. The di / dt control circuit section 2004 creates a gate drive current return loop from the gate drive power supply 19 to the power ground 20, and this current return loop flows through one of the branches having a common stray inductance 4 and a resistance 5. The branch selection may be performed by the demultiplexer circuit 21 and the electronic switch 23 according to the di / dt selection input 28. Since the common stray inductance 4 and the resistance 5 are coupled to the emitter current path from the (one or more) power semiconductor die 2 and the (one or more) freewheeling diode die 3 to the power terminal 12, during the turn-on and turn-off transitions, due to the current change (or di / dt) in the emitter current path, a voltage drop is generated across the common stray inductance 4 and the resistance 5. Since the voltage drop has a negative impact on the gate drive loop for the semiconductor device, it helps to slow down and stabilize the turn-on and turn-off current transition speeds, which establishes a stable di / dt value. Among the four auxiliary emitter terminals 8 - 11, the auxiliary emitter terminal 8 provides the fastest turn-on and turn-off speeds, which generates the highest di / dt value. The auxiliary emitter terminal 9 provides the second fastest turn-on and turn-off speeds and the second highest di / dt value. While the auxiliary terminals 10 and 11 provide the third and fourth highest di / dt values respectively.

[0047] Figure 3B The circuit diagram 2100 is similar to Figure 3A the circuit diagram 2000, and includes a gate drive circuit section 2102 similar to the gate drive circuit section 2002 and an alternative di / dt control circuit section 2104.

[0048] In Figure 3B the example of, the electronic switch 23 connected to the auxiliary emitter terminal 8 in Figure 3A has been modified to a diode 30. When the anode of the diode 30 is connected to the auxiliary emitter terminal 8 of the power semiconductor devices 1000, 1100 (which is the configuration shown in Figure 3B ), the turn-on transient has the fastest transition speed and the highest di / dt, and the di / dt control circuit section 2104 only affects the turn-off transition. When the cathode of the diode 30 is connected to the auxiliary emitter terminal 8 of the semiconductor devices 1000, 1100 (not shown), the turn-off transient has the fastest transition speed and the highest di / dt, and the di / dt control circuit section 2104 will only affect the turn-on transition. In this way, the turn-on and turn-off transients can be decoupled from each other, and the circuit designer can choose which transient to design with di / dt control.

[0049] Figure 3C The circuit diagram 2200 of Figure 3B is similar to the circuit diagram 2100 of

[0050] In Figure 3C the example of, the gate drive circuit section 2204 implements both converter system level di / dt control and gate drive level closed-loop di / dt control. As shown in Figure 3C , a di / dt detection circuit 44, a di / dt processing logic circuit 42, and an error amplification circuit 43 are added to the di / dt control circuit section 2204. A di / dt reference input 41 feeds into the di / dt processing logic 42, which determines one of the feedback branches from the auxiliary emitter terminals 9 - 11 to be used. Then, the output of the di / dt processing logic circuit 42 controls the electrical switch 23 to turn on through a demultiplexer circuit 21. In this way, the converter system can select an appropriate di / dt feedback strength through the common stray inductance 4 and resistance 5, and check the output through the di / dt feedback 45. This realizes the converter system level di / dt control.

[0051] In addition, in Figure 3C the example of, the di / dt reference input 41 feeds into the positive input of the error amplifier 43. The di / dt feedback signal 45 detected by the di / dt detection circuit 44 through the auxiliary emitter terminal 8 is fed into the negative input of the error amplifier 43. Then, the output signal 47 of the error amplifier 43 is input into the gate drive circuit block 14. This is the gate drive level closed-loop di / dt control, which can provide faster and more accurate di / dt control.

[0052] Such as Figures 3A to 3C The gate drive circuit portions 2002, 2102, 2202, the di / dt control circuit portions 2004, 2104, 2204, and the power semiconductor devices 1000, 1100 shown in the circuit diagrams 2000, 2100, 2200 such as

[0052] can be integrated into an electronic device (not shown).

[0053] Figure 4A and Figure 4B are graphs showing the verification results of the configuration shown in Figure 3A . Similar verification results can be obtained for the configurations shown in Figure 3B or Figure 3C . The verification has been performed using the simulation of the circuit diagram 2000 and the 650V / 100A IGBT device 2 in the 'Integrated Circuit Focused Simulation Program' (SPICE) simulator software . Four auxiliary emitter terminal ends 8 - 11 as shown in Figure 3A are used. For each common stray inductance 4, a 2nH inductor is used, and for each resistor 5, a 10mΩ resistor is used. Figure 3A as Figure 3B or Figure 3C as as Figure 3A as

[0054] Figure 4A and Figure 4B present turn - on and turn - off waveforms. Graphs 100 and 200 represent the voltage between the gate pad and the emitter pad on the semiconductor die 2, graphs 110 and 210 represent the voltage between the collector pad and the emitter pad, and graphs 120 and 220 represent the current flowing into the collector pad of the semiconductor die 2. The waveforms 101, 111, 121, 201, 211, 221 are recorded by the di / dt control circuit connected to the auxiliary emitter terminal end 8 having the fastest transition speed and the highest di / dt. The waveforms 102, 112, 122, 202, 212, 222 are recorded by the di / dt control circuit connected to the auxiliary emitter terminal end 9, the waveforms 103, 113, 123, 203, 213, 223 are recorded by the di / dt control circuit connected to the auxiliary emitter terminal end 10, and the waveforms 104, 114, 124, 204, 214, 224 are recorded by the di / dt control circuit connected to the auxiliary emitter terminal end 11, which respectively produce the 2nd, 3rd, and 4th fastest transition speeds and the highest di / dt.

[0055] During the turn-on transient, di / dt is successfully regulated as shown in graph 120, with no significant effect on dv / dt plotted as in 110 or on the turn-on gate voltage delay as shown in graph 100. Similarly, during the turn-off transient, di / dt is regulated as shown in graph 220, with no significant change in dv / dt as shown in graph 210. Notably, the overshoot voltage may be significantly reduced from 630V to 430V. Additionally, there is no turn-off gate voltage delay as shown in graph 200.

[0056] Table 1 presents the detailed numerical results of simulation verification as illustrated in Figure 4, where for two scenarios (i.e., di / dt of 1.6 - 2.0 kA / us and di / dt of 1.1 - 1.3 kA / us), the verification data of the solution of the present disclosure (highlighted by thick borders) is compared with the conventional fixed-gate-resistor-based solution (non-highlighted columns). The present disclosure is not limited to the scenarios and verification data of Table 1, which are presented only as examples.

[0057]

[0058] In the first scenario, the converter system of the present disclosure uses a common stray inductance of 2 nH, a resistance of 10 mΩ, and turn-on and turn-off gate resistors (Rg_on / Rg_off) of 2 Ω to achieve a di / dt of 1.6 kA / us for turn-on and 2.0 kA / us for turn-off. To achieve a similar level of di / dt control performance in the conventional solution, the turn-on and turn-off gate resistors (Rg_on / Rg_off) need to be as high as 16 Ω and 13 Ω respectively. As a result, in the solution of the present disclosure, the turn-on switching loss (Eon) is reduced from 1.452 mJ to 0.885 mJ, and the turn-off loss (Eoff) is reduced from 1.001 mJ to 0.802 mJ. Advantageously, in the solution of the present disclosure, these two switching losses are thus reduced by 39% and 20% respectively, which reduces the total system power loss, reduces the device junction temperature, and reduces the design cost of the power semiconductor device and the converter system.

[0059] Furthermore, with the solution of the present disclosure, the turn-on delay (tdon) is advantageously reduced from 35.8 ns to 15.0 ns, while the turn-off delay (tdoff) is advantageously reduced from 432.3 ns to 184.4 ns, which is more than halved. Higher turn-on and turn-off delays would require a high value of bridge dead time to avoid short circuits, which sacrifices the utility of the converter input current. Therefore, lower turn-on and turn-off delays are preferred.

[0060] In addition, the voltage transition speeds (dv / dt_fall and dv / dt_rise) increase advantageously when using the solution of the present disclosure.

[0061] In the comparison between the solution of the present disclosure and the conventional solution, the switch current rise time (tr), fall time (tf), and turn-off surge voltage (Voff_surge) remain substantially the same because these variables are directly related to the di / dt value, which remains the same in each scenario.

[0062] Based on columns 4 and 5 of Table 1 related to the second scenario (di / dt is 1.1 - 1.3 kA / us), a similar comparison can be made between the solution of the present disclosure and the conventional solution.

Claims

1. A power semiconductor device, comprising: A power semiconductor die, the power semiconductor die forming a power switch, the power switch comprising an input pad, an output pad and a control pad; a collector power terminal coupled to the input pad of the power switch; an auxiliary gate terminal coupled to the control pad of the power switch; Emitter power terminal; two or more inductor / resistor pairs, wherein each inductor / resistor pair comprises a common stray inductance and a resistance arranged in series between the output pad and the emitter power terminal of the power switch; and A plurality of auxiliary emitter terminals, wherein the auxiliary emitter terminals are coupled to both sides of the inductor / resistor pair, such that one auxiliary emitter terminal is coupled to one side of one inductor / resistor pair. 2 . The power semiconductor device according to claim 1 , wherein the common stray inductance and the resistance are formed by wire bonding and / or substrate copper traces. 3 . The power semiconductor device according to claim 1 , wherein the first inductance value of the common stray inductance and / or the first resistance value of the resistor are the same in different inductance / resistance pairs. 4 . The power semiconductor device according to claim 1 , wherein the second inductance value of the common stray inductance and / or the second resistance value of the resistor are different in different inductance / resistance pairs.

5. A power semiconductor device according to any one of the preceding claims, comprising a plurality of power semiconductor dies forming a plurality of power switches.

6. A power semiconductor device according to any one of the preceding claims, further comprising a device package, And wherein the collector power terminal, the auxiliary gate terminal, the emitter power terminal and the plurality of auxiliary emitter terminals extend through the device package.

7. A control circuit for di / dt control of a power semiconductor device according to any one of claims 1 to 6, wherein the control circuit is arranged to be coupled to a plurality of inductor / resistor pairs of the power semiconductor device, wherein the control circuit is arranged to form a gate drive current return loop through an inductor / resistor pair, And wherein the control circuit is arranged to select the inductor / resistor pair.

8. The control circuit according to claim 7, comprising: A plurality of electronic switches, wherein each electronic switch is arranged to be coupled to one side of an inductor / resistor pair.

9. The control circuit according to claim 8, further comprising: an input arranged to receive a di / dt select input signal; a demultiplexer circuit arranged to receive the di / dt select input signal via the input and coupled to the plurality of electronic switches; as well as One or more oscillation damping resistors coupled between the electronic switch and a gate drive power supply ground.

10. The control circuit according to claim 8, further comprising: an input arranged to receive a di / dt select input signal; a demultiplexer circuit arranged to receive the di / dt select input signal via the input and coupled to the plurality of electronic switches; one or more oscillation damping resistors coupled between the electronic switch and a gate drive power supply ground; as well as a diode, wherein one side of the diode is arranged to be coupled to one side of a first one of the inductor / resistor pairs, wherein the one side of the first one of the inductor / resistor pairs is coupled to an output pad of a power switch of the power semiconductor device, and wherein the other side of the diode is coupled to the gate drive power ground.

11. The control circuit according to claim 8, further comprising: a first input arranged to receive a di / dt reference input signal; a second input arranged to receive a di / dt feedback signal; a di / dt processing logic circuit arranged to receive the di / dt reference input signal via the first input; a demultiplexer circuit coupled to the di / dt processing logic circuit and to the plurality of electronic switches; one or more oscillation damping resistors coupled between the electronic switch and a gate drive power supply ground; a di / dt detection circuit arranged to receive the di / dt feedback signal via the second input and arranged to be coupled to one side of a first one of the inductor / resistor pairs, wherein the one side of the first one of the inductor / resistor pairs is coupled to an output pad of a power switch of the power semiconductor device; an error amplifier circuit arranged to receive the di / dt reference input signal via the first input and arranged to receive the di / dt feedback signal via the second input, wherein the error amplifier circuit is coupled to a gate drive circuit for closed-loop di / dt control of a gate drive level. 12 . An electronic device comprising the power semiconductor device according to claim 1 and the control circuit according to claim 7 . 13 . The electronic device of claim 12 , further comprising a gate drive circuit arranged to be coupled to an input pad and a control pad of a power switch of the power semiconductor device.

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