Disorder correction circuit, disorder correction system and driving chip

Abstract

The application discloses a kind of unbalance correction circuit, unbalance correction system and drive chip, it is related to analog-digital converter correction field, the unbalance correction circuit disclosed includes, including: control module and correction module;The control module is connected with the analog-digital converter and the correction module respectively;The correction module is connected with the analog-digital converter;The correction module is used to carry out parameter correction to the analog-digital converter when circuit is powered on, and when the parameter correction is completed, correction completion signal is transmitted to the control module;The control module is used to compare the correction completion signal with preset completion signal, and when the correction completion signal is consistent with the preset completion signal, the power of the analog-digital converter is obtained;The control module is also used to carry out power correction to the analog-digital converter, so that the output power of the analog-digital converter reaches preset power range.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter correction technology, and in particular to an offset correction circuit, an offset correction system, and a driver chip. Background Technology

[0002] In recent years, with the advancements and improvements in wireless communication technology, analog-to-digital converters (ADCs) have been driven towards better bandwidth, speed, and power consumption, leading to the development of continuous-time delta-sigma ADCs. To improve the performance of continuous-time delta-sigma ADCs, sampling clock rates have increased to GHz (gigahertz), placing increasingly higher demands on quantizers. Therefore, fully dynamic comparators are used in quantizers. While these comparators offer high speed, they also exhibit significant offset and noise. Large offset voltages can cause variations in the transfer function of the continuous-time delta-sigma ADC, degrading ADC performance or causing system oscillations.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this invention is to provide an offset correction circuit, an offset correction system, and a driver chip, aiming to solve the technical problem of performance degradation in analog-to-digital converters.

[0005] To achieve the above objectives, the present invention proposes an offset correction circuit, which is applied to an analog-to-digital converter, and the offset correction circuit includes:

[0006] Control module and calibration module;

[0007] The control module is connected to both the analog-to-digital converter and the correction module; the correction module is connected to the analog-to-digital converter.

[0008] The calibration module is used to perform parameter calibration on the analog-to-digital converter when the circuit is powered on, and to transmit a calibration completion signal to the control module when the parameter calibration is completed.

[0009] The control module is used to compare the calibration completion signal with a preset completion signal, and when the calibration completion signal matches the preset completion signal, obtain the power of the analog-to-digital converter;

[0010] The control module is also used to perform power correction on the analog-to-digital converter so that the output power of the analog-to-digital converter reaches a preset power range.

[0011] In one embodiment, the data correction includes DAC correction, quantizer correction, and RC parameter correction; the correction completion signal includes a DAC correction completion signal, a quantizer correction completion signal, and an RC correction completion signal; the correction module includes:

[0012] DAC correction subunit, quantizer correction subunit, and RC correction subunit;

[0013] The control module and the analog-to-digital converter are respectively connected to the DAC correction subunit, the quantizer correction subunit, and the RC correction subunit;

[0014] The DAC correction subunit is used to perform DAC correction on the analog-to-digital converter when the circuit is powered on, and to transmit the DAC correction completion signal to the control module when the DAC correction is completed.

[0015] The quantizer correction subunit is used to perform quantizer correction on the analog-to-digital converter when the DAC correction is completed, and to transmit the quantizer correction completion signal to the control module when the quantizer correction is completed.

[0016] The RC correction subunit is used to perform RC parameter correction on the analog-to-digital converter when the quantizer correction is completed, and to transmit the RC correction completion signal to the control module when the RC parameter correction is completed.

[0017] In one embodiment, the preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal, and an RC preset completion signal, and the control module includes:

[0018] DAC control subunit, quantizer control subunit, and RC control subunit;

[0019] The DAC control subunit is connected to the quantizer control subunit, the DAC correction subunit, and the quantizer correction subunit, respectively; the quantizer control subunit is connected to the RC control subunit and the quantizer correction subunit, respectively; the RC control subunit is connected to the RC correction subunit and the analog-to-digital converter, respectively.

[0020] The DAC control subunit is used to compare the DAC correction completion signal with the DAC preset completion signal, and when the DAC correction completion signal is consistent with the DAC preset completion signal, send a first execution signal to the quantizer control subunit.

[0021] The quantizer control subunit is configured to compare the quantizer calibration completion signal with the quantizer preset completion signal when it receives the first execution signal, and send a second execution signal to the RC control subunit when the quantizer calibration completion signal is consistent with the quantizer preset completion signal.

[0022] The RC control subunit is configured to compare the RC correction completion signal with the RC preset completion signal when it receives the second execution signal, and to obtain the power of the analog-to-digital converter when the RC correction completion signal and the RC preset completion signal are consistent.

[0023] In one embodiment, the offset correction circuit further includes:

[0024] Clock module;

[0025] The clock module is connected to both the control module and the analog-to-digital converter.

[0026] The clock module is used to provide clock signals to the analog-to-digital converter and the control module.

[0027] In one embodiment, the offset correction circuit further includes:

[0028] Downsampling module;

[0029] The downsampling module is connected to the analog-to-digital converter;

[0030] The downsampling module is used to reduce the amount of data for the power.

[0031] In one embodiment, the offset correction circuit further includes:

[0032] Power detection module;

[0033] The power detection module is connected to both the downsampling module and the control module.

[0034] The power detection module is used to acquire the power of the reduced data volume, compare the power with the preset power range, and send a power correction signal to the control module when the power does not reach the preset power range.

[0035] In one embodiment, the control module is further configured to transmit a correction execution signal to the correction module when power-on of the circuit is detected.

[0036] In one embodiment, the control module is further configured to perform power correction on the analog-to-digital converter according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

[0037] Furthermore, to achieve the above objectives, the present invention also proposes an offset correction system, which includes the offset correction circuit described above.

[0038] In addition, to achieve the above objectives, the present invention also proposes a driver chip, which includes the aforementioned analog-to-digital converter and offset correction circuit, wherein the analog-to-digital converter is connected to the offset correction circuit.

[0039] One or more technical solutions proposed in this invention have at least the following technical effects:

[0040] The offset correction circuit of the present invention includes: a control module and a correction module; the control module is connected to both the analog-to-digital converter (ADC) and the correction module; the correction module is connected to the ADC; the correction module is used to perform parameter correction on the ADC when the circuit is powered on, and transmit a correction completion signal to the control module when the parameter correction is completed; the control module is used to compare the correction completion signal with a preset completion signal, and obtain the power of the ADC when the correction completion signal matches the preset completion signal; the control module is also used to perform power correction on the ADC to make the output power of the ADC reach a preset power range. By performing DAC correction, quantizer correction, and RC parameter correction on the ADC, the performance of the ADC is improved. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 1 of the present invention;

[0044] Figure 2 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 2 of the present invention.

[0045] Explanation of icon numbers:

[0046]

[0047]

[0048] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0051] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0052] With the advancement and continuous improvement of wireless communication technology, the bandwidth, speed, and power consumption of analog-to-digital converters (ADCs) are being optimized, leading to the development of continuous-time delta-sigma ADCs. To enhance the performance of continuous-time delta-sigma ADCs, sampling clock rates are increasingly higher, reaching GHz (gigahertz), placing increasingly stringent demands on quantizers. Therefore, fully dynamic comparators are used in quantizers. While these comparators offer high speed, they also exhibit significant offset and noise. Large offset voltages can cause variations in the transfer function of the continuous-time delta-sigma ADC, degrading ADC performance or causing system oscillations.

[0053] To address the above problems, this invention proposes an offset correction circuit, aiming to solve the technical problem of performance degradation in analog-to-digital converters.

[0054] refer to Figure 1 , Figure 1 This is a schematic diagram of the offset correction circuit according to a first embodiment of the present invention. The offset correction circuit is applied to the analog-to-digital converter 3, and includes:

[0055] Control module 1 and calibration module 2;

[0056] The control module 1 is connected to both the analog-to-digital converter 3 and the correction module 2; the correction module 2 is connected to the analog-to-digital converter 3.

[0057] The correction module 2 is used to perform data correction on the analog-to-digital converter 3 when the circuit is powered on, and to transmit a correction completion signal to the control module 1 when the data correction is completed.

[0058] The control module 1 is used to compare the correction completion signal with the preset completion signal, and to obtain the power of the analog-to-digital converter 3 when the correction completion signal is consistent with the preset completion signal;

[0059] The control module 1 is also used to perform power correction on the analog-to-digital converter 3 so that the output power of the analog-to-digital converter 3 reaches a preset power range.

[0060] It should be noted that, in this embodiment, the analog-to-digital converter is a continuous-time delta-sigma ADC (Delta-Sigma Analog-to-Digital Converter);

[0061] It should be noted that the above-mentioned preset power range can be the power range of the above-mentioned analog-to-digital converter 3 when the accuracy and dynamic performance both meet the target requirements under PVT (process, voltage, temperature) conditions. The specific range shall be calibrated by the technicians according to the actual needs.

[0062] In its implementation, the correction module 2 performs data correction on the analog-to-digital converter 3 when the entire offset correction circuit is powered on, and transmits a correction completion signal to the control module 1 upon completion of the data correction. Upon receiving the correction completion signal, the control module 1 compares it with a preset completion signal. If the correction completion signal matches the preset completion signal, the power of the analog-to-digital converter 3 is obtained. If the correction completion signal does not match the preset completion signal, the control module 2 is controlled to re-perform the data correction on the analog-to-digital converter 3, repeating this process until the correction completion signal matches the preset completion signal. The control module 1 also performs power correction on the analog-to-digital converter 3. If the output power of the analog-to-digital converter 3 reaches the preset power range, the power correction operation of the control module 1 is stopped. If the output power of the analog-to-digital converter 3 does not reach the preset power range, the capacitor array in the correction module 3 is controlled to correct the output power of the analog-to-digital converter 3. These data correction and power correction methods ensure the performance of the analog-to-digital converter during operation.

[0063] To ensure that the aforementioned analog-to-digital converter 3 is more accurate and efficient during the calibration process, refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 2 of the present invention.

[0064] In this embodiment, the data correction includes DAC correction, quantizer correction, and RC parameter correction. The correction completion signal includes a DAC correction completion signal, a quantizer correction completion signal, and an RC correction completion signal. The correction module 2 includes:

[0065] DAC correction subunit 21, quantizer correction subunit 22, and RC correction subunit 23;

[0066] The control module 1 and the analog-to-digital converter 3 are respectively connected to the DAC correction subunit 21, the quantizer correction subunit 22 and the RC correction subunit 23;

[0067] The DAC correction subunit 21 is used to perform DAC correction on the analog-to-digital converter 3 when the circuit is powered on, and to transmit the DAC correction completion signal to the control module 1 when the DAC correction is completed.

[0068] The quantizer correction subunit 22 is used to perform the quantizer correction on the analog-to-digital converter 3 when the DAC correction is completed, and to transmit the quantizer correction completion signal to the control module 1 when the quantizer correction is completed.

[0069] The RC correction subunit 23 is used to perform RC parameter correction on the analog-to-digital converter 3 when the quantizer correction is completed, and to transmit the RC correction completion signal to the control module 1 when the RC parameter correction is completed.

[0070] It should be noted that the DAC correction described above is current source mismatch correction. Current source mismatch correction refers to the process of calibrating the current source to eliminate or reduce its mismatch error. In current-driven digital-to-analog converters (DACs), current source mismatch negatively impacts the DAC's linearity and performance.

[0071] It should be noted that the quantizer calibration described above is comparator offset calibration. The causes of comparator offset may include manufacturing process deviations, temperature variations, power supply voltage fluctuations, and component aging. These factors can all cause changes in the comparator's input offset voltage or offset current, thus affecting its normal operation.

[0072] It should be noted that the above RC parameter correction refers to the correction and adjustment of the resistance and capacitance values ​​in the circuit.

[0073] It is understandable that the above-mentioned DAC correction completion signal, the above-mentioned quantizer correction completion signal, and the above-mentioned RC correction completion signal are all high-level signals.

[0074] In a specific implementation, the DAC correction subunit 21 performs DAC correction on the analog-to-digital converter 3 when the circuit is powered on, and transmits the DAC correction completion signal to the control module 1 when the DAC correction is completed. The quantizer correction subunit 22 performs quantizer correction on the analog-to-digital converter 3 when the DAC correction is completed, and transmits the quantizer correction completion signal to the control module 1 when the quantizer correction is completed. The DAC correction steps can be interchanged with the quantizer correction steps. The RC correction subunit performs RC parameter correction on the analog-to-digital converter 3 when both the DAC correction and the quantizer correction are completed, and transmits the RC correction completion signal to the control module 1 when the RC parameter correction is completed. The RC parameter correction is performed as the last step.

[0075] In one embodiment, the preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal, and an RC preset completion signal, and the control module 1 includes:

[0076] DAC control subunit 11, quantizer control subunit 12, and RC control subunit 13;

[0077] The DAC control subunit 11 is connected to the quantizer control subunit 12, the DAC correction subunit 21, and the quantizer correction subunit 22, respectively; the quantizer control subunit 12 is connected to the RC control subunit 13 and the quantizer correction subunit 22, respectively; the RC control subunit 13 is connected to the RC correction subunit 23 and the analog-to-digital converter 3, respectively.

[0078] The DAC control subunit 11 is used to compare the DAC correction completion signal with the DAC preset completion signal, and when the DAC correction completion signal is consistent with the DAC preset completion signal, send a first execution signal to the quantizer control subunit 12.

[0079] The quantizer control subunit 12 is used to compare the quantizer calibration completion signal with the quantizer preset completion signal when it receives the first execution signal, and send a second execution signal to the RC control subunit 13 when the quantizer calibration completion signal is consistent with the quantizer preset completion signal.

[0080] The RC control subunit 13 is used to compare the RC correction completion signal with the RC preset completion signal when it receives the second execution signal, and to obtain the power of the analog-to-digital converter 3 when the RC correction completion signal is consistent with the RC preset completion signal.

[0081] It should be noted that, in order to meet the timing requirements of the circuit, the first execution signal is used to control the quantizer control subunit 12 to operate when the DAC control subunit 11 has finished operating, and the second execution signal is used to control the RC control subunit 13 to operate when the quantizer control subunit 12 has finished operating.

[0082] It is understood that the aforementioned DAC preset completion signal is a 16-bit data precision signal, the aforementioned first execution signal is a 128-bit data precision signal, the aforementioned quantizer preset completion signal and the aforementioned second execution signal are 64-bit data precision signals, and the aforementioned RC preset completion signal is an 8-bit data precision signal.

[0083] In a specific implementation, the DAC control subunit 11 is used to compare the DAC correction completion signal with the DAC preset completion signal, and when the DAC correction completion signal is consistent with the DAC preset completion signal, send the first execution signal to the quantizer control subunit; the quantizer control subunit 12 is used to compare the quantizer correction completion signal with the quantizer preset completion signal when receiving the first execution signal, and send the second execution signal to the RC control subunit 13 when the quantizer correction completion signal is consistent with the quantizer preset completion signal; the RC control subunit 13 is used to compare the RC correction completion signal with the RC preset completion signal when receiving the second execution signal, and obtain the power of the analog-to-digital converter 3 when the RC correction completion signal is consistent with the RC preset completion signal.

[0084] In one embodiment, the offset correction circuit further includes:

[0085] Clock module 4;

[0086] The clock module 4 is connected to the control module 1 and the analog-to-digital converter 3 respectively;

[0087] The clock module 4 is used to provide clock signals to the analog-to-digital converter 3 and the control module 1.

[0088] In the specific implementation, the clock module 4 is used to provide clocks for the control module 1 and the analog-to-digital converter 3. Since the clock rate of the analog-to-digital converter is very high, reaching GHz, operating at this rate can lead to timing irregularities and high power consumption. Therefore, the clock of the analog-to-digital converter 3 needs to be divided. Low-speed division is used in the DAC correction and quantizer correction, while a normal clock is used during RC parameter correction and normal operation. To ensure that the two clocks do not interfere with each other, the control module 1 uses a low-speed clock during DAC correction and quantizer correction, and automatically shuts off this clock after correction is complete, then starts outputting a high-speed clock.

[0089] In one embodiment, the offset correction circuit further includes:

[0090] Downsampling module 5;

[0091] The downsampling module 5 is connected to the analog-to-digital converter 3;

[0092] The downsampling module 5 is used to reduce the amount of data related to the power.

[0093] In practice, due to the high clock frequency, the aforementioned offset correction circuit is difficult to operate at such a high frequency. Therefore, it is necessary to reduce the sampling rate in order to perform subsequent digital processing, that is, to reduce the amount of data related to the aforementioned power.

[0094] In one embodiment, the offset correction circuit further includes:

[0095] Power detection module 6;

[0096] The power detection module 6 is connected to the downsampling module 5 and the control module 1 respectively;

[0097] The power detection module 6 is used to acquire the power of the reduced data volume, compare the power with the preset power range, and send a power correction signal to the control module 1 when the power does not reach the preset power range.

[0098] In a specific implementation, the power detection module 6 is used to compare the power with the preset power range, and when the power does not reach the preset power range, send the power correction signal to the control module 1.

[0099] In one embodiment, the control module 1 is further configured to transmit a correction execution signal to the correction module 2 when the circuit is detected to be powered on.

[0100] It should be noted that the above-mentioned correction execution signal is used to activate the above-mentioned correction module 2.

[0101] In a specific implementation, when the control module 1 detects that the circuit is powered on, it transmits the correction execution signal to the correction module 2.

[0102] In one embodiment, the control module 1 is further configured to perform power correction on the analog-to-digital converter 3 according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

[0103] In a specific implementation, the control module 1 is further configured to control the capacitor array in the RC correction module 23 to adjust the power of the analog-to-digital converter 3 according to the power correction signal, that is, to perform power correction on the analog-to-digital converter 3 so that the output power of the analog-to-digital converter 3 reaches the preset power range.

[0104] Furthermore, to achieve the above objectives, the present invention also proposes an offset correction system, which includes the offset correction circuit as described above. Other embodiments or specific implementations of the offset correction system of the present invention can be found in the embodiments of the offset correction circuit described above, and will not be repeated here.

[0105] Furthermore, to achieve the above objectives, the present invention also proposes a driver chip, which includes an analog-to-digital converter as described above and an offset correction circuit. Other embodiments or specific implementations of the driver chip of the present invention can be found in the embodiments of the offset correction circuit described above, and will not be repeated here.

[0106] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An offset correction circuit, characterized in that, The offset correction circuit is applied to the analog-to-digital converter, and the offset correction circuit includes: Control module and calibration module; The control module is connected to both the analog-to-digital converter and the correction module; the correction module is connected to the analog-to-digital converter. The correction module is used to perform data correction on the analog-to-digital converter when the circuit is powered on, and to transmit a correction completion signal to the control module when the data correction is completed. The control module is used to compare the calibration completion signal with a preset completion signal, and when the calibration completion signal matches the preset completion signal, obtain the power of the analog-to-digital converter; The control module is also used to perform power correction on the analog-to-digital converter so that the output power of the analog-to-digital converter reaches a preset power range; The preset completion signal includes a DAC preset completion signal, a quantizer preset completion signal, and an RC preset completion signal. The control module includes: DAC control subunit, quantizer control subunit, and RC control subunit; The DAC control subunit is connected to the quantizer control subunit, the DAC correction subunit, and the quantizer correction subunit, respectively; the quantizer control subunit is connected to the RC control subunit and the quantizer correction subunit, respectively; the RC control subunit is connected to the RC correction subunit and the analog-to-digital converter, respectively. The DAC control subunit is used to compare the DAC correction completion signal with the DAC preset completion signal, and when the DAC correction completion signal is consistent with the DAC preset completion signal, send a first execution signal to the quantizer control subunit. The quantizer control subunit is configured to compare the quantizer calibration completion signal with the quantizer preset completion signal when it receives the first execution signal, and send a second execution signal to the RC control subunit when the quantizer calibration completion signal is consistent with the quantizer preset completion signal. The RC control subunit is configured to compare the RC correction completion signal with the RC preset completion signal when it receives the second execution signal, and to obtain the power of the analog-to-digital converter when the RC correction completion signal is consistent with the RC preset completion signal.

2. The offset correction circuit as described in claim 1, characterized in that, The data correction includes DAC correction, quantizer correction, and RC parameter correction. The correction completion signal includes a DAC correction completion signal, a quantizer correction completion signal, and an RC correction completion signal. The correction module includes: DAC correction subunit, quantizer correction subunit, and RC correction subunit; The control module and the analog-to-digital converter are respectively connected to the DAC correction subunit, the quantizer correction subunit, and the RC correction subunit; The DAC correction subunit is used to perform DAC correction on the analog-to-digital converter when the circuit is powered on, and to transmit the DAC correction completion signal to the control module when the DAC correction is completed. The quantizer correction subunit is used to perform quantizer correction on the analog-to-digital converter when the DAC correction is completed, and to transmit the quantizer correction completion signal to the control module when the quantizer correction is completed. The RC correction subunit is used to perform RC parameter correction on the analog-to-digital converter when the quantizer correction is completed, and to transmit the RC correction completion signal to the control module when the RC parameter correction is completed.

3. The offset correction circuit as described in claim 1, characterized in that, The offset correction circuit also includes: Clock module; The clock module is connected to both the control module and the analog-to-digital converter. The clock module is used to provide clock signals to the analog-to-digital converter and the control module.

4. The offset correction circuit as described in claim 3, characterized in that, The offset correction circuit also includes: Downsampling module; The downsampling module is connected to the analog-to-digital converter; The downsampling module is used to reduce the amount of data for the power.

5. The offset correction circuit as described in claim 4, characterized in that, The offset correction circuit also includes: Power detection module; The power detection module is connected to both the downsampling module and the control module. The power detection module is used to acquire the power of the reduced data volume, compare the power with the preset power range, and send a power correction signal to the control module when the power does not reach the preset power range.

6. The offset correction circuit as described in claim 5, characterized in that, The control module is also used to transmit a correction execution signal to the correction module when the circuit is detected to be powered on.

7. The offset correction circuit as described in claim 5, characterized in that, The control module is further configured to perform power correction on the analog-to-digital converter according to the power correction signal, so that the output power of the analog-to-digital converter reaches the preset power range.

8. An offset correction system, characterized in that, The offset correction system includes: the offset correction circuit according to any one of claims 1 to 6.

9. A driver chip, characterized in that, The driver chip includes: an analog-to-digital converter and an offset correction circuit as described in any one of claims 1 to 6, wherein the analog-to-digital converter is connected to the offset correction circuit.

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