Signal sampling processing system and method for multi-chip synchronization

Abstract

The invention discloses a signal sampling processing system and method for multi-chip synchronization, and relates to the field of transceiver chips. A clock generation circuit inputs a first differential signal and a second differential signal; synchronously sampling the received signals of the plurality of transceiver chips to obtain a first synchronous signal and a second synchronous signal; delaying the first synchronization signal and the second synchronization signal until the signals are stable; respectively generating two control signals with a phase difference of 180 degrees by using the first synchronizing signal and the second synchronizing signal; any control signal is selected to be connected with a switch between the clock generation circuit, and if phase ambiguity occurs to the four-phase local oscillator clock signal output by the clock generation circuit, another control signal is selected to be sent to the clock generation circuit. According to the invention, multi-chip synchronization can be realized, phase ambiguity is eliminated, and the phase of a chip clock is kept unchanged.

Description

Technical Field

[0001] The present invention relates to the field of transceiver chips, and specifically to a signal sampling and processing system and method for multi-chip synchronization. Background Art

[0002] In modern communication systems, the synchronization of radio frequency transceiver chips is a key issue. When multiple transceiver chips work simultaneously, it is crucial to ensure the phase consistency of their local oscillator (LO) clocks and baseband clocks. However, in the prior art, due to factors such as temperature changes and signal interference, the clock phase may become ambiguous, resulting in the inability of multi-chips to achieve precise synchronization. This phase ambiguity problem mainly stems from the randomness of the phase-locked loop (PLL) and clock generation circuits when aligning signal edges, posing challenges to the stability and performance of the system. In recent years, although some solutions have attempted to alleviate this problem by improving circuit design or adding calibration steps, the impact of phase ambiguity cannot be fundamentally eliminated.

[0003] Specifically, when multiple radio frequency transceiver chips work simultaneously, after the system sends a synchronization signal to each chip, it is required that the LO IQ clocks of each transceiver chip are in a fixed phase state. The same requirement applies to the phase of the baseband clock, which means that there should be no phase ambiguity problem in the LO clock and baseband clock generation circuits. If the LO frequency is generated by fractional division of the PLL, the LO IQ clock can be looped back to the PLL, and the digital algorithm can be used to keep the phase of the LO clock fixed by the PLL loop. This method is difficult to handle the case of integer division of the PLL. Therefore, there is another method of delaying and selecting the synchronization signal sent by the system to stagger the clock edges of the LO PLL or baseband PLL to avoid the phase ambiguity problem of the output clock. This method is difficult to ensure whether the synchronization signal can still be staggered from the PLL clock edge when the temperature changes, especially when the frequency is high (the operating frequency of radio frequency transceivers is generally very high, and the frequency output by the PLL can reach 13 GHz). Therefore, this method is also unreliable. Therefore, there is currently a need for a signal sampling and processing system and method for multi-chip synchronization that can achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the LO clock or baseband clock remains unchanged after each synchronization signal arrives at the chip. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the LO clock or baseband clock remains unchanged after each synchronization signal arrives at the chip. The purpose is to provide a signal sampling and processing system and method for multi-chip synchronization, which solves the above technical problems.

[0005] The present invention is achieved by the following technical solutions:

[0006] A signal sampling and processing system for multi-chip synchronization, which is applied to multiple transceiver chips; the processing system includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing system further includes:

[0007] A sampling unit for synchronously sampling the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal, wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal;

[0008] A delay unit for delaying the first synchronization signal and the second synchronization signal to synchronize the first differential signal with the first synchronization signal and the second differential signal with the second synchronization signal;

[0009] A synchronization unit for generating two control signals based on the first synchronization signal and the second synchronization signal respectively, the duty cycles and frequencies of the two control signals are the same, and the phase difference is 180°;

[0010] A switch selection unit for selecting any one of the control signals and sending it to the clock generation circuit, and if the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, then sequentially select the other control signal and send it to the clock generation circuit until there is no phase ambiguity.

[0011] Further, the sampling unit includes a first RS flip-flop and a second RS flip-flop; the first RS flip-flop and the second RS flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS flip-flop is the first differential signal, and the sampling signal of the second RS flip-flop is the second differential signal.

[0012] Further, the sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is the first differential signal, and the sampling signal of the sixth D flip-flop is the second differential signal.

[0013] Further, the delay unit includes a third RS flip-flop and a fourth RS flip-flop; the input end of the third RS flip-flop is connected to the output end of the first RS flip-flop; the input end of the fourth RS flip-flop is connected to the output end of the second RS flip-flop; the sampling signal of the third RS flip-flop is the second differential signal; the sampling signal of the fourth RS flip-flop is the first differential signal.

[0014] Further, the synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop, and the third RS flip-flop are in parallel; the sampling signal of the first D flip-flop is a first differential signal; the sampling signal of the second D flip-flop is a second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop, and the fourth RS flip-flop are in parallel; the sampling signal of the fourth D flip-flop is a first differential signal; the sampling signal of the third D flip-flop is a second differential signal.

[0015] Further, the switch selection unit includes a first switch, a second switch, a third switch, and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generation circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generation circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generation circuit through the third switch; the output end of the fourth D flip-flop is connected to the input end of the clock generation circuit through the fourth switch.

[0016] Further, the phase-locked loop is a local oscillator phase-locked loop, and the clock generation circuit is a local oscillator clock or a baseband clock generation circuit.

[0017] A signal sampling processing method for multi-chip synchronization, which is applied to multiple transceiver chips; the processing method includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing method further includes the following steps:

[0018] Synchronously sample the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein, the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal;

[0019] Delay the first synchronization signal and the second synchronization signal to synchronize the first differential signal with the first synchronization signal and the second differential signal with the second synchronization signal;

[0020] Generate two control signals based on the first synchronization signal and the second synchronization signal respectively, and the duty cycles and frequencies of the two control signals are the same, and the phase difference is 180°;

[0021] Select any one of the control signals and send it to the clock generation circuit, and if the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, then sequentially select the other control signal and send it to the clock generation circuit until there is no phase ambiguity.

[0022] Further, the sampling unit includes a first RS flip-flop and a second RS flip-flop; the first RS flip-flop and the second RS flip-flop respectively receive the synchronization control signals of the plurality of transceiver chips; the sampling signal of the first RS flip-flop is the first differential signal, and the sampling signal of the second RS flip-flop is the second differential signal.

[0023] Further, the sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of the plurality of transceiver chips; the sampling signal of the fifth D flip-flop is the first differential signal, and the sampling signal of the sixth D flip-flop is the second differential signal.

[0024] Further, the delay unit includes a third RS flip-flop and a fourth RS flip-flop; the input end of the third RS flip-flop is connected to the output end of the first RS flip-flop; the input end of the fourth RS flip-flop is connected to the output end of the second RS flip-flop; the sampling signal of the third RS flip-flop is the second differential signal; the sampling signal of the fourth RS flip-flop is the first differential signal.

[0025] Further, the synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is the first differential signal; the sampling signal of the second D flip-flop is the second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; the sampling signal of the third D flip-flop is the second differential signal.

[0026] The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generation circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generation circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generation circuit through the third switch; the output end of the fourth D flip-flop is connected to the input end of the clock generation circuit through the fourth switch.

[0027] The phase-locked loop is a local oscillator phase-locked loop;

[0028] The clock generation circuit is a local oscillator clock or a baseband clock generation circuit.

[0029] A signal sampling and processing method for multi-chip synchronization, which is applied to multiple transceiver chips; the processing method includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing method further includes the following steps:

[0030] Synchronously sample the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein, the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal;

[0031] Delay the first synchronization signal and the second synchronization signal to synchronize the first differential signal with the first synchronization signal and the second differential signal with the second synchronization signal;

[0032] Generate two control signals based on the first synchronization signal and the second synchronization signal respectively, the duty cycles and frequencies of the two control signals are the same, and the phase difference is 180°;

[0033] Select any one of the control signals and send it to the clock generation circuit. If the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, then sequentially select the other control signal and send it to the clock generation circuit until there is no phase ambiguity.

[0034] The synchronously sampling the synchronization control signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal includes:

[0035] Sample the first synchronization signal and the second synchronization signal respectively using an RS flip-flop or a D flip-flop;

[0036] The delaying the first synchronization signal and the second synchronization signal includes:

[0037] Block the first synchronization signal and the second synchronization signal using an RS flip-flop;

[0038] The generating two control signals based on the first synchronization signal and the second synchronization signal respectively includes:

[0039] Generate two control signals of the first synchronization signal and the synchronization signal respectively using two D flip-flops;

[0040] The selecting any one of the control signals and sending it to the clock generation circuit includes:

[0041] Use different switches to control whether each control signal is sent to the clock generation circuit.

[0042] Selecting any one of the control signals and sending it to the clock generation circuit includes:

[0043] Sending the two control signals generated based on the first synchronization signal and the two control signals generated based on the second synchronization signal to the clock generation circuit respectively.

[0044] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0045] The present invention provides a signal sampling and processing system for multi-chip synchronization. By using the differential clock signal provided by a phase-locked loop, the synchronization signal input from outside the chip is resynchronized, and through a signal selection mechanism, synchronization signals with different phases are output to ensure that the local oscillator clock and the baseband clock of the transceiver remain unchanged in phase after the synchronization signal arrives. Specifically, a first differential signal and a second differential signal are generated by the phase-locked loop and input to the clock generation circuit; a sampling unit synchronously samples the received signals of multiple transceiver chips; the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal; a delay unit delays the first synchronization signal and the second synchronization signal until the signals are stable, and then the synchronization unit generates two control signals respectively using the first synchronization signal and the second synchronization signal; the phase difference between the two control signals is 180°; a switch selection unit sequentially selects the switches between each control signal and the clock generation circuit to be connected; if the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, it means that the selected control signal can be obtained by sequentially selecting at most four times. The present invention uses a phase-locked loop to resynchronize the synchronization signals input to multiple chips; the signals enter the clock generation circuit and output four synchronization signals, and signal selection is performed according to the phase ambiguity represented by different phases to avoid phase ambiguity caused by the signal edges colliding with the signals sent by the phase-locked loop; the synchronization signals selected by the phase-locked loop can ensure that they are far from the signal edges of the phase-locked loop itself, so that phase ambiguity does not occur even when the temperature changes. The present invention can achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the local oscillator clock or the baseband clock of the chip remains unchanged after each synchronization signal arrives. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0047] Figure 1 It is a schematic diagram of the phase-locked loop and the clock generation circuit in the ideal case of the embodiment of the present application;

[0048] Figure 2 Schematic diagram of signal synchronization for the clock generation circuit in the ideal case of the embodiment of the present application;

[0049] Figure 3 Schematic diagram of signal synchronization for the clock generation circuit of the prior art of the present application;

[0050] Figure 4 Schematic diagram of the inverter delay signal of the prior art of the embodiment of the present application;

[0051] Figure 5 Schematic diagram of signal synchronization for the clock generation circuit of the prior art of the embodiment of the present application;

[0052] Figure 6 Schematic diagram of the signal sampling and processing system for multi-chip synchronization of the embodiment of the present application;

[0053] Figure 7 Schematic diagram of the existing RS flip-flop adopted in the embodiment of the present application;

[0054] Figure 8 Example diagram of the sampling unit of the embodiment of the present application;

[0055] Figure 9 Example diagram of the synchronization unit of the embodiment of the present application. Detailed implementation manners

[0056] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with embodiments and the accompanying drawings. The illustrative embodiments and descriptions thereof of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0057] The following will describe in detail the specific implementation manners of the present application in conjunction with the accompanying drawings. It should be understood that the specific implementation manners described herein are only used to explain the relevant invention and are not intended to limit the invention. Additionally, it should be noted that for the sake of convenience of description, only the parts related to the relevant invention are shown in the drawings.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific implementation manners and are not intended to limit this application; unless specifically defined, all technical and scientific terms used herein have the ordinary meaning understood by those of ordinary skill in the technical field to which this application belongs; for the purpose of avoiding unnecessary disputes, the terms "first", "second", etc. cited in this application are only set to distinguish similar things and have no other special meaning.

[0059] In addition, although the flowcharts in the accompanying drawings described in this application show the processing procedures according to various embodiments of this application, it should be understood that this application is not limited to the order and arrangement shown in the accompanying drawings. Instead, it is possible to execute the processing in a different order from that shown in the accompanying drawings (such as, substantially simultaneously, or in reverse order), depending on the functions / operations involved.

[0060] Embodiment

[0061] A phase-locked loop (PLL) is a circuit used to generate a stable clock signal. It can lock the phase and frequency of an input signal and thus output a signal with the same phase and frequency as the input signal. In this solution, the output of the PLL is a differential clock signal, which consists of two complementary signal lines and can better resist electromagnetic interference and improve signal integrity.

[0062] As Figures 6 to 9 shown, the embodiment of this application provides a signal sampling processing system for multi-chip synchronization, which is applied to multiple transceiver chips; the processing system includes: a phase-locked loop for generating a first differential signal and a second differential signal; a clock generation circuit for inputting the first differential signal and the second differential signal; the processing system further includes:

[0063] a sampling unit for synchronously sampling the received signals of multiple transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein, the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal;

[0064] a delay unit for delaying the first synchronization signal and the second synchronization signal to synchronize the first differential signal with the first synchronization signal and the second differential signal with the second synchronization signal;

[0065] a synchronization unit for respectively generating two control signals based on the first synchronization signal and the second synchronization signal. The duty cycles and frequencies of the two control signals are the same, and the phase difference is 180°;

[0066] a switch selection unit for selecting any one of the control signals and sending it to the clock generation circuit; if the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, which means that the phases of the four signals are different at this time, then sequentially select another control signal and send it to the clock generation circuit until a control signal without phase ambiguity is selected and sent to the clock generation circuit. Thus, by selecting another control signal and sending it to the clock generation circuit at most four times.

[0067] A transceiver chip, also known as an interface transceiver chip, is an integrated circuit used for data communication and is mainly responsible for sending and receiving data between different devices or systems.

[0068] A phase-locked loop or phase-locked circuit (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types. The simplest is an electronic circuit consisting of a voltage-controlled oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of this signal with the phase of the input periodic signal, adjusting the oscillator to maintain phase matching. Keeping the input and output phases in lock step also means keeping the input and output frequencies the same. Therefore, in addition to synchronizing signals, a phase-locked loop can track the input frequency or can generate the input frequency.

[0069] A clock circuit is an oscillating circuit that generates a motion as accurate as a clock. Any work is in chronological order. The circuit used to generate this time is the clock circuit. A clock circuit generally consists of a crystal oscillator, a crystal oscillator control chip, and capacitors. An oscillator is a circuit that can generate a stable periodic signal. The working principle of a clock circuit is based on the characteristics of an oscillator. When an oscillator is connected to an appropriate feedback network, self-oscillation occurs, and a continuous periodic waveform is output. These waveforms are usually square waves, sine waves, or pulse waveforms, used to represent discrete intervals of time.

[0070] The phase-locked loop is a local oscillator phase-locked loop, and the clock generation circuit is a local oscillator clock or baseband clock generation circuit.

[0071] The local oscillator phase-locked loop is a closed-loop system composed of a phase-locked loop (PLL) and an oscillator (VCO). The PLL is a negative feedback control system used to keep the phase of an input signal and the phase of a reference signal at a constant phase difference. The VCO is a voltage-controlled oscillator whose output frequency can be adjusted by controlling the input voltage. When the phase-locked loop works, first, the reference signal needs to be divided by a frequency divider to obtain a reference frequency, and then multiplied by the input signal to obtain an error signal. This error signal is filtered and amplified and then input into the VCO as a control signal to adjust the output frequency of the VCO. By continuously adjusting the frequency of the VCO, the phase difference between the input signal and the reference signal is kept at a constant value, thus achieving frequency stability and accuracy.

[0072] The sampling unit includes a first RS flip-flop and a second RS flip-flop; the first RS flip-flop and the second RS flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS flip-flop is a first differential signal, and the sampling signal of the second RS flip-flop is a second differential signal.

[0073] The sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the input terminals of the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is a first differential signal, and the sampling signal of the sixth D flip-flop is a second differential signal.

[0074] The delay unit includes a third RS flip-flop and a fourth RS flip-flop; the input terminal of the third RS flip-flop is connected to the output terminal of the first RS flip-flop; the input terminal of the fourth RS flip-flop is connected to the output terminal of the second RS flip-flop; the sampling signal of the third RS flip-flop is the second differential signal; the sampling signal of the fourth RS flip-flop is the first differential signal.

[0075] The synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input terminal of the second D flip-flop is connected to the output terminal of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are in parallel; the sampling signal of the first D flip-flop is the first differential signal; the sampling signal of the second D flip-flop is the second differential signal; the input terminal of the fourth D flip-flop is connected to the output terminal of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; the sampling signal of the third D flip-flop is the second differential signal.

[0076] The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output terminal of the first D flip-flop is connected to the input terminal of the clock generation circuit through the first switch; the output terminal of the second D flip-flop is connected to the input terminal of the clock generation circuit through the second switch; the output terminal of the third D flip-flop is connected to the input terminal of the clock generation circuit through the third switch; the output terminal of the fourth D flip-flop is connected to the input terminal of the clock generation circuit through the fourth switch.

[0077] Figure 1 This is an ideal situation of the prior art. In fact, the synchronization signal sync_en of multiple chips sent by the system is asynchronous with the first differential signal PLL_outn and the second differential signal PLL_outp output by the phase-locked loop, and sync_en may appear at any phase of the PLL output clock generation circuit. Figure 2 denote Figure 1 In the ideal situation shown, after receiving this signal, the local oscillator clock generation circuit starts from the next rising edge of PLL_outp (falling edge of PLL_outn), and sequentially generates the four-phase local oscillator Q, I, QB, and IB signals in this process. Figure 3 Show the situation where sync_en appears at the rising edge of PLL_outp (falling edge of PLL_outn). Here, since sync_en exactly appears at the edge where the local oscillator clock generation circuit is about to change, due to the influence of clock jitter, temperature, etc., the circuit may respond immediately here (corresponding to Figure 3 the first case); it is also possible that the circuit cannot respond immediately at this time, then it will be postponed to the next rising edge of PLL_outp, that is, the next falling edge of PLL_outn (corresponding to Figure 3The second case). Compared with the quadrature local oscillator clock in the first case and the second case, the phase difference is 180°. That is, there may be two cases after sync_en arrives, which is called the phase ambiguity phenomenon. Since the radio frequency phase-locked loop operates at high frequencies (from several GHz to more than a dozen GHz), the clock edge is not very steep, and the proportion of the circuit response time in the clock cycle is also relatively high. Therefore, the probability of this phenomenon is not low. Figure 3 For example, if the local oscillator clock and the local oscillator phase-locked loop clock are not in a divide-by-two relationship, then the phase difference of the phase ambiguity may not be 180°. This phenomenon will affect the synchronization function of the multi-transceiver chip. The baseband clock generation circuit also has the same problem.

[0078] Figure 4 and Figure 5 The figure shows an existing technology that delays the sync_en signal through an inverter delay, and then selects an appropriate sync_en_out signal through a switch to stagger the edge of the phase-locked loop clock. The disadvantage of this technology is that the staggering amplitude of the delay may not be sufficient. Even if the chip is configured at room temperature to make the circuit free of phase ambiguity problems, there may still be points that cause phase ambiguity in the local oscillator clock generation circuit within the chip operating temperature range. As Figure 5 shown, there is still a certain temperature between -40°C and 130°C that causes phase ambiguity in the local oscillator clock generation circuit. Especially when the phase-locked loop operates at high frequencies, this problem is more obvious. This will cause the chip to be unable to work stably. It is difficult to implement the above technology to determine whether the phase staggering amplitude is sufficient and how to select the size of the phase delay.

[0079] Figure 6 The switch selection unit selects the synchronization signal and consists of an RS flip-flop, a D flip-flop, and a switch. Figure 7An example of an RS flip-flop. First, the externally received chip synchronization signal sync_en is sampled once by the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2), and the sampled signals are the first differential signal PLL_outn and the second differential signal PLL_outp of the phase-locked loop respectively. The purpose of using two differential signals for sampling in this step is to avoid the edges of the sampling signals meeting the edge of the sync_en signal at this step, which may cause phase ambiguity. For example, if the edge of sync_en meets the edge of PLL_outp, the distance between sync_en and PLL_outn will be exactly at the most suitable position, and the phase difference between PLL_outp and PLL_outn is 180°. Then, a choice can be made between the first switch sync_en_sel1 and the second switch sync_en_sel2, rather than choosing the third sync_en_sel3 and the fourth sync_en_sel4 that may have phase ambiguity. After the first-step sampling, the first synchronization signal sync_en_int1 and the second synchronization signal sync_en_int2 are respectively sent to the first D flip-flop (D flip-flop 1), the second D flip-flop (D flip-flop 2), or the third D flip-flop (D flip-flop 3), the fourth D flip-flop (D flip-flop 4) for the second-step sampling. The sampling signals are still the two differential signals PLL_outn and PLL_outp of the phase-locked loop. The purpose of this step of sampling is to generate two control signals with a phase difference of 180°. Here, there are two groups of control signals with a phase difference of 180°, namely the first switch sync_en_sel1 and the second switch sync_en_sel2, or the third switch sync_en_sel3 and the fourth switch sync_en_sel4. As before, only one of these two groups may be appropriate. Assume that sync_en_sel1 and sync_en_sel2 are more appropriate. Arbitrarily choose one of them to be the Figure 1 "sync_en" signal in. If this signal causes phase ambiguity with Figure 1 PLL_outp / PLL_outn in (as shown in Figure 3 ), then the switch selection circuit can select the other signal as "sync_en", and then this signal will be in the most suitable position because the difference between sync_en_sel1 and sync_en_sel2 is exactly 180°.

[0080] The signal selection process can traverse the control signals output when the first switch (sync_en_sel1), the second switch (sync_en_sel2), the third switch (sync_en_sel3), and the fourth switch (sync_en_sel4) are separately connected, and select the one without phase ambiguity according to the test results. It can be determined after at most four selections.

[0081] The third RS flip-flop (RS flip-flop 3) and the fourth RS flip-flop (RS flip-flop 4) are used to ensure that the sampling of the first synchronization signal sync_en_int1 and the second synchronization signal sync_en_int2 in the second step does not have timing issues. Since the phase-locked loop operates at a relatively high frequency, the delays of the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2) may exceed half of the period of the signals PLL_outp / PLL_outn. To avoid sampling errors, the RST_n signals of the first RS flip-flop (RS flip-flop 1) and the second RS flip-flop (RS flip-flop 2) input to the second D flip-flop (D flip-flop 2) and the fourth D flip-flop (D flip-flop 4) are blocked for a certain period of time, and then sampled after sync_en_int1 and sync_en_int2 are stable.

[0082] Figure 8 and Figure 9 This is an example of signal selection when the switch selection unit finally selects the control signal sync_en to be transmitted to the clock generation circuit. Figure 8 This shows an example of the first-step sampling. As can be seen from the figure, when sync_en is close to an edge of PLL_outp, if there are differences in device delays at -40°C to 130°C, this will make sync_en_int2 uncertain, and the difference will be greater than half of the phase-locked loop clock period. At this time, the sensitive edges of sync_en and PLL_outn are at the farthest distance, and sync_en_int1 will be very stable at -40°C to 130°C, with only a small deviation, which will not affect the next-step sampling.

[0083] Figure 9 This shows an example of the sampling of the synchronization unit. Taking the sampling of the first synchronization signal sync_en_int1 as an example, the figure also shows the delays of the D flip-flop and the RS flip-flop. As can be seen from the figure, when the first switch sync_en_sel1 signal obtained by sampling sync_en_int1 through PLL_outn may meet the sensitive edges of PLL_outp / PLL_outn after passing through the D flip-flop and the routing delay at -40°C to 130°C, resulting in phase ambiguity (the first switch sync_en_sel1 is located at a sensitive edge of PLL_outp / PLL_outn, see Figure 1 and Figure 3);The second switch sync_en_sel2 is sampled by PLL_outp. Its phase is 180° different from that of the first switch sync_en_sel1 (after passing through the same D flip-flop and routing delay), and it will be in the safest position. Even at -40°C to 130°C, there will be no phase ambiguity problem (the second switch sync_en_sel2 can avoid the sensitive edges of PLL_outp / PLL_outn). Subsequently, the selection switch selects the second switch sync_en_sel2 as Figure 1 the "sync_en" signal in, then the phase ambiguity problem is solved. The function of the delay unit to delay the signal blk_p is as before, ensuring that the sampling of sync_en_int1 by PLL_outp is correct.

[0084] In addition to Figure 6 the scheme shown, the first RS flip-flop and the second RS flip-flop can also use D flip-flops, but their delay is longer. Attention needs to be paid to the subsequent sampling timing issues of sync_en_int1 and sync_en_int2. In addition, when the circuit operates at high frequencies, reasonable layout routing is also required to ensure that the phase difference between sync_en_sel1 and 2 and sync_en_sel3 and 4 is 180°.

[0085] Figure 8 and Figure 9 is just an example, and the actual situation may be different. No matter what situation occurs, when using Figure 6 the scheme shown, the chip only needs to make at most four selections to select the most suitable configuration. The local oscillator clock and the baseband clock can both use this scheme to eliminate the clock phase ambiguity, making the chip suitable for multi-chip synchronization applications.

[0086] In some alternative embodiments, the clock generation circuit includes an N-stage trigger chain; wherein, the first differential signal and the second differential signal are input to the clock generation circuit, and the first synchronization signal and the second synchronization signal are input to the previous-stage trigger of the clock generation circuit.

[0087] In an alternative embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1” and Q2” respectively; the N flip-flop stage chain includes N + 2 flip-flop stages; wherein, the i-th stage flip-flop includes a first flip-flop T1(i) and a second flip-flop T2(i); the (N + 2)-th stage flip-flop includes a third flip-flop T3(N + 2) and a fourth flip-flop T4(N + 2); the input terminal of the first flip-flop T1(i) is connected to the output terminal of the second flip-flop T2(i - 1); the input terminal of the second flip-flop T2(i) is connected to the output terminal of the first flip-flop T1(i - 1); the input terminal of the third flip-flop T3(N + 2) is connected to the output terminal of the fourth flip-flop T4(N + 2); the input terminal of the fourth flip-flop T4(N + 2) is connected to the output terminal of the third flip-flop T3(N + 2); the sampling signal of the first flip-flop T1(i) is the second differential signal; the sampling signal of the second flip-flop T2(i) is the first differential signal; the sampling signal of the third flip-flop T3(N + 2) is the second differential signal; the sampling signal of the fourth flip-flop T4(N + 2) is the first differential signal; the first differential signal and the second differential signal are input into the first flip-flop T1(1) and the second flip-flop T2(1); the first synchronization signal and the second synchronization signal are input into the third flip-flop T3(N + 2) and the fourth flip-flop T4(N + 2).

[0088] In an alternative embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1” and Q2” respectively; the N flip-flop stage chain includes N + 2 flip-flop stages; wherein, the i-th stage flip-flop includes a first flip-flop T1(i) and a second flip-flop T2(i); the (N + 2)-th stage flip-flop includes a third flip-flop T3(N + 2) and a fourth flip-flop T4(N + 2); the input terminal of the first flip-flop T1(i) is connected to the output terminal of the second flip-flop T2(i - 1); the input terminal of the second flip-flop T2(i) is connected to the output terminal of the first flip-flop T1(i - 1); the input terminal of the third flip-flop T3(N + 2) is connected to the output terminal of the fourth flip-flop T4(N + 2); the input terminal of the fourth flip-flop T4(N + 2) is connected to the output terminal of the third flip-flop T3(N + 2); the sampling signal of the first flip-flop T1(i) is the second differential signal; the sampling signal of the second flip-flop T2(i) is the first differential signal; the sampling signal of the third flip-flop T3(N + 2) is the second differential signal; the sampling signal of the fourth flip-flop T4(N + 2) is the first differential signal; the first differential signal and the second differential signal are input into the first flip-flop T1(1) and the second flip-flop T2(1); the first synchronization signal and the second synchronization signal are input into the third flip-flop T3(N + 2) and the fourth flip-flop T4(N + 2).

[0089] In an optional embodiment, the first differential signal and the second differential signal are Q1 and Q2 respectively; the first synchronization signal and the second synchronization signal are Q1" and Q2" respectively; the N flip-flop stage chain includes N + 2 flip-flop stages; wherein, the i-th stage flip-flop includes a first flip-flop T1(i) and a second flip-flop T2(i); the (N + 2)-th stage flip-flop includes a third flip-flop T3(N + 2) and a fourth flip-flop T4(N + 2); the input end of the first flip-flop T1(i) is connected to the output end of the second flip-flop T2(i - 1); the input end of the second flip-flop T2(i) is connected to the output end of the first flip-flop T1(i - 1); the input end of the third flip-flop T3(N + 2) is connected to the output end of the fourth flip-flop T4(N + 2); the input end of the fourth flip-flop T4(N + 2) is connected to the output end of the third flip-flop T3(N + 2); the sampling signal of the first flip-flop T1(i) is the second differential signal; the sampling signal of the second flip-flop T2(i) is the first differential signal; the sampling signal of the third flip-flop T3(N + 2) is the second differential signal; the sampling signal of the fourth flip-flop T4(N + 2) is the first differential signal; the first differential signal and the second differential signal are input to the first flip-flop T1(1) and the second flip-flop T2(1); the first synchronization signal and the second synchronization signal are input to the third flip-flop T3(N + 2) and the fourth flip-flop T4(N + 2).

[0090] In summary, the embodiment of the present application provides a signal sampling processing system and method for multi-chip synchronization: a first differential signal and a second differential signal are generated by a phase-locked loop and input to a clock generation circuit; a sampling unit synchronously samples the received signals of multiple transceiver chips; the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of the other signal is the second differential signal; a delay unit delays the first synchronization signal and the second synchronization signal until the signals are stable, and then a synchronization unit generates two control signals respectively by using the first synchronization signal and the second synchronization signal; the phase difference between the two control signals is 180°; a switch selection unit selects the switch connection between any one of the control signals and the clock generation circuit; if the four-phase local oscillator clock signal output by the clock generation circuit has phase ambiguity, then sequentially select the other control signal until there is no phase ambiguity, and obtain the control signal finally sent to the clock generation circuit. Thus, the phase ambiguity problem can be eliminated by selecting at most four times. The present invention re-synchronizes the synchronization signals input to multiple chips by using a phase-locked loop; the signals enter the clock generation circuit and output four synchronization signals, and signal selection is performed according to the phase difference indicating phase ambiguity to avoid phase ambiguity caused by the signal edge collision with the signal sent by the phase-locked loop; the synchronization signal selected by the phase-locked loop can ensure a relatively large distance from the signal edge of the phase-locked loop itself, so that phase ambiguity does not occur even when the temperature changes. The present invention can achieve multi-chip synchronization, eliminate phase ambiguity, and ensure that the phase of the local oscillator clock or the baseband clock remains unchanged after each synchronization signal arrives at the chip.

[0091] The externally input synchronization signal will actually be sampled by the chip reference clock first, and the chip reference clock is also the reference clock of the phase-locked loop. Therefore, they have a certain timing relationship. However, since the circuit operates at high frequencies, it cannot be guaranteed in the local oscillator clock generation circuit whether the synchronization signal will collide with the sensitive edge of the phase-locked loop, resulting in phase ambiguity. By using the method introduced in the present invention, phase ambiguity can be avoided.

[0092] The above specific implementation manners further elaborate in detail the purpose, technical solution and beneficial effects of the present invention. It should be understood that the above are only the specific implementation manners of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A signal sampling and processing system for multi-chip synchronization, applied to multiple transceiver chips, the processing system comprising: A phase-locked loop, used for generating a first differential signal and a second differential signal; A clock generating circuit, used for inputting the first differential signal and the second differential signal, wherein the processing system further comprises: A sampling unit, synchronously sampling the synchronization control signals of the plurality of transceiver chips to obtain a first synchronization signal and a second synchronization signal, wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal; a delay unit, used for delaying the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal, and the second differential signal is synchronized with the second synchronization signal; a synchronization unit, generating two control signals based on the first synchronization signal and the second synchronization signal respectively, wherein the two control signals have the same duty cycle and frequency and a phase difference of 180°; The switch selection unit selects any one of the control signals to be sent to the clock generating circuit. If the four-phase local oscillator clock signal output by the clock generating circuit is phase-ambiguous, another control signal is selected in turn to be sent to the clock generating circuit until no phase ambiguity occurs.

2. A signal sampling and processing system for multi-chip synchronization according to claim 1, characterized in that: The sampling unit includes a first RS trigger and a second RS trigger; the first RS trigger and the second RS trigger respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the first RS trigger is the first differential signal, and the sampling signal of the second RS trigger is the second differential signal.

3. The signal sampling and processing system for multi-chip synchronization according to claim 2, characterized in that: The sampling unit includes a fifth D flip-flop and a sixth D flip-flop; the fifth D flip-flop and the sixth D flip-flop respectively receive the synchronization control signals of multiple transceiver chips; the sampling signal of the fifth D flip-flop is the first differential signal, and the sampling signal of the sixth D flip-flop is the second differential signal.

4. A signal sampling and processing system for multi-chip synchronization according to claim 2 or 3, characterized in that: The delay unit includes a third RS trigger and a fourth RS trigger; the input end of the third RS trigger is connected to the output end of the first RS trigger; the input end of the fourth RS trigger is connected to the output end of the second RS trigger; the sampling signal of the third RS trigger is the second differential signal; The sampling signal of the fourth RS trigger is the first differential signal.

5. The signal sampling and processing system for multi-chip synchronization according to claim 4, characterized in that: The synchronization unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the input end of the second D flip-flop is connected to the output end of the first RS flip-flop; the first D flip-flop, the second D flip-flop and the third RS flip-flop are connected in parallel; the sampling signal of the first D flip-flop is the first differential signal; The sampling signal of the second D flip-flop is the second differential signal; the input end of the fourth D flip-flop is connected to the output end of the second RS flip-flop; the third D flip-flop, the fourth D flip-flop and the fourth RS flip-flop are connected in parallel; the sampling signal of the fourth D flip-flop is the first differential signal; the sampling signal of the third D flip-flop is the second differential signal.

6. The signal sampling and processing system for multi-chip synchronization according to claim 5, characterized in that: The switch selection unit includes a first switch, a second switch, a third switch and a fourth switch; the output end of the first D flip-flop is connected to the input end of the clock generating circuit through the first switch; the output end of the second D flip-flop is connected to the input end of the clock generating circuit through the second switch; the output end of the third D flip-flop is connected to the input end of the clock generating circuit through the third switch; and the output end of the fourth D flip-flop is connected to the input end of the clock generating circuit through the fourth switch.

7. The signal sampling and processing system for multi-chip synchronization according to claim 1, characterized in that: The phase-locked loop is a local oscillator phase-locked loop; The clock generating circuit is a local oscillator clock or a baseband clock generating circuit.

8. A signal sampling and processing method for multi-chip synchronization, applied to multiple transceiver chips; The processing method comprises: A phase-locked loop is used to generate a first differential signal and a second differential signal; a clock generating circuit is used to input the first differential signal and the second differential signal; wherein the processing method further comprises the following steps: Synchronously sampling received signals of a plurality of transceiver chips to obtain a first synchronization signal and a second synchronization signal; wherein the sampling signal of the first synchronization signal is the first differential signal, and the sampling signal of another signal is the second differential signal; Delaying the first synchronization signal and the second synchronization signal so that the first differential signal is synchronized with the first synchronization signal and the second differential signal is synchronized with the second synchronization signal; Generate two control signals based on the first synchronization signal and the second synchronization signal respectively, the two control signals have the same duty cycle and frequency, and a phase difference of 180°; Any one of the control signals is selected and sent to the clock generating circuit. If the four-phase local oscillator clock signal output by the clock generating circuit is phase-ambiguous, another control signal is selected in turn and sent to the clock generating circuit until no phase ambiguity occurs.

9. The signal sampling and processing method for multi-chip synchronization according to claim 8, characterized in that: The synchronous sampling of the synchronous control signals of the plurality of transceiver chips to obtain the first synchronous signal and the second synchronous signal comprises: Using an RS trigger or a D trigger to sample the first synchronization signal and the second synchronization signal respectively; The delaying the first synchronization signal and the second synchronization signal comprises: Using an RS trigger to block the first synchronization signal and the second synchronization signal; The generating two control signals based on the first synchronization signal and the second synchronization signal respectively comprises: Two D flip-flops are respectively used to generate two control signals, the first synchronization signal and the synchronization signal; The selecting any one of the control signals to be sent to the clock generating circuit comprises: Different switches are used to control whether each of the control signals is sent to the clock generating circuit.

10. The signal sampling and processing method for multi-chip synchronization according to claim 8, characterized in that: The selecting any one of the control signals to be sent to the clock generating circuit comprises: Any one of the two control signals generated by the first synchronization signal and the two control signals generated based on the second synchronization signal is selected and sent to the clock generating circuit.

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