Frequency offset estimation method and device, storage medium, communication equipment and chip

Abstract

The invention discloses a frequency offset estimation method and device, a storage medium, communication equipment and a chip, and relates to the technical field of communication, and the method comprises the steps: carrying out the differential frequency offset estimation based on a main synchronization signal and an auxiliary synchronization signal, and obtaining the main and auxiliary differential frequency offset; correcting the main and auxiliary difference frequency offset by using a half-symbol frequency offset corresponding to the main synchronization signal to obtain a target correction value; and finally, determining a target frequency offset estimation value according to the target correction value and the correction frequency offset corresponding to the main synchronization signal. According to the invention, the broadcast message is read by a single branch based on the frequency offset correction value and the target frequency offset estimation value determined by the correction frequency offset, and the frequency offset does not need to be determined through multi-branch attempts, so that the signal processing complexity of the terminal equipment is reduced, and the influence on the performance of the terminal equipment is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a frequency offset estimation method, apparatus, storage medium, communication device, and chip. Background Art

[0002] Terminal devices generally use a digitally compensated crystal oscillator (DCXO) with a relatively low cost to provide a clock source. To alleviate the problem of a large frequency error of the DCXO, additional frequency offset estimation is usually introduced in baseband processing. Summary of the Invention

[0003] The present disclosure provides a frequency offset estimation method, apparatus, storage medium, communication device, and chip, and the main purpose is to improve the technical problem that the use of the branch trial method requires multiple attempts by the terminal device, resulting in a relatively high signal processing complexity of the terminal device and affecting the performance of the terminal device.

[0004] According to a first aspect of an embodiment of the present disclosure, a frequency offset estimation method is provided, including:

[0005] Performing differential frequency offset estimation based on a primary synchronization signal and a secondary synchronization signal to obtain a primary-secondary differential frequency offset;

[0006] Using a half-symbol frequency offset corresponding to the primary synchronization signal to correct the primary-secondary differential frequency offset to obtain a target correction value;

[0007] Determining a target frequency offset estimation value according to the target correction value and a frequency correction frequency offset corresponding to the primary synchronization signal.

[0008] In some embodiments of the present disclosure, the using the half-symbol frequency offset corresponding to the primary synchronization signal to correct the primary-secondary differential frequency offset to obtain a target correction value includes:

[0009] Obtaining a frequency offset correction value according to a frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset;

[0010] Using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to perform periodic correction on the primary-secondary differential frequency offset to determine a target correction value.

[0011] In some embodiments of the present disclosure, the using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to perform periodic correction on the primary-secondary differential frequency offset to determine a target correction value includes:

[0012] Obtaining a frequency deviation value between the frequency offset correction value and the half-symbol frequency offset respectively;

[0013] Determine the frequency offset correction value corresponding to the minimum frequency deviation value as the target correction value after cycle correction.

[0014] In some embodiments of the present disclosure, before obtaining the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, the method further includes:

[0015] Determine the frequency offset estimation range based on the maximum frequency offset estimation values corresponding to the primary synchronization signal and the secondary synchronization signal.

[0016] In some embodiments of the present disclosure, obtaining the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset includes:

[0017] Determine the primary-secondary differential frequency offset as the frequency offset correction value; and / or,

[0018] Determine the frequency offset obtained by adding the primary-secondary differential frequency offset to the maximum frequency offset estimation value as the frequency offset correction value; and / or;

[0019] Determine the frequency offset obtained by subtracting the primary-secondary differential frequency offset from the maximum frequency offset estimation value as the frequency offset correction value.

[0020] In some embodiments of the present disclosure, the method further includes:

[0021] Perform primary synchronization sequence detection on the received primary synchronization signal to obtain the frequency offset for frequency correction;

[0022] Use the frequency offset for frequency correction to perform pre-frequency correction on the original primary synchronization signal and the original secondary synchronization signal respectively, to obtain the frequency-corrected primary synchronization signal and the secondary synchronization signal.

[0023] In some embodiments of the present disclosure, performing primary synchronization sequence detection on the primary synchronization signal includes:

[0024] Obtain the primary synchronization detection branch corresponding to the current residual frequency offset, and use the primary synchronization detection branch to perform primary synchronization sequence detection on the primary synchronization signal.

[0025] In some embodiments of the present disclosure, the method further includes:

[0026] Correct the current residual frequency offset based on the target frequency offset estimation value to obtain the corrected frequency;

[0027] Receive the broadcast message sent by the network device according to the frequency.

[0028] In some embodiments of the present disclosure, determining the target frequency offset estimate according to the target correction value and the frequency correction frequency offset corresponding to the primary synchronization signal includes:

[0029] Adding the target correction value to the frequency correction frequency offset corresponding to the primary synchronization signal to obtain the target frequency offset estimate.

[0030] According to a second aspect of the embodiments of the present disclosure, there is provided a frequency offset estimation device, including:

[0031] An acquisition module, configured to acquire the primary synchronization signal after frequency correction of the primary synchronization signal and the secondary synchronization signal after frequency correction of the secondary synchronization signal;

[0032] An acquisition module, configured to perform differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset;

[0033] A correction module, configured to correct the primary-secondary differential frequency offset by using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value;

[0034] A determination module, configured to determine a target frequency offset estimate according to the target correction value and the frequency correction frequency offset corresponding to the primary synchronization signal.

[0035] According to a third aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the first aspect is implemented.

[0036] According to a fourth aspect of the embodiments of the present disclosure, there is provided a communication device, including: a transceiver; a memory; a processor, respectively connected to the transceiver and the memory, configured to control wireless signal transceiver of the transceiver by executing computer-executable instructions on the memory, and capable of implementing the method described in the first aspect.

[0037] According to a fifth aspect of the embodiments of the present disclosure, there is provided a computer program product, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the first aspect is implemented.

[0038] According to a sixth aspect of the embodiments of the present disclosure, there is provided a chip, including at least one processor and a communication interface; the communication interface is used to receive a signal input to the chip or a signal output from the chip, and the processor communicates with the communication interface and implements the method described in the first aspect through logic circuits or by executing code instructions.

[0039] With the above technical solutions, the present disclosure provides a frequency offset estimation method, apparatus, storage medium, communication device, and chip. Specifically, first, differential frequency offset estimation is performed based on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset; then, the half-symbol frequency offset corresponding to the primary synchronization signal is used to correct the primary-secondary differential frequency offset to obtain a target correction value; finally, based on the target correction value and the frequency offset correction frequency corresponding to the primary synchronization signal, a target frequency offset estimation value is determined. In this application, the primary-secondary differential frequency offset after differential frequency offset estimation of the primary synchronization signal and the secondary synchronization signal is obtained, and then the half-symbol frequency offset corresponding to the primary synchronization signal is used to correct the primary-secondary differential frequency offset to obtain a target correction value, so that the primary-secondary differential frequency offset corrected by the target correction value is close to the half-symbol frequency offset with a larger frequency offset estimation range, reducing the frequency offset estimation error. Finally, based on the frequency offset correction value and the frequency offset correction frequency, a target frequency offset estimation value is determined to perform single-branch reading of broadcast messages, without the need to determine the frequency offset through multi-branch attempts, reducing the complexity of signal processing of the terminal device, and thus reducing the impact on the performance of the terminal device.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0042] Figure 1 FIG. shows a schematic flowchart of a frequency offset estimation method provided by an embodiment of the present application;

[0043] Figure 2 FIG. shows a schematic flowchart of a frequency offset estimation method provided by an embodiment of the present application;

[0044] Figure 3 FIG. shows a schematic structural diagram of a frequency offset estimation apparatus provided by an embodiment of the present application;

[0045] Figure 4 FIG. shows a schematic structural diagram of a communication device provided by an embodiment of the present disclosure;

[0046] Figure 5 FIG. shows a schematic structural diagram of a chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] Some embodiments of the present disclosure will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will become apparent after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the orders set forth herein, but can be changed as will be apparent after understanding the present disclosure, except for operations that must be performed in a specific order. Additionally, descriptions of features known in the art may be omitted for the sake of clarity and conciseness. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other.

[0048] Some embodiments of the present disclosure will be introduced below. It should be noted that the implementation manners described in some embodiments of the present disclosure below do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0049] In some embodiments, the branch trial method is used for frequency offset estimation, and the optimal frequency offset estimation value is found by trying multiple possible frequency offset values. However, using the branch trial method requires the terminal device to try multiple times, resulting in a relatively high signal processing complexity of the terminal device and affecting the performance of the terminal device.

[0050] To improve the technical problem that using the branch trial method requires the terminal device to try multiple times, resulting in a relatively high signal processing complexity of the terminal device and affecting the performance of the terminal device. Embodiments of the present disclosure provide a frequency offset estimation method, as Figure 1 shown, Figure 1 is a flowchart of a frequency offset estimation method shown according to some embodiments of the present disclosure, including the following steps.

[0051] Step 101, perform differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset.

[0052] For the execution subject of this embodiment, it may be a communication device or a communication equipment, such as an electronic device or a chip, etc., and can be configured on the terminal side.

[0053] In some examples, a terminal may be referred to as a terminal device, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. The terminal may also be an automobile with communication capabilities, a smart vehicle, a mobile phone, a wearable device, a tablet computer (Pad), a computer with wireless transceiver capabilities, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal device in industrial control, a wireless terminal device in self-driving, a wireless terminal device in remote medical surgery, a wireless terminal device in a smart grid, a wireless terminal device in transportation safety, a wireless terminal device in a smart city, a wireless terminal device in a smart home, and so on. This embodiment does not limit the specific technologies and specific device forms adopted by the terminal.

[0054] In some examples, the network device may be a device such as a base station or a satellite, which is not specifically limited in this embodiment. The network device may be an entity on the network side for transmitting or receiving signals. For example, the network device may be a communication satellite, an evolved NodeB (eNB), a transmission reception point (TRP), a next generation NodeB (gNB) in an NR system, a base station in other future mobile communication systems, or an access node in a wireless fidelity (WiFi) system. The embodiments of the present disclosure do not limit the specific technologies and specific device forms adopted by the network device. The network device provided in this embodiment may be composed of a central unit (CU) and a distributed unit (DU). Among them, the CU may also be referred to as a control unit. Adopting the CU-DU structure can split the protocol layer of the network device, such as a base station. The functions of some protocol layers are centrally controlled by the CU, and the functions of the remaining part or all protocol layers are distributed in the DU, and the DU is centrally controlled by the CU.

[0055] Among them, the signals obtained after frequency correction processing of the Primary Synchronization Signal (PSS); the signals obtained after frequency correction processing of the Secondary Synchronization Signal (SSS).

[0056] In some examples, during the process of cell search by the terminal, it is usually necessary to obtain the primary synchronization signal and the secondary synchronization signal, and perform frequency offset estimation and correction on the primary synchronization signal and the secondary synchronization signal, so that the terminal device can accurately synchronize with the carrier frequency of the communication device. Exemplarily, first, the current residual frequency offset of the terminal can be roughly estimated to obtain the frequency correction offset, and then the received primary synchronization signal and secondary synchronization signal are respectively frequency-corrected using the frequency correction offset to obtain the frequency-corrected primary synchronization signal and secondary synchronization signal, achieving frequency offset correction in a large range.

[0057] In some examples, the communication system corresponding to the terminal can be determined first, such as the 5G NR system, the LTE system, etc., then the phase difference calculation method corresponding to the differential frequency offset estimation is determined according to the communication system, and then the primary and secondary differential frequency offsets are obtained based on the phase difference and the absolute time difference between the primary synchronization signal and the secondary synchronization signal. Among them, the primary and secondary differential frequency offsets can be the frequency offset estimation values calculated after differential frequency offset estimation of the primary synchronization sequence corresponding to the primary synchronization signal and the secondary synchronization sequence corresponding to the secondary synchronization signal, which helps to obtain a more accurate frequency offset, improve the accuracy of frequency offset estimation, and reduce the error of frequency offset estimation.

[0058] Step 102: Use the half-symbol frequency offset corresponding to the primary synchronization signal to correct the primary and secondary differential frequency offsets to obtain the target correction value.

[0059] Among them, the half-symbol frequency offset can be the frequency offset estimation value of half a symbol (such as an OFDM symbol) period of the primary synchronization signal, which can be used to determine a large estimation range of the frequency offset.

[0060] Exemplarily, the phase difference of the first and second half symbols of the primary synchronization sequence corresponding to the primary synchronization signal can be calculated, the half-symbol frequency offset estimation value corresponding to the primary synchronization signal is obtained based on the half-symbol phase difference, the primary and secondary differential frequency offsets are compared with the half-symbol frequency offset, and the primary and secondary differential frequency offsets are corrected according to the comparison result, so that the corrected primary and secondary differential frequency offsets are close to the half-symbol frequency offset. Within the half-symbol frequency offset estimation range, the frequency offset correction value closest to the half-symbol frequency offset is used as the target correction value, thereby realizing a finer-grained frequency offset estimation and obtaining a more accurate frequency offset estimation value.

[0061] Step 103: Determine the target frequency offset estimation value according to the target correction value and the frequency correction offset corresponding to the primary synchronization signal.

[0062] In the embodiments of the present disclosure, frequency offset correction can be used to perform pre-frequency offset correction on the primary synchronization signal and the secondary synchronization signal respectively. Using the frequency offset estimation value roughly estimated with a relatively large frequency offset interval, the target correction value can be the half-symbol frequency offset to correct the primary-secondary differential frequency offset. Further, the frequency offset correction value within a relatively small frequency offset range is estimated. Finally, combining the frequency offset correction value and the frequency offset correction frequency, a target frequency offset estimation value with a large frequency offset estimation range and small error is obtained, which can meet the frequency offset access conditions of the subsequent modules (for example, modules such as broadcasting and system message reading). The subsequent modules do not need to perform multiple frequency offset attempt branches, and only need to retain the single frequency offset attempt branch corresponding to the target frequency offset estimation value to read the broadcast message, reducing the complexity of signal processing of the terminal device.

[0063] Compared with the current existing technologies, in this embodiment, the primary-secondary differential frequency offset between the primary synchronization signal and the secondary synchronization signal can be obtained first. The primary-secondary differential frequency offset is corrected using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain the target correction value, so that the primary-secondary differential frequency offset corrected using the target correction value is close to the half-symbol frequency offset with a relatively large frequency offset estimation range, reducing the frequency offset estimation error. Finally, based on the target frequency offset estimation value determined by the frequency offset correction value and the frequency offset correction frequency, the broadcast message is read through a single branch, without determining the frequency offset through multiple branch attempts, reducing the complexity of signal processing of the terminal device, and further reducing the impact on the performance of the terminal device.

[0064] Further, to illustrate the specific implementation process of the method in this embodiment, this embodiment provides a specific method as shown in Figure 2 which includes:

[0065] Step 201: Perform primary synchronization sequence detection on the received original primary synchronization signal to obtain the frequency offset correction frequency.

[0066] In a specific application scenario, the original primary synchronization signal can be the unprocessed primary synchronization signal received by the terminal. First, through the primary synchronization sequence detection of the original primary synchronization signal, frequency offset estimation with a relatively large frequency offset interval is performed on the original primary synchronization signal for rough estimation to reduce the frequency offset attempt branches of the primary synchronization detection. Then, the pre-correction value obtained through the primary synchronization sequence detection is used as the frequency offset correction frequency to perform rough and large-range frequency offset correction on the original primary synchronization signal and the original secondary synchronization signal, removing the large-range frequency offset for subsequent detailed and small-range frequency offset estimation.

[0067] Optionally, performing primary synchronization sequence detection on the original primary synchronization signal may specifically include: obtaining the primary synchronization detection branch corresponding to the current residual frequency offset, and using the primary synchronization detection branch to perform primary synchronization sequence detection on the original primary synchronization signal.

[0068] In some embodiments, the terminal may attempt multiple primary synchronization detection branches with a relatively large frequency offset interval according to the current residual frequency offset. The primary synchronization sequence corresponding to the received original primary synchronization signal can be expressed as y(i), where i = 0, 1, 2, …, len - 1; the primary synchronization local sequence can be expressed as p(k, i), where i = 0, 1, …, M - 1 and k = 0, 1, 2. Here, k represents the k-th primary synchronization sequence; each primary synchronization detection branch (frequency offset attempt branch) can be expressed as fn(n), where n = 0, 1, …, N - 1. Exemplarily, the frequency offset interval between the frequency offset attempt branches can be set to 10k or 20k.

[0069] Exemplarily, the specific implementation process of the primary synchronization sequence detection is as follows:

[0070] (1) Use each primary synchronization detection branch to perform pre-frequency correction processing on the primary synchronization sequence of the original primary synchronization signal respectively, and obtain the primary synchronization data pn(k, i) = p(k, i) * exp(j * 2 * pi * fn(n) * i) after pre-frequency correction processing, where pi = 3.14; then, perform a correlation operation on the received primary synchronization sequence and the primary synchronization data pn(i) after pre-frequency correction processing to obtain the primary synchronization correlation result yr(k, i). The operation formula for the primary synchronization correlation result is as follows:

[0071] i = 0, 1, 2, …, len - 1; k = 0, 1, 2

[0072] (2) Calculate the modulus square of the primary synchronization correlation result yr(k, i) to obtain the primary synchronization correlation power corresponding to the received data. The calculation formula for the primary synchronization correlation power yp(k, i) is as follows:

[0073] yp(k, i) = (yr(k, i)) 2 , i = 0, 1, 2, …, len - 1; k = 0, 1, 2

[0074] (3) Perform peak detection on the primary synchronization correlation power to obtain the primary synchronization detection result. The specific detection method can be to select the preset number (such as nmax_p) of values with the highest ranking in the primary synchronization correlation power and their corresponding positions, primary synchronization codes, and pre-correction values as the detection results of the primary synchronization sequence.

[0075] Optionally, the secondary synchronization sequence detection can be performed according to the primary synchronization sequence detection result. The secondary synchronization sequence is obtained through the position output by the primary synchronization detection result. The secondary synchronization sequence can be expressed as ys(i), where i = 0, 1, 2, …, M - 1; the secondary synchronization local sequence can be expressed as s(k, i), where k = 0, N - 1; i = 0, 1, …, M - 1, and k represents the k-th secondary synchronization sequence.

[0076] Exemplarily, the specific implementation process of the secondary synchronization sequence detection is as follows:

[0077] (1) Perform pre - frequency - correction processing on the secondary synchronization sequence ys(i) to obtain the pre - frequency - corrected secondary synchronization data ysn(i)=ys(i)*exp(-j*2*pi*fn*i), where pi = 3.14 and fn can be the main synchronization frequency offset trial value in the main synchronization detection result; then perform a correlation operation on the received data secondary synchronization sequence ys(i) and s(k, i) to obtain the secondary synchronization correlation result ysr(k), and the correlation operation is as follows:

[0078]

[0079] (2) Calculate the modulus square of ysr(k) to obtain the received data secondary synchronization correlation power, and the calculation formula for the secondary synchronization correlation power ysp(k) is as follows:

[0080] ysp(k)=(ysr(k)) 2 , k = 0, N - 1

[0081] (3) Perform peak detection on the secondary synchronization correlation power to obtain the secondary synchronization detection result. The specific detection method can be to select the preset number (such as nmax_s) of values with the highest secondary synchronization correlation power and their secondary synchronization codes and pre - correction values as the detection result of the secondary synchronization sequence.

[0082] Step 202: Use the frequency - correction frequency offset to perform pre - frequency - correction on the original primary synchronization signal and the original secondary synchronization signal respectively to obtain the frequency - corrected primary synchronization signal and secondary synchronization signal.

[0083] Among them, the original secondary synchronization signal can be the unprocessed secondary synchronization signal received by the terminal.

[0084] Exemplarily, obtain the received data yp(i) of the primary synchronization symbol according to the primary / secondary synchronization detection result, i = 0, 1, 2, …, M - 1, the primary synchronization local sequence can be expressed as p(i), i = 0, 1, …, M - 1, and the received data ys(i) of the secondary synchronization symbol, i = 0, 1, 2, …, M - 1, the secondary synchronization local sequence can be expressed as s(i), i = 0, 1, …, M - 1; and the main synchronization detection frequency offset trial value fn of this cell is used as the frequency - correction frequency offset.

[0085] Then, the frequency - correction frequency offset can be used to perform pre - correction on the primary synchronization sequence corresponding to the original primary synchronization signal and the secondary synchronization sequence corresponding to the original secondary synchronization signal respectively. The primary synchronization signal can be expressed as ypn(i)=yp(i)*exp(-j*2*pi*fn*i), and the secondary synchronization signal can be expressed as ysn(i)=ys(i)*exp(-j*2*pi*fn*i), i = 0, 1, …, M - 1, where pi = 3.14.

[0086] In this way, the original primary synchronization signal and the original secondary synchronization signal are pre-corrected for frequency offset using frequency offset correction, and frequency offset correction within a relatively large estimation range is performed, facilitating accurate estimation of the frequency offset.

[0087] Step 203: Perform differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset.

[0088] Exemplarily, the specific steps for performing differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal are as follows:

[0089] (1) Multiply the secondary synchronization sequence of the secondary synchronization signal by the conjugate of the secondary synchronization local sequence. The resulting secondary synchronization conjugate result can be expressed as:

[0090] ysn_ls(i) = ysn(i) * conj(s(i)), where i = 0, 1, …, M - 1

[0091] (2) Calculate the correlation values between the primary synchronization sequence of the primary synchronization signal and the secondary synchronization sequence of the secondary synchronization signal, which are respectively expressed as:

[0092]

[0093] (3) Calculate the phase difference phase1 between the front and back of the frequency-offset-corrected synchronization sequence:

[0094] When the terminal is an LTE system: phase1 = ysn_cor * conj(ypn_cor)

[0095] When the terminal is an NR system: phase1 = ypn_cor * conj(ysn_cor)

[0096] (4) Calculate the primary-secondary differential frequency offset (the frequency offset estimation value of the primary-secondary synchronization sequence) f1:

[0097] f1 = angle(phase1) / deltaT1

[0098] In the formula, angle represents calculating the radian value of phase1, and deltaT1 represents the absolute time difference between the primary-secondary synchronization sequences.

[0099] Step 204: Obtain the frequency offset correction value based on the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset.

[0100] Optionally, before step 204, the method of this embodiment may further specifically include: determining the frequency offset estimation range based on the maximum frequency offset estimation values corresponding to the primary synchronization signal and the secondary synchronization signal.

[0101] In the embodiments of the present disclosure, first, according to the communication system and communication protocol of the terminal, the absolute value f1_max of the maximum frequency offset value that can be estimated by the primary and secondary synchronization sequences corresponding to the primary synchronization signal and the secondary synchronization signal is obtained as the maximum frequency offset estimation value, providing a frequency offset estimation range. For example, if the terminal is LTE TDD, then based on the absolute time difference of the primary and secondary synchronization sequences, f1_max = 2336 hz can be calculated; correspondingly, if the terminal system is LTE FDD, f1_max = 7007 hz; when the NR subcarrier spacing is 15 khz, f1_max = 3504 hz; when the NR subcarrier spacing is 30 khz, f1_max = 7007 hz.

[0102] Optionally, according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, a frequency offset correction value is obtained, which may specifically include: determining the primary-secondary differential frequency offset as the frequency offset correction value; and / or, determining the frequency offset after adding the primary-secondary differential frequency offset to the maximum frequency offset estimation value as the frequency offset correction value; and / or, determining the frequency offset after subtracting the primary-secondary differential frequency offset from the maximum frequency offset estimation value as the frequency offset correction value.

[0103] Exemplarily, the frequency offset estimation range f_period can be calculated according to the following formula:

[0104] f_period = 2 * f1_max

[0105] Exemplarily, based on the maximum frequency offset estimation value and the primary-secondary differential frequency offset, the following 3 frequency offset correction values can be obtained, namely f1_0, f1_1, f1_2:

[0106] f1_0 = f1

[0107] f1_1 = f1 + f_period

[0108] f1_2 = f1 - f_period

[0109] In this way, according to the maximum frequency offset estimation value, frequency offset correction values corresponding to different periods are obtained, and the period adjustment of the primary-secondary differential frequency offset is carried out, which helps to obtain a more accurate period of the primary-secondary differential frequency offset and improve the accuracy of frequency offset estimation.

[0110] Step 205: Use the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to perform period correction on the primary-secondary differential frequency offset and determine the target correction value.

[0111] Exemplarily, the half-symbol differential frequency offset estimation of the primary synchronization sequence corresponding to the primary synchronization signal may include the following steps:

[0112] (1) Calculate the conjugate multiplication of the primary synchronization sequence of the primary synchronization signal and the primary synchronization local sequence. The obtained primary synchronization conjugate result can be expressed as:

[0113] ypn_ls(i) = ypn(i) * conj(p(i)), i = 0, 1, …, M - 1

[0114] (2) Calculate the correlation values of the first and second half symbols of the primary synchronization sequence corresponding to the primary synchronization signal. The formulas for calculating the correlation value ypn_cor0 of the first half symbol of the primary synchronization sequence and the correlation value ypn_cor1 of the second half symbol of the primary synchronization sequence are as follows:

[0115]

[0116] (3) Calculate the phase difference phase0 between the first and second half symbols of the primary synchronization sequence corresponding to the primary synchronization signal:

[0117] phase0 = ypn_cor1 * conj(ypn_cor0)

[0118] (4) Calculate the half-symbol frequency offset (half-symbol frequency offset estimation value) f0 of the primary synchronization sequence corresponding to the primary synchronization signal:

[0119] f0 = angle(phase0) / deltaT0

[0120] In the formula, angle represents the radian value of calculating phase0, and deltaT0 represents the absolute time difference of half a symbol of the primary synchronization sequence.

[0121] In this way, the half-symbol frequency offset corresponding to a larger estimation range is obtained, so as to facilitate the periodic correction of the frequency offset.

[0122] Optionally, step 205 may specifically include: obtaining the frequency deviation values between the frequency offset correction values and the half-symbol frequency offset respectively; determining the frequency offset correction value corresponding to the minimum frequency deviation value as the target correction value after periodic correction.

[0123] In some embodiments, multiple (such as 3) obtained frequency offset correction values may be respectively compared with the estimated value of the half-symbol frequency offset of the primary synchronization, and the frequency offset correction value closest to the estimated value of the half-symbol frequency offset may be selected and output as the final target correction value (joint frequency offset estimation result) output. Exemplarily, the differences between each frequency offset correction value and the half-symbol frequency offset may be expressed by the following formula:

[0124] deltaf1_0 = |f1_0 - f0|

[0125] deltaf1_1 = |f1_1 - f0|

[0126] deltaf1_2 = |f1_2 - f0|

[0127] Wherein, deltaf1_0, deltaf1_1, and deltaf1_2 are respectively the differences between the frequency offset correction values f1_0, f1_1, f1_2 and the half-symbol frequency offset f0. The frequency offset correction value f1_x corresponding to the minimum frequency deviation value can be selected from deltaf1_0, deltaf1_1, and deltaf1_2 for output, and the combined frequency offset estimation result f_union = f1_x is obtained, where x = 0, 1, 2. For example, if it is determined through comparison that deltaf1_0 is the smallest, then the combined final combined frequency offset estimation result f_union can be determined as f1_0; if deltaf1_1 is the smallest, then the combined final combined frequency offset estimation result f_union can be determined as f1_1; if deltaf1_2 is the smallest, then the combined final combined frequency offset estimation result f_union can be determined as f1_2.

[0128] In this way, the main synchronization sequence half-symbol differential frequency offset estimation is used to determine the approximate range of the frequency offset, and then the main and secondary synchronization sequence differential frequency offset estimation is used to ensure the accuracy of the frequency offset, making the frequency offset estimation result more accurate, with smaller errors, and better meeting the frequency offset access conditions of the subsequent modules.

[0129] Step 206: Determine the target frequency offset estimation value according to the target correction value and the frequency offset correction corresponding to the primary synchronization signal.

[0130] Optionally, step 206 may specifically include: adding the target correction value to the frequency offset correction corresponding to the primary synchronization signal to obtain the target frequency offset estimation value.

[0131] In some embodiments, the target frequency offset estimation value may be obtained according to the main and secondary synchronization sequence detection results and the combined frequency offset estimation result. The calculation formula of the target frequency offset estimation value is as follows:

[0132] fn_mib = fn + f_union

[0133] Wherein, fn is the frequency offset correction, which can be the frequency offset trial value for the primary synchronization detection of this cell, and f_union can be the combined frequency offset estimation result estimated by the combined frequency offset estimation unit.

[0134] As a possible implementation, primary synchronization detection can be first adopted to perform multi-branch attempts with a large frequency offset interval. Then, secondary synchronization signal detection is carried out based on the primary synchronization detection result. Next, through the joint frequency offset estimation unit, according to the primary and secondary synchronization detection results, half-symbol differential frequency offset estimation of the primary synchronization and differential frequency offset estimation of the primary and secondary synchronization sequences are performed to obtain the joint frequency offset estimation result (joint frequency offset estimation value). Finally, the subsequent module can read the broadcast message according to the target frequency offset estimation value corresponding to the joint frequency offset estimation value without performing multi-branch attempts. In this way, the frequency offset attempt branches of the primary synchronization detection and the broadcast message reading are reduced, the overall complexity of the terminal is lowered, and at the same time, the problem that the accuracy of the differential frequency offset estimation for the first half and the second half of the primary synchronization sequence is poor and cannot meet the frequency offset access conditions of the subsequent module is solved.

[0135] Optionally, the method of this embodiment may further include: correcting the current residual frequency offset based on the target frequency offset estimation value to obtain the corrected frequency; receiving the broadcast message sent by the communication device according to the frequency.

[0136] In some embodiments, the received data is subjected to frequency offset soft correction or the crystal oscillator is adjusted by using the joint frequency offset estimation result fn_mib, and then the data is received again according to the corrected frequency, and the broadcast message sent by the base station is read. Since the joint frequency offset estimation has a large frequency offset estimation range and a small frequency offset estimation error, the subsequent module does not need to perform multi-frequency offset attempt branches and only a single frequency offset attempt branch needs to be retained, reducing the signal processing complexity of the subsequent module.

[0137] As a possible implementation, primary synchronization detection can be first adopted to perform multi-branch attempts with a large frequency offset interval, then half-symbol differential frequency offset estimation of the primary synchronization is performed, and then secondary synchronization detection is carried out. Finally, the subsequent module uses a small frequency offset interval to perform multi-branch attempts to determine the frequency offset. In this way, the problem that the accuracy of the differential frequency offset estimation for the first half and the second half of the primary synchronization sequence is poor and cannot meet the frequency offset access conditions of the subsequent module is solved.

[0138] As another possible implementation, primary / secondary synchronization detection can be first adopted to perform branch attempts with a small frequency offset interval. When detecting the primary and secondary synchronization sequences, multiple possible frequency offset value branches are tried to find the most likely frequency offset value. Then, differential frequency offset estimation of the primary and secondary synchronization sequences is performed, and more accurate frequency offset is obtained by using the primary synchronization sequence and the secondary synchronization sequence for differential frequency offset estimation to meet the frequency offset access conditions of the subsequent module. Finally, the subsequent module can perform single-branch attempts, reducing the signal processing complexity of the subsequent module.

[0139] Compared with the current existing technologies, in this embodiment, first, frequency offset correction is used to pre-correct the primary synchronization signal and the secondary synchronization signal respectively, and frequency offset correction with a relatively large estimation range is performed. Then, based on the frequency offset estimation range, the frequency offset correction values corresponding to different periods are obtained, and the semi-symbol frequency offset is used to adjust the periods of the primary and secondary differential frequency offsets to determine the target correction value. Finally, based on the target correction value and the target frequency offset estimation value determined by the frequency offset correction, correction is performed, and the corrected frequency is directly used for reading broadcast messages, correcting the periods of the primary and secondary differential frequency offsets, improving the accuracy of frequency offset estimation, and at the same time reducing the frequency offset branch attempts during the message reading process and reducing the complexity of signal processing of the terminal device.

[0140] Figure 3 is a block diagram of a frequency offset estimation device shown according to some embodiments of the present disclosure. Referring to Figure 3 this, the device includes: an acquisition module 31, a correction module 32, and a determination module 33.

[0141] The acquisition module 31 is configured to perform differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal to obtain the primary and secondary differential frequency offsets;

[0142] The correction module 32 is configured to correct the primary and secondary differential frequency offsets by using the semi-symbol frequency offset corresponding to the primary synchronization signal to obtain a frequency offset correction value;

[0143] The determination module 33 is configured to determine a target frequency offset estimation value according to the target correction value and the frequency offset correction corresponding to the primary synchronization signal.

[0144] In some examples of this embodiment, the correction module 32 is specifically configured to obtain a frequency offset correction value according to the frequency offset estimation ranges corresponding to the primary synchronization signal and the secondary synchronization signal and the primary and secondary differential frequency offsets; use the semi-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to perform period correction on the primary and secondary differential frequency offsets to determine the target correction value.

[0145] In some examples of this embodiment, the correction module 32 is specifically configured to obtain the frequency deviation values between the frequency offset correction value and the semi-symbol frequency offset respectively; determine the frequency offset correction value corresponding to the minimum frequency deviation value as the target correction value after period correction.

[0146] In some examples of this embodiment, the correction module 32 is specifically configured to determine the frequency offset estimation range based on the maximum frequency offset estimation values corresponding to the primary synchronization signal and the secondary synchronization signal.

[0147] In some examples of this embodiment, the correction module 32 is specifically configured to determine the primary and secondary differential frequency offsets as the frequency offset correction value; and / or determine the frequency offset obtained by adding the primary and secondary differential frequency offsets to the maximum frequency offset estimation value as the frequency offset correction value; and / or determine the frequency offset obtained by subtracting the primary and secondary differential frequency offsets from the maximum frequency offset estimation value as the frequency offset correction value.

[0148] In some examples of this embodiment, the obtaining module 31 is specifically configured to perform primary synchronization sequence detection on the received original primary synchronization signal to obtain a frequency correction frequency offset; use the frequency correction frequency offset to perform pre-frequency correction on the original primary synchronization signal and the original secondary synchronization signal respectively to obtain the pre-frequency corrected primary synchronization signal and secondary synchronization signal.

[0149] In some examples of this embodiment, the obtaining module 31 is specifically configured to obtain the primary synchronization detection branch corresponding to the current residual frequency offset, and use the primary synchronization detection branch to perform primary synchronization sequence detection on the original primary synchronization signal.

[0150] In some examples of this embodiment, the obtaining module 31 is further specifically configured to correct the current residual frequency offset based on the target frequency offset estimation value to obtain the corrected frequency; receive the broadcast message sent by the network device according to the frequency.

[0151] In some examples of this embodiment, the determining module 33 is specifically configured to add the target correction value to the frequency correction frequency offset corresponding to the primary synchronization signal to obtain the target frequency offset estimation value.

[0152] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0153] Figure 4 It is a schematic structural diagram of a communication device 1800 provided in this embodiment. The communication device 1800 can be a terminal device, a network device, a chip, a chip system, or a processor that supports the network device to implement the above method, or a chip, a chip system, or a processor that supports the user equipment to implement the above method. The device can be used to implement the method described in the above method embodiments, and specific reference can be made to the description in the above method embodiments.

[0154] The communication device 1800 includes: a transceiver; a memory; a processor, which is respectively connected to the transceiver and the memory, and is configured to control the wireless signal transceiver of the transceiver by executing computer-executable instructions on the memory, and can implement the functions of any of the above method embodiments.

[0155] The communication device 1800 may include one or more processors 1801. The processor 1801 can be a general-purpose processor or a dedicated processor, etc. For example, it can be a baseband processor or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processing unit can be used to control a communication device (such as a base station, a baseband chip, a terminal device, a terminal device chip, a DU or a CU, etc.), execute a computer program, and process the data of the computer program.

[0156] Optionally, the communication device 1800 may further include one or more memories 1802, on which a computer program 1804 may be stored, and the processor 1801 executes the computer program 1804, so that the communication device 1800 performs the method described in the above method embodiment. Optionally, data may also be stored in the memory 1802. The communication device 1800 and the memory 1802 may be provided separately or integrated together.

[0157] Optionally, the communication device 1800 may further include a transceiver 1805 and an antenna 1806. The transceiver 1805 may be referred to as a transceiver unit, a transceiver, or a transceiver circuit, etc., and is used to implement a transceiver function. The transceiver 1805 may include a receiver and a transmitter, the receiver may be referred to as a receiver or a receiving circuit, etc., and is used to implement a receiving function; the transmitter may be referred to as a transmitter or a transmitting circuit, etc., and is used to implement a transmitting function.

[0158] Optionally, the communication device 1800 may further include one or more interface circuits 1807. The interface circuit 1807 is used to receive code instructions and transmit them to the processor 1801. The processor 1801 executes the code instructions to enable the communication device 1800 to execute the method described in the above method embodiment.

[0159] In one implementation, the processor 1801 may include a transceiver for implementing the receiving and sending functions. For example, the transceiver may be a transceiver circuit, an interface, or an interface circuit. The transceiver circuit, interface, or interface circuit for implementing the receiving and sending functions may be separate or integrated. The above-mentioned transceiver circuit, interface, or interface circuit may be used for reading and writing code / data, or the above-mentioned transceiver circuit, interface, or interface circuit may be used for transmitting or delivering signals.

[0160] In one implementation, the processor 1801 may store a computer program 1803, which runs on the processor 1801 and enables the communication device 1800 to perform the method described in the above method embodiment. The computer program 1803 may be fixed in the processor 1801, in which case the processor 1801 may be implemented by hardware.

[0161] In one implementation, the communication device 1800 may include circuitry that can implement the functions of transmitting, receiving, or communicating in the foregoing method embodiments. The processors and transceivers described in this disclosure may be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit (RFIC), a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, and the like. The processors and transceivers may also be fabricated using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), BiCMOS, silicon germanium (SiGe), gallium arsenide (GaAs), and the like.

[0162] The communication device described in the above embodiments may be a network device or a user equipment, but the scope of the communication device described in this disclosure is not limited thereto, and the structure of the communication device may not be limited by Figure 4 . The communication device may be an independent device or may be part of a larger device. For example, the communication device may be:

[0163] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0164] (2) A collection of one or more ICs. Optionally, the IC collection may also include a storage component for storing data and computer programs;

[0165] (3) An ASIC, such as a modem;

[0166] (4) A module that can be embedded in other devices;

[0167] (5) A receiver, a terminal device, a smart terminal device, a cellular phone, a wireless device, a handheld device, a mobile unit, a vehicle-mounted device, a network device, a cloud device, an artificial intelligence device, and so on;

[0168] (6) Others, and so on.

[0169] Based on the above embodiments, the present embodiment further provides a chip, including at least one processor and a communication interface; the communication interface is configured to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method shown above through logic circuits or by executing code instructions.

[0170] Figure 5 FIG. 4 is a schematic structural diagram of a chip 1000 for implementing the above frequency offset estimation method provided by the present embodiment. Referring to Figure 5 , the chip 1000 includes at least one communication interface 1001 and a processor 1002. The communication interface 1001 is configured to receive signals input to the chip 1000 or signals output from the above chip 1000, and the processor 1002 communicates with the communication interface 1001 and implements the frequency offset estimation method described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0171] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present disclosure can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. For each specific application, those skilled in the art can use various methods to implement the described function, but such implementation should not be construed as exceeding the scope protected by the embodiments of the present disclosure.

[0172] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor of the computer, it implements the functions of any one of the above method embodiments.

[0173] The present disclosure also provides a computer program product. When the computer program product is executed by a computer, it implements the functions of any one of the above method embodiments. For example, a computer program is stored thereon, and when the computer program product is executed by a processor of the computer, it implements the functions of any one of the above method embodiments.

[0174] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs. When the computer program is loaded and executed on a computer, the processes or functions according to the embodiments of the present disclosure are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer program can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a high-density digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0175] Those of ordinary skill in the art can understand that the various numerical numbers such as the first, second, etc. involved in the present disclosure are only for the convenience of description and are not used to limit the scope of the embodiments of the present disclosure, nor do they represent the order of precedence.

[0176] At least one in the present disclosure can also be described as one or more. The plurality can be two, three, four, or more, and the present disclosure does not make any restrictions. In the embodiments of the present disclosure, for a technical feature, the technical features in this technical feature are distinguished by "first", "second", "third", "A", "B", "C", and "D", etc. There is no order of precedence or size order among the technical features described by the "first", "second", "third", "A", "B", "C", and "D".

[0177] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (such as a disk, optical disc, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0178] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0179] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other.

[0180] It should be understood that the various forms of the flow shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this disclosure application can be achieved, and this is not limited herein.

[0181] In addition, it should be understood that the various embodiments described in this disclosure can be implemented separately or, where the solution permits, in combination with other embodiments.

[0182] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in connection with the embodiments claimed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this disclosure.

[0183] Those skilled in the art can clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the systems, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0184] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims described above.

Claims

1. A frequency offset estimation method, characterized in that: include: Perform differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal to obtain primary and secondary differential frequency offsets; Using the half-symbol frequency deviation corresponding to the primary synchronization signal, the primary-auxiliary differential frequency deviation is corrected to obtain a target correction value; A target frequency deviation estimation value is determined according to the target correction value and the frequency correction frequency deviation corresponding to the primary synchronization signal.

2. The method according to claim 1, characterized in that The method of correcting the primary-auxiliary differential frequency offset by using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value includes: Acquire a frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary and secondary differential frequency offsets; The primary and secondary differential frequency offsets are periodically corrected using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to determine a target correction value.

3. The method according to claim 2, characterized in that The method of periodically correcting the primary and secondary differential frequency offsets by using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to determine a target correction value includes: Obtaining the frequency offset correction value and the frequency offset value of the half-symbol frequency offset respectively; The frequency deviation correction value corresponding to the minimum frequency deviation value is determined as the target correction value after periodic correction.

4. The method according to claim 2, characterized in that: Before acquiring the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary and secondary differential frequency offsets, the method further includes: The frequency offset estimation range is determined according to maximum frequency offset estimation values ​​corresponding to the primary synchronization signal and the secondary synchronization signal.

5. The method according to claim 4, characterized in that The acquiring the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary and secondary differential frequency offsets includes: determining the primary and secondary differential frequency offsets as the frequency offset correction value; and / or, Determine the frequency offset obtained by adding the primary and secondary differential frequency offsets to the maximum frequency offset estimation value as the frequency offset correction value; and / or, The frequency offset obtained by subtracting the main and auxiliary differential frequency offsets from the maximum frequency offset estimate is determined as the frequency offset correction value.

6. The method according to claim 1, characterized in that Also includes: Performing main synchronization sequence detection on the received original main synchronization signal to obtain the frequency correction frequency deviation; The frequency correction frequency deviation is used to pre-correct the original main synchronization signal and the original auxiliary synchronization signal respectively, so as to obtain the main synchronization signal and the auxiliary synchronization signal after frequency correction.

7. The method according to claim 6, characterized in that The performing main synchronization sequence detection on the original main synchronization signal comprises: A primary synchronization detection branch corresponding to the current residual frequency offset is obtained, and the primary synchronization detection branch is used to perform primary synchronization sequence detection on the original primary synchronization signal.

8. The method according to claim 7, characterized in that The method further comprises: Correcting the current residual frequency offset based on the target frequency offset estimation value to obtain a corrected frequency; The broadcast message sent by the network device is received according to the frequency.

9. The method according to claim 1, characterized in that: The determining a target frequency deviation estimation value according to the target correction value and the frequency correction frequency deviation corresponding to the primary synchronization signal includes: The target correction value is added to the frequency correction frequency offset corresponding to the primary synchronization signal to obtain the target frequency offset estimation value.

10. A frequency offset estimation device, characterized in that: include: An acquisition module is configured to acquire a main synchronization signal after frequency correction of the main synchronization signal and an auxiliary synchronization signal after frequency correction of the auxiliary synchronization signal; An acquisition module is configured to perform differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal to obtain a primary and secondary differential frequency offset; A correction module is configured to correct the primary and secondary differential frequency offsets using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value; The determination module is configured to determine a target frequency deviation estimation value according to the target correction value and the frequency correction frequency deviation corresponding to the primary synchronization signal.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

12. A communication device, wherein: include: Transceiver; Memory; A processor is connected to the transceiver and the memory, respectively, and is configured to control the wireless signal reception and transmission of the transceiver by executing computer executable instructions on the memory, and can implement the method described in any one of claims 1 to 9.

13. A chip, characterized in that: It includes at least one processor and a communication interface; the communication interface is used to receive a signal input to the chip or a signal output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 9 through a logic circuit or executing code instructions.

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